1c6b6a421SHawking Zhang /* 2c6b6a421SHawking Zhang * Copyright 2019 Advanced Micro Devices, Inc. 3c6b6a421SHawking Zhang * 4c6b6a421SHawking Zhang * Permission is hereby granted, free of charge, to any person obtaining a 5c6b6a421SHawking Zhang * copy of this software and associated documentation files (the "Software"), 6c6b6a421SHawking Zhang * to deal in the Software without restriction, including without limitation 7c6b6a421SHawking Zhang * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8c6b6a421SHawking Zhang * and/or sell copies of the Software, and to permit persons to whom the 9c6b6a421SHawking Zhang * Software is furnished to do so, subject to the following conditions: 10c6b6a421SHawking Zhang * 11c6b6a421SHawking Zhang * The above copyright notice and this permission notice shall be included in 12c6b6a421SHawking Zhang * all copies or substantial portions of the Software. 13c6b6a421SHawking Zhang * 14c6b6a421SHawking Zhang * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15c6b6a421SHawking Zhang * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16c6b6a421SHawking Zhang * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17c6b6a421SHawking Zhang * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18c6b6a421SHawking Zhang * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19c6b6a421SHawking Zhang * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20c6b6a421SHawking Zhang * OTHER DEALINGS IN THE SOFTWARE. 21c6b6a421SHawking Zhang * 22c6b6a421SHawking Zhang */ 23c6b6a421SHawking Zhang #include <linux/firmware.h> 24c6b6a421SHawking Zhang #include <linux/slab.h> 25c6b6a421SHawking Zhang #include <linux/module.h> 26e9eea902SAlex Deucher #include <linux/pci.h> 27e9eea902SAlex Deucher 28c6b6a421SHawking Zhang #include "amdgpu.h" 29c6b6a421SHawking Zhang #include "amdgpu_atombios.h" 30c6b6a421SHawking Zhang #include "amdgpu_ih.h" 31c6b6a421SHawking Zhang #include "amdgpu_uvd.h" 32c6b6a421SHawking Zhang #include "amdgpu_vce.h" 33c6b6a421SHawking Zhang #include "amdgpu_ucode.h" 34c6b6a421SHawking Zhang #include "amdgpu_psp.h" 35767acabdSKevin Wang #include "amdgpu_smu.h" 36c6b6a421SHawking Zhang #include "atom.h" 37c6b6a421SHawking Zhang #include "amd_pcie.h" 38c6b6a421SHawking Zhang 39c6b6a421SHawking Zhang #include "gc/gc_10_1_0_offset.h" 40c6b6a421SHawking Zhang #include "gc/gc_10_1_0_sh_mask.h" 41c6b6a421SHawking Zhang #include "hdp/hdp_5_0_0_offset.h" 42c6b6a421SHawking Zhang #include "hdp/hdp_5_0_0_sh_mask.h" 4329bc37b4SAlex Deucher #include "smuio/smuio_11_0_0_offset.h" 443967ae6dSAlex Deucher #include "mp/mp_11_0_offset.h" 45c6b6a421SHawking Zhang 46c6b6a421SHawking Zhang #include "soc15.h" 47c6b6a421SHawking Zhang #include "soc15_common.h" 48c6b6a421SHawking Zhang #include "gmc_v10_0.h" 49c6b6a421SHawking Zhang #include "gfxhub_v2_0.h" 50c6b6a421SHawking Zhang #include "mmhub_v2_0.h" 51bebc0762SHawking Zhang #include "nbio_v2_3.h" 52a7e91bd7SHuang Rui #include "nbio_v7_2.h" 53c6b6a421SHawking Zhang #include "nv.h" 54c6b6a421SHawking Zhang #include "navi10_ih.h" 55c6b6a421SHawking Zhang #include "gfx_v10_0.h" 56c6b6a421SHawking Zhang #include "sdma_v5_0.h" 57157e72e8SLikun Gao #include "sdma_v5_2.h" 58c6b6a421SHawking Zhang #include "vcn_v2_0.h" 595be45a26SLeo Liu #include "jpeg_v2_0.h" 60b8f10585SLeo Liu #include "vcn_v3_0.h" 614d72dd12SLeo Liu #include "jpeg_v3_0.h" 62c6b6a421SHawking Zhang #include "dce_virtual.h" 63c6b6a421SHawking Zhang #include "mes_v10_1.h" 64b05b6903SJiange Zhao #include "mxgpu_nv.h" 65c6b6a421SHawking Zhang 66c6b6a421SHawking Zhang static const struct amd_ip_funcs nv_common_ip_funcs; 67c6b6a421SHawking Zhang 68c6b6a421SHawking Zhang /* 69c6b6a421SHawking Zhang * Indirect registers accessor 70c6b6a421SHawking Zhang */ 71c6b6a421SHawking Zhang static u32 nv_pcie_rreg(struct amdgpu_device *adev, u32 reg) 72c6b6a421SHawking Zhang { 73705a2b5bSHawking Zhang unsigned long address, data; 74bebc0762SHawking Zhang address = adev->nbio.funcs->get_pcie_index_offset(adev); 75bebc0762SHawking Zhang data = adev->nbio.funcs->get_pcie_data_offset(adev); 76c6b6a421SHawking Zhang 77705a2b5bSHawking Zhang return amdgpu_device_indirect_rreg(adev, address, data, reg); 78c6b6a421SHawking Zhang } 79c6b6a421SHawking Zhang 80c6b6a421SHawking Zhang static void nv_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v) 81c6b6a421SHawking Zhang { 82705a2b5bSHawking Zhang unsigned long address, data; 83c6b6a421SHawking Zhang 84bebc0762SHawking Zhang address = adev->nbio.funcs->get_pcie_index_offset(adev); 85bebc0762SHawking Zhang data = adev->nbio.funcs->get_pcie_data_offset(adev); 86c6b6a421SHawking Zhang 87705a2b5bSHawking Zhang amdgpu_device_indirect_wreg(adev, address, data, reg, v); 88c6b6a421SHawking Zhang } 89c6b6a421SHawking Zhang 904922f1bcSJohn Clements static u64 nv_pcie_rreg64(struct amdgpu_device *adev, u32 reg) 914922f1bcSJohn Clements { 92705a2b5bSHawking Zhang unsigned long address, data; 934922f1bcSJohn Clements address = adev->nbio.funcs->get_pcie_index_offset(adev); 944922f1bcSJohn Clements data = adev->nbio.funcs->get_pcie_data_offset(adev); 954922f1bcSJohn Clements 96705a2b5bSHawking Zhang return amdgpu_device_indirect_rreg64(adev, address, data, reg); 974922f1bcSJohn Clements } 984922f1bcSJohn Clements 995de54343SHuang Rui static u32 nv_pcie_port_rreg(struct amdgpu_device *adev, u32 reg) 1005de54343SHuang Rui { 1015de54343SHuang Rui unsigned long flags, address, data; 1025de54343SHuang Rui u32 r; 1035de54343SHuang Rui address = adev->nbio.funcs->get_pcie_port_index_offset(adev); 1045de54343SHuang Rui data = adev->nbio.funcs->get_pcie_port_data_offset(adev); 1055de54343SHuang Rui 1065de54343SHuang Rui spin_lock_irqsave(&adev->pcie_idx_lock, flags); 1075de54343SHuang Rui WREG32(address, reg * 4); 1085de54343SHuang Rui (void)RREG32(address); 1095de54343SHuang Rui r = RREG32(data); 1105de54343SHuang Rui spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); 1115de54343SHuang Rui return r; 1125de54343SHuang Rui } 1135de54343SHuang Rui 1144922f1bcSJohn Clements static void nv_pcie_wreg64(struct amdgpu_device *adev, u32 reg, u64 v) 1154922f1bcSJohn Clements { 116705a2b5bSHawking Zhang unsigned long address, data; 1174922f1bcSJohn Clements 1184922f1bcSJohn Clements address = adev->nbio.funcs->get_pcie_index_offset(adev); 1194922f1bcSJohn Clements data = adev->nbio.funcs->get_pcie_data_offset(adev); 1204922f1bcSJohn Clements 121705a2b5bSHawking Zhang amdgpu_device_indirect_wreg64(adev, address, data, reg, v); 1224922f1bcSJohn Clements } 1234922f1bcSJohn Clements 1245de54343SHuang Rui static void nv_pcie_port_wreg(struct amdgpu_device *adev, u32 reg, u32 v) 1255de54343SHuang Rui { 1265de54343SHuang Rui unsigned long flags, address, data; 1275de54343SHuang Rui 1285de54343SHuang Rui address = adev->nbio.funcs->get_pcie_port_index_offset(adev); 1295de54343SHuang Rui data = adev->nbio.funcs->get_pcie_port_data_offset(adev); 1305de54343SHuang Rui 1315de54343SHuang Rui spin_lock_irqsave(&adev->pcie_idx_lock, flags); 1325de54343SHuang Rui WREG32(address, reg * 4); 1335de54343SHuang Rui (void)RREG32(address); 1345de54343SHuang Rui WREG32(data, v); 1355de54343SHuang Rui (void)RREG32(data); 1365de54343SHuang Rui spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); 1375de54343SHuang Rui } 1385de54343SHuang Rui 139c6b6a421SHawking Zhang static u32 nv_didt_rreg(struct amdgpu_device *adev, u32 reg) 140c6b6a421SHawking Zhang { 141c6b6a421SHawking Zhang unsigned long flags, address, data; 142c6b6a421SHawking Zhang u32 r; 143c6b6a421SHawking Zhang 144c6b6a421SHawking Zhang address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX); 145c6b6a421SHawking Zhang data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA); 146c6b6a421SHawking Zhang 147c6b6a421SHawking Zhang spin_lock_irqsave(&adev->didt_idx_lock, flags); 148c6b6a421SHawking Zhang WREG32(address, (reg)); 149c6b6a421SHawking Zhang r = RREG32(data); 150c6b6a421SHawking Zhang spin_unlock_irqrestore(&adev->didt_idx_lock, flags); 151c6b6a421SHawking Zhang return r; 152c6b6a421SHawking Zhang } 153c6b6a421SHawking Zhang 154c6b6a421SHawking Zhang static void nv_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v) 155c6b6a421SHawking Zhang { 156c6b6a421SHawking Zhang unsigned long flags, address, data; 157c6b6a421SHawking Zhang 158c6b6a421SHawking Zhang address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX); 159c6b6a421SHawking Zhang data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA); 160c6b6a421SHawking Zhang 161c6b6a421SHawking Zhang spin_lock_irqsave(&adev->didt_idx_lock, flags); 162c6b6a421SHawking Zhang WREG32(address, (reg)); 163c6b6a421SHawking Zhang WREG32(data, (v)); 164c6b6a421SHawking Zhang spin_unlock_irqrestore(&adev->didt_idx_lock, flags); 165c6b6a421SHawking Zhang } 166c6b6a421SHawking Zhang 167c6b6a421SHawking Zhang static u32 nv_get_config_memsize(struct amdgpu_device *adev) 168c6b6a421SHawking Zhang { 169bebc0762SHawking Zhang return adev->nbio.funcs->get_memsize(adev); 170c6b6a421SHawking Zhang } 171c6b6a421SHawking Zhang 172c6b6a421SHawking Zhang static u32 nv_get_xclk(struct amdgpu_device *adev) 173c6b6a421SHawking Zhang { 174462a70d8STao Zhou return adev->clock.spll.reference_freq; 175c6b6a421SHawking Zhang } 176c6b6a421SHawking Zhang 177c6b6a421SHawking Zhang 178c6b6a421SHawking Zhang void nv_grbm_select(struct amdgpu_device *adev, 179c6b6a421SHawking Zhang u32 me, u32 pipe, u32 queue, u32 vmid) 180c6b6a421SHawking Zhang { 181c6b6a421SHawking Zhang u32 grbm_gfx_cntl = 0; 182c6b6a421SHawking Zhang grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, PIPEID, pipe); 183c6b6a421SHawking Zhang grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, MEID, me); 184c6b6a421SHawking Zhang grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, VMID, vmid); 185c6b6a421SHawking Zhang grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, QUEUEID, queue); 186c6b6a421SHawking Zhang 187c6b6a421SHawking Zhang WREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_CNTL), grbm_gfx_cntl); 188c6b6a421SHawking Zhang } 189c6b6a421SHawking Zhang 190c6b6a421SHawking Zhang static void nv_vga_set_state(struct amdgpu_device *adev, bool state) 191c6b6a421SHawking Zhang { 192c6b6a421SHawking Zhang /* todo */ 193c6b6a421SHawking Zhang } 194c6b6a421SHawking Zhang 195c6b6a421SHawking Zhang static bool nv_read_disabled_bios(struct amdgpu_device *adev) 196c6b6a421SHawking Zhang { 197c6b6a421SHawking Zhang /* todo */ 198c6b6a421SHawking Zhang return false; 199c6b6a421SHawking Zhang } 200c6b6a421SHawking Zhang 201c6b6a421SHawking Zhang static bool nv_read_bios_from_rom(struct amdgpu_device *adev, 202c6b6a421SHawking Zhang u8 *bios, u32 length_bytes) 203c6b6a421SHawking Zhang { 20429bc37b4SAlex Deucher u32 *dw_ptr; 20529bc37b4SAlex Deucher u32 i, length_dw; 20629bc37b4SAlex Deucher 20729bc37b4SAlex Deucher if (bios == NULL) 208c6b6a421SHawking Zhang return false; 20929bc37b4SAlex Deucher if (length_bytes == 0) 21029bc37b4SAlex Deucher return false; 21129bc37b4SAlex Deucher /* APU vbios image is part of sbios image */ 21229bc37b4SAlex Deucher if (adev->flags & AMD_IS_APU) 21329bc37b4SAlex Deucher return false; 21429bc37b4SAlex Deucher 21529bc37b4SAlex Deucher dw_ptr = (u32 *)bios; 21629bc37b4SAlex Deucher length_dw = ALIGN(length_bytes, 4) / 4; 21729bc37b4SAlex Deucher 21829bc37b4SAlex Deucher /* set rom index to 0 */ 21929bc37b4SAlex Deucher WREG32(SOC15_REG_OFFSET(SMUIO, 0, mmROM_INDEX), 0); 22029bc37b4SAlex Deucher /* read out the rom data */ 22129bc37b4SAlex Deucher for (i = 0; i < length_dw; i++) 22229bc37b4SAlex Deucher dw_ptr[i] = RREG32(SOC15_REG_OFFSET(SMUIO, 0, mmROM_DATA)); 22329bc37b4SAlex Deucher 22429bc37b4SAlex Deucher return true; 225c6b6a421SHawking Zhang } 226c6b6a421SHawking Zhang 227c6b6a421SHawking Zhang static struct soc15_allowed_register_entry nv_allowed_read_registers[] = { 228c6b6a421SHawking Zhang { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS)}, 229c6b6a421SHawking Zhang { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS2)}, 230c6b6a421SHawking Zhang { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE0)}, 231c6b6a421SHawking Zhang { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE1)}, 232c6b6a421SHawking Zhang { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE2)}, 233c6b6a421SHawking Zhang { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE3)}, 234c6b6a421SHawking Zhang { SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_STATUS_REG)}, 235c6b6a421SHawking Zhang { SOC15_REG_ENTRY(SDMA1, 0, mmSDMA1_STATUS_REG)}, 236c6b6a421SHawking Zhang { SOC15_REG_ENTRY(GC, 0, mmCP_STAT)}, 237c6b6a421SHawking Zhang { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT1)}, 238c6b6a421SHawking Zhang { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT2)}, 239c6b6a421SHawking Zhang { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT3)}, 240c6b6a421SHawking Zhang { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_BUSY_STAT)}, 241c6b6a421SHawking Zhang { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STALLED_STAT1)}, 242c6b6a421SHawking Zhang { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STATUS)}, 243664fe85aSMarek Olšák { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_BUSY_STAT)}, 244c6b6a421SHawking Zhang { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STALLED_STAT1)}, 245c6b6a421SHawking Zhang { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STATUS)}, 246c6b6a421SHawking Zhang { SOC15_REG_ENTRY(GC, 0, mmGB_ADDR_CONFIG)}, 247c6b6a421SHawking Zhang }; 248c6b6a421SHawking Zhang 249c6b6a421SHawking Zhang static uint32_t nv_read_indexed_register(struct amdgpu_device *adev, u32 se_num, 250c6b6a421SHawking Zhang u32 sh_num, u32 reg_offset) 251c6b6a421SHawking Zhang { 252c6b6a421SHawking Zhang uint32_t val; 253c6b6a421SHawking Zhang 254c6b6a421SHawking Zhang mutex_lock(&adev->grbm_idx_mutex); 255c6b6a421SHawking Zhang if (se_num != 0xffffffff || sh_num != 0xffffffff) 256c6b6a421SHawking Zhang amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff); 257c6b6a421SHawking Zhang 258c6b6a421SHawking Zhang val = RREG32(reg_offset); 259c6b6a421SHawking Zhang 260c6b6a421SHawking Zhang if (se_num != 0xffffffff || sh_num != 0xffffffff) 261c6b6a421SHawking Zhang amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 262c6b6a421SHawking Zhang mutex_unlock(&adev->grbm_idx_mutex); 263c6b6a421SHawking Zhang return val; 264c6b6a421SHawking Zhang } 265c6b6a421SHawking Zhang 266c6b6a421SHawking Zhang static uint32_t nv_get_register_value(struct amdgpu_device *adev, 267c6b6a421SHawking Zhang bool indexed, u32 se_num, 268c6b6a421SHawking Zhang u32 sh_num, u32 reg_offset) 269c6b6a421SHawking Zhang { 270c6b6a421SHawking Zhang if (indexed) { 271c6b6a421SHawking Zhang return nv_read_indexed_register(adev, se_num, sh_num, reg_offset); 272c6b6a421SHawking Zhang } else { 273c6b6a421SHawking Zhang if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG)) 274c6b6a421SHawking Zhang return adev->gfx.config.gb_addr_config; 275c6b6a421SHawking Zhang return RREG32(reg_offset); 276c6b6a421SHawking Zhang } 277c6b6a421SHawking Zhang } 278c6b6a421SHawking Zhang 279c6b6a421SHawking Zhang static int nv_read_register(struct amdgpu_device *adev, u32 se_num, 280c6b6a421SHawking Zhang u32 sh_num, u32 reg_offset, u32 *value) 281c6b6a421SHawking Zhang { 282c6b6a421SHawking Zhang uint32_t i; 283c6b6a421SHawking Zhang struct soc15_allowed_register_entry *en; 284c6b6a421SHawking Zhang 285c6b6a421SHawking Zhang *value = 0; 286c6b6a421SHawking Zhang for (i = 0; i < ARRAY_SIZE(nv_allowed_read_registers); i++) { 287c6b6a421SHawking Zhang en = &nv_allowed_read_registers[i]; 288fced3c3aSHuang Rui if ((i == 7 && (adev->sdma.num_instances == 1)) || /* some asics don't have SDMA1 */ 289fced3c3aSHuang Rui reg_offset != 290c6b6a421SHawking Zhang (adev->reg_offset[en->hwip][en->inst][en->seg] + en->reg_offset)) 291c6b6a421SHawking Zhang continue; 292c6b6a421SHawking Zhang 293c6b6a421SHawking Zhang *value = nv_get_register_value(adev, 294c6b6a421SHawking Zhang nv_allowed_read_registers[i].grbm_indexed, 295c6b6a421SHawking Zhang se_num, sh_num, reg_offset); 296c6b6a421SHawking Zhang return 0; 297c6b6a421SHawking Zhang } 298c6b6a421SHawking Zhang return -EINVAL; 299c6b6a421SHawking Zhang } 300c6b6a421SHawking Zhang 3013e2bb60aSKevin Wang static int nv_asic_mode1_reset(struct amdgpu_device *adev) 3023e2bb60aSKevin Wang { 3033e2bb60aSKevin Wang u32 i; 3043e2bb60aSKevin Wang int ret = 0; 3053e2bb60aSKevin Wang 3063e2bb60aSKevin Wang amdgpu_atombios_scratch_regs_engine_hung(adev, true); 3073e2bb60aSKevin Wang 3083e2bb60aSKevin Wang /* disable BM */ 3093e2bb60aSKevin Wang pci_clear_master(adev->pdev); 3103e2bb60aSKevin Wang 311c1dd4aa6SAndrey Grodzovsky amdgpu_device_cache_pci_state(adev->pdev); 3123e2bb60aSKevin Wang 313311531f0SWenhui Sheng if (amdgpu_dpm_is_mode1_reset_supported(adev)) { 314311531f0SWenhui Sheng dev_info(adev->dev, "GPU smu mode1 reset\n"); 315311531f0SWenhui Sheng ret = amdgpu_dpm_mode1_reset(adev); 316311531f0SWenhui Sheng } else { 317311531f0SWenhui Sheng dev_info(adev->dev, "GPU psp mode1 reset\n"); 3183e2bb60aSKevin Wang ret = psp_gpu_reset(adev); 319311531f0SWenhui Sheng } 320311531f0SWenhui Sheng 3213e2bb60aSKevin Wang if (ret) 3223e2bb60aSKevin Wang dev_err(adev->dev, "GPU mode1 reset failed\n"); 323c1dd4aa6SAndrey Grodzovsky amdgpu_device_load_pci_state(adev->pdev); 3243e2bb60aSKevin Wang 3253e2bb60aSKevin Wang /* wait for asic to come out of reset */ 3263e2bb60aSKevin Wang for (i = 0; i < adev->usec_timeout; i++) { 327bebc0762SHawking Zhang u32 memsize = adev->nbio.funcs->get_memsize(adev); 3283e2bb60aSKevin Wang 3293e2bb60aSKevin Wang if (memsize != 0xffffffff) 3303e2bb60aSKevin Wang break; 3313e2bb60aSKevin Wang udelay(1); 3323e2bb60aSKevin Wang } 3333e2bb60aSKevin Wang 3343e2bb60aSKevin Wang amdgpu_atombios_scratch_regs_engine_hung(adev, false); 3353e2bb60aSKevin Wang 3363e2bb60aSKevin Wang return ret; 3373e2bb60aSKevin Wang } 3382ddc6c3eSAlex Deucher 339ac742616SAlex Deucher static bool nv_asic_supports_baco(struct amdgpu_device *adev) 340ac742616SAlex Deucher { 341ac742616SAlex Deucher struct smu_context *smu = &adev->smu; 342ac742616SAlex Deucher 343ac742616SAlex Deucher if (smu_baco_is_support(smu)) 344ac742616SAlex Deucher return true; 345ac742616SAlex Deucher else 346ac742616SAlex Deucher return false; 347ac742616SAlex Deucher } 348ac742616SAlex Deucher 3492ddc6c3eSAlex Deucher static enum amd_reset_method 3502ddc6c3eSAlex Deucher nv_asic_reset_method(struct amdgpu_device *adev) 3512ddc6c3eSAlex Deucher { 3522ddc6c3eSAlex Deucher struct smu_context *smu = &adev->smu; 3532ddc6c3eSAlex Deucher 354273da6ffSWenhui Sheng if (amdgpu_reset_method == AMD_RESET_METHOD_MODE1 || 355273da6ffSWenhui Sheng amdgpu_reset_method == AMD_RESET_METHOD_BACO) 356273da6ffSWenhui Sheng return amdgpu_reset_method; 357273da6ffSWenhui Sheng 358273da6ffSWenhui Sheng if (amdgpu_reset_method != -1) 359273da6ffSWenhui Sheng dev_warn(adev->dev, "Specified reset method:%d isn't supported, using AUTO instead.\n", 360273da6ffSWenhui Sheng amdgpu_reset_method); 361273da6ffSWenhui Sheng 362ca6fd7a6SLikun Gao switch (adev->asic_type) { 363ca6fd7a6SLikun Gao case CHIP_SIENNA_CICHLID: 36422dd44f4SJiansong Chen case CHIP_NAVY_FLOUNDER: 365ca6fd7a6SLikun Gao return AMD_RESET_METHOD_MODE1; 366ca6fd7a6SLikun Gao default: 367311531f0SWenhui Sheng if (smu_baco_is_support(smu)) 3682ddc6c3eSAlex Deucher return AMD_RESET_METHOD_BACO; 3692ddc6c3eSAlex Deucher else 3702ddc6c3eSAlex Deucher return AMD_RESET_METHOD_MODE1; 3712ddc6c3eSAlex Deucher } 372ca6fd7a6SLikun Gao } 3732ddc6c3eSAlex Deucher 374c6b6a421SHawking Zhang static int nv_asic_reset(struct amdgpu_device *adev) 375c6b6a421SHawking Zhang { 376767acabdSKevin Wang int ret = 0; 377767acabdSKevin Wang struct smu_context *smu = &adev->smu; 378c6b6a421SHawking Zhang 379e3526257SMonk Liu if (nv_asic_reset_method(adev) == AMD_RESET_METHOD_BACO) { 38011043b7aSAlex Deucher dev_info(adev->dev, "BACO reset\n"); 381311531f0SWenhui Sheng 38211520f27SAlex Deucher ret = smu_baco_enter(smu); 38311520f27SAlex Deucher if (ret) 38411520f27SAlex Deucher return ret; 38511520f27SAlex Deucher ret = smu_baco_exit(smu); 38611520f27SAlex Deucher if (ret) 38711520f27SAlex Deucher return ret; 38811043b7aSAlex Deucher } else { 38911043b7aSAlex Deucher dev_info(adev->dev, "MODE1 reset\n"); 3903e2bb60aSKevin Wang ret = nv_asic_mode1_reset(adev); 39111043b7aSAlex Deucher } 392767acabdSKevin Wang 393767acabdSKevin Wang return ret; 394c6b6a421SHawking Zhang } 395c6b6a421SHawking Zhang 396c6b6a421SHawking Zhang static int nv_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk) 397c6b6a421SHawking Zhang { 398c6b6a421SHawking Zhang /* todo */ 399c6b6a421SHawking Zhang return 0; 400c6b6a421SHawking Zhang } 401c6b6a421SHawking Zhang 402c6b6a421SHawking Zhang static int nv_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk) 403c6b6a421SHawking Zhang { 404c6b6a421SHawking Zhang /* todo */ 405c6b6a421SHawking Zhang return 0; 406c6b6a421SHawking Zhang } 407c6b6a421SHawking Zhang 408c6b6a421SHawking Zhang static void nv_pcie_gen3_enable(struct amdgpu_device *adev) 409c6b6a421SHawking Zhang { 410c6b6a421SHawking Zhang if (pci_is_root_bus(adev->pdev->bus)) 411c6b6a421SHawking Zhang return; 412c6b6a421SHawking Zhang 413c6b6a421SHawking Zhang if (amdgpu_pcie_gen2 == 0) 414c6b6a421SHawking Zhang return; 415c6b6a421SHawking Zhang 416c6b6a421SHawking Zhang if (!(adev->pm.pcie_gen_mask & (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 | 417c6b6a421SHawking Zhang CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3))) 418c6b6a421SHawking Zhang return; 419c6b6a421SHawking Zhang 420c6b6a421SHawking Zhang /* todo */ 421c6b6a421SHawking Zhang } 422c6b6a421SHawking Zhang 423c6b6a421SHawking Zhang static void nv_program_aspm(struct amdgpu_device *adev) 424c6b6a421SHawking Zhang { 425c6b6a421SHawking Zhang 426c6b6a421SHawking Zhang if (amdgpu_aspm == 0) 427c6b6a421SHawking Zhang return; 428c6b6a421SHawking Zhang 429c6b6a421SHawking Zhang /* todo */ 430c6b6a421SHawking Zhang } 431c6b6a421SHawking Zhang 432c6b6a421SHawking Zhang static void nv_enable_doorbell_aperture(struct amdgpu_device *adev, 433c6b6a421SHawking Zhang bool enable) 434c6b6a421SHawking Zhang { 435bebc0762SHawking Zhang adev->nbio.funcs->enable_doorbell_aperture(adev, enable); 436bebc0762SHawking Zhang adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, enable); 437c6b6a421SHawking Zhang } 438c6b6a421SHawking Zhang 439c6b6a421SHawking Zhang static const struct amdgpu_ip_block_version nv_common_ip_block = 440c6b6a421SHawking Zhang { 441c6b6a421SHawking Zhang .type = AMD_IP_BLOCK_TYPE_COMMON, 442c6b6a421SHawking Zhang .major = 1, 443c6b6a421SHawking Zhang .minor = 0, 444c6b6a421SHawking Zhang .rev = 0, 445c6b6a421SHawking Zhang .funcs = &nv_common_ip_funcs, 446c6b6a421SHawking Zhang }; 447c6b6a421SHawking Zhang 448b5c73856SXiaojie Yuan static int nv_reg_base_init(struct amdgpu_device *adev) 449c6b6a421SHawking Zhang { 450b5c73856SXiaojie Yuan int r; 451b5c73856SXiaojie Yuan 452b5c73856SXiaojie Yuan if (amdgpu_discovery) { 453b5c73856SXiaojie Yuan r = amdgpu_discovery_reg_base_init(adev); 454b5c73856SXiaojie Yuan if (r) { 455b5c73856SXiaojie Yuan DRM_WARN("failed to init reg base from ip discovery table, " 456b5c73856SXiaojie Yuan "fallback to legacy init method\n"); 457b5c73856SXiaojie Yuan goto legacy_init; 458b5c73856SXiaojie Yuan } 459b5c73856SXiaojie Yuan 460b5c73856SXiaojie Yuan return 0; 461b5c73856SXiaojie Yuan } 462b5c73856SXiaojie Yuan 463b5c73856SXiaojie Yuan legacy_init: 464c6b6a421SHawking Zhang switch (adev->asic_type) { 465c6b6a421SHawking Zhang case CHIP_NAVI10: 466c6b6a421SHawking Zhang navi10_reg_base_init(adev); 467c6b6a421SHawking Zhang break; 468a0f6d926SXiaojie Yuan case CHIP_NAVI14: 469a0f6d926SXiaojie Yuan navi14_reg_base_init(adev); 470a0f6d926SXiaojie Yuan break; 47103d0a073SXiaojie Yuan case CHIP_NAVI12: 47203d0a073SXiaojie Yuan navi12_reg_base_init(adev); 47303d0a073SXiaojie Yuan break; 474dccdbf3fSLikun Gao case CHIP_SIENNA_CICHLID: 475c8c959f6SJiansong Chen case CHIP_NAVY_FLOUNDER: 476dccdbf3fSLikun Gao sienna_cichlid_reg_base_init(adev); 477dccdbf3fSLikun Gao break; 478026570e6SHuang Rui case CHIP_VANGOGH: 479026570e6SHuang Rui vangogh_reg_base_init(adev); 480026570e6SHuang Rui break; 481038d757bSTao Zhou case CHIP_DIMGREY_CAVEFISH: 482038d757bSTao Zhou dimgrey_cavefish_reg_base_init(adev); 483038d757bSTao Zhou break; 484c6b6a421SHawking Zhang default: 485c6b6a421SHawking Zhang return -EINVAL; 486c6b6a421SHawking Zhang } 487c6b6a421SHawking Zhang 488b5c73856SXiaojie Yuan return 0; 489b5c73856SXiaojie Yuan } 490b5c73856SXiaojie Yuan 491c1299461SWenhui Sheng void nv_set_virt_ops(struct amdgpu_device *adev) 492c1299461SWenhui Sheng { 493c1299461SWenhui Sheng adev->virt.ops = &xgpu_nv_virt_ops; 494c1299461SWenhui Sheng } 495c1299461SWenhui Sheng 4969c94b5efSFlora Cui static bool nv_is_headless_sku(struct pci_dev *pdev) 497aa5375c5STianci.Yin { 498dd657888SFlora Cui if ((pdev->device == 0x731E && 499dd657888SFlora Cui (pdev->revision == 0xC6 || pdev->revision == 0xC7)) || 500dd657888SFlora Cui (pdev->device == 0x7340 && pdev->revision == 0xC9)) 501aa5375c5STianci.Yin return true; 502aa5375c5STianci.Yin return false; 503aa5375c5STianci.Yin } 504aa5375c5STianci.Yin 505b5c73856SXiaojie Yuan int nv_set_ip_blocks(struct amdgpu_device *adev) 506b5c73856SXiaojie Yuan { 507b5c73856SXiaojie Yuan int r; 508b5c73856SXiaojie Yuan 509a7e91bd7SHuang Rui if (adev->flags & AMD_IS_APU) { 510a7e91bd7SHuang Rui adev->nbio.funcs = &nbio_v7_2_funcs; 511a7e91bd7SHuang Rui adev->nbio.hdp_flush_reg = &nbio_v7_2_hdp_flush_reg; 512a7e91bd7SHuang Rui } else { 513122078deSMonk Liu adev->nbio.funcs = &nbio_v2_3_funcs; 514122078deSMonk Liu adev->nbio.hdp_flush_reg = &nbio_v2_3_hdp_flush_reg; 515a7e91bd7SHuang Rui } 516122078deSMonk Liu 517c652923aSJohn Clements if (adev->asic_type == CHIP_SIENNA_CICHLID) 518c652923aSJohn Clements adev->gmc.xgmi.supported = true; 519c652923aSJohn Clements 520b5c73856SXiaojie Yuan /* Set IP register base before any HW register access */ 521b5c73856SXiaojie Yuan r = nv_reg_base_init(adev); 522b5c73856SXiaojie Yuan if (r) 523b5c73856SXiaojie Yuan return r; 524b5c73856SXiaojie Yuan 525c6b6a421SHawking Zhang switch (adev->asic_type) { 526c6b6a421SHawking Zhang case CHIP_NAVI10: 527d1daf850SAlex Deucher case CHIP_NAVI14: 528c6b6a421SHawking Zhang amdgpu_device_ip_block_add(adev, &nv_common_ip_block); 529c6b6a421SHawking Zhang amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block); 530c6b6a421SHawking Zhang amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block); 531c6b6a421SHawking Zhang amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block); 532c6b6a421SHawking Zhang if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP && 5339530273eSEvan Quan !amdgpu_sriov_vf(adev)) 534c6b6a421SHawking Zhang amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 535c6b6a421SHawking Zhang if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) 536c6b6a421SHawking Zhang amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block); 537f8a7976bSAlex Deucher #if defined(CONFIG_DRM_AMD_DC) 538*8301f6b9STianci.Yin else if (amdgpu_device_has_dc_support(adev)) 539b4f199c7SHarry Wentland amdgpu_device_ip_block_add(adev, &dm_ip_block); 540f8a7976bSAlex Deucher #endif 541c6b6a421SHawking Zhang amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block); 542c6b6a421SHawking Zhang amdgpu_device_ip_block_add(adev, &sdma_v5_0_ip_block); 543c6b6a421SHawking Zhang if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT && 5449530273eSEvan Quan !amdgpu_sriov_vf(adev)) 545c6b6a421SHawking Zhang amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 5469c94b5efSFlora Cui if (!nv_is_headless_sku(adev->pdev)) 547c6b6a421SHawking Zhang amdgpu_device_ip_block_add(adev, &vcn_v2_0_ip_block); 5485be45a26SLeo Liu amdgpu_device_ip_block_add(adev, &jpeg_v2_0_ip_block); 549c6b6a421SHawking Zhang if (adev->enable_mes) 550c6b6a421SHawking Zhang amdgpu_device_ip_block_add(adev, &mes_v10_1_ip_block); 551c6b6a421SHawking Zhang break; 55244e9e7c9SXiaojie Yuan case CHIP_NAVI12: 55344e9e7c9SXiaojie Yuan amdgpu_device_ip_block_add(adev, &nv_common_ip_block); 55444e9e7c9SXiaojie Yuan amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block); 55544e9e7c9SXiaojie Yuan amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block); 5566b66ae2eSXiaojie Yuan amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block); 55779bebabbSMonk Liu if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) 5587f47efebSXiaojie Yuan amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 55979902029SXiaojie Yuan if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) 56079902029SXiaojie Yuan amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block); 56120c14ee1SPetr Cvek #if defined(CONFIG_DRM_AMD_DC) 562078655d9SLeo Li else if (amdgpu_device_has_dc_support(adev)) 563078655d9SLeo Li amdgpu_device_ip_block_add(adev, &dm_ip_block); 56420c14ee1SPetr Cvek #endif 56544e9e7c9SXiaojie Yuan amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block); 56644e9e7c9SXiaojie Yuan amdgpu_device_ip_block_add(adev, &sdma_v5_0_ip_block); 5677f47efebSXiaojie Yuan if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT && 5689530273eSEvan Quan !amdgpu_sriov_vf(adev)) 5697f47efebSXiaojie Yuan amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 5701fbed280SBoyuan Zhang amdgpu_device_ip_block_add(adev, &vcn_v2_0_ip_block); 571fe442491SMonk Liu if (!amdgpu_sriov_vf(adev)) 5725be45a26SLeo Liu amdgpu_device_ip_block_add(adev, &jpeg_v2_0_ip_block); 57344e9e7c9SXiaojie Yuan break; 5742e1ba10eSLikun Gao case CHIP_SIENNA_CICHLID: 5752e1ba10eSLikun Gao amdgpu_device_ip_block_add(adev, &nv_common_ip_block); 5760b3df16bSLikun Gao amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block); 577757b3af8SLikun Gao amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block); 57856304e72SLikun Gao if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) 5795aa02350SLikun Gao amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block); 580b07e5c60SLikun Gao if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP && 58138d5bbefSshaoyunl is_support_sw_smu(adev) && !amdgpu_sriov_vf(adev)) 582b07e5c60SLikun Gao amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 5839a986760SLikun Gao if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) 5849a986760SLikun Gao amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block); 585464ab91aSBhawanpreet Lakha #if defined(CONFIG_DRM_AMD_DC) 586464ab91aSBhawanpreet Lakha else if (amdgpu_device_has_dc_support(adev)) 587464ab91aSBhawanpreet Lakha amdgpu_device_ip_block_add(adev, &dm_ip_block); 588464ab91aSBhawanpreet Lakha #endif 589933c8a93SLikun Gao amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block); 590157e72e8SLikun Gao amdgpu_device_ip_block_add(adev, &sdma_v5_2_ip_block); 591b8f10585SLeo Liu amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block); 592c45fbe1bSJack Zhang if (!amdgpu_sriov_vf(adev)) 5934d72dd12SLeo Liu amdgpu_device_ip_block_add(adev, &jpeg_v3_0_ip_block); 594c45fbe1bSJack Zhang 595a346ef86SJack Xiao if (adev->enable_mes) 596a346ef86SJack Xiao amdgpu_device_ip_block_add(adev, &mes_v10_1_ip_block); 5972e1ba10eSLikun Gao break; 5988515e0a4SJiansong Chen case CHIP_NAVY_FLOUNDER: 5998515e0a4SJiansong Chen amdgpu_device_ip_block_add(adev, &nv_common_ip_block); 600fc8f07daSJiansong Chen amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block); 601026c396bSJiansong Chen amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block); 6027420eab2SJiansong Chen if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) 6037420eab2SJiansong Chen amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block); 6047420eab2SJiansong Chen if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP && 6057420eab2SJiansong Chen is_support_sw_smu(adev)) 6067420eab2SJiansong Chen amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 6075404f073SJiansong Chen if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) 6085404f073SJiansong Chen amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block); 609a6c5308fSBhawanpreet Lakha #if defined(CONFIG_DRM_AMD_DC) 610a6c5308fSBhawanpreet Lakha else if (amdgpu_device_has_dc_support(adev)) 611a6c5308fSBhawanpreet Lakha amdgpu_device_ip_block_add(adev, &dm_ip_block); 612a6c5308fSBhawanpreet Lakha #endif 613885eb3faSJiansong Chen amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block); 614df2d15dfSJiansong Chen amdgpu_device_ip_block_add(adev, &sdma_v5_2_ip_block); 615290b4ad5SBoyuan Zhang amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block); 616290b4ad5SBoyuan Zhang amdgpu_device_ip_block_add(adev, &jpeg_v3_0_ip_block); 617f4497d10SJiansong Chen if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT && 618f4497d10SJiansong Chen is_support_sw_smu(adev)) 619f4497d10SJiansong Chen amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 6208515e0a4SJiansong Chen break; 62188edbad6SHuang Rui case CHIP_VANGOGH: 62288edbad6SHuang Rui amdgpu_device_ip_block_add(adev, &nv_common_ip_block); 62388edbad6SHuang Rui amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block); 62488edbad6SHuang Rui amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block); 625ed3b7353SHuang Rui if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) 626ed3b7353SHuang Rui amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block); 627c821e0fbSHuang Rui amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 62888edbad6SHuang Rui if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) 62988edbad6SHuang Rui amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block); 63084b934bcSHuang Rui #if defined(CONFIG_DRM_AMD_DC) 63184b934bcSHuang Rui else if (amdgpu_device_has_dc_support(adev)) 63284b934bcSHuang Rui amdgpu_device_ip_block_add(adev, &dm_ip_block); 63384b934bcSHuang Rui #endif 63488edbad6SHuang Rui amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block); 63588edbad6SHuang Rui amdgpu_device_ip_block_add(adev, &sdma_v5_2_ip_block); 636b4e532d6SThong Thai amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block); 637b4e532d6SThong Thai amdgpu_device_ip_block_add(adev, &jpeg_v3_0_ip_block); 63888edbad6SHuang Rui break; 6392aa92b12STao Zhou case CHIP_DIMGREY_CAVEFISH: 6402aa92b12STao Zhou amdgpu_device_ip_block_add(adev, &nv_common_ip_block); 6413e02ad44STao Zhou amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block); 642771cc67eSTao Zhou amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block); 643aff39cdeSTao Zhou if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) 644aff39cdeSTao Zhou amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block); 645aff39cdeSTao Zhou if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP && 646aff39cdeSTao Zhou is_support_sw_smu(adev)) 647aff39cdeSTao Zhou amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 64876a2d9eaSTao Zhou if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) 64976a2d9eaSTao Zhou amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block); 6507cc656e2STao Zhou #if defined(CONFIG_DRM_AMD_DC) 6517cc656e2STao Zhou else if (amdgpu_device_has_dc_support(adev)) 6527cc656e2STao Zhou amdgpu_device_ip_block_add(adev, &dm_ip_block); 6537cc656e2STao Zhou #endif 654feb6329cSTao Zhou amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block); 65501069226STao Zhou amdgpu_device_ip_block_add(adev, &sdma_v5_2_ip_block); 6560afc770bSJames Zhu amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block); 657be6b1cd3SJames Zhu amdgpu_device_ip_block_add(adev, &jpeg_v3_0_ip_block); 6582aa92b12STao Zhou break; 659c6b6a421SHawking Zhang default: 660c6b6a421SHawking Zhang return -EINVAL; 661c6b6a421SHawking Zhang } 662c6b6a421SHawking Zhang 663c6b6a421SHawking Zhang return 0; 664c6b6a421SHawking Zhang } 665c6b6a421SHawking Zhang 666c6b6a421SHawking Zhang static uint32_t nv_get_rev_id(struct amdgpu_device *adev) 667c6b6a421SHawking Zhang { 668bebc0762SHawking Zhang return adev->nbio.funcs->get_rev_id(adev); 669c6b6a421SHawking Zhang } 670c6b6a421SHawking Zhang 671c6b6a421SHawking Zhang static void nv_flush_hdp(struct amdgpu_device *adev, struct amdgpu_ring *ring) 672c6b6a421SHawking Zhang { 673bebc0762SHawking Zhang adev->nbio.funcs->hdp_flush(adev, ring); 674c6b6a421SHawking Zhang } 675c6b6a421SHawking Zhang 676c6b6a421SHawking Zhang static void nv_invalidate_hdp(struct amdgpu_device *adev, 677c6b6a421SHawking Zhang struct amdgpu_ring *ring) 678c6b6a421SHawking Zhang { 679c6b6a421SHawking Zhang if (!ring || !ring->funcs->emit_wreg) { 68078f0aef1SStanley.Yang WREG32_SOC15_NO_KIQ(HDP, 0, mmHDP_READ_CACHE_INVALIDATE, 1); 681c6b6a421SHawking Zhang } else { 682c6b6a421SHawking Zhang amdgpu_ring_emit_wreg(ring, SOC15_REG_OFFSET( 683c6b6a421SHawking Zhang HDP, 0, mmHDP_READ_CACHE_INVALIDATE), 1); 684c6b6a421SHawking Zhang } 685c6b6a421SHawking Zhang } 686c6b6a421SHawking Zhang 687c6b6a421SHawking Zhang static bool nv_need_full_reset(struct amdgpu_device *adev) 688c6b6a421SHawking Zhang { 689c6b6a421SHawking Zhang return true; 690c6b6a421SHawking Zhang } 691c6b6a421SHawking Zhang 692c6b6a421SHawking Zhang static bool nv_need_reset_on_init(struct amdgpu_device *adev) 693c6b6a421SHawking Zhang { 694c6b6a421SHawking Zhang u32 sol_reg; 695c6b6a421SHawking Zhang 696c6b6a421SHawking Zhang if (adev->flags & AMD_IS_APU) 697c6b6a421SHawking Zhang return false; 698c6b6a421SHawking Zhang 699c6b6a421SHawking Zhang /* Check sOS sign of life register to confirm sys driver and sOS 700c6b6a421SHawking Zhang * are already been loaded. 701c6b6a421SHawking Zhang */ 702c6b6a421SHawking Zhang sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81); 703c6b6a421SHawking Zhang if (sol_reg) 704c6b6a421SHawking Zhang return true; 7053967ae6dSAlex Deucher 706c6b6a421SHawking Zhang return false; 707c6b6a421SHawking Zhang } 708c6b6a421SHawking Zhang 7092af81531SKevin Wang static uint64_t nv_get_pcie_replay_count(struct amdgpu_device *adev) 7102af81531SKevin Wang { 7112af81531SKevin Wang 7122af81531SKevin Wang /* TODO 7132af81531SKevin Wang * dummy implement for pcie_replay_count sysfs interface 7142af81531SKevin Wang * */ 7152af81531SKevin Wang 7162af81531SKevin Wang return 0; 7172af81531SKevin Wang } 7182af81531SKevin Wang 719c6b6a421SHawking Zhang static void nv_init_doorbell_index(struct amdgpu_device *adev) 720c6b6a421SHawking Zhang { 721c6b6a421SHawking Zhang adev->doorbell_index.kiq = AMDGPU_NAVI10_DOORBELL_KIQ; 722c6b6a421SHawking Zhang adev->doorbell_index.mec_ring0 = AMDGPU_NAVI10_DOORBELL_MEC_RING0; 723c6b6a421SHawking Zhang adev->doorbell_index.mec_ring1 = AMDGPU_NAVI10_DOORBELL_MEC_RING1; 724c6b6a421SHawking Zhang adev->doorbell_index.mec_ring2 = AMDGPU_NAVI10_DOORBELL_MEC_RING2; 725c6b6a421SHawking Zhang adev->doorbell_index.mec_ring3 = AMDGPU_NAVI10_DOORBELL_MEC_RING3; 726c6b6a421SHawking Zhang adev->doorbell_index.mec_ring4 = AMDGPU_NAVI10_DOORBELL_MEC_RING4; 727c6b6a421SHawking Zhang adev->doorbell_index.mec_ring5 = AMDGPU_NAVI10_DOORBELL_MEC_RING5; 728c6b6a421SHawking Zhang adev->doorbell_index.mec_ring6 = AMDGPU_NAVI10_DOORBELL_MEC_RING6; 729c6b6a421SHawking Zhang adev->doorbell_index.mec_ring7 = AMDGPU_NAVI10_DOORBELL_MEC_RING7; 730c6b6a421SHawking Zhang adev->doorbell_index.userqueue_start = AMDGPU_NAVI10_DOORBELL_USERQUEUE_START; 731c6b6a421SHawking Zhang adev->doorbell_index.userqueue_end = AMDGPU_NAVI10_DOORBELL_USERQUEUE_END; 732c6b6a421SHawking Zhang adev->doorbell_index.gfx_ring0 = AMDGPU_NAVI10_DOORBELL_GFX_RING0; 733c6b6a421SHawking Zhang adev->doorbell_index.gfx_ring1 = AMDGPU_NAVI10_DOORBELL_GFX_RING1; 73420519232SJack Xiao adev->doorbell_index.mes_ring = AMDGPU_NAVI10_DOORBELL_MES_RING; 735c6b6a421SHawking Zhang adev->doorbell_index.sdma_engine[0] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE0; 736c6b6a421SHawking Zhang adev->doorbell_index.sdma_engine[1] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE1; 737157e72e8SLikun Gao adev->doorbell_index.sdma_engine[2] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE2; 738157e72e8SLikun Gao adev->doorbell_index.sdma_engine[3] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE3; 739c6b6a421SHawking Zhang adev->doorbell_index.ih = AMDGPU_NAVI10_DOORBELL_IH; 740c6b6a421SHawking Zhang adev->doorbell_index.vcn.vcn_ring0_1 = AMDGPU_NAVI10_DOORBELL64_VCN0_1; 741c6b6a421SHawking Zhang adev->doorbell_index.vcn.vcn_ring2_3 = AMDGPU_NAVI10_DOORBELL64_VCN2_3; 742c6b6a421SHawking Zhang adev->doorbell_index.vcn.vcn_ring4_5 = AMDGPU_NAVI10_DOORBELL64_VCN4_5; 743c6b6a421SHawking Zhang adev->doorbell_index.vcn.vcn_ring6_7 = AMDGPU_NAVI10_DOORBELL64_VCN6_7; 744c6b6a421SHawking Zhang adev->doorbell_index.first_non_cp = AMDGPU_NAVI10_DOORBELL64_FIRST_NON_CP; 745c6b6a421SHawking Zhang adev->doorbell_index.last_non_cp = AMDGPU_NAVI10_DOORBELL64_LAST_NON_CP; 746c6b6a421SHawking Zhang 747c6b6a421SHawking Zhang adev->doorbell_index.max_assignment = AMDGPU_NAVI10_DOORBELL_MAX_ASSIGNMENT << 1; 748c6b6a421SHawking Zhang adev->doorbell_index.sdma_doorbell_range = 20; 749c6b6a421SHawking Zhang } 750c6b6a421SHawking Zhang 751a7173731SAlex Deucher static void nv_pre_asic_init(struct amdgpu_device *adev) 752a7173731SAlex Deucher { 753a7173731SAlex Deucher } 754a7173731SAlex Deucher 75527747293SEvan Quan static int nv_update_umd_stable_pstate(struct amdgpu_device *adev, 75627747293SEvan Quan bool enter) 75727747293SEvan Quan { 75827747293SEvan Quan if (enter) 75927747293SEvan Quan amdgpu_gfx_rlc_enter_safe_mode(adev); 76027747293SEvan Quan else 76127747293SEvan Quan amdgpu_gfx_rlc_exit_safe_mode(adev); 76227747293SEvan Quan 76327747293SEvan Quan if (adev->gfx.funcs->update_perfmon_mgcg) 76427747293SEvan Quan adev->gfx.funcs->update_perfmon_mgcg(adev, !enter); 76527747293SEvan Quan 76627747293SEvan Quan /* 76727747293SEvan Quan * The ASPM function is not fully enabled and verified on 76827747293SEvan Quan * Navi yet. Temporarily skip this until ASPM enabled. 76927747293SEvan Quan */ 77027747293SEvan Quan #if 0 77127747293SEvan Quan if (adev->nbio.funcs->enable_aspm) 77227747293SEvan Quan adev->nbio.funcs->enable_aspm(adev, !enter); 77327747293SEvan Quan #endif 77427747293SEvan Quan 77527747293SEvan Quan return 0; 77627747293SEvan Quan } 77727747293SEvan Quan 778c6b6a421SHawking Zhang static const struct amdgpu_asic_funcs nv_asic_funcs = 779c6b6a421SHawking Zhang { 780c6b6a421SHawking Zhang .read_disabled_bios = &nv_read_disabled_bios, 781c6b6a421SHawking Zhang .read_bios_from_rom = &nv_read_bios_from_rom, 782c6b6a421SHawking Zhang .read_register = &nv_read_register, 783c6b6a421SHawking Zhang .reset = &nv_asic_reset, 7842ddc6c3eSAlex Deucher .reset_method = &nv_asic_reset_method, 785c6b6a421SHawking Zhang .set_vga_state = &nv_vga_set_state, 786c6b6a421SHawking Zhang .get_xclk = &nv_get_xclk, 787c6b6a421SHawking Zhang .set_uvd_clocks = &nv_set_uvd_clocks, 788c6b6a421SHawking Zhang .set_vce_clocks = &nv_set_vce_clocks, 789c6b6a421SHawking Zhang .get_config_memsize = &nv_get_config_memsize, 790c6b6a421SHawking Zhang .flush_hdp = &nv_flush_hdp, 791c6b6a421SHawking Zhang .invalidate_hdp = &nv_invalidate_hdp, 792c6b6a421SHawking Zhang .init_doorbell_index = &nv_init_doorbell_index, 793c6b6a421SHawking Zhang .need_full_reset = &nv_need_full_reset, 794c6b6a421SHawking Zhang .need_reset_on_init = &nv_need_reset_on_init, 7952af81531SKevin Wang .get_pcie_replay_count = &nv_get_pcie_replay_count, 796ac742616SAlex Deucher .supports_baco = &nv_asic_supports_baco, 797a7173731SAlex Deucher .pre_asic_init = &nv_pre_asic_init, 79827747293SEvan Quan .update_umd_stable_pstate = &nv_update_umd_stable_pstate, 799c6b6a421SHawking Zhang }; 800c6b6a421SHawking Zhang 801c6b6a421SHawking Zhang static int nv_common_early_init(void *handle) 802c6b6a421SHawking Zhang { 803923c087aSYong Zhao #define MMIO_REG_HOLE_OFFSET (0x80000 - PAGE_SIZE) 804c6b6a421SHawking Zhang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 805c6b6a421SHawking Zhang 806923c087aSYong Zhao adev->rmmio_remap.reg_offset = MMIO_REG_HOLE_OFFSET; 807923c087aSYong Zhao adev->rmmio_remap.bus_addr = adev->rmmio_base + MMIO_REG_HOLE_OFFSET; 808c6b6a421SHawking Zhang adev->smc_rreg = NULL; 809c6b6a421SHawking Zhang adev->smc_wreg = NULL; 810c6b6a421SHawking Zhang adev->pcie_rreg = &nv_pcie_rreg; 811c6b6a421SHawking Zhang adev->pcie_wreg = &nv_pcie_wreg; 8124922f1bcSJohn Clements adev->pcie_rreg64 = &nv_pcie_rreg64; 8134922f1bcSJohn Clements adev->pcie_wreg64 = &nv_pcie_wreg64; 8145de54343SHuang Rui adev->pciep_rreg = &nv_pcie_port_rreg; 8155de54343SHuang Rui adev->pciep_wreg = &nv_pcie_port_wreg; 816c6b6a421SHawking Zhang 817c6b6a421SHawking Zhang /* TODO: will add them during VCN v2 implementation */ 818c6b6a421SHawking Zhang adev->uvd_ctx_rreg = NULL; 819c6b6a421SHawking Zhang adev->uvd_ctx_wreg = NULL; 820c6b6a421SHawking Zhang 821c6b6a421SHawking Zhang adev->didt_rreg = &nv_didt_rreg; 822c6b6a421SHawking Zhang adev->didt_wreg = &nv_didt_wreg; 823c6b6a421SHawking Zhang 824c6b6a421SHawking Zhang adev->asic_funcs = &nv_asic_funcs; 825c6b6a421SHawking Zhang 826c6b6a421SHawking Zhang adev->rev_id = nv_get_rev_id(adev); 827c6b6a421SHawking Zhang adev->external_rev_id = 0xff; 828c6b6a421SHawking Zhang switch (adev->asic_type) { 829c6b6a421SHawking Zhang case CHIP_NAVI10: 830c6b6a421SHawking Zhang adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 831c6b6a421SHawking Zhang AMD_CG_SUPPORT_GFX_CGCG | 832c6b6a421SHawking Zhang AMD_CG_SUPPORT_IH_CG | 833c6b6a421SHawking Zhang AMD_CG_SUPPORT_HDP_MGCG | 834c6b6a421SHawking Zhang AMD_CG_SUPPORT_HDP_LS | 835c6b6a421SHawking Zhang AMD_CG_SUPPORT_SDMA_MGCG | 836c6b6a421SHawking Zhang AMD_CG_SUPPORT_SDMA_LS | 837c6b6a421SHawking Zhang AMD_CG_SUPPORT_MC_MGCG | 838c6b6a421SHawking Zhang AMD_CG_SUPPORT_MC_LS | 839c6b6a421SHawking Zhang AMD_CG_SUPPORT_ATHUB_MGCG | 840c6b6a421SHawking Zhang AMD_CG_SUPPORT_ATHUB_LS | 841c6b6a421SHawking Zhang AMD_CG_SUPPORT_VCN_MGCG | 842099d66e4SLeo Liu AMD_CG_SUPPORT_JPEG_MGCG | 843c6b6a421SHawking Zhang AMD_CG_SUPPORT_BIF_MGCG | 844c6b6a421SHawking Zhang AMD_CG_SUPPORT_BIF_LS; 845157710eaSLeo Liu adev->pg_flags = AMD_PG_SUPPORT_VCN | 846c12d410fSHuang Rui AMD_PG_SUPPORT_VCN_DPG | 847099d66e4SLeo Liu AMD_PG_SUPPORT_JPEG | 848a201b6acSHuang Rui AMD_PG_SUPPORT_ATHUB; 849c6b6a421SHawking Zhang adev->external_rev_id = adev->rev_id + 0x1; 850c6b6a421SHawking Zhang break; 8515e71e011SXiaojie Yuan case CHIP_NAVI14: 852d0c39f8cSXiaojie Yuan adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 853d0c39f8cSXiaojie Yuan AMD_CG_SUPPORT_GFX_CGCG | 854d0c39f8cSXiaojie Yuan AMD_CG_SUPPORT_IH_CG | 855d0c39f8cSXiaojie Yuan AMD_CG_SUPPORT_HDP_MGCG | 856d0c39f8cSXiaojie Yuan AMD_CG_SUPPORT_HDP_LS | 857d0c39f8cSXiaojie Yuan AMD_CG_SUPPORT_SDMA_MGCG | 858d0c39f8cSXiaojie Yuan AMD_CG_SUPPORT_SDMA_LS | 859d0c39f8cSXiaojie Yuan AMD_CG_SUPPORT_MC_MGCG | 860d0c39f8cSXiaojie Yuan AMD_CG_SUPPORT_MC_LS | 861d0c39f8cSXiaojie Yuan AMD_CG_SUPPORT_ATHUB_MGCG | 862d0c39f8cSXiaojie Yuan AMD_CG_SUPPORT_ATHUB_LS | 863d0c39f8cSXiaojie Yuan AMD_CG_SUPPORT_VCN_MGCG | 864099d66e4SLeo Liu AMD_CG_SUPPORT_JPEG_MGCG | 865d0c39f8cSXiaojie Yuan AMD_CG_SUPPORT_BIF_MGCG | 866d0c39f8cSXiaojie Yuan AMD_CG_SUPPORT_BIF_LS; 8670377b088SXiaojie Yuan adev->pg_flags = AMD_PG_SUPPORT_VCN | 868099d66e4SLeo Liu AMD_PG_SUPPORT_JPEG | 8690377b088SXiaojie Yuan AMD_PG_SUPPORT_VCN_DPG; 87035ef88faStiancyin adev->external_rev_id = adev->rev_id + 20; 8715e71e011SXiaojie Yuan break; 87274b5e509SXiaojie Yuan case CHIP_NAVI12: 873dca009e7SXiaojie Yuan adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 874dca009e7SXiaojie Yuan AMD_CG_SUPPORT_GFX_MGLS | 875dca009e7SXiaojie Yuan AMD_CG_SUPPORT_GFX_CGCG | 876dca009e7SXiaojie Yuan AMD_CG_SUPPORT_GFX_CP_LS | 8775211c37aSXiaojie Yuan AMD_CG_SUPPORT_GFX_RLC_LS | 878fbe0bc57SXiaojie Yuan AMD_CG_SUPPORT_IH_CG | 8795211c37aSXiaojie Yuan AMD_CG_SUPPORT_HDP_MGCG | 880358ab97fSXiaojie Yuan AMD_CG_SUPPORT_HDP_LS | 881358ab97fSXiaojie Yuan AMD_CG_SUPPORT_SDMA_MGCG | 8828b797b3dSXiaojie Yuan AMD_CG_SUPPORT_SDMA_LS | 8838b797b3dSXiaojie Yuan AMD_CG_SUPPORT_MC_MGCG | 884ca51678dSXiaojie Yuan AMD_CG_SUPPORT_MC_LS | 885ca51678dSXiaojie Yuan AMD_CG_SUPPORT_ATHUB_MGCG | 88665872e59SXiaojie Yuan AMD_CG_SUPPORT_ATHUB_LS | 887099d66e4SLeo Liu AMD_CG_SUPPORT_VCN_MGCG | 888099d66e4SLeo Liu AMD_CG_SUPPORT_JPEG_MGCG; 889c1653ea0SXiaojie Yuan adev->pg_flags = AMD_PG_SUPPORT_VCN | 8905ef3b8acSXiaojie Yuan AMD_PG_SUPPORT_VCN_DPG | 891099d66e4SLeo Liu AMD_PG_SUPPORT_JPEG | 8921b0443b1SLikun Gao AMD_PG_SUPPORT_ATHUB; 893df5e984cSTiecheng Zhou /* guest vm gets 0xffffffff when reading RCC_DEV0_EPF0_STRAP0, 894df5e984cSTiecheng Zhou * as a consequence, the rev_id and external_rev_id are wrong. 895df5e984cSTiecheng Zhou * workaround it by hardcoding rev_id to 0 (default value). 896df5e984cSTiecheng Zhou */ 897df5e984cSTiecheng Zhou if (amdgpu_sriov_vf(adev)) 898df5e984cSTiecheng Zhou adev->rev_id = 0; 89974b5e509SXiaojie Yuan adev->external_rev_id = adev->rev_id + 0xa; 90074b5e509SXiaojie Yuan break; 901117910edSLikun Gao case CHIP_SIENNA_CICHLID: 90200194defSLikun Gao adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 90300194defSLikun Gao AMD_CG_SUPPORT_GFX_CGCG | 90400194defSLikun Gao AMD_CG_SUPPORT_GFX_3D_CGCG | 90598f8ea29SLikun Gao AMD_CG_SUPPORT_MC_MGCG | 90600194defSLikun Gao AMD_CG_SUPPORT_VCN_MGCG | 907ca36461fSKenneth Feng AMD_CG_SUPPORT_JPEG_MGCG | 908ca36461fSKenneth Feng AMD_CG_SUPPORT_HDP_MGCG | 9093a32c25aSKenneth Feng AMD_CG_SUPPORT_HDP_LS | 910bcc8367fSKenneth Feng AMD_CG_SUPPORT_IH_CG | 911bcc8367fSKenneth Feng AMD_CG_SUPPORT_MC_LS; 912b467c4f5SLeo Liu adev->pg_flags = AMD_PG_SUPPORT_VCN | 913d00b0fa9SBoyuan Zhang AMD_PG_SUPPORT_VCN_DPG | 914b794616dSKenneth Feng AMD_PG_SUPPORT_JPEG | 9151b0443b1SLikun Gao AMD_PG_SUPPORT_ATHUB | 9161b0443b1SLikun Gao AMD_PG_SUPPORT_MMHUB; 917c45fbe1bSJack Zhang if (amdgpu_sriov_vf(adev)) { 918c45fbe1bSJack Zhang /* hypervisor control CG and PG enablement */ 919c45fbe1bSJack Zhang adev->cg_flags = 0; 920c45fbe1bSJack Zhang adev->pg_flags = 0; 921c45fbe1bSJack Zhang } 922117910edSLikun Gao adev->external_rev_id = adev->rev_id + 0x28; 923117910edSLikun Gao break; 924543aa259SJiansong Chen case CHIP_NAVY_FLOUNDER: 92540582e67SJiansong Chen adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 92640582e67SJiansong Chen AMD_CG_SUPPORT_GFX_CGCG | 92740582e67SJiansong Chen AMD_CG_SUPPORT_GFX_3D_CGCG | 92840582e67SJiansong Chen AMD_CG_SUPPORT_VCN_MGCG | 92992c73756SJiansong Chen AMD_CG_SUPPORT_JPEG_MGCG | 93092c73756SJiansong Chen AMD_CG_SUPPORT_MC_MGCG | 9314759f887SJiansong Chen AMD_CG_SUPPORT_MC_LS | 9324759f887SJiansong Chen AMD_CG_SUPPORT_HDP_MGCG | 93385e7151bSJiansong Chen AMD_CG_SUPPORT_HDP_LS | 93485e7151bSJiansong Chen AMD_CG_SUPPORT_IH_CG; 935c6e9dd0eSBoyuan Zhang adev->pg_flags = AMD_PG_SUPPORT_VCN | 93600740df9SBoyuan Zhang AMD_PG_SUPPORT_VCN_DPG | 93747fc894aSJiansong Chen AMD_PG_SUPPORT_JPEG | 93847fc894aSJiansong Chen AMD_PG_SUPPORT_ATHUB | 93947fc894aSJiansong Chen AMD_PG_SUPPORT_MMHUB; 940543aa259SJiansong Chen adev->external_rev_id = adev->rev_id + 0x32; 941543aa259SJiansong Chen break; 942543aa259SJiansong Chen 943026570e6SHuang Rui case CHIP_VANGOGH: 944c345c89bSHuang Rui adev->apu_flags |= AMD_APU_IS_VANGOGH; 94551a7e938SJinzhou.Su adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 94651a7e938SJinzhou.Su AMD_CG_SUPPORT_GFX_MGLS | 94751a7e938SJinzhou.Su AMD_CG_SUPPORT_GFX_CP_LS | 94851a7e938SJinzhou.Su AMD_CG_SUPPORT_GFX_RLC_LS | 94951a7e938SJinzhou.Su AMD_CG_SUPPORT_GFX_CGCG | 950ac0dc4c5SHuang Rui AMD_CG_SUPPORT_GFX_CGLS | 951ac0dc4c5SHuang Rui AMD_CG_SUPPORT_GFX_3D_CGCG | 95207f9c22fSBoyuan Zhang AMD_CG_SUPPORT_GFX_3D_CGLS | 9530ebce667SJinzhou.Su AMD_CG_SUPPORT_MC_MGCG | 9540ebce667SJinzhou.Su AMD_CG_SUPPORT_MC_LS | 955a3964ec4SJinzhou.Su AMD_CG_SUPPORT_GFX_FGCG | 95607f9c22fSBoyuan Zhang AMD_CG_SUPPORT_VCN_MGCG | 95707f9c22fSBoyuan Zhang AMD_CG_SUPPORT_JPEG_MGCG; 95807f9c22fSBoyuan Zhang adev->pg_flags = AMD_PG_SUPPORT_GFX_PG | 95907f9c22fSBoyuan Zhang AMD_PG_SUPPORT_VCN | 96007f9c22fSBoyuan Zhang AMD_PG_SUPPORT_VCN_DPG | 96107f9c22fSBoyuan Zhang AMD_PG_SUPPORT_JPEG; 962c345c89bSHuang Rui if (adev->apu_flags & AMD_APU_IS_VANGOGH) 963026570e6SHuang Rui adev->external_rev_id = adev->rev_id + 0x01; 964026570e6SHuang Rui break; 965550c58e0STao Zhou case CHIP_DIMGREY_CAVEFISH: 966583e5a5eSTao Zhou adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 967583e5a5eSTao Zhou AMD_CG_SUPPORT_GFX_CGCG | 968583e5a5eSTao Zhou AMD_CG_SUPPORT_GFX_3D_CGCG | 969583e5a5eSTao Zhou AMD_CG_SUPPORT_VCN_MGCG | 970135333a0STao Zhou AMD_CG_SUPPORT_JPEG_MGCG | 971135333a0STao Zhou AMD_CG_SUPPORT_MC_MGCG | 9722c70c332STao Zhou AMD_CG_SUPPORT_MC_LS | 9732c70c332STao Zhou AMD_CG_SUPPORT_HDP_MGCG | 9748e3bfb99STao Zhou AMD_CG_SUPPORT_HDP_LS | 9758e3bfb99STao Zhou AMD_CG_SUPPORT_IH_CG; 976d5bc1579SJames Zhu adev->pg_flags = AMD_PG_SUPPORT_VCN | 977cc6161aaSJames Zhu AMD_PG_SUPPORT_VCN_DPG | 97873da8e86STao Zhou AMD_PG_SUPPORT_JPEG | 97973da8e86STao Zhou AMD_PG_SUPPORT_ATHUB | 98073da8e86STao Zhou AMD_PG_SUPPORT_MMHUB; 981550c58e0STao Zhou adev->external_rev_id = adev->rev_id + 0x3c; 982550c58e0STao Zhou break; 983c6b6a421SHawking Zhang default: 984c6b6a421SHawking Zhang /* FIXME: not supported yet */ 985c6b6a421SHawking Zhang return -EINVAL; 986c6b6a421SHawking Zhang } 987c6b6a421SHawking Zhang 988b05b6903SJiange Zhao if (amdgpu_sriov_vf(adev)) { 989b05b6903SJiange Zhao amdgpu_virt_init_setting(adev); 990b05b6903SJiange Zhao xgpu_nv_mailbox_set_irq_funcs(adev); 991b05b6903SJiange Zhao } 992b05b6903SJiange Zhao 993c6b6a421SHawking Zhang return 0; 994c6b6a421SHawking Zhang } 995c6b6a421SHawking Zhang 996c6b6a421SHawking Zhang static int nv_common_late_init(void *handle) 997c6b6a421SHawking Zhang { 998b05b6903SJiange Zhao struct amdgpu_device *adev = (struct amdgpu_device *)handle; 999b05b6903SJiange Zhao 1000b05b6903SJiange Zhao if (amdgpu_sriov_vf(adev)) 1001b05b6903SJiange Zhao xgpu_nv_mailbox_get_irq(adev); 1002b05b6903SJiange Zhao 1003c6b6a421SHawking Zhang return 0; 1004c6b6a421SHawking Zhang } 1005c6b6a421SHawking Zhang 1006c6b6a421SHawking Zhang static int nv_common_sw_init(void *handle) 1007c6b6a421SHawking Zhang { 1008b05b6903SJiange Zhao struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1009b05b6903SJiange Zhao 1010b05b6903SJiange Zhao if (amdgpu_sriov_vf(adev)) 1011b05b6903SJiange Zhao xgpu_nv_mailbox_add_irq_id(adev); 1012b05b6903SJiange Zhao 1013c6b6a421SHawking Zhang return 0; 1014c6b6a421SHawking Zhang } 1015c6b6a421SHawking Zhang 1016c6b6a421SHawking Zhang static int nv_common_sw_fini(void *handle) 1017c6b6a421SHawking Zhang { 1018c6b6a421SHawking Zhang return 0; 1019c6b6a421SHawking Zhang } 1020c6b6a421SHawking Zhang 1021c6b6a421SHawking Zhang static int nv_common_hw_init(void *handle) 1022c6b6a421SHawking Zhang { 1023c6b6a421SHawking Zhang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1024c6b6a421SHawking Zhang 1025c6b6a421SHawking Zhang /* enable pcie gen2/3 link */ 1026c6b6a421SHawking Zhang nv_pcie_gen3_enable(adev); 1027c6b6a421SHawking Zhang /* enable aspm */ 1028c6b6a421SHawking Zhang nv_program_aspm(adev); 1029c6b6a421SHawking Zhang /* setup nbio registers */ 1030bebc0762SHawking Zhang adev->nbio.funcs->init_registers(adev); 1031923c087aSYong Zhao /* remap HDP registers to a hole in mmio space, 1032923c087aSYong Zhao * for the purpose of expose those registers 1033923c087aSYong Zhao * to process space 1034923c087aSYong Zhao */ 1035923c087aSYong Zhao if (adev->nbio.funcs->remap_hdp_registers) 1036923c087aSYong Zhao adev->nbio.funcs->remap_hdp_registers(adev); 1037c6b6a421SHawking Zhang /* enable the doorbell aperture */ 1038c6b6a421SHawking Zhang nv_enable_doorbell_aperture(adev, true); 1039c6b6a421SHawking Zhang 1040c6b6a421SHawking Zhang return 0; 1041c6b6a421SHawking Zhang } 1042c6b6a421SHawking Zhang 1043c6b6a421SHawking Zhang static int nv_common_hw_fini(void *handle) 1044c6b6a421SHawking Zhang { 1045c6b6a421SHawking Zhang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1046c6b6a421SHawking Zhang 1047c6b6a421SHawking Zhang /* disable the doorbell aperture */ 1048c6b6a421SHawking Zhang nv_enable_doorbell_aperture(adev, false); 1049c6b6a421SHawking Zhang 1050c6b6a421SHawking Zhang return 0; 1051c6b6a421SHawking Zhang } 1052c6b6a421SHawking Zhang 1053c6b6a421SHawking Zhang static int nv_common_suspend(void *handle) 1054c6b6a421SHawking Zhang { 1055c6b6a421SHawking Zhang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1056c6b6a421SHawking Zhang 1057c6b6a421SHawking Zhang return nv_common_hw_fini(adev); 1058c6b6a421SHawking Zhang } 1059c6b6a421SHawking Zhang 1060c6b6a421SHawking Zhang static int nv_common_resume(void *handle) 1061c6b6a421SHawking Zhang { 1062c6b6a421SHawking Zhang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1063c6b6a421SHawking Zhang 1064c6b6a421SHawking Zhang return nv_common_hw_init(adev); 1065c6b6a421SHawking Zhang } 1066c6b6a421SHawking Zhang 1067c6b6a421SHawking Zhang static bool nv_common_is_idle(void *handle) 1068c6b6a421SHawking Zhang { 1069c6b6a421SHawking Zhang return true; 1070c6b6a421SHawking Zhang } 1071c6b6a421SHawking Zhang 1072c6b6a421SHawking Zhang static int nv_common_wait_for_idle(void *handle) 1073c6b6a421SHawking Zhang { 1074c6b6a421SHawking Zhang return 0; 1075c6b6a421SHawking Zhang } 1076c6b6a421SHawking Zhang 1077c6b6a421SHawking Zhang static int nv_common_soft_reset(void *handle) 1078c6b6a421SHawking Zhang { 1079c6b6a421SHawking Zhang return 0; 1080c6b6a421SHawking Zhang } 1081c6b6a421SHawking Zhang 1082c6b6a421SHawking Zhang static void nv_update_hdp_mem_power_gating(struct amdgpu_device *adev, 1083c6b6a421SHawking Zhang bool enable) 1084c6b6a421SHawking Zhang { 1085c6b6a421SHawking Zhang uint32_t hdp_clk_cntl, hdp_clk_cntl1; 1086c6b6a421SHawking Zhang uint32_t hdp_mem_pwr_cntl; 1087c6b6a421SHawking Zhang 1088c6b6a421SHawking Zhang if (!(adev->cg_flags & (AMD_CG_SUPPORT_HDP_LS | 1089c6b6a421SHawking Zhang AMD_CG_SUPPORT_HDP_DS | 1090c6b6a421SHawking Zhang AMD_CG_SUPPORT_HDP_SD))) 1091c6b6a421SHawking Zhang return; 1092c6b6a421SHawking Zhang 1093c6b6a421SHawking Zhang hdp_clk_cntl = hdp_clk_cntl1 = RREG32_SOC15(HDP, 0, mmHDP_CLK_CNTL); 1094c6b6a421SHawking Zhang hdp_mem_pwr_cntl = RREG32_SOC15(HDP, 0, mmHDP_MEM_POWER_CTRL); 1095c6b6a421SHawking Zhang 1096c6b6a421SHawking Zhang /* Before doing clock/power mode switch, 1097c6b6a421SHawking Zhang * forced on IPH & RC clock */ 1098c6b6a421SHawking Zhang hdp_clk_cntl = REG_SET_FIELD(hdp_clk_cntl, HDP_CLK_CNTL, 1099c6b6a421SHawking Zhang IPH_MEM_CLK_SOFT_OVERRIDE, 1); 1100c6b6a421SHawking Zhang hdp_clk_cntl = REG_SET_FIELD(hdp_clk_cntl, HDP_CLK_CNTL, 1101c6b6a421SHawking Zhang RC_MEM_CLK_SOFT_OVERRIDE, 1); 1102c6b6a421SHawking Zhang WREG32_SOC15(HDP, 0, mmHDP_CLK_CNTL, hdp_clk_cntl); 1103c6b6a421SHawking Zhang 1104c6b6a421SHawking Zhang /* HDP 5.0 doesn't support dynamic power mode switch, 1105c6b6a421SHawking Zhang * disable clock and power gating before any changing */ 1106c6b6a421SHawking Zhang hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, 1107c6b6a421SHawking Zhang IPH_MEM_POWER_CTRL_EN, 0); 1108c6b6a421SHawking Zhang hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, 1109c6b6a421SHawking Zhang IPH_MEM_POWER_LS_EN, 0); 1110c6b6a421SHawking Zhang hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, 1111c6b6a421SHawking Zhang IPH_MEM_POWER_DS_EN, 0); 1112c6b6a421SHawking Zhang hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, 1113c6b6a421SHawking Zhang IPH_MEM_POWER_SD_EN, 0); 1114c6b6a421SHawking Zhang hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, 1115c6b6a421SHawking Zhang RC_MEM_POWER_CTRL_EN, 0); 1116c6b6a421SHawking Zhang hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, 1117c6b6a421SHawking Zhang RC_MEM_POWER_LS_EN, 0); 1118c6b6a421SHawking Zhang hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, 1119c6b6a421SHawking Zhang RC_MEM_POWER_DS_EN, 0); 1120c6b6a421SHawking Zhang hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, 1121c6b6a421SHawking Zhang RC_MEM_POWER_SD_EN, 0); 1122c6b6a421SHawking Zhang WREG32_SOC15(HDP, 0, mmHDP_MEM_POWER_CTRL, hdp_mem_pwr_cntl); 1123c6b6a421SHawking Zhang 1124c6b6a421SHawking Zhang /* only one clock gating mode (LS/DS/SD) can be enabled */ 1125c6b6a421SHawking Zhang if (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS) { 1126c6b6a421SHawking Zhang hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, 1127c6b6a421SHawking Zhang HDP_MEM_POWER_CTRL, 1128c6b6a421SHawking Zhang IPH_MEM_POWER_LS_EN, enable); 1129c6b6a421SHawking Zhang hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, 1130c6b6a421SHawking Zhang HDP_MEM_POWER_CTRL, 1131c6b6a421SHawking Zhang RC_MEM_POWER_LS_EN, enable); 1132c6b6a421SHawking Zhang } else if (adev->cg_flags & AMD_CG_SUPPORT_HDP_DS) { 1133c6b6a421SHawking Zhang hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, 1134c6b6a421SHawking Zhang HDP_MEM_POWER_CTRL, 1135c6b6a421SHawking Zhang IPH_MEM_POWER_DS_EN, enable); 1136c6b6a421SHawking Zhang hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, 1137c6b6a421SHawking Zhang HDP_MEM_POWER_CTRL, 1138c6b6a421SHawking Zhang RC_MEM_POWER_DS_EN, enable); 1139c6b6a421SHawking Zhang } else if (adev->cg_flags & AMD_CG_SUPPORT_HDP_SD) { 1140c6b6a421SHawking Zhang hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, 1141c6b6a421SHawking Zhang HDP_MEM_POWER_CTRL, 1142c6b6a421SHawking Zhang IPH_MEM_POWER_SD_EN, enable); 1143c6b6a421SHawking Zhang /* RC should not use shut down mode, fallback to ds */ 1144c6b6a421SHawking Zhang hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, 1145c6b6a421SHawking Zhang HDP_MEM_POWER_CTRL, 1146c6b6a421SHawking Zhang RC_MEM_POWER_DS_EN, enable); 1147c6b6a421SHawking Zhang } 1148c6b6a421SHawking Zhang 114991c6adf8SKenneth Feng /* confirmed that IPH_MEM_POWER_CTRL_EN and RC_MEM_POWER_CTRL_EN have to 115091c6adf8SKenneth Feng * be set for SRAM LS/DS/SD */ 115191c6adf8SKenneth Feng if (adev->cg_flags & (AMD_CG_SUPPORT_HDP_LS | AMD_CG_SUPPORT_HDP_DS | 115291c6adf8SKenneth Feng AMD_CG_SUPPORT_HDP_SD)) { 115391c6adf8SKenneth Feng hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, 115491c6adf8SKenneth Feng IPH_MEM_POWER_CTRL_EN, 1); 115591c6adf8SKenneth Feng hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, 115691c6adf8SKenneth Feng RC_MEM_POWER_CTRL_EN, 1); 115791c6adf8SKenneth Feng } 115891c6adf8SKenneth Feng 1159c6b6a421SHawking Zhang WREG32_SOC15(HDP, 0, mmHDP_MEM_POWER_CTRL, hdp_mem_pwr_cntl); 1160c6b6a421SHawking Zhang 1161c6b6a421SHawking Zhang /* restore IPH & RC clock override after clock/power mode changing */ 1162c6b6a421SHawking Zhang WREG32_SOC15(HDP, 0, mmHDP_CLK_CNTL, hdp_clk_cntl1); 1163c6b6a421SHawking Zhang } 1164c6b6a421SHawking Zhang 1165c6b6a421SHawking Zhang static void nv_update_hdp_clock_gating(struct amdgpu_device *adev, 1166c6b6a421SHawking Zhang bool enable) 1167c6b6a421SHawking Zhang { 1168c6b6a421SHawking Zhang uint32_t hdp_clk_cntl; 1169c6b6a421SHawking Zhang 1170c6b6a421SHawking Zhang if (!(adev->cg_flags & AMD_CG_SUPPORT_HDP_MGCG)) 1171c6b6a421SHawking Zhang return; 1172c6b6a421SHawking Zhang 1173c6b6a421SHawking Zhang hdp_clk_cntl = RREG32_SOC15(HDP, 0, mmHDP_CLK_CNTL); 1174c6b6a421SHawking Zhang 1175c6b6a421SHawking Zhang if (enable) { 1176c6b6a421SHawking Zhang hdp_clk_cntl &= 1177c6b6a421SHawking Zhang ~(uint32_t) 1178c6b6a421SHawking Zhang (HDP_CLK_CNTL__IPH_MEM_CLK_SOFT_OVERRIDE_MASK | 1179c6b6a421SHawking Zhang HDP_CLK_CNTL__RC_MEM_CLK_SOFT_OVERRIDE_MASK | 1180c6b6a421SHawking Zhang HDP_CLK_CNTL__DBUS_CLK_SOFT_OVERRIDE_MASK | 1181c6b6a421SHawking Zhang HDP_CLK_CNTL__DYN_CLK_SOFT_OVERRIDE_MASK | 1182c6b6a421SHawking Zhang HDP_CLK_CNTL__XDP_REG_CLK_SOFT_OVERRIDE_MASK | 1183c6b6a421SHawking Zhang HDP_CLK_CNTL__HDP_REG_CLK_SOFT_OVERRIDE_MASK); 1184c6b6a421SHawking Zhang } else { 1185c6b6a421SHawking Zhang hdp_clk_cntl |= HDP_CLK_CNTL__IPH_MEM_CLK_SOFT_OVERRIDE_MASK | 1186c6b6a421SHawking Zhang HDP_CLK_CNTL__RC_MEM_CLK_SOFT_OVERRIDE_MASK | 1187c6b6a421SHawking Zhang HDP_CLK_CNTL__DBUS_CLK_SOFT_OVERRIDE_MASK | 1188c6b6a421SHawking Zhang HDP_CLK_CNTL__DYN_CLK_SOFT_OVERRIDE_MASK | 1189c6b6a421SHawking Zhang HDP_CLK_CNTL__XDP_REG_CLK_SOFT_OVERRIDE_MASK | 1190c6b6a421SHawking Zhang HDP_CLK_CNTL__HDP_REG_CLK_SOFT_OVERRIDE_MASK; 1191c6b6a421SHawking Zhang } 1192c6b6a421SHawking Zhang 1193c6b6a421SHawking Zhang WREG32_SOC15(HDP, 0, mmHDP_CLK_CNTL, hdp_clk_cntl); 1194c6b6a421SHawking Zhang } 1195c6b6a421SHawking Zhang 1196c6b6a421SHawking Zhang static int nv_common_set_clockgating_state(void *handle, 1197c6b6a421SHawking Zhang enum amd_clockgating_state state) 1198c6b6a421SHawking Zhang { 1199c6b6a421SHawking Zhang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1200c6b6a421SHawking Zhang 1201c6b6a421SHawking Zhang if (amdgpu_sriov_vf(adev)) 1202c6b6a421SHawking Zhang return 0; 1203c6b6a421SHawking Zhang 1204c6b6a421SHawking Zhang switch (adev->asic_type) { 1205c6b6a421SHawking Zhang case CHIP_NAVI10: 12065e71e011SXiaojie Yuan case CHIP_NAVI14: 12077e17e58bSXiaojie Yuan case CHIP_NAVI12: 1208117910edSLikun Gao case CHIP_SIENNA_CICHLID: 1209543aa259SJiansong Chen case CHIP_NAVY_FLOUNDER: 1210550c58e0STao Zhou case CHIP_DIMGREY_CAVEFISH: 1211bebc0762SHawking Zhang adev->nbio.funcs->update_medium_grain_clock_gating(adev, 1212a9d4fe2fSNirmoy Das state == AMD_CG_STATE_GATE); 1213bebc0762SHawking Zhang adev->nbio.funcs->update_medium_grain_light_sleep(adev, 1214a9d4fe2fSNirmoy Das state == AMD_CG_STATE_GATE); 1215c6b6a421SHawking Zhang nv_update_hdp_mem_power_gating(adev, 1216a9d4fe2fSNirmoy Das state == AMD_CG_STATE_GATE); 1217c6b6a421SHawking Zhang nv_update_hdp_clock_gating(adev, 1218a9d4fe2fSNirmoy Das state == AMD_CG_STATE_GATE); 1219c6b6a421SHawking Zhang break; 1220c6b6a421SHawking Zhang default: 1221c6b6a421SHawking Zhang break; 1222c6b6a421SHawking Zhang } 1223c6b6a421SHawking Zhang return 0; 1224c6b6a421SHawking Zhang } 1225c6b6a421SHawking Zhang 1226c6b6a421SHawking Zhang static int nv_common_set_powergating_state(void *handle, 1227c6b6a421SHawking Zhang enum amd_powergating_state state) 1228c6b6a421SHawking Zhang { 1229c6b6a421SHawking Zhang /* TODO */ 1230c6b6a421SHawking Zhang return 0; 1231c6b6a421SHawking Zhang } 1232c6b6a421SHawking Zhang 1233c6b6a421SHawking Zhang static void nv_common_get_clockgating_state(void *handle, u32 *flags) 1234c6b6a421SHawking Zhang { 1235c6b6a421SHawking Zhang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1236c6b6a421SHawking Zhang uint32_t tmp; 1237c6b6a421SHawking Zhang 1238c6b6a421SHawking Zhang if (amdgpu_sriov_vf(adev)) 1239c6b6a421SHawking Zhang *flags = 0; 1240c6b6a421SHawking Zhang 1241bebc0762SHawking Zhang adev->nbio.funcs->get_clockgating_state(adev, flags); 1242c6b6a421SHawking Zhang 1243c6b6a421SHawking Zhang /* AMD_CG_SUPPORT_HDP_MGCG */ 1244c6b6a421SHawking Zhang tmp = RREG32_SOC15(HDP, 0, mmHDP_CLK_CNTL); 1245c6b6a421SHawking Zhang if (!(tmp & (HDP_CLK_CNTL__IPH_MEM_CLK_SOFT_OVERRIDE_MASK | 1246c6b6a421SHawking Zhang HDP_CLK_CNTL__RC_MEM_CLK_SOFT_OVERRIDE_MASK | 1247c6b6a421SHawking Zhang HDP_CLK_CNTL__DBUS_CLK_SOFT_OVERRIDE_MASK | 1248c6b6a421SHawking Zhang HDP_CLK_CNTL__DYN_CLK_SOFT_OVERRIDE_MASK | 1249c6b6a421SHawking Zhang HDP_CLK_CNTL__XDP_REG_CLK_SOFT_OVERRIDE_MASK | 1250c6b6a421SHawking Zhang HDP_CLK_CNTL__HDP_REG_CLK_SOFT_OVERRIDE_MASK))) 1251c6b6a421SHawking Zhang *flags |= AMD_CG_SUPPORT_HDP_MGCG; 1252c6b6a421SHawking Zhang 1253c6b6a421SHawking Zhang /* AMD_CG_SUPPORT_HDP_LS/DS/SD */ 1254c6b6a421SHawking Zhang tmp = RREG32_SOC15(HDP, 0, mmHDP_MEM_POWER_CTRL); 1255c6b6a421SHawking Zhang if (tmp & HDP_MEM_POWER_CTRL__IPH_MEM_POWER_LS_EN_MASK) 1256c6b6a421SHawking Zhang *flags |= AMD_CG_SUPPORT_HDP_LS; 1257c6b6a421SHawking Zhang else if (tmp & HDP_MEM_POWER_CTRL__IPH_MEM_POWER_DS_EN_MASK) 1258c6b6a421SHawking Zhang *flags |= AMD_CG_SUPPORT_HDP_DS; 1259c6b6a421SHawking Zhang else if (tmp & HDP_MEM_POWER_CTRL__IPH_MEM_POWER_SD_EN_MASK) 1260c6b6a421SHawking Zhang *flags |= AMD_CG_SUPPORT_HDP_SD; 1261c6b6a421SHawking Zhang 1262c6b6a421SHawking Zhang return; 1263c6b6a421SHawking Zhang } 1264c6b6a421SHawking Zhang 1265c6b6a421SHawking Zhang static const struct amd_ip_funcs nv_common_ip_funcs = { 1266c6b6a421SHawking Zhang .name = "nv_common", 1267c6b6a421SHawking Zhang .early_init = nv_common_early_init, 1268c6b6a421SHawking Zhang .late_init = nv_common_late_init, 1269c6b6a421SHawking Zhang .sw_init = nv_common_sw_init, 1270c6b6a421SHawking Zhang .sw_fini = nv_common_sw_fini, 1271c6b6a421SHawking Zhang .hw_init = nv_common_hw_init, 1272c6b6a421SHawking Zhang .hw_fini = nv_common_hw_fini, 1273c6b6a421SHawking Zhang .suspend = nv_common_suspend, 1274c6b6a421SHawking Zhang .resume = nv_common_resume, 1275c6b6a421SHawking Zhang .is_idle = nv_common_is_idle, 1276c6b6a421SHawking Zhang .wait_for_idle = nv_common_wait_for_idle, 1277c6b6a421SHawking Zhang .soft_reset = nv_common_soft_reset, 1278c6b6a421SHawking Zhang .set_clockgating_state = nv_common_set_clockgating_state, 1279c6b6a421SHawking Zhang .set_powergating_state = nv_common_set_powergating_state, 1280c6b6a421SHawking Zhang .get_clockgating_state = nv_common_get_clockgating_state, 1281c6b6a421SHawking Zhang }; 1282