1c6b6a421SHawking Zhang /* 2c6b6a421SHawking Zhang * Copyright 2019 Advanced Micro Devices, Inc. 3c6b6a421SHawking Zhang * 4c6b6a421SHawking Zhang * Permission is hereby granted, free of charge, to any person obtaining a 5c6b6a421SHawking Zhang * copy of this software and associated documentation files (the "Software"), 6c6b6a421SHawking Zhang * to deal in the Software without restriction, including without limitation 7c6b6a421SHawking Zhang * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8c6b6a421SHawking Zhang * and/or sell copies of the Software, and to permit persons to whom the 9c6b6a421SHawking Zhang * Software is furnished to do so, subject to the following conditions: 10c6b6a421SHawking Zhang * 11c6b6a421SHawking Zhang * The above copyright notice and this permission notice shall be included in 12c6b6a421SHawking Zhang * all copies or substantial portions of the Software. 13c6b6a421SHawking Zhang * 14c6b6a421SHawking Zhang * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15c6b6a421SHawking Zhang * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16c6b6a421SHawking Zhang * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17c6b6a421SHawking Zhang * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18c6b6a421SHawking Zhang * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19c6b6a421SHawking Zhang * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20c6b6a421SHawking Zhang * OTHER DEALINGS IN THE SOFTWARE. 21c6b6a421SHawking Zhang * 22c6b6a421SHawking Zhang */ 23c6b6a421SHawking Zhang #include <linux/firmware.h> 24c6b6a421SHawking Zhang #include <linux/slab.h> 25c6b6a421SHawking Zhang #include <linux/module.h> 26e9eea902SAlex Deucher #include <linux/pci.h> 27e9eea902SAlex Deucher 28c6b6a421SHawking Zhang #include "amdgpu.h" 29c6b6a421SHawking Zhang #include "amdgpu_atombios.h" 30c6b6a421SHawking Zhang #include "amdgpu_ih.h" 31c6b6a421SHawking Zhang #include "amdgpu_uvd.h" 32c6b6a421SHawking Zhang #include "amdgpu_vce.h" 33c6b6a421SHawking Zhang #include "amdgpu_ucode.h" 34c6b6a421SHawking Zhang #include "amdgpu_psp.h" 35767acabdSKevin Wang #include "amdgpu_smu.h" 36c6b6a421SHawking Zhang #include "atom.h" 37c6b6a421SHawking Zhang #include "amd_pcie.h" 38c6b6a421SHawking Zhang 39c6b6a421SHawking Zhang #include "gc/gc_10_1_0_offset.h" 40c6b6a421SHawking Zhang #include "gc/gc_10_1_0_sh_mask.h" 41c6b6a421SHawking Zhang #include "hdp/hdp_5_0_0_offset.h" 42c6b6a421SHawking Zhang #include "hdp/hdp_5_0_0_sh_mask.h" 4329bc37b4SAlex Deucher #include "smuio/smuio_11_0_0_offset.h" 443967ae6dSAlex Deucher #include "mp/mp_11_0_offset.h" 45c6b6a421SHawking Zhang 46c6b6a421SHawking Zhang #include "soc15.h" 47c6b6a421SHawking Zhang #include "soc15_common.h" 48c6b6a421SHawking Zhang #include "gmc_v10_0.h" 49c6b6a421SHawking Zhang #include "gfxhub_v2_0.h" 50c6b6a421SHawking Zhang #include "mmhub_v2_0.h" 51bebc0762SHawking Zhang #include "nbio_v2_3.h" 52c6b6a421SHawking Zhang #include "nv.h" 53c6b6a421SHawking Zhang #include "navi10_ih.h" 54c6b6a421SHawking Zhang #include "gfx_v10_0.h" 55c6b6a421SHawking Zhang #include "sdma_v5_0.h" 56157e72e8SLikun Gao #include "sdma_v5_2.h" 57c6b6a421SHawking Zhang #include "vcn_v2_0.h" 585be45a26SLeo Liu #include "jpeg_v2_0.h" 59b8f10585SLeo Liu #include "vcn_v3_0.h" 604d72dd12SLeo Liu #include "jpeg_v3_0.h" 61c6b6a421SHawking Zhang #include "dce_virtual.h" 62c6b6a421SHawking Zhang #include "mes_v10_1.h" 63b05b6903SJiange Zhao #include "mxgpu_nv.h" 64c6b6a421SHawking Zhang 65c6b6a421SHawking Zhang static const struct amd_ip_funcs nv_common_ip_funcs; 66c6b6a421SHawking Zhang 67c6b6a421SHawking Zhang /* 68c6b6a421SHawking Zhang * Indirect registers accessor 69c6b6a421SHawking Zhang */ 70c6b6a421SHawking Zhang static u32 nv_pcie_rreg(struct amdgpu_device *adev, u32 reg) 71c6b6a421SHawking Zhang { 72c6b6a421SHawking Zhang unsigned long flags, address, data; 73c6b6a421SHawking Zhang u32 r; 74bebc0762SHawking Zhang address = adev->nbio.funcs->get_pcie_index_offset(adev); 75bebc0762SHawking Zhang data = adev->nbio.funcs->get_pcie_data_offset(adev); 76c6b6a421SHawking Zhang 77c6b6a421SHawking Zhang spin_lock_irqsave(&adev->pcie_idx_lock, flags); 78c6b6a421SHawking Zhang WREG32(address, reg); 79c6b6a421SHawking Zhang (void)RREG32(address); 80c6b6a421SHawking Zhang r = RREG32(data); 81c6b6a421SHawking Zhang spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); 82c6b6a421SHawking Zhang return r; 83c6b6a421SHawking Zhang } 84c6b6a421SHawking Zhang 85c6b6a421SHawking Zhang static void nv_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v) 86c6b6a421SHawking Zhang { 87c6b6a421SHawking Zhang unsigned long flags, address, data; 88c6b6a421SHawking Zhang 89bebc0762SHawking Zhang address = adev->nbio.funcs->get_pcie_index_offset(adev); 90bebc0762SHawking Zhang data = adev->nbio.funcs->get_pcie_data_offset(adev); 91c6b6a421SHawking Zhang 92c6b6a421SHawking Zhang spin_lock_irqsave(&adev->pcie_idx_lock, flags); 93c6b6a421SHawking Zhang WREG32(address, reg); 94c6b6a421SHawking Zhang (void)RREG32(address); 95c6b6a421SHawking Zhang WREG32(data, v); 96c6b6a421SHawking Zhang (void)RREG32(data); 97c6b6a421SHawking Zhang spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); 98c6b6a421SHawking Zhang } 99c6b6a421SHawking Zhang 1004922f1bcSJohn Clements static u64 nv_pcie_rreg64(struct amdgpu_device *adev, u32 reg) 1014922f1bcSJohn Clements { 1024922f1bcSJohn Clements unsigned long flags, address, data; 1034922f1bcSJohn Clements u64 r; 1044922f1bcSJohn Clements address = adev->nbio.funcs->get_pcie_index_offset(adev); 1054922f1bcSJohn Clements data = adev->nbio.funcs->get_pcie_data_offset(adev); 1064922f1bcSJohn Clements 1074922f1bcSJohn Clements spin_lock_irqsave(&adev->pcie_idx_lock, flags); 1084922f1bcSJohn Clements /* read low 32 bit */ 1094922f1bcSJohn Clements WREG32(address, reg); 1104922f1bcSJohn Clements (void)RREG32(address); 1114922f1bcSJohn Clements r = RREG32(data); 1124922f1bcSJohn Clements 1134922f1bcSJohn Clements /* read high 32 bit*/ 1144922f1bcSJohn Clements WREG32(address, reg + 4); 1154922f1bcSJohn Clements (void)RREG32(address); 1164922f1bcSJohn Clements r |= ((u64)RREG32(data) << 32); 1174922f1bcSJohn Clements spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); 1184922f1bcSJohn Clements return r; 1194922f1bcSJohn Clements } 1204922f1bcSJohn Clements 1214922f1bcSJohn Clements static void nv_pcie_wreg64(struct amdgpu_device *adev, u32 reg, u64 v) 1224922f1bcSJohn Clements { 1234922f1bcSJohn Clements unsigned long flags, address, data; 1244922f1bcSJohn Clements 1254922f1bcSJohn Clements address = adev->nbio.funcs->get_pcie_index_offset(adev); 1264922f1bcSJohn Clements data = adev->nbio.funcs->get_pcie_data_offset(adev); 1274922f1bcSJohn Clements 1284922f1bcSJohn Clements spin_lock_irqsave(&adev->pcie_idx_lock, flags); 1294922f1bcSJohn Clements /* write low 32 bit */ 1304922f1bcSJohn Clements WREG32(address, reg); 1314922f1bcSJohn Clements (void)RREG32(address); 1324922f1bcSJohn Clements WREG32(data, (u32)(v & 0xffffffffULL)); 1334922f1bcSJohn Clements (void)RREG32(data); 1344922f1bcSJohn Clements 1354922f1bcSJohn Clements /* write high 32 bit */ 1364922f1bcSJohn Clements WREG32(address, reg + 4); 1374922f1bcSJohn Clements (void)RREG32(address); 1384922f1bcSJohn Clements WREG32(data, (u32)(v >> 32)); 1394922f1bcSJohn Clements (void)RREG32(data); 1404922f1bcSJohn Clements spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); 1414922f1bcSJohn Clements } 1424922f1bcSJohn Clements 143c6b6a421SHawking Zhang static u32 nv_didt_rreg(struct amdgpu_device *adev, u32 reg) 144c6b6a421SHawking Zhang { 145c6b6a421SHawking Zhang unsigned long flags, address, data; 146c6b6a421SHawking Zhang u32 r; 147c6b6a421SHawking Zhang 148c6b6a421SHawking Zhang address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX); 149c6b6a421SHawking Zhang data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA); 150c6b6a421SHawking Zhang 151c6b6a421SHawking Zhang spin_lock_irqsave(&adev->didt_idx_lock, flags); 152c6b6a421SHawking Zhang WREG32(address, (reg)); 153c6b6a421SHawking Zhang r = RREG32(data); 154c6b6a421SHawking Zhang spin_unlock_irqrestore(&adev->didt_idx_lock, flags); 155c6b6a421SHawking Zhang return r; 156c6b6a421SHawking Zhang } 157c6b6a421SHawking Zhang 158c6b6a421SHawking Zhang static void nv_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v) 159c6b6a421SHawking Zhang { 160c6b6a421SHawking Zhang unsigned long flags, address, data; 161c6b6a421SHawking Zhang 162c6b6a421SHawking Zhang address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX); 163c6b6a421SHawking Zhang data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA); 164c6b6a421SHawking Zhang 165c6b6a421SHawking Zhang spin_lock_irqsave(&adev->didt_idx_lock, flags); 166c6b6a421SHawking Zhang WREG32(address, (reg)); 167c6b6a421SHawking Zhang WREG32(data, (v)); 168c6b6a421SHawking Zhang spin_unlock_irqrestore(&adev->didt_idx_lock, flags); 169c6b6a421SHawking Zhang } 170c6b6a421SHawking Zhang 171c6b6a421SHawking Zhang static u32 nv_get_config_memsize(struct amdgpu_device *adev) 172c6b6a421SHawking Zhang { 173bebc0762SHawking Zhang return adev->nbio.funcs->get_memsize(adev); 174c6b6a421SHawking Zhang } 175c6b6a421SHawking Zhang 176c6b6a421SHawking Zhang static u32 nv_get_xclk(struct amdgpu_device *adev) 177c6b6a421SHawking Zhang { 178462a70d8STao Zhou return adev->clock.spll.reference_freq; 179c6b6a421SHawking Zhang } 180c6b6a421SHawking Zhang 181c6b6a421SHawking Zhang 182c6b6a421SHawking Zhang void nv_grbm_select(struct amdgpu_device *adev, 183c6b6a421SHawking Zhang u32 me, u32 pipe, u32 queue, u32 vmid) 184c6b6a421SHawking Zhang { 185c6b6a421SHawking Zhang u32 grbm_gfx_cntl = 0; 186c6b6a421SHawking Zhang grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, PIPEID, pipe); 187c6b6a421SHawking Zhang grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, MEID, me); 188c6b6a421SHawking Zhang grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, VMID, vmid); 189c6b6a421SHawking Zhang grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, QUEUEID, queue); 190c6b6a421SHawking Zhang 191c6b6a421SHawking Zhang WREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_CNTL), grbm_gfx_cntl); 192c6b6a421SHawking Zhang } 193c6b6a421SHawking Zhang 194c6b6a421SHawking Zhang static void nv_vga_set_state(struct amdgpu_device *adev, bool state) 195c6b6a421SHawking Zhang { 196c6b6a421SHawking Zhang /* todo */ 197c6b6a421SHawking Zhang } 198c6b6a421SHawking Zhang 199c6b6a421SHawking Zhang static bool nv_read_disabled_bios(struct amdgpu_device *adev) 200c6b6a421SHawking Zhang { 201c6b6a421SHawking Zhang /* todo */ 202c6b6a421SHawking Zhang return false; 203c6b6a421SHawking Zhang } 204c6b6a421SHawking Zhang 205c6b6a421SHawking Zhang static bool nv_read_bios_from_rom(struct amdgpu_device *adev, 206c6b6a421SHawking Zhang u8 *bios, u32 length_bytes) 207c6b6a421SHawking Zhang { 20829bc37b4SAlex Deucher u32 *dw_ptr; 20929bc37b4SAlex Deucher u32 i, length_dw; 21029bc37b4SAlex Deucher 21129bc37b4SAlex Deucher if (bios == NULL) 212c6b6a421SHawking Zhang return false; 21329bc37b4SAlex Deucher if (length_bytes == 0) 21429bc37b4SAlex Deucher return false; 21529bc37b4SAlex Deucher /* APU vbios image is part of sbios image */ 21629bc37b4SAlex Deucher if (adev->flags & AMD_IS_APU) 21729bc37b4SAlex Deucher return false; 21829bc37b4SAlex Deucher 21929bc37b4SAlex Deucher dw_ptr = (u32 *)bios; 22029bc37b4SAlex Deucher length_dw = ALIGN(length_bytes, 4) / 4; 22129bc37b4SAlex Deucher 22229bc37b4SAlex Deucher /* set rom index to 0 */ 22329bc37b4SAlex Deucher WREG32(SOC15_REG_OFFSET(SMUIO, 0, mmROM_INDEX), 0); 22429bc37b4SAlex Deucher /* read out the rom data */ 22529bc37b4SAlex Deucher for (i = 0; i < length_dw; i++) 22629bc37b4SAlex Deucher dw_ptr[i] = RREG32(SOC15_REG_OFFSET(SMUIO, 0, mmROM_DATA)); 22729bc37b4SAlex Deucher 22829bc37b4SAlex Deucher return true; 229c6b6a421SHawking Zhang } 230c6b6a421SHawking Zhang 231c6b6a421SHawking Zhang static struct soc15_allowed_register_entry nv_allowed_read_registers[] = { 232c6b6a421SHawking Zhang { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS)}, 233c6b6a421SHawking Zhang { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS2)}, 234c6b6a421SHawking Zhang { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE0)}, 235c6b6a421SHawking Zhang { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE1)}, 236c6b6a421SHawking Zhang { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE2)}, 237c6b6a421SHawking Zhang { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE3)}, 238c6b6a421SHawking Zhang { SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_STATUS_REG)}, 239c6b6a421SHawking Zhang { SOC15_REG_ENTRY(SDMA1, 0, mmSDMA1_STATUS_REG)}, 240c6b6a421SHawking Zhang { SOC15_REG_ENTRY(GC, 0, mmCP_STAT)}, 241c6b6a421SHawking Zhang { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT1)}, 242c6b6a421SHawking Zhang { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT2)}, 243c6b6a421SHawking Zhang { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT3)}, 244c6b6a421SHawking Zhang { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_BUSY_STAT)}, 245c6b6a421SHawking Zhang { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STALLED_STAT1)}, 246c6b6a421SHawking Zhang { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STATUS)}, 247664fe85aSMarek Olšák { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_BUSY_STAT)}, 248c6b6a421SHawking Zhang { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STALLED_STAT1)}, 249c6b6a421SHawking Zhang { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STATUS)}, 250c6b6a421SHawking Zhang { SOC15_REG_ENTRY(GC, 0, mmGB_ADDR_CONFIG)}, 251c6b6a421SHawking Zhang }; 252c6b6a421SHawking Zhang 253c6b6a421SHawking Zhang static uint32_t nv_read_indexed_register(struct amdgpu_device *adev, u32 se_num, 254c6b6a421SHawking Zhang u32 sh_num, u32 reg_offset) 255c6b6a421SHawking Zhang { 256c6b6a421SHawking Zhang uint32_t val; 257c6b6a421SHawking Zhang 258c6b6a421SHawking Zhang mutex_lock(&adev->grbm_idx_mutex); 259c6b6a421SHawking Zhang if (se_num != 0xffffffff || sh_num != 0xffffffff) 260c6b6a421SHawking Zhang amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff); 261c6b6a421SHawking Zhang 262c6b6a421SHawking Zhang val = RREG32(reg_offset); 263c6b6a421SHawking Zhang 264c6b6a421SHawking Zhang if (se_num != 0xffffffff || sh_num != 0xffffffff) 265c6b6a421SHawking Zhang amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 266c6b6a421SHawking Zhang mutex_unlock(&adev->grbm_idx_mutex); 267c6b6a421SHawking Zhang return val; 268c6b6a421SHawking Zhang } 269c6b6a421SHawking Zhang 270c6b6a421SHawking Zhang static uint32_t nv_get_register_value(struct amdgpu_device *adev, 271c6b6a421SHawking Zhang bool indexed, u32 se_num, 272c6b6a421SHawking Zhang u32 sh_num, u32 reg_offset) 273c6b6a421SHawking Zhang { 274c6b6a421SHawking Zhang if (indexed) { 275c6b6a421SHawking Zhang return nv_read_indexed_register(adev, se_num, sh_num, reg_offset); 276c6b6a421SHawking Zhang } else { 277c6b6a421SHawking Zhang if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG)) 278c6b6a421SHawking Zhang return adev->gfx.config.gb_addr_config; 279c6b6a421SHawking Zhang return RREG32(reg_offset); 280c6b6a421SHawking Zhang } 281c6b6a421SHawking Zhang } 282c6b6a421SHawking Zhang 283c6b6a421SHawking Zhang static int nv_read_register(struct amdgpu_device *adev, u32 se_num, 284c6b6a421SHawking Zhang u32 sh_num, u32 reg_offset, u32 *value) 285c6b6a421SHawking Zhang { 286c6b6a421SHawking Zhang uint32_t i; 287c6b6a421SHawking Zhang struct soc15_allowed_register_entry *en; 288c6b6a421SHawking Zhang 289c6b6a421SHawking Zhang *value = 0; 290c6b6a421SHawking Zhang for (i = 0; i < ARRAY_SIZE(nv_allowed_read_registers); i++) { 291c6b6a421SHawking Zhang en = &nv_allowed_read_registers[i]; 292c6b6a421SHawking Zhang if (reg_offset != 293c6b6a421SHawking Zhang (adev->reg_offset[en->hwip][en->inst][en->seg] + en->reg_offset)) 294c6b6a421SHawking Zhang continue; 295c6b6a421SHawking Zhang 296c6b6a421SHawking Zhang *value = nv_get_register_value(adev, 297c6b6a421SHawking Zhang nv_allowed_read_registers[i].grbm_indexed, 298c6b6a421SHawking Zhang se_num, sh_num, reg_offset); 299c6b6a421SHawking Zhang return 0; 300c6b6a421SHawking Zhang } 301c6b6a421SHawking Zhang return -EINVAL; 302c6b6a421SHawking Zhang } 303c6b6a421SHawking Zhang 3043e2bb60aSKevin Wang static int nv_asic_mode1_reset(struct amdgpu_device *adev) 3053e2bb60aSKevin Wang { 3063e2bb60aSKevin Wang u32 i; 3073e2bb60aSKevin Wang int ret = 0; 3083e2bb60aSKevin Wang 3093e2bb60aSKevin Wang amdgpu_atombios_scratch_regs_engine_hung(adev, true); 3103e2bb60aSKevin Wang 3113e2bb60aSKevin Wang /* disable BM */ 3123e2bb60aSKevin Wang pci_clear_master(adev->pdev); 3133e2bb60aSKevin Wang 314c1dd4aa6SAndrey Grodzovsky amdgpu_device_cache_pci_state(adev->pdev); 3153e2bb60aSKevin Wang 316311531f0SWenhui Sheng if (amdgpu_dpm_is_mode1_reset_supported(adev)) { 317311531f0SWenhui Sheng dev_info(adev->dev, "GPU smu mode1 reset\n"); 318311531f0SWenhui Sheng ret = amdgpu_dpm_mode1_reset(adev); 319311531f0SWenhui Sheng } else { 320311531f0SWenhui Sheng dev_info(adev->dev, "GPU psp mode1 reset\n"); 3213e2bb60aSKevin Wang ret = psp_gpu_reset(adev); 322311531f0SWenhui Sheng } 323311531f0SWenhui Sheng 3243e2bb60aSKevin Wang if (ret) 3253e2bb60aSKevin Wang dev_err(adev->dev, "GPU mode1 reset failed\n"); 326c1dd4aa6SAndrey Grodzovsky amdgpu_device_load_pci_state(adev->pdev); 3273e2bb60aSKevin Wang 3283e2bb60aSKevin Wang /* wait for asic to come out of reset */ 3293e2bb60aSKevin Wang for (i = 0; i < adev->usec_timeout; i++) { 330bebc0762SHawking Zhang u32 memsize = adev->nbio.funcs->get_memsize(adev); 3313e2bb60aSKevin Wang 3323e2bb60aSKevin Wang if (memsize != 0xffffffff) 3333e2bb60aSKevin Wang break; 3343e2bb60aSKevin Wang udelay(1); 3353e2bb60aSKevin Wang } 3363e2bb60aSKevin Wang 3373e2bb60aSKevin Wang amdgpu_atombios_scratch_regs_engine_hung(adev, false); 3383e2bb60aSKevin Wang 3393e2bb60aSKevin Wang return ret; 3403e2bb60aSKevin Wang } 3412ddc6c3eSAlex Deucher 342ac742616SAlex Deucher static bool nv_asic_supports_baco(struct amdgpu_device *adev) 343ac742616SAlex Deucher { 344ac742616SAlex Deucher struct smu_context *smu = &adev->smu; 345ac742616SAlex Deucher 346ac742616SAlex Deucher if (smu_baco_is_support(smu)) 347ac742616SAlex Deucher return true; 348ac742616SAlex Deucher else 349ac742616SAlex Deucher return false; 350ac742616SAlex Deucher } 351ac742616SAlex Deucher 3522ddc6c3eSAlex Deucher static enum amd_reset_method 3532ddc6c3eSAlex Deucher nv_asic_reset_method(struct amdgpu_device *adev) 3542ddc6c3eSAlex Deucher { 3552ddc6c3eSAlex Deucher struct smu_context *smu = &adev->smu; 3562ddc6c3eSAlex Deucher 357273da6ffSWenhui Sheng if (amdgpu_reset_method == AMD_RESET_METHOD_MODE1 || 358273da6ffSWenhui Sheng amdgpu_reset_method == AMD_RESET_METHOD_BACO) 359273da6ffSWenhui Sheng return amdgpu_reset_method; 360273da6ffSWenhui Sheng 361273da6ffSWenhui Sheng if (amdgpu_reset_method != -1) 362273da6ffSWenhui Sheng dev_warn(adev->dev, "Specified reset method:%d isn't supported, using AUTO instead.\n", 363273da6ffSWenhui Sheng amdgpu_reset_method); 364273da6ffSWenhui Sheng 365ca6fd7a6SLikun Gao switch (adev->asic_type) { 366ca6fd7a6SLikun Gao case CHIP_SIENNA_CICHLID: 36722dd44f4SJiansong Chen case CHIP_NAVY_FLOUNDER: 368ca6fd7a6SLikun Gao return AMD_RESET_METHOD_MODE1; 369ca6fd7a6SLikun Gao default: 370311531f0SWenhui Sheng if (smu_baco_is_support(smu)) 3712ddc6c3eSAlex Deucher return AMD_RESET_METHOD_BACO; 3722ddc6c3eSAlex Deucher else 3732ddc6c3eSAlex Deucher return AMD_RESET_METHOD_MODE1; 3742ddc6c3eSAlex Deucher } 375ca6fd7a6SLikun Gao } 3762ddc6c3eSAlex Deucher 377c6b6a421SHawking Zhang static int nv_asic_reset(struct amdgpu_device *adev) 378c6b6a421SHawking Zhang { 379767acabdSKevin Wang int ret = 0; 380767acabdSKevin Wang struct smu_context *smu = &adev->smu; 381c6b6a421SHawking Zhang 382e3526257SMonk Liu if (nv_asic_reset_method(adev) == AMD_RESET_METHOD_BACO) { 38311043b7aSAlex Deucher dev_info(adev->dev, "BACO reset\n"); 384311531f0SWenhui Sheng 38511520f27SAlex Deucher ret = smu_baco_enter(smu); 38611520f27SAlex Deucher if (ret) 38711520f27SAlex Deucher return ret; 38811520f27SAlex Deucher ret = smu_baco_exit(smu); 38911520f27SAlex Deucher if (ret) 39011520f27SAlex Deucher return ret; 39111043b7aSAlex Deucher } else { 39211043b7aSAlex Deucher dev_info(adev->dev, "MODE1 reset\n"); 3933e2bb60aSKevin Wang ret = nv_asic_mode1_reset(adev); 39411043b7aSAlex Deucher } 395767acabdSKevin Wang 396767acabdSKevin Wang return ret; 397c6b6a421SHawking Zhang } 398c6b6a421SHawking Zhang 399c6b6a421SHawking Zhang static int nv_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk) 400c6b6a421SHawking Zhang { 401c6b6a421SHawking Zhang /* todo */ 402c6b6a421SHawking Zhang return 0; 403c6b6a421SHawking Zhang } 404c6b6a421SHawking Zhang 405c6b6a421SHawking Zhang static int nv_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk) 406c6b6a421SHawking Zhang { 407c6b6a421SHawking Zhang /* todo */ 408c6b6a421SHawking Zhang return 0; 409c6b6a421SHawking Zhang } 410c6b6a421SHawking Zhang 411c6b6a421SHawking Zhang static void nv_pcie_gen3_enable(struct amdgpu_device *adev) 412c6b6a421SHawking Zhang { 413c6b6a421SHawking Zhang if (pci_is_root_bus(adev->pdev->bus)) 414c6b6a421SHawking Zhang return; 415c6b6a421SHawking Zhang 416c6b6a421SHawking Zhang if (amdgpu_pcie_gen2 == 0) 417c6b6a421SHawking Zhang return; 418c6b6a421SHawking Zhang 419c6b6a421SHawking Zhang if (!(adev->pm.pcie_gen_mask & (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 | 420c6b6a421SHawking Zhang CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3))) 421c6b6a421SHawking Zhang return; 422c6b6a421SHawking Zhang 423c6b6a421SHawking Zhang /* todo */ 424c6b6a421SHawking Zhang } 425c6b6a421SHawking Zhang 426c6b6a421SHawking Zhang static void nv_program_aspm(struct amdgpu_device *adev) 427c6b6a421SHawking Zhang { 428c6b6a421SHawking Zhang 429c6b6a421SHawking Zhang if (amdgpu_aspm == 0) 430c6b6a421SHawking Zhang return; 431c6b6a421SHawking Zhang 432c6b6a421SHawking Zhang /* todo */ 433c6b6a421SHawking Zhang } 434c6b6a421SHawking Zhang 435c6b6a421SHawking Zhang static void nv_enable_doorbell_aperture(struct amdgpu_device *adev, 436c6b6a421SHawking Zhang bool enable) 437c6b6a421SHawking Zhang { 438bebc0762SHawking Zhang adev->nbio.funcs->enable_doorbell_aperture(adev, enable); 439bebc0762SHawking Zhang adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, enable); 440c6b6a421SHawking Zhang } 441c6b6a421SHawking Zhang 442c6b6a421SHawking Zhang static const struct amdgpu_ip_block_version nv_common_ip_block = 443c6b6a421SHawking Zhang { 444c6b6a421SHawking Zhang .type = AMD_IP_BLOCK_TYPE_COMMON, 445c6b6a421SHawking Zhang .major = 1, 446c6b6a421SHawking Zhang .minor = 0, 447c6b6a421SHawking Zhang .rev = 0, 448c6b6a421SHawking Zhang .funcs = &nv_common_ip_funcs, 449c6b6a421SHawking Zhang }; 450c6b6a421SHawking Zhang 451b5c73856SXiaojie Yuan static int nv_reg_base_init(struct amdgpu_device *adev) 452c6b6a421SHawking Zhang { 453b5c73856SXiaojie Yuan int r; 454b5c73856SXiaojie Yuan 455b5c73856SXiaojie Yuan if (amdgpu_discovery) { 456b5c73856SXiaojie Yuan r = amdgpu_discovery_reg_base_init(adev); 457b5c73856SXiaojie Yuan if (r) { 458b5c73856SXiaojie Yuan DRM_WARN("failed to init reg base from ip discovery table, " 459b5c73856SXiaojie Yuan "fallback to legacy init method\n"); 460b5c73856SXiaojie Yuan goto legacy_init; 461b5c73856SXiaojie Yuan } 462b5c73856SXiaojie Yuan 463b5c73856SXiaojie Yuan return 0; 464b5c73856SXiaojie Yuan } 465b5c73856SXiaojie Yuan 466b5c73856SXiaojie Yuan legacy_init: 467c6b6a421SHawking Zhang switch (adev->asic_type) { 468c6b6a421SHawking Zhang case CHIP_NAVI10: 469c6b6a421SHawking Zhang navi10_reg_base_init(adev); 470c6b6a421SHawking Zhang break; 471a0f6d926SXiaojie Yuan case CHIP_NAVI14: 472a0f6d926SXiaojie Yuan navi14_reg_base_init(adev); 473a0f6d926SXiaojie Yuan break; 47403d0a073SXiaojie Yuan case CHIP_NAVI12: 47503d0a073SXiaojie Yuan navi12_reg_base_init(adev); 47603d0a073SXiaojie Yuan break; 477dccdbf3fSLikun Gao case CHIP_SIENNA_CICHLID: 478c8c959f6SJiansong Chen case CHIP_NAVY_FLOUNDER: 479dccdbf3fSLikun Gao sienna_cichlid_reg_base_init(adev); 480dccdbf3fSLikun Gao break; 481c6b6a421SHawking Zhang default: 482c6b6a421SHawking Zhang return -EINVAL; 483c6b6a421SHawking Zhang } 484c6b6a421SHawking Zhang 485b5c73856SXiaojie Yuan return 0; 486b5c73856SXiaojie Yuan } 487b5c73856SXiaojie Yuan 488c1299461SWenhui Sheng void nv_set_virt_ops(struct amdgpu_device *adev) 489c1299461SWenhui Sheng { 490c1299461SWenhui Sheng adev->virt.ops = &xgpu_nv_virt_ops; 491c1299461SWenhui Sheng } 492c1299461SWenhui Sheng 493b5c73856SXiaojie Yuan int nv_set_ip_blocks(struct amdgpu_device *adev) 494b5c73856SXiaojie Yuan { 495b5c73856SXiaojie Yuan int r; 496b5c73856SXiaojie Yuan 497122078deSMonk Liu adev->nbio.funcs = &nbio_v2_3_funcs; 498122078deSMonk Liu adev->nbio.hdp_flush_reg = &nbio_v2_3_hdp_flush_reg; 499122078deSMonk Liu 500c652923aSJohn Clements if (adev->asic_type == CHIP_SIENNA_CICHLID) 501c652923aSJohn Clements adev->gmc.xgmi.supported = true; 502c652923aSJohn Clements 503b5c73856SXiaojie Yuan /* Set IP register base before any HW register access */ 504b5c73856SXiaojie Yuan r = nv_reg_base_init(adev); 505b5c73856SXiaojie Yuan if (r) 506b5c73856SXiaojie Yuan return r; 507b5c73856SXiaojie Yuan 508c6b6a421SHawking Zhang switch (adev->asic_type) { 509c6b6a421SHawking Zhang case CHIP_NAVI10: 510d1daf850SAlex Deucher case CHIP_NAVI14: 511c6b6a421SHawking Zhang amdgpu_device_ip_block_add(adev, &nv_common_ip_block); 512c6b6a421SHawking Zhang amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block); 513c6b6a421SHawking Zhang amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block); 514c6b6a421SHawking Zhang amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block); 515c6b6a421SHawking Zhang if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP && 5169530273eSEvan Quan !amdgpu_sriov_vf(adev)) 517c6b6a421SHawking Zhang amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 518c6b6a421SHawking Zhang if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) 519c6b6a421SHawking Zhang amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block); 520f8a7976bSAlex Deucher #if defined(CONFIG_DRM_AMD_DC) 521b4f199c7SHarry Wentland else if (amdgpu_device_has_dc_support(adev)) 522b4f199c7SHarry Wentland amdgpu_device_ip_block_add(adev, &dm_ip_block); 523f8a7976bSAlex Deucher #endif 524c6b6a421SHawking Zhang amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block); 525c6b6a421SHawking Zhang amdgpu_device_ip_block_add(adev, &sdma_v5_0_ip_block); 526c6b6a421SHawking Zhang if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT && 5279530273eSEvan Quan !amdgpu_sriov_vf(adev)) 528c6b6a421SHawking Zhang amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 529c6b6a421SHawking Zhang amdgpu_device_ip_block_add(adev, &vcn_v2_0_ip_block); 5305be45a26SLeo Liu amdgpu_device_ip_block_add(adev, &jpeg_v2_0_ip_block); 531c6b6a421SHawking Zhang if (adev->enable_mes) 532c6b6a421SHawking Zhang amdgpu_device_ip_block_add(adev, &mes_v10_1_ip_block); 533c6b6a421SHawking Zhang break; 53444e9e7c9SXiaojie Yuan case CHIP_NAVI12: 53544e9e7c9SXiaojie Yuan amdgpu_device_ip_block_add(adev, &nv_common_ip_block); 53644e9e7c9SXiaojie Yuan amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block); 53744e9e7c9SXiaojie Yuan amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block); 5386b66ae2eSXiaojie Yuan amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block); 53979bebabbSMonk Liu if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) 5407f47efebSXiaojie Yuan amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 54179902029SXiaojie Yuan if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) 54279902029SXiaojie Yuan amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block); 54320c14ee1SPetr Cvek #if defined(CONFIG_DRM_AMD_DC) 544078655d9SLeo Li else if (amdgpu_device_has_dc_support(adev)) 545078655d9SLeo Li amdgpu_device_ip_block_add(adev, &dm_ip_block); 54620c14ee1SPetr Cvek #endif 54744e9e7c9SXiaojie Yuan amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block); 54844e9e7c9SXiaojie Yuan amdgpu_device_ip_block_add(adev, &sdma_v5_0_ip_block); 5497f47efebSXiaojie Yuan if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT && 5509530273eSEvan Quan !amdgpu_sriov_vf(adev)) 5517f47efebSXiaojie Yuan amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 5521fbed280SBoyuan Zhang amdgpu_device_ip_block_add(adev, &vcn_v2_0_ip_block); 553fe442491SMonk Liu if (!amdgpu_sriov_vf(adev)) 5545be45a26SLeo Liu amdgpu_device_ip_block_add(adev, &jpeg_v2_0_ip_block); 55544e9e7c9SXiaojie Yuan break; 5562e1ba10eSLikun Gao case CHIP_SIENNA_CICHLID: 5572e1ba10eSLikun Gao amdgpu_device_ip_block_add(adev, &nv_common_ip_block); 5580b3df16bSLikun Gao amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block); 559757b3af8SLikun Gao amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block); 56056304e72SLikun Gao if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) 5615aa02350SLikun Gao amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block); 562b07e5c60SLikun Gao if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP && 56338d5bbefSshaoyunl is_support_sw_smu(adev) && !amdgpu_sriov_vf(adev)) 564b07e5c60SLikun Gao amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 5659a986760SLikun Gao if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) 5669a986760SLikun Gao amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block); 567464ab91aSBhawanpreet Lakha #if defined(CONFIG_DRM_AMD_DC) 568464ab91aSBhawanpreet Lakha else if (amdgpu_device_has_dc_support(adev)) 569464ab91aSBhawanpreet Lakha amdgpu_device_ip_block_add(adev, &dm_ip_block); 570464ab91aSBhawanpreet Lakha #endif 571933c8a93SLikun Gao amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block); 572157e72e8SLikun Gao amdgpu_device_ip_block_add(adev, &sdma_v5_2_ip_block); 573b8f10585SLeo Liu amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block); 574c45fbe1bSJack Zhang if (!amdgpu_sriov_vf(adev)) 5754d72dd12SLeo Liu amdgpu_device_ip_block_add(adev, &jpeg_v3_0_ip_block); 576c45fbe1bSJack Zhang 577a346ef86SJack Xiao if (adev->enable_mes) 578a346ef86SJack Xiao amdgpu_device_ip_block_add(adev, &mes_v10_1_ip_block); 5792e1ba10eSLikun Gao break; 5808515e0a4SJiansong Chen case CHIP_NAVY_FLOUNDER: 5818515e0a4SJiansong Chen amdgpu_device_ip_block_add(adev, &nv_common_ip_block); 582fc8f07daSJiansong Chen amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block); 583026c396bSJiansong Chen amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block); 5847420eab2SJiansong Chen if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) 5857420eab2SJiansong Chen amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block); 5867420eab2SJiansong Chen if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP && 5877420eab2SJiansong Chen is_support_sw_smu(adev)) 5887420eab2SJiansong Chen amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 5895404f073SJiansong Chen if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) 5905404f073SJiansong Chen amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block); 591a6c5308fSBhawanpreet Lakha #if defined(CONFIG_DRM_AMD_DC) 592a6c5308fSBhawanpreet Lakha else if (amdgpu_device_has_dc_support(adev)) 593a6c5308fSBhawanpreet Lakha amdgpu_device_ip_block_add(adev, &dm_ip_block); 594a6c5308fSBhawanpreet Lakha #endif 595885eb3faSJiansong Chen amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block); 596df2d15dfSJiansong Chen amdgpu_device_ip_block_add(adev, &sdma_v5_2_ip_block); 597290b4ad5SBoyuan Zhang amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block); 598290b4ad5SBoyuan Zhang amdgpu_device_ip_block_add(adev, &jpeg_v3_0_ip_block); 599f4497d10SJiansong Chen if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT && 600f4497d10SJiansong Chen is_support_sw_smu(adev)) 601f4497d10SJiansong Chen amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 6028515e0a4SJiansong Chen break; 603c6b6a421SHawking Zhang default: 604c6b6a421SHawking Zhang return -EINVAL; 605c6b6a421SHawking Zhang } 606c6b6a421SHawking Zhang 607c6b6a421SHawking Zhang return 0; 608c6b6a421SHawking Zhang } 609c6b6a421SHawking Zhang 610c6b6a421SHawking Zhang static uint32_t nv_get_rev_id(struct amdgpu_device *adev) 611c6b6a421SHawking Zhang { 612bebc0762SHawking Zhang return adev->nbio.funcs->get_rev_id(adev); 613c6b6a421SHawking Zhang } 614c6b6a421SHawking Zhang 615c6b6a421SHawking Zhang static void nv_flush_hdp(struct amdgpu_device *adev, struct amdgpu_ring *ring) 616c6b6a421SHawking Zhang { 617bebc0762SHawking Zhang adev->nbio.funcs->hdp_flush(adev, ring); 618c6b6a421SHawking Zhang } 619c6b6a421SHawking Zhang 620c6b6a421SHawking Zhang static void nv_invalidate_hdp(struct amdgpu_device *adev, 621c6b6a421SHawking Zhang struct amdgpu_ring *ring) 622c6b6a421SHawking Zhang { 623c6b6a421SHawking Zhang if (!ring || !ring->funcs->emit_wreg) { 62478f0aef1SStanley.Yang WREG32_SOC15_NO_KIQ(HDP, 0, mmHDP_READ_CACHE_INVALIDATE, 1); 625c6b6a421SHawking Zhang } else { 626c6b6a421SHawking Zhang amdgpu_ring_emit_wreg(ring, SOC15_REG_OFFSET( 627c6b6a421SHawking Zhang HDP, 0, mmHDP_READ_CACHE_INVALIDATE), 1); 628c6b6a421SHawking Zhang } 629c6b6a421SHawking Zhang } 630c6b6a421SHawking Zhang 631c6b6a421SHawking Zhang static bool nv_need_full_reset(struct amdgpu_device *adev) 632c6b6a421SHawking Zhang { 633c6b6a421SHawking Zhang return true; 634c6b6a421SHawking Zhang } 635c6b6a421SHawking Zhang 636c6b6a421SHawking Zhang static bool nv_need_reset_on_init(struct amdgpu_device *adev) 637c6b6a421SHawking Zhang { 638c6b6a421SHawking Zhang u32 sol_reg; 639c6b6a421SHawking Zhang 640c6b6a421SHawking Zhang if (adev->flags & AMD_IS_APU) 641c6b6a421SHawking Zhang return false; 642c6b6a421SHawking Zhang 643c6b6a421SHawking Zhang /* Check sOS sign of life register to confirm sys driver and sOS 644c6b6a421SHawking Zhang * are already been loaded. 645c6b6a421SHawking Zhang */ 646c6b6a421SHawking Zhang sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81); 647c6b6a421SHawking Zhang if (sol_reg) 648c6b6a421SHawking Zhang return true; 6493967ae6dSAlex Deucher 650c6b6a421SHawking Zhang return false; 651c6b6a421SHawking Zhang } 652c6b6a421SHawking Zhang 6532af81531SKevin Wang static uint64_t nv_get_pcie_replay_count(struct amdgpu_device *adev) 6542af81531SKevin Wang { 6552af81531SKevin Wang 6562af81531SKevin Wang /* TODO 6572af81531SKevin Wang * dummy implement for pcie_replay_count sysfs interface 6582af81531SKevin Wang * */ 6592af81531SKevin Wang 6602af81531SKevin Wang return 0; 6612af81531SKevin Wang } 6622af81531SKevin Wang 663c6b6a421SHawking Zhang static void nv_init_doorbell_index(struct amdgpu_device *adev) 664c6b6a421SHawking Zhang { 665c6b6a421SHawking Zhang adev->doorbell_index.kiq = AMDGPU_NAVI10_DOORBELL_KIQ; 666c6b6a421SHawking Zhang adev->doorbell_index.mec_ring0 = AMDGPU_NAVI10_DOORBELL_MEC_RING0; 667c6b6a421SHawking Zhang adev->doorbell_index.mec_ring1 = AMDGPU_NAVI10_DOORBELL_MEC_RING1; 668c6b6a421SHawking Zhang adev->doorbell_index.mec_ring2 = AMDGPU_NAVI10_DOORBELL_MEC_RING2; 669c6b6a421SHawking Zhang adev->doorbell_index.mec_ring3 = AMDGPU_NAVI10_DOORBELL_MEC_RING3; 670c6b6a421SHawking Zhang adev->doorbell_index.mec_ring4 = AMDGPU_NAVI10_DOORBELL_MEC_RING4; 671c6b6a421SHawking Zhang adev->doorbell_index.mec_ring5 = AMDGPU_NAVI10_DOORBELL_MEC_RING5; 672c6b6a421SHawking Zhang adev->doorbell_index.mec_ring6 = AMDGPU_NAVI10_DOORBELL_MEC_RING6; 673c6b6a421SHawking Zhang adev->doorbell_index.mec_ring7 = AMDGPU_NAVI10_DOORBELL_MEC_RING7; 674c6b6a421SHawking Zhang adev->doorbell_index.userqueue_start = AMDGPU_NAVI10_DOORBELL_USERQUEUE_START; 675c6b6a421SHawking Zhang adev->doorbell_index.userqueue_end = AMDGPU_NAVI10_DOORBELL_USERQUEUE_END; 676c6b6a421SHawking Zhang adev->doorbell_index.gfx_ring0 = AMDGPU_NAVI10_DOORBELL_GFX_RING0; 677c6b6a421SHawking Zhang adev->doorbell_index.gfx_ring1 = AMDGPU_NAVI10_DOORBELL_GFX_RING1; 67820519232SJack Xiao adev->doorbell_index.mes_ring = AMDGPU_NAVI10_DOORBELL_MES_RING; 679c6b6a421SHawking Zhang adev->doorbell_index.sdma_engine[0] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE0; 680c6b6a421SHawking Zhang adev->doorbell_index.sdma_engine[1] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE1; 681157e72e8SLikun Gao adev->doorbell_index.sdma_engine[2] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE2; 682157e72e8SLikun Gao adev->doorbell_index.sdma_engine[3] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE3; 683c6b6a421SHawking Zhang adev->doorbell_index.ih = AMDGPU_NAVI10_DOORBELL_IH; 684c6b6a421SHawking Zhang adev->doorbell_index.vcn.vcn_ring0_1 = AMDGPU_NAVI10_DOORBELL64_VCN0_1; 685c6b6a421SHawking Zhang adev->doorbell_index.vcn.vcn_ring2_3 = AMDGPU_NAVI10_DOORBELL64_VCN2_3; 686c6b6a421SHawking Zhang adev->doorbell_index.vcn.vcn_ring4_5 = AMDGPU_NAVI10_DOORBELL64_VCN4_5; 687c6b6a421SHawking Zhang adev->doorbell_index.vcn.vcn_ring6_7 = AMDGPU_NAVI10_DOORBELL64_VCN6_7; 688c6b6a421SHawking Zhang adev->doorbell_index.first_non_cp = AMDGPU_NAVI10_DOORBELL64_FIRST_NON_CP; 689c6b6a421SHawking Zhang adev->doorbell_index.last_non_cp = AMDGPU_NAVI10_DOORBELL64_LAST_NON_CP; 690c6b6a421SHawking Zhang 691c6b6a421SHawking Zhang adev->doorbell_index.max_assignment = AMDGPU_NAVI10_DOORBELL_MAX_ASSIGNMENT << 1; 692c6b6a421SHawking Zhang adev->doorbell_index.sdma_doorbell_range = 20; 693c6b6a421SHawking Zhang } 694c6b6a421SHawking Zhang 695a7173731SAlex Deucher static void nv_pre_asic_init(struct amdgpu_device *adev) 696a7173731SAlex Deucher { 697a7173731SAlex Deucher } 698a7173731SAlex Deucher 699c6b6a421SHawking Zhang static const struct amdgpu_asic_funcs nv_asic_funcs = 700c6b6a421SHawking Zhang { 701c6b6a421SHawking Zhang .read_disabled_bios = &nv_read_disabled_bios, 702c6b6a421SHawking Zhang .read_bios_from_rom = &nv_read_bios_from_rom, 703c6b6a421SHawking Zhang .read_register = &nv_read_register, 704c6b6a421SHawking Zhang .reset = &nv_asic_reset, 7052ddc6c3eSAlex Deucher .reset_method = &nv_asic_reset_method, 706c6b6a421SHawking Zhang .set_vga_state = &nv_vga_set_state, 707c6b6a421SHawking Zhang .get_xclk = &nv_get_xclk, 708c6b6a421SHawking Zhang .set_uvd_clocks = &nv_set_uvd_clocks, 709c6b6a421SHawking Zhang .set_vce_clocks = &nv_set_vce_clocks, 710c6b6a421SHawking Zhang .get_config_memsize = &nv_get_config_memsize, 711c6b6a421SHawking Zhang .flush_hdp = &nv_flush_hdp, 712c6b6a421SHawking Zhang .invalidate_hdp = &nv_invalidate_hdp, 713c6b6a421SHawking Zhang .init_doorbell_index = &nv_init_doorbell_index, 714c6b6a421SHawking Zhang .need_full_reset = &nv_need_full_reset, 715c6b6a421SHawking Zhang .need_reset_on_init = &nv_need_reset_on_init, 7162af81531SKevin Wang .get_pcie_replay_count = &nv_get_pcie_replay_count, 717ac742616SAlex Deucher .supports_baco = &nv_asic_supports_baco, 718a7173731SAlex Deucher .pre_asic_init = &nv_pre_asic_init, 719c6b6a421SHawking Zhang }; 720c6b6a421SHawking Zhang 721c6b6a421SHawking Zhang static int nv_common_early_init(void *handle) 722c6b6a421SHawking Zhang { 723923c087aSYong Zhao #define MMIO_REG_HOLE_OFFSET (0x80000 - PAGE_SIZE) 724c6b6a421SHawking Zhang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 725c6b6a421SHawking Zhang 726923c087aSYong Zhao adev->rmmio_remap.reg_offset = MMIO_REG_HOLE_OFFSET; 727923c087aSYong Zhao adev->rmmio_remap.bus_addr = adev->rmmio_base + MMIO_REG_HOLE_OFFSET; 728c6b6a421SHawking Zhang adev->smc_rreg = NULL; 729c6b6a421SHawking Zhang adev->smc_wreg = NULL; 730c6b6a421SHawking Zhang adev->pcie_rreg = &nv_pcie_rreg; 731c6b6a421SHawking Zhang adev->pcie_wreg = &nv_pcie_wreg; 7324922f1bcSJohn Clements adev->pcie_rreg64 = &nv_pcie_rreg64; 7334922f1bcSJohn Clements adev->pcie_wreg64 = &nv_pcie_wreg64; 734c6b6a421SHawking Zhang 735c6b6a421SHawking Zhang /* TODO: will add them during VCN v2 implementation */ 736c6b6a421SHawking Zhang adev->uvd_ctx_rreg = NULL; 737c6b6a421SHawking Zhang adev->uvd_ctx_wreg = NULL; 738c6b6a421SHawking Zhang 739c6b6a421SHawking Zhang adev->didt_rreg = &nv_didt_rreg; 740c6b6a421SHawking Zhang adev->didt_wreg = &nv_didt_wreg; 741c6b6a421SHawking Zhang 742c6b6a421SHawking Zhang adev->asic_funcs = &nv_asic_funcs; 743c6b6a421SHawking Zhang 744c6b6a421SHawking Zhang adev->rev_id = nv_get_rev_id(adev); 745c6b6a421SHawking Zhang adev->external_rev_id = 0xff; 746c6b6a421SHawking Zhang switch (adev->asic_type) { 747c6b6a421SHawking Zhang case CHIP_NAVI10: 748c6b6a421SHawking Zhang adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 749c6b6a421SHawking Zhang AMD_CG_SUPPORT_GFX_CGCG | 750c6b6a421SHawking Zhang AMD_CG_SUPPORT_IH_CG | 751c6b6a421SHawking Zhang AMD_CG_SUPPORT_HDP_MGCG | 752c6b6a421SHawking Zhang AMD_CG_SUPPORT_HDP_LS | 753c6b6a421SHawking Zhang AMD_CG_SUPPORT_SDMA_MGCG | 754c6b6a421SHawking Zhang AMD_CG_SUPPORT_SDMA_LS | 755c6b6a421SHawking Zhang AMD_CG_SUPPORT_MC_MGCG | 756c6b6a421SHawking Zhang AMD_CG_SUPPORT_MC_LS | 757c6b6a421SHawking Zhang AMD_CG_SUPPORT_ATHUB_MGCG | 758c6b6a421SHawking Zhang AMD_CG_SUPPORT_ATHUB_LS | 759c6b6a421SHawking Zhang AMD_CG_SUPPORT_VCN_MGCG | 760099d66e4SLeo Liu AMD_CG_SUPPORT_JPEG_MGCG | 761c6b6a421SHawking Zhang AMD_CG_SUPPORT_BIF_MGCG | 762c6b6a421SHawking Zhang AMD_CG_SUPPORT_BIF_LS; 763157710eaSLeo Liu adev->pg_flags = AMD_PG_SUPPORT_VCN | 764c12d410fSHuang Rui AMD_PG_SUPPORT_VCN_DPG | 765099d66e4SLeo Liu AMD_PG_SUPPORT_JPEG | 766a201b6acSHuang Rui AMD_PG_SUPPORT_ATHUB; 767c6b6a421SHawking Zhang adev->external_rev_id = adev->rev_id + 0x1; 768c6b6a421SHawking Zhang break; 7695e71e011SXiaojie Yuan case CHIP_NAVI14: 770d0c39f8cSXiaojie Yuan adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 771d0c39f8cSXiaojie Yuan AMD_CG_SUPPORT_GFX_CGCG | 772d0c39f8cSXiaojie Yuan AMD_CG_SUPPORT_IH_CG | 773d0c39f8cSXiaojie Yuan AMD_CG_SUPPORT_HDP_MGCG | 774d0c39f8cSXiaojie Yuan AMD_CG_SUPPORT_HDP_LS | 775d0c39f8cSXiaojie Yuan AMD_CG_SUPPORT_SDMA_MGCG | 776d0c39f8cSXiaojie Yuan AMD_CG_SUPPORT_SDMA_LS | 777d0c39f8cSXiaojie Yuan AMD_CG_SUPPORT_MC_MGCG | 778d0c39f8cSXiaojie Yuan AMD_CG_SUPPORT_MC_LS | 779d0c39f8cSXiaojie Yuan AMD_CG_SUPPORT_ATHUB_MGCG | 780d0c39f8cSXiaojie Yuan AMD_CG_SUPPORT_ATHUB_LS | 781d0c39f8cSXiaojie Yuan AMD_CG_SUPPORT_VCN_MGCG | 782099d66e4SLeo Liu AMD_CG_SUPPORT_JPEG_MGCG | 783d0c39f8cSXiaojie Yuan AMD_CG_SUPPORT_BIF_MGCG | 784d0c39f8cSXiaojie Yuan AMD_CG_SUPPORT_BIF_LS; 7850377b088SXiaojie Yuan adev->pg_flags = AMD_PG_SUPPORT_VCN | 786099d66e4SLeo Liu AMD_PG_SUPPORT_JPEG | 7870377b088SXiaojie Yuan AMD_PG_SUPPORT_VCN_DPG; 78835ef88faStiancyin adev->external_rev_id = adev->rev_id + 20; 7895e71e011SXiaojie Yuan break; 79074b5e509SXiaojie Yuan case CHIP_NAVI12: 791dca009e7SXiaojie Yuan adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 792dca009e7SXiaojie Yuan AMD_CG_SUPPORT_GFX_MGLS | 793dca009e7SXiaojie Yuan AMD_CG_SUPPORT_GFX_CGCG | 794dca009e7SXiaojie Yuan AMD_CG_SUPPORT_GFX_CP_LS | 7955211c37aSXiaojie Yuan AMD_CG_SUPPORT_GFX_RLC_LS | 796fbe0bc57SXiaojie Yuan AMD_CG_SUPPORT_IH_CG | 7975211c37aSXiaojie Yuan AMD_CG_SUPPORT_HDP_MGCG | 798358ab97fSXiaojie Yuan AMD_CG_SUPPORT_HDP_LS | 799358ab97fSXiaojie Yuan AMD_CG_SUPPORT_SDMA_MGCG | 8008b797b3dSXiaojie Yuan AMD_CG_SUPPORT_SDMA_LS | 8018b797b3dSXiaojie Yuan AMD_CG_SUPPORT_MC_MGCG | 802ca51678dSXiaojie Yuan AMD_CG_SUPPORT_MC_LS | 803ca51678dSXiaojie Yuan AMD_CG_SUPPORT_ATHUB_MGCG | 80465872e59SXiaojie Yuan AMD_CG_SUPPORT_ATHUB_LS | 805099d66e4SLeo Liu AMD_CG_SUPPORT_VCN_MGCG | 806099d66e4SLeo Liu AMD_CG_SUPPORT_JPEG_MGCG; 807c1653ea0SXiaojie Yuan adev->pg_flags = AMD_PG_SUPPORT_VCN | 8085ef3b8acSXiaojie Yuan AMD_PG_SUPPORT_VCN_DPG | 809099d66e4SLeo Liu AMD_PG_SUPPORT_JPEG | 8101b0443b1SLikun Gao AMD_PG_SUPPORT_ATHUB; 811df5e984cSTiecheng Zhou /* guest vm gets 0xffffffff when reading RCC_DEV0_EPF0_STRAP0, 812df5e984cSTiecheng Zhou * as a consequence, the rev_id and external_rev_id are wrong. 813df5e984cSTiecheng Zhou * workaround it by hardcoding rev_id to 0 (default value). 814df5e984cSTiecheng Zhou */ 815df5e984cSTiecheng Zhou if (amdgpu_sriov_vf(adev)) 816df5e984cSTiecheng Zhou adev->rev_id = 0; 81774b5e509SXiaojie Yuan adev->external_rev_id = adev->rev_id + 0xa; 81874b5e509SXiaojie Yuan break; 819117910edSLikun Gao case CHIP_SIENNA_CICHLID: 82000194defSLikun Gao adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 82100194defSLikun Gao AMD_CG_SUPPORT_GFX_CGCG | 82200194defSLikun Gao AMD_CG_SUPPORT_GFX_3D_CGCG | 82398f8ea29SLikun Gao AMD_CG_SUPPORT_MC_MGCG | 82400194defSLikun Gao AMD_CG_SUPPORT_VCN_MGCG | 825ca36461fSKenneth Feng AMD_CG_SUPPORT_JPEG_MGCG | 826ca36461fSKenneth Feng AMD_CG_SUPPORT_HDP_MGCG | 8273a32c25aSKenneth Feng AMD_CG_SUPPORT_HDP_LS | 828bcc8367fSKenneth Feng AMD_CG_SUPPORT_IH_CG | 829bcc8367fSKenneth Feng AMD_CG_SUPPORT_MC_LS; 830b467c4f5SLeo Liu adev->pg_flags = AMD_PG_SUPPORT_VCN | 831d00b0fa9SBoyuan Zhang AMD_PG_SUPPORT_VCN_DPG | 832b794616dSKenneth Feng AMD_PG_SUPPORT_JPEG | 8331b0443b1SLikun Gao AMD_PG_SUPPORT_ATHUB | 8341b0443b1SLikun Gao AMD_PG_SUPPORT_MMHUB; 835c45fbe1bSJack Zhang if (amdgpu_sriov_vf(adev)) { 836c45fbe1bSJack Zhang /* hypervisor control CG and PG enablement */ 837c45fbe1bSJack Zhang adev->cg_flags = 0; 838c45fbe1bSJack Zhang adev->pg_flags = 0; 839c45fbe1bSJack Zhang } 840117910edSLikun Gao adev->external_rev_id = adev->rev_id + 0x28; 841117910edSLikun Gao break; 842543aa259SJiansong Chen case CHIP_NAVY_FLOUNDER: 84340582e67SJiansong Chen adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 84440582e67SJiansong Chen AMD_CG_SUPPORT_GFX_CGCG | 84540582e67SJiansong Chen AMD_CG_SUPPORT_GFX_3D_CGCG | 84640582e67SJiansong Chen AMD_CG_SUPPORT_VCN_MGCG | 84792c73756SJiansong Chen AMD_CG_SUPPORT_JPEG_MGCG | 84892c73756SJiansong Chen AMD_CG_SUPPORT_MC_MGCG | 8494759f887SJiansong Chen AMD_CG_SUPPORT_MC_LS | 8504759f887SJiansong Chen AMD_CG_SUPPORT_HDP_MGCG | 85185e7151bSJiansong Chen AMD_CG_SUPPORT_HDP_LS | 85285e7151bSJiansong Chen AMD_CG_SUPPORT_IH_CG; 853c6e9dd0eSBoyuan Zhang adev->pg_flags = AMD_PG_SUPPORT_VCN | 85400740df9SBoyuan Zhang AMD_PG_SUPPORT_VCN_DPG | 85547fc894aSJiansong Chen AMD_PG_SUPPORT_JPEG | 85647fc894aSJiansong Chen AMD_PG_SUPPORT_ATHUB | 85747fc894aSJiansong Chen AMD_PG_SUPPORT_MMHUB; 858543aa259SJiansong Chen adev->external_rev_id = adev->rev_id + 0x32; 859543aa259SJiansong Chen break; 860543aa259SJiansong Chen 861c6b6a421SHawking Zhang default: 862c6b6a421SHawking Zhang /* FIXME: not supported yet */ 863c6b6a421SHawking Zhang return -EINVAL; 864c6b6a421SHawking Zhang } 865c6b6a421SHawking Zhang 866b05b6903SJiange Zhao if (amdgpu_sriov_vf(adev)) { 867b05b6903SJiange Zhao amdgpu_virt_init_setting(adev); 868b05b6903SJiange Zhao xgpu_nv_mailbox_set_irq_funcs(adev); 869b05b6903SJiange Zhao } 870b05b6903SJiange Zhao 871c6b6a421SHawking Zhang return 0; 872c6b6a421SHawking Zhang } 873c6b6a421SHawking Zhang 874c6b6a421SHawking Zhang static int nv_common_late_init(void *handle) 875c6b6a421SHawking Zhang { 876b05b6903SJiange Zhao struct amdgpu_device *adev = (struct amdgpu_device *)handle; 877b05b6903SJiange Zhao 878b05b6903SJiange Zhao if (amdgpu_sriov_vf(adev)) 879b05b6903SJiange Zhao xgpu_nv_mailbox_get_irq(adev); 880b05b6903SJiange Zhao 881c6b6a421SHawking Zhang return 0; 882c6b6a421SHawking Zhang } 883c6b6a421SHawking Zhang 884c6b6a421SHawking Zhang static int nv_common_sw_init(void *handle) 885c6b6a421SHawking Zhang { 886b05b6903SJiange Zhao struct amdgpu_device *adev = (struct amdgpu_device *)handle; 887b05b6903SJiange Zhao 888b05b6903SJiange Zhao if (amdgpu_sriov_vf(adev)) 889b05b6903SJiange Zhao xgpu_nv_mailbox_add_irq_id(adev); 890b05b6903SJiange Zhao 891c6b6a421SHawking Zhang return 0; 892c6b6a421SHawking Zhang } 893c6b6a421SHawking Zhang 894c6b6a421SHawking Zhang static int nv_common_sw_fini(void *handle) 895c6b6a421SHawking Zhang { 896c6b6a421SHawking Zhang return 0; 897c6b6a421SHawking Zhang } 898c6b6a421SHawking Zhang 899c6b6a421SHawking Zhang static int nv_common_hw_init(void *handle) 900c6b6a421SHawking Zhang { 901c6b6a421SHawking Zhang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 902c6b6a421SHawking Zhang 903c6b6a421SHawking Zhang /* enable pcie gen2/3 link */ 904c6b6a421SHawking Zhang nv_pcie_gen3_enable(adev); 905c6b6a421SHawking Zhang /* enable aspm */ 906c6b6a421SHawking Zhang nv_program_aspm(adev); 907c6b6a421SHawking Zhang /* setup nbio registers */ 908bebc0762SHawking Zhang adev->nbio.funcs->init_registers(adev); 909923c087aSYong Zhao /* remap HDP registers to a hole in mmio space, 910923c087aSYong Zhao * for the purpose of expose those registers 911923c087aSYong Zhao * to process space 912923c087aSYong Zhao */ 913923c087aSYong Zhao if (adev->nbio.funcs->remap_hdp_registers) 914923c087aSYong Zhao adev->nbio.funcs->remap_hdp_registers(adev); 915c6b6a421SHawking Zhang /* enable the doorbell aperture */ 916c6b6a421SHawking Zhang nv_enable_doorbell_aperture(adev, true); 917c6b6a421SHawking Zhang 918c6b6a421SHawking Zhang return 0; 919c6b6a421SHawking Zhang } 920c6b6a421SHawking Zhang 921c6b6a421SHawking Zhang static int nv_common_hw_fini(void *handle) 922c6b6a421SHawking Zhang { 923c6b6a421SHawking Zhang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 924c6b6a421SHawking Zhang 925c6b6a421SHawking Zhang /* disable the doorbell aperture */ 926c6b6a421SHawking Zhang nv_enable_doorbell_aperture(adev, false); 927c6b6a421SHawking Zhang 928c6b6a421SHawking Zhang return 0; 929c6b6a421SHawking Zhang } 930c6b6a421SHawking Zhang 931c6b6a421SHawking Zhang static int nv_common_suspend(void *handle) 932c6b6a421SHawking Zhang { 933c6b6a421SHawking Zhang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 934c6b6a421SHawking Zhang 935c6b6a421SHawking Zhang return nv_common_hw_fini(adev); 936c6b6a421SHawking Zhang } 937c6b6a421SHawking Zhang 938c6b6a421SHawking Zhang static int nv_common_resume(void *handle) 939c6b6a421SHawking Zhang { 940c6b6a421SHawking Zhang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 941c6b6a421SHawking Zhang 942c6b6a421SHawking Zhang return nv_common_hw_init(adev); 943c6b6a421SHawking Zhang } 944c6b6a421SHawking Zhang 945c6b6a421SHawking Zhang static bool nv_common_is_idle(void *handle) 946c6b6a421SHawking Zhang { 947c6b6a421SHawking Zhang return true; 948c6b6a421SHawking Zhang } 949c6b6a421SHawking Zhang 950c6b6a421SHawking Zhang static int nv_common_wait_for_idle(void *handle) 951c6b6a421SHawking Zhang { 952c6b6a421SHawking Zhang return 0; 953c6b6a421SHawking Zhang } 954c6b6a421SHawking Zhang 955c6b6a421SHawking Zhang static int nv_common_soft_reset(void *handle) 956c6b6a421SHawking Zhang { 957c6b6a421SHawking Zhang return 0; 958c6b6a421SHawking Zhang } 959c6b6a421SHawking Zhang 960c6b6a421SHawking Zhang static void nv_update_hdp_mem_power_gating(struct amdgpu_device *adev, 961c6b6a421SHawking Zhang bool enable) 962c6b6a421SHawking Zhang { 963c6b6a421SHawking Zhang uint32_t hdp_clk_cntl, hdp_clk_cntl1; 964c6b6a421SHawking Zhang uint32_t hdp_mem_pwr_cntl; 965c6b6a421SHawking Zhang 966c6b6a421SHawking Zhang if (!(adev->cg_flags & (AMD_CG_SUPPORT_HDP_LS | 967c6b6a421SHawking Zhang AMD_CG_SUPPORT_HDP_DS | 968c6b6a421SHawking Zhang AMD_CG_SUPPORT_HDP_SD))) 969c6b6a421SHawking Zhang return; 970c6b6a421SHawking Zhang 971c6b6a421SHawking Zhang hdp_clk_cntl = hdp_clk_cntl1 = RREG32_SOC15(HDP, 0, mmHDP_CLK_CNTL); 972c6b6a421SHawking Zhang hdp_mem_pwr_cntl = RREG32_SOC15(HDP, 0, mmHDP_MEM_POWER_CTRL); 973c6b6a421SHawking Zhang 974c6b6a421SHawking Zhang /* Before doing clock/power mode switch, 975c6b6a421SHawking Zhang * forced on IPH & RC clock */ 976c6b6a421SHawking Zhang hdp_clk_cntl = REG_SET_FIELD(hdp_clk_cntl, HDP_CLK_CNTL, 977c6b6a421SHawking Zhang IPH_MEM_CLK_SOFT_OVERRIDE, 1); 978c6b6a421SHawking Zhang hdp_clk_cntl = REG_SET_FIELD(hdp_clk_cntl, HDP_CLK_CNTL, 979c6b6a421SHawking Zhang RC_MEM_CLK_SOFT_OVERRIDE, 1); 980c6b6a421SHawking Zhang WREG32_SOC15(HDP, 0, mmHDP_CLK_CNTL, hdp_clk_cntl); 981c6b6a421SHawking Zhang 982c6b6a421SHawking Zhang /* HDP 5.0 doesn't support dynamic power mode switch, 983c6b6a421SHawking Zhang * disable clock and power gating before any changing */ 984c6b6a421SHawking Zhang hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, 985c6b6a421SHawking Zhang IPH_MEM_POWER_CTRL_EN, 0); 986c6b6a421SHawking Zhang hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, 987c6b6a421SHawking Zhang IPH_MEM_POWER_LS_EN, 0); 988c6b6a421SHawking Zhang hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, 989c6b6a421SHawking Zhang IPH_MEM_POWER_DS_EN, 0); 990c6b6a421SHawking Zhang hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, 991c6b6a421SHawking Zhang IPH_MEM_POWER_SD_EN, 0); 992c6b6a421SHawking Zhang hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, 993c6b6a421SHawking Zhang RC_MEM_POWER_CTRL_EN, 0); 994c6b6a421SHawking Zhang hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, 995c6b6a421SHawking Zhang RC_MEM_POWER_LS_EN, 0); 996c6b6a421SHawking Zhang hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, 997c6b6a421SHawking Zhang RC_MEM_POWER_DS_EN, 0); 998c6b6a421SHawking Zhang hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, 999c6b6a421SHawking Zhang RC_MEM_POWER_SD_EN, 0); 1000c6b6a421SHawking Zhang WREG32_SOC15(HDP, 0, mmHDP_MEM_POWER_CTRL, hdp_mem_pwr_cntl); 1001c6b6a421SHawking Zhang 1002c6b6a421SHawking Zhang /* only one clock gating mode (LS/DS/SD) can be enabled */ 1003c6b6a421SHawking Zhang if (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS) { 1004c6b6a421SHawking Zhang hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, 1005c6b6a421SHawking Zhang HDP_MEM_POWER_CTRL, 1006c6b6a421SHawking Zhang IPH_MEM_POWER_LS_EN, enable); 1007c6b6a421SHawking Zhang hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, 1008c6b6a421SHawking Zhang HDP_MEM_POWER_CTRL, 1009c6b6a421SHawking Zhang RC_MEM_POWER_LS_EN, enable); 1010c6b6a421SHawking Zhang } else if (adev->cg_flags & AMD_CG_SUPPORT_HDP_DS) { 1011c6b6a421SHawking Zhang hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, 1012c6b6a421SHawking Zhang HDP_MEM_POWER_CTRL, 1013c6b6a421SHawking Zhang IPH_MEM_POWER_DS_EN, enable); 1014c6b6a421SHawking Zhang hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, 1015c6b6a421SHawking Zhang HDP_MEM_POWER_CTRL, 1016c6b6a421SHawking Zhang RC_MEM_POWER_DS_EN, enable); 1017c6b6a421SHawking Zhang } else if (adev->cg_flags & AMD_CG_SUPPORT_HDP_SD) { 1018c6b6a421SHawking Zhang hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, 1019c6b6a421SHawking Zhang HDP_MEM_POWER_CTRL, 1020c6b6a421SHawking Zhang IPH_MEM_POWER_SD_EN, enable); 1021c6b6a421SHawking Zhang /* RC should not use shut down mode, fallback to ds */ 1022c6b6a421SHawking Zhang hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, 1023c6b6a421SHawking Zhang HDP_MEM_POWER_CTRL, 1024c6b6a421SHawking Zhang RC_MEM_POWER_DS_EN, enable); 1025c6b6a421SHawking Zhang } 1026c6b6a421SHawking Zhang 102791c6adf8SKenneth Feng /* confirmed that IPH_MEM_POWER_CTRL_EN and RC_MEM_POWER_CTRL_EN have to 102891c6adf8SKenneth Feng * be set for SRAM LS/DS/SD */ 102991c6adf8SKenneth Feng if (adev->cg_flags & (AMD_CG_SUPPORT_HDP_LS | AMD_CG_SUPPORT_HDP_DS | 103091c6adf8SKenneth Feng AMD_CG_SUPPORT_HDP_SD)) { 103191c6adf8SKenneth Feng hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, 103291c6adf8SKenneth Feng IPH_MEM_POWER_CTRL_EN, 1); 103391c6adf8SKenneth Feng hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, 103491c6adf8SKenneth Feng RC_MEM_POWER_CTRL_EN, 1); 103591c6adf8SKenneth Feng } 103691c6adf8SKenneth Feng 1037c6b6a421SHawking Zhang WREG32_SOC15(HDP, 0, mmHDP_MEM_POWER_CTRL, hdp_mem_pwr_cntl); 1038c6b6a421SHawking Zhang 1039c6b6a421SHawking Zhang /* restore IPH & RC clock override after clock/power mode changing */ 1040c6b6a421SHawking Zhang WREG32_SOC15(HDP, 0, mmHDP_CLK_CNTL, hdp_clk_cntl1); 1041c6b6a421SHawking Zhang } 1042c6b6a421SHawking Zhang 1043c6b6a421SHawking Zhang static void nv_update_hdp_clock_gating(struct amdgpu_device *adev, 1044c6b6a421SHawking Zhang bool enable) 1045c6b6a421SHawking Zhang { 1046c6b6a421SHawking Zhang uint32_t hdp_clk_cntl; 1047c6b6a421SHawking Zhang 1048c6b6a421SHawking Zhang if (!(adev->cg_flags & AMD_CG_SUPPORT_HDP_MGCG)) 1049c6b6a421SHawking Zhang return; 1050c6b6a421SHawking Zhang 1051c6b6a421SHawking Zhang hdp_clk_cntl = RREG32_SOC15(HDP, 0, mmHDP_CLK_CNTL); 1052c6b6a421SHawking Zhang 1053c6b6a421SHawking Zhang if (enable) { 1054c6b6a421SHawking Zhang hdp_clk_cntl &= 1055c6b6a421SHawking Zhang ~(uint32_t) 1056c6b6a421SHawking Zhang (HDP_CLK_CNTL__IPH_MEM_CLK_SOFT_OVERRIDE_MASK | 1057c6b6a421SHawking Zhang HDP_CLK_CNTL__RC_MEM_CLK_SOFT_OVERRIDE_MASK | 1058c6b6a421SHawking Zhang HDP_CLK_CNTL__DBUS_CLK_SOFT_OVERRIDE_MASK | 1059c6b6a421SHawking Zhang HDP_CLK_CNTL__DYN_CLK_SOFT_OVERRIDE_MASK | 1060c6b6a421SHawking Zhang HDP_CLK_CNTL__XDP_REG_CLK_SOFT_OVERRIDE_MASK | 1061c6b6a421SHawking Zhang HDP_CLK_CNTL__HDP_REG_CLK_SOFT_OVERRIDE_MASK); 1062c6b6a421SHawking Zhang } else { 1063c6b6a421SHawking Zhang hdp_clk_cntl |= HDP_CLK_CNTL__IPH_MEM_CLK_SOFT_OVERRIDE_MASK | 1064c6b6a421SHawking Zhang HDP_CLK_CNTL__RC_MEM_CLK_SOFT_OVERRIDE_MASK | 1065c6b6a421SHawking Zhang HDP_CLK_CNTL__DBUS_CLK_SOFT_OVERRIDE_MASK | 1066c6b6a421SHawking Zhang HDP_CLK_CNTL__DYN_CLK_SOFT_OVERRIDE_MASK | 1067c6b6a421SHawking Zhang HDP_CLK_CNTL__XDP_REG_CLK_SOFT_OVERRIDE_MASK | 1068c6b6a421SHawking Zhang HDP_CLK_CNTL__HDP_REG_CLK_SOFT_OVERRIDE_MASK; 1069c6b6a421SHawking Zhang } 1070c6b6a421SHawking Zhang 1071c6b6a421SHawking Zhang WREG32_SOC15(HDP, 0, mmHDP_CLK_CNTL, hdp_clk_cntl); 1072c6b6a421SHawking Zhang } 1073c6b6a421SHawking Zhang 1074c6b6a421SHawking Zhang static int nv_common_set_clockgating_state(void *handle, 1075c6b6a421SHawking Zhang enum amd_clockgating_state state) 1076c6b6a421SHawking Zhang { 1077c6b6a421SHawking Zhang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1078c6b6a421SHawking Zhang 1079c6b6a421SHawking Zhang if (amdgpu_sriov_vf(adev)) 1080c6b6a421SHawking Zhang return 0; 1081c6b6a421SHawking Zhang 1082c6b6a421SHawking Zhang switch (adev->asic_type) { 1083c6b6a421SHawking Zhang case CHIP_NAVI10: 10845e71e011SXiaojie Yuan case CHIP_NAVI14: 10857e17e58bSXiaojie Yuan case CHIP_NAVI12: 1086117910edSLikun Gao case CHIP_SIENNA_CICHLID: 1087543aa259SJiansong Chen case CHIP_NAVY_FLOUNDER: 1088bebc0762SHawking Zhang adev->nbio.funcs->update_medium_grain_clock_gating(adev, 1089a9d4fe2fSNirmoy Das state == AMD_CG_STATE_GATE); 1090bebc0762SHawking Zhang adev->nbio.funcs->update_medium_grain_light_sleep(adev, 1091a9d4fe2fSNirmoy Das state == AMD_CG_STATE_GATE); 1092c6b6a421SHawking Zhang nv_update_hdp_mem_power_gating(adev, 1093a9d4fe2fSNirmoy Das state == AMD_CG_STATE_GATE); 1094c6b6a421SHawking Zhang nv_update_hdp_clock_gating(adev, 1095a9d4fe2fSNirmoy Das state == AMD_CG_STATE_GATE); 1096c6b6a421SHawking Zhang break; 1097c6b6a421SHawking Zhang default: 1098c6b6a421SHawking Zhang break; 1099c6b6a421SHawking Zhang } 1100c6b6a421SHawking Zhang return 0; 1101c6b6a421SHawking Zhang } 1102c6b6a421SHawking Zhang 1103c6b6a421SHawking Zhang static int nv_common_set_powergating_state(void *handle, 1104c6b6a421SHawking Zhang enum amd_powergating_state state) 1105c6b6a421SHawking Zhang { 1106c6b6a421SHawking Zhang /* TODO */ 1107c6b6a421SHawking Zhang return 0; 1108c6b6a421SHawking Zhang } 1109c6b6a421SHawking Zhang 1110c6b6a421SHawking Zhang static void nv_common_get_clockgating_state(void *handle, u32 *flags) 1111c6b6a421SHawking Zhang { 1112c6b6a421SHawking Zhang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1113c6b6a421SHawking Zhang uint32_t tmp; 1114c6b6a421SHawking Zhang 1115c6b6a421SHawking Zhang if (amdgpu_sriov_vf(adev)) 1116c6b6a421SHawking Zhang *flags = 0; 1117c6b6a421SHawking Zhang 1118bebc0762SHawking Zhang adev->nbio.funcs->get_clockgating_state(adev, flags); 1119c6b6a421SHawking Zhang 1120c6b6a421SHawking Zhang /* AMD_CG_SUPPORT_HDP_MGCG */ 1121c6b6a421SHawking Zhang tmp = RREG32_SOC15(HDP, 0, mmHDP_CLK_CNTL); 1122c6b6a421SHawking Zhang if (!(tmp & (HDP_CLK_CNTL__IPH_MEM_CLK_SOFT_OVERRIDE_MASK | 1123c6b6a421SHawking Zhang HDP_CLK_CNTL__RC_MEM_CLK_SOFT_OVERRIDE_MASK | 1124c6b6a421SHawking Zhang HDP_CLK_CNTL__DBUS_CLK_SOFT_OVERRIDE_MASK | 1125c6b6a421SHawking Zhang HDP_CLK_CNTL__DYN_CLK_SOFT_OVERRIDE_MASK | 1126c6b6a421SHawking Zhang HDP_CLK_CNTL__XDP_REG_CLK_SOFT_OVERRIDE_MASK | 1127c6b6a421SHawking Zhang HDP_CLK_CNTL__HDP_REG_CLK_SOFT_OVERRIDE_MASK))) 1128c6b6a421SHawking Zhang *flags |= AMD_CG_SUPPORT_HDP_MGCG; 1129c6b6a421SHawking Zhang 1130c6b6a421SHawking Zhang /* AMD_CG_SUPPORT_HDP_LS/DS/SD */ 1131c6b6a421SHawking Zhang tmp = RREG32_SOC15(HDP, 0, mmHDP_MEM_POWER_CTRL); 1132c6b6a421SHawking Zhang if (tmp & HDP_MEM_POWER_CTRL__IPH_MEM_POWER_LS_EN_MASK) 1133c6b6a421SHawking Zhang *flags |= AMD_CG_SUPPORT_HDP_LS; 1134c6b6a421SHawking Zhang else if (tmp & HDP_MEM_POWER_CTRL__IPH_MEM_POWER_DS_EN_MASK) 1135c6b6a421SHawking Zhang *flags |= AMD_CG_SUPPORT_HDP_DS; 1136c6b6a421SHawking Zhang else if (tmp & HDP_MEM_POWER_CTRL__IPH_MEM_POWER_SD_EN_MASK) 1137c6b6a421SHawking Zhang *flags |= AMD_CG_SUPPORT_HDP_SD; 1138c6b6a421SHawking Zhang 1139c6b6a421SHawking Zhang return; 1140c6b6a421SHawking Zhang } 1141c6b6a421SHawking Zhang 1142c6b6a421SHawking Zhang static const struct amd_ip_funcs nv_common_ip_funcs = { 1143c6b6a421SHawking Zhang .name = "nv_common", 1144c6b6a421SHawking Zhang .early_init = nv_common_early_init, 1145c6b6a421SHawking Zhang .late_init = nv_common_late_init, 1146c6b6a421SHawking Zhang .sw_init = nv_common_sw_init, 1147c6b6a421SHawking Zhang .sw_fini = nv_common_sw_fini, 1148c6b6a421SHawking Zhang .hw_init = nv_common_hw_init, 1149c6b6a421SHawking Zhang .hw_fini = nv_common_hw_fini, 1150c6b6a421SHawking Zhang .suspend = nv_common_suspend, 1151c6b6a421SHawking Zhang .resume = nv_common_resume, 1152c6b6a421SHawking Zhang .is_idle = nv_common_is_idle, 1153c6b6a421SHawking Zhang .wait_for_idle = nv_common_wait_for_idle, 1154c6b6a421SHawking Zhang .soft_reset = nv_common_soft_reset, 1155c6b6a421SHawking Zhang .set_clockgating_state = nv_common_set_clockgating_state, 1156c6b6a421SHawking Zhang .set_powergating_state = nv_common_set_powergating_state, 1157c6b6a421SHawking Zhang .get_clockgating_state = nv_common_get_clockgating_state, 1158c6b6a421SHawking Zhang }; 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