1c6b6a421SHawking Zhang /* 2c6b6a421SHawking Zhang * Copyright 2019 Advanced Micro Devices, Inc. 3c6b6a421SHawking Zhang * 4c6b6a421SHawking Zhang * Permission is hereby granted, free of charge, to any person obtaining a 5c6b6a421SHawking Zhang * copy of this software and associated documentation files (the "Software"), 6c6b6a421SHawking Zhang * to deal in the Software without restriction, including without limitation 7c6b6a421SHawking Zhang * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8c6b6a421SHawking Zhang * and/or sell copies of the Software, and to permit persons to whom the 9c6b6a421SHawking Zhang * Software is furnished to do so, subject to the following conditions: 10c6b6a421SHawking Zhang * 11c6b6a421SHawking Zhang * The above copyright notice and this permission notice shall be included in 12c6b6a421SHawking Zhang * all copies or substantial portions of the Software. 13c6b6a421SHawking Zhang * 14c6b6a421SHawking Zhang * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15c6b6a421SHawking Zhang * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16c6b6a421SHawking Zhang * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17c6b6a421SHawking Zhang * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18c6b6a421SHawking Zhang * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19c6b6a421SHawking Zhang * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20c6b6a421SHawking Zhang * OTHER DEALINGS IN THE SOFTWARE. 21c6b6a421SHawking Zhang * 22c6b6a421SHawking Zhang */ 23c6b6a421SHawking Zhang #include <linux/firmware.h> 24c6b6a421SHawking Zhang #include <linux/slab.h> 25c6b6a421SHawking Zhang #include <linux/module.h> 26e9eea902SAlex Deucher #include <linux/pci.h> 27e9eea902SAlex Deucher 28c6b6a421SHawking Zhang #include "amdgpu.h" 29c6b6a421SHawking Zhang #include "amdgpu_atombios.h" 30c6b6a421SHawking Zhang #include "amdgpu_ih.h" 31c6b6a421SHawking Zhang #include "amdgpu_uvd.h" 32c6b6a421SHawking Zhang #include "amdgpu_vce.h" 33c6b6a421SHawking Zhang #include "amdgpu_ucode.h" 34c6b6a421SHawking Zhang #include "amdgpu_psp.h" 35767acabdSKevin Wang #include "amdgpu_smu.h" 36c6b6a421SHawking Zhang #include "atom.h" 37c6b6a421SHawking Zhang #include "amd_pcie.h" 38c6b6a421SHawking Zhang 39c6b6a421SHawking Zhang #include "gc/gc_10_1_0_offset.h" 40c6b6a421SHawking Zhang #include "gc/gc_10_1_0_sh_mask.h" 41c6b6a421SHawking Zhang #include "hdp/hdp_5_0_0_offset.h" 42c6b6a421SHawking Zhang #include "hdp/hdp_5_0_0_sh_mask.h" 4329bc37b4SAlex Deucher #include "smuio/smuio_11_0_0_offset.h" 443967ae6dSAlex Deucher #include "mp/mp_11_0_offset.h" 45c6b6a421SHawking Zhang 46c6b6a421SHawking Zhang #include "soc15.h" 47c6b6a421SHawking Zhang #include "soc15_common.h" 48c6b6a421SHawking Zhang #include "gmc_v10_0.h" 49c6b6a421SHawking Zhang #include "gfxhub_v2_0.h" 50c6b6a421SHawking Zhang #include "mmhub_v2_0.h" 51bebc0762SHawking Zhang #include "nbio_v2_3.h" 52c6b6a421SHawking Zhang #include "nv.h" 53c6b6a421SHawking Zhang #include "navi10_ih.h" 54c6b6a421SHawking Zhang #include "gfx_v10_0.h" 55c6b6a421SHawking Zhang #include "sdma_v5_0.h" 56157e72e8SLikun Gao #include "sdma_v5_2.h" 57c6b6a421SHawking Zhang #include "vcn_v2_0.h" 585be45a26SLeo Liu #include "jpeg_v2_0.h" 59b8f10585SLeo Liu #include "vcn_v3_0.h" 604d72dd12SLeo Liu #include "jpeg_v3_0.h" 61c6b6a421SHawking Zhang #include "dce_virtual.h" 62c6b6a421SHawking Zhang #include "mes_v10_1.h" 63b05b6903SJiange Zhao #include "mxgpu_nv.h" 64c6b6a421SHawking Zhang 65c6b6a421SHawking Zhang static const struct amd_ip_funcs nv_common_ip_funcs; 66c6b6a421SHawking Zhang 67c6b6a421SHawking Zhang /* 68c6b6a421SHawking Zhang * Indirect registers accessor 69c6b6a421SHawking Zhang */ 70c6b6a421SHawking Zhang static u32 nv_pcie_rreg(struct amdgpu_device *adev, u32 reg) 71c6b6a421SHawking Zhang { 72705a2b5bSHawking Zhang unsigned long address, data; 73bebc0762SHawking Zhang address = adev->nbio.funcs->get_pcie_index_offset(adev); 74bebc0762SHawking Zhang data = adev->nbio.funcs->get_pcie_data_offset(adev); 75c6b6a421SHawking Zhang 76705a2b5bSHawking Zhang return amdgpu_device_indirect_rreg(adev, address, data, reg); 77c6b6a421SHawking Zhang } 78c6b6a421SHawking Zhang 79c6b6a421SHawking Zhang static void nv_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v) 80c6b6a421SHawking Zhang { 81705a2b5bSHawking Zhang unsigned long address, data; 82c6b6a421SHawking Zhang 83bebc0762SHawking Zhang address = adev->nbio.funcs->get_pcie_index_offset(adev); 84bebc0762SHawking Zhang data = adev->nbio.funcs->get_pcie_data_offset(adev); 85c6b6a421SHawking Zhang 86705a2b5bSHawking Zhang amdgpu_device_indirect_wreg(adev, address, data, reg, v); 87c6b6a421SHawking Zhang } 88c6b6a421SHawking Zhang 894922f1bcSJohn Clements static u64 nv_pcie_rreg64(struct amdgpu_device *adev, u32 reg) 904922f1bcSJohn Clements { 91705a2b5bSHawking Zhang unsigned long address, data; 924922f1bcSJohn Clements address = adev->nbio.funcs->get_pcie_index_offset(adev); 934922f1bcSJohn Clements data = adev->nbio.funcs->get_pcie_data_offset(adev); 944922f1bcSJohn Clements 95705a2b5bSHawking Zhang return amdgpu_device_indirect_rreg64(adev, address, data, reg); 964922f1bcSJohn Clements } 974922f1bcSJohn Clements 984922f1bcSJohn Clements static void nv_pcie_wreg64(struct amdgpu_device *adev, u32 reg, u64 v) 994922f1bcSJohn Clements { 100705a2b5bSHawking Zhang unsigned long address, data; 1014922f1bcSJohn Clements 1024922f1bcSJohn Clements address = adev->nbio.funcs->get_pcie_index_offset(adev); 1034922f1bcSJohn Clements data = adev->nbio.funcs->get_pcie_data_offset(adev); 1044922f1bcSJohn Clements 105705a2b5bSHawking Zhang amdgpu_device_indirect_wreg64(adev, address, data, reg, v); 1064922f1bcSJohn Clements } 1074922f1bcSJohn Clements 108c6b6a421SHawking Zhang static u32 nv_didt_rreg(struct amdgpu_device *adev, u32 reg) 109c6b6a421SHawking Zhang { 110c6b6a421SHawking Zhang unsigned long flags, address, data; 111c6b6a421SHawking Zhang u32 r; 112c6b6a421SHawking Zhang 113c6b6a421SHawking Zhang address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX); 114c6b6a421SHawking Zhang data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA); 115c6b6a421SHawking Zhang 116c6b6a421SHawking Zhang spin_lock_irqsave(&adev->didt_idx_lock, flags); 117c6b6a421SHawking Zhang WREG32(address, (reg)); 118c6b6a421SHawking Zhang r = RREG32(data); 119c6b6a421SHawking Zhang spin_unlock_irqrestore(&adev->didt_idx_lock, flags); 120c6b6a421SHawking Zhang return r; 121c6b6a421SHawking Zhang } 122c6b6a421SHawking Zhang 123c6b6a421SHawking Zhang static void nv_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v) 124c6b6a421SHawking Zhang { 125c6b6a421SHawking Zhang unsigned long flags, address, data; 126c6b6a421SHawking Zhang 127c6b6a421SHawking Zhang address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX); 128c6b6a421SHawking Zhang data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA); 129c6b6a421SHawking Zhang 130c6b6a421SHawking Zhang spin_lock_irqsave(&adev->didt_idx_lock, flags); 131c6b6a421SHawking Zhang WREG32(address, (reg)); 132c6b6a421SHawking Zhang WREG32(data, (v)); 133c6b6a421SHawking Zhang spin_unlock_irqrestore(&adev->didt_idx_lock, flags); 134c6b6a421SHawking Zhang } 135c6b6a421SHawking Zhang 136c6b6a421SHawking Zhang static u32 nv_get_config_memsize(struct amdgpu_device *adev) 137c6b6a421SHawking Zhang { 138bebc0762SHawking Zhang return adev->nbio.funcs->get_memsize(adev); 139c6b6a421SHawking Zhang } 140c6b6a421SHawking Zhang 141c6b6a421SHawking Zhang static u32 nv_get_xclk(struct amdgpu_device *adev) 142c6b6a421SHawking Zhang { 143462a70d8STao Zhou return adev->clock.spll.reference_freq; 144c6b6a421SHawking Zhang } 145c6b6a421SHawking Zhang 146c6b6a421SHawking Zhang 147c6b6a421SHawking Zhang void nv_grbm_select(struct amdgpu_device *adev, 148c6b6a421SHawking Zhang u32 me, u32 pipe, u32 queue, u32 vmid) 149c6b6a421SHawking Zhang { 150c6b6a421SHawking Zhang u32 grbm_gfx_cntl = 0; 151c6b6a421SHawking Zhang grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, PIPEID, pipe); 152c6b6a421SHawking Zhang grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, MEID, me); 153c6b6a421SHawking Zhang grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, VMID, vmid); 154c6b6a421SHawking Zhang grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, QUEUEID, queue); 155c6b6a421SHawking Zhang 156c6b6a421SHawking Zhang WREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_CNTL), grbm_gfx_cntl); 157c6b6a421SHawking Zhang } 158c6b6a421SHawking Zhang 159c6b6a421SHawking Zhang static void nv_vga_set_state(struct amdgpu_device *adev, bool state) 160c6b6a421SHawking Zhang { 161c6b6a421SHawking Zhang /* todo */ 162c6b6a421SHawking Zhang } 163c6b6a421SHawking Zhang 164c6b6a421SHawking Zhang static bool nv_read_disabled_bios(struct amdgpu_device *adev) 165c6b6a421SHawking Zhang { 166c6b6a421SHawking Zhang /* todo */ 167c6b6a421SHawking Zhang return false; 168c6b6a421SHawking Zhang } 169c6b6a421SHawking Zhang 170c6b6a421SHawking Zhang static bool nv_read_bios_from_rom(struct amdgpu_device *adev, 171c6b6a421SHawking Zhang u8 *bios, u32 length_bytes) 172c6b6a421SHawking Zhang { 17329bc37b4SAlex Deucher u32 *dw_ptr; 17429bc37b4SAlex Deucher u32 i, length_dw; 17529bc37b4SAlex Deucher 17629bc37b4SAlex Deucher if (bios == NULL) 177c6b6a421SHawking Zhang return false; 17829bc37b4SAlex Deucher if (length_bytes == 0) 17929bc37b4SAlex Deucher return false; 18029bc37b4SAlex Deucher /* APU vbios image is part of sbios image */ 18129bc37b4SAlex Deucher if (adev->flags & AMD_IS_APU) 18229bc37b4SAlex Deucher return false; 18329bc37b4SAlex Deucher 18429bc37b4SAlex Deucher dw_ptr = (u32 *)bios; 18529bc37b4SAlex Deucher length_dw = ALIGN(length_bytes, 4) / 4; 18629bc37b4SAlex Deucher 18729bc37b4SAlex Deucher /* set rom index to 0 */ 18829bc37b4SAlex Deucher WREG32(SOC15_REG_OFFSET(SMUIO, 0, mmROM_INDEX), 0); 18929bc37b4SAlex Deucher /* read out the rom data */ 19029bc37b4SAlex Deucher for (i = 0; i < length_dw; i++) 19129bc37b4SAlex Deucher dw_ptr[i] = RREG32(SOC15_REG_OFFSET(SMUIO, 0, mmROM_DATA)); 19229bc37b4SAlex Deucher 19329bc37b4SAlex Deucher return true; 194c6b6a421SHawking Zhang } 195c6b6a421SHawking Zhang 196c6b6a421SHawking Zhang static struct soc15_allowed_register_entry nv_allowed_read_registers[] = { 197c6b6a421SHawking Zhang { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS)}, 198c6b6a421SHawking Zhang { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS2)}, 199c6b6a421SHawking Zhang { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE0)}, 200c6b6a421SHawking Zhang { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE1)}, 201c6b6a421SHawking Zhang { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE2)}, 202c6b6a421SHawking Zhang { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE3)}, 203c6b6a421SHawking Zhang { SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_STATUS_REG)}, 204c6b6a421SHawking Zhang { SOC15_REG_ENTRY(SDMA1, 0, mmSDMA1_STATUS_REG)}, 205c6b6a421SHawking Zhang { SOC15_REG_ENTRY(GC, 0, mmCP_STAT)}, 206c6b6a421SHawking Zhang { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT1)}, 207c6b6a421SHawking Zhang { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT2)}, 208c6b6a421SHawking Zhang { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT3)}, 209c6b6a421SHawking Zhang { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_BUSY_STAT)}, 210c6b6a421SHawking Zhang { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STALLED_STAT1)}, 211c6b6a421SHawking Zhang { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STATUS)}, 212664fe85aSMarek Olšák { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_BUSY_STAT)}, 213c6b6a421SHawking Zhang { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STALLED_STAT1)}, 214c6b6a421SHawking Zhang { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STATUS)}, 215c6b6a421SHawking Zhang { SOC15_REG_ENTRY(GC, 0, mmGB_ADDR_CONFIG)}, 216c6b6a421SHawking Zhang }; 217c6b6a421SHawking Zhang 218c6b6a421SHawking Zhang static uint32_t nv_read_indexed_register(struct amdgpu_device *adev, u32 se_num, 219c6b6a421SHawking Zhang u32 sh_num, u32 reg_offset) 220c6b6a421SHawking Zhang { 221c6b6a421SHawking Zhang uint32_t val; 222c6b6a421SHawking Zhang 223c6b6a421SHawking Zhang mutex_lock(&adev->grbm_idx_mutex); 224c6b6a421SHawking Zhang if (se_num != 0xffffffff || sh_num != 0xffffffff) 225c6b6a421SHawking Zhang amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff); 226c6b6a421SHawking Zhang 227c6b6a421SHawking Zhang val = RREG32(reg_offset); 228c6b6a421SHawking Zhang 229c6b6a421SHawking Zhang if (se_num != 0xffffffff || sh_num != 0xffffffff) 230c6b6a421SHawking Zhang amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 231c6b6a421SHawking Zhang mutex_unlock(&adev->grbm_idx_mutex); 232c6b6a421SHawking Zhang return val; 233c6b6a421SHawking Zhang } 234c6b6a421SHawking Zhang 235c6b6a421SHawking Zhang static uint32_t nv_get_register_value(struct amdgpu_device *adev, 236c6b6a421SHawking Zhang bool indexed, u32 se_num, 237c6b6a421SHawking Zhang u32 sh_num, u32 reg_offset) 238c6b6a421SHawking Zhang { 239c6b6a421SHawking Zhang if (indexed) { 240c6b6a421SHawking Zhang return nv_read_indexed_register(adev, se_num, sh_num, reg_offset); 241c6b6a421SHawking Zhang } else { 242c6b6a421SHawking Zhang if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG)) 243c6b6a421SHawking Zhang return adev->gfx.config.gb_addr_config; 244c6b6a421SHawking Zhang return RREG32(reg_offset); 245c6b6a421SHawking Zhang } 246c6b6a421SHawking Zhang } 247c6b6a421SHawking Zhang 248c6b6a421SHawking Zhang static int nv_read_register(struct amdgpu_device *adev, u32 se_num, 249c6b6a421SHawking Zhang u32 sh_num, u32 reg_offset, u32 *value) 250c6b6a421SHawking Zhang { 251c6b6a421SHawking Zhang uint32_t i; 252c6b6a421SHawking Zhang struct soc15_allowed_register_entry *en; 253c6b6a421SHawking Zhang 254c6b6a421SHawking Zhang *value = 0; 255c6b6a421SHawking Zhang for (i = 0; i < ARRAY_SIZE(nv_allowed_read_registers); i++) { 256c6b6a421SHawking Zhang en = &nv_allowed_read_registers[i]; 257c6b6a421SHawking Zhang if (reg_offset != 258c6b6a421SHawking Zhang (adev->reg_offset[en->hwip][en->inst][en->seg] + en->reg_offset)) 259c6b6a421SHawking Zhang continue; 260c6b6a421SHawking Zhang 261c6b6a421SHawking Zhang *value = nv_get_register_value(adev, 262c6b6a421SHawking Zhang nv_allowed_read_registers[i].grbm_indexed, 263c6b6a421SHawking Zhang se_num, sh_num, reg_offset); 264c6b6a421SHawking Zhang return 0; 265c6b6a421SHawking Zhang } 266c6b6a421SHawking Zhang return -EINVAL; 267c6b6a421SHawking Zhang } 268c6b6a421SHawking Zhang 2693e2bb60aSKevin Wang static int nv_asic_mode1_reset(struct amdgpu_device *adev) 2703e2bb60aSKevin Wang { 2713e2bb60aSKevin Wang u32 i; 2723e2bb60aSKevin Wang int ret = 0; 2733e2bb60aSKevin Wang 2743e2bb60aSKevin Wang amdgpu_atombios_scratch_regs_engine_hung(adev, true); 2753e2bb60aSKevin Wang 2763e2bb60aSKevin Wang /* disable BM */ 2773e2bb60aSKevin Wang pci_clear_master(adev->pdev); 2783e2bb60aSKevin Wang 279c1dd4aa6SAndrey Grodzovsky amdgpu_device_cache_pci_state(adev->pdev); 2803e2bb60aSKevin Wang 281311531f0SWenhui Sheng if (amdgpu_dpm_is_mode1_reset_supported(adev)) { 282311531f0SWenhui Sheng dev_info(adev->dev, "GPU smu mode1 reset\n"); 283311531f0SWenhui Sheng ret = amdgpu_dpm_mode1_reset(adev); 284311531f0SWenhui Sheng } else { 285311531f0SWenhui Sheng dev_info(adev->dev, "GPU psp mode1 reset\n"); 2863e2bb60aSKevin Wang ret = psp_gpu_reset(adev); 287311531f0SWenhui Sheng } 288311531f0SWenhui Sheng 2893e2bb60aSKevin Wang if (ret) 2903e2bb60aSKevin Wang dev_err(adev->dev, "GPU mode1 reset failed\n"); 291c1dd4aa6SAndrey Grodzovsky amdgpu_device_load_pci_state(adev->pdev); 2923e2bb60aSKevin Wang 2933e2bb60aSKevin Wang /* wait for asic to come out of reset */ 2943e2bb60aSKevin Wang for (i = 0; i < adev->usec_timeout; i++) { 295bebc0762SHawking Zhang u32 memsize = adev->nbio.funcs->get_memsize(adev); 2963e2bb60aSKevin Wang 2973e2bb60aSKevin Wang if (memsize != 0xffffffff) 2983e2bb60aSKevin Wang break; 2993e2bb60aSKevin Wang udelay(1); 3003e2bb60aSKevin Wang } 3013e2bb60aSKevin Wang 3023e2bb60aSKevin Wang amdgpu_atombios_scratch_regs_engine_hung(adev, false); 3033e2bb60aSKevin Wang 3043e2bb60aSKevin Wang return ret; 3053e2bb60aSKevin Wang } 3062ddc6c3eSAlex Deucher 307ac742616SAlex Deucher static bool nv_asic_supports_baco(struct amdgpu_device *adev) 308ac742616SAlex Deucher { 309ac742616SAlex Deucher struct smu_context *smu = &adev->smu; 310ac742616SAlex Deucher 311ac742616SAlex Deucher if (smu_baco_is_support(smu)) 312ac742616SAlex Deucher return true; 313ac742616SAlex Deucher else 314ac742616SAlex Deucher return false; 315ac742616SAlex Deucher } 316ac742616SAlex Deucher 3172ddc6c3eSAlex Deucher static enum amd_reset_method 3182ddc6c3eSAlex Deucher nv_asic_reset_method(struct amdgpu_device *adev) 3192ddc6c3eSAlex Deucher { 3202ddc6c3eSAlex Deucher struct smu_context *smu = &adev->smu; 3212ddc6c3eSAlex Deucher 322273da6ffSWenhui Sheng if (amdgpu_reset_method == AMD_RESET_METHOD_MODE1 || 323273da6ffSWenhui Sheng amdgpu_reset_method == AMD_RESET_METHOD_BACO) 324273da6ffSWenhui Sheng return amdgpu_reset_method; 325273da6ffSWenhui Sheng 326273da6ffSWenhui Sheng if (amdgpu_reset_method != -1) 327273da6ffSWenhui Sheng dev_warn(adev->dev, "Specified reset method:%d isn't supported, using AUTO instead.\n", 328273da6ffSWenhui Sheng amdgpu_reset_method); 329273da6ffSWenhui Sheng 330ca6fd7a6SLikun Gao switch (adev->asic_type) { 331ca6fd7a6SLikun Gao case CHIP_SIENNA_CICHLID: 33222dd44f4SJiansong Chen case CHIP_NAVY_FLOUNDER: 333ca6fd7a6SLikun Gao return AMD_RESET_METHOD_MODE1; 334ca6fd7a6SLikun Gao default: 335311531f0SWenhui Sheng if (smu_baco_is_support(smu)) 3362ddc6c3eSAlex Deucher return AMD_RESET_METHOD_BACO; 3372ddc6c3eSAlex Deucher else 3382ddc6c3eSAlex Deucher return AMD_RESET_METHOD_MODE1; 3392ddc6c3eSAlex Deucher } 340ca6fd7a6SLikun Gao } 3412ddc6c3eSAlex Deucher 342c6b6a421SHawking Zhang static int nv_asic_reset(struct amdgpu_device *adev) 343c6b6a421SHawking Zhang { 344767acabdSKevin Wang int ret = 0; 345767acabdSKevin Wang struct smu_context *smu = &adev->smu; 346c6b6a421SHawking Zhang 347e3526257SMonk Liu if (nv_asic_reset_method(adev) == AMD_RESET_METHOD_BACO) { 34811043b7aSAlex Deucher dev_info(adev->dev, "BACO reset\n"); 349311531f0SWenhui Sheng 35011520f27SAlex Deucher ret = smu_baco_enter(smu); 35111520f27SAlex Deucher if (ret) 35211520f27SAlex Deucher return ret; 35311520f27SAlex Deucher ret = smu_baco_exit(smu); 35411520f27SAlex Deucher if (ret) 35511520f27SAlex Deucher return ret; 35611043b7aSAlex Deucher } else { 35711043b7aSAlex Deucher dev_info(adev->dev, "MODE1 reset\n"); 3583e2bb60aSKevin Wang ret = nv_asic_mode1_reset(adev); 35911043b7aSAlex Deucher } 360767acabdSKevin Wang 361767acabdSKevin Wang return ret; 362c6b6a421SHawking Zhang } 363c6b6a421SHawking Zhang 364c6b6a421SHawking Zhang static int nv_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk) 365c6b6a421SHawking Zhang { 366c6b6a421SHawking Zhang /* todo */ 367c6b6a421SHawking Zhang return 0; 368c6b6a421SHawking Zhang } 369c6b6a421SHawking Zhang 370c6b6a421SHawking Zhang static int nv_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk) 371c6b6a421SHawking Zhang { 372c6b6a421SHawking Zhang /* todo */ 373c6b6a421SHawking Zhang return 0; 374c6b6a421SHawking Zhang } 375c6b6a421SHawking Zhang 376c6b6a421SHawking Zhang static void nv_pcie_gen3_enable(struct amdgpu_device *adev) 377c6b6a421SHawking Zhang { 378c6b6a421SHawking Zhang if (pci_is_root_bus(adev->pdev->bus)) 379c6b6a421SHawking Zhang return; 380c6b6a421SHawking Zhang 381c6b6a421SHawking Zhang if (amdgpu_pcie_gen2 == 0) 382c6b6a421SHawking Zhang return; 383c6b6a421SHawking Zhang 384c6b6a421SHawking Zhang if (!(adev->pm.pcie_gen_mask & (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 | 385c6b6a421SHawking Zhang CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3))) 386c6b6a421SHawking Zhang return; 387c6b6a421SHawking Zhang 388c6b6a421SHawking Zhang /* todo */ 389c6b6a421SHawking Zhang } 390c6b6a421SHawking Zhang 391c6b6a421SHawking Zhang static void nv_program_aspm(struct amdgpu_device *adev) 392c6b6a421SHawking Zhang { 393c6b6a421SHawking Zhang 394c6b6a421SHawking Zhang if (amdgpu_aspm == 0) 395c6b6a421SHawking Zhang return; 396c6b6a421SHawking Zhang 397c6b6a421SHawking Zhang /* todo */ 398c6b6a421SHawking Zhang } 399c6b6a421SHawking Zhang 400c6b6a421SHawking Zhang static void nv_enable_doorbell_aperture(struct amdgpu_device *adev, 401c6b6a421SHawking Zhang bool enable) 402c6b6a421SHawking Zhang { 403bebc0762SHawking Zhang adev->nbio.funcs->enable_doorbell_aperture(adev, enable); 404bebc0762SHawking Zhang adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, enable); 405c6b6a421SHawking Zhang } 406c6b6a421SHawking Zhang 407c6b6a421SHawking Zhang static const struct amdgpu_ip_block_version nv_common_ip_block = 408c6b6a421SHawking Zhang { 409c6b6a421SHawking Zhang .type = AMD_IP_BLOCK_TYPE_COMMON, 410c6b6a421SHawking Zhang .major = 1, 411c6b6a421SHawking Zhang .minor = 0, 412c6b6a421SHawking Zhang .rev = 0, 413c6b6a421SHawking Zhang .funcs = &nv_common_ip_funcs, 414c6b6a421SHawking Zhang }; 415c6b6a421SHawking Zhang 416b5c73856SXiaojie Yuan static int nv_reg_base_init(struct amdgpu_device *adev) 417c6b6a421SHawking Zhang { 418b5c73856SXiaojie Yuan int r; 419b5c73856SXiaojie Yuan 420b5c73856SXiaojie Yuan if (amdgpu_discovery) { 421b5c73856SXiaojie Yuan r = amdgpu_discovery_reg_base_init(adev); 422b5c73856SXiaojie Yuan if (r) { 423b5c73856SXiaojie Yuan DRM_WARN("failed to init reg base from ip discovery table, " 424b5c73856SXiaojie Yuan "fallback to legacy init method\n"); 425b5c73856SXiaojie Yuan goto legacy_init; 426b5c73856SXiaojie Yuan } 427b5c73856SXiaojie Yuan 428b5c73856SXiaojie Yuan return 0; 429b5c73856SXiaojie Yuan } 430b5c73856SXiaojie Yuan 431b5c73856SXiaojie Yuan legacy_init: 432c6b6a421SHawking Zhang switch (adev->asic_type) { 433c6b6a421SHawking Zhang case CHIP_NAVI10: 434c6b6a421SHawking Zhang navi10_reg_base_init(adev); 435c6b6a421SHawking Zhang break; 436a0f6d926SXiaojie Yuan case CHIP_NAVI14: 437a0f6d926SXiaojie Yuan navi14_reg_base_init(adev); 438a0f6d926SXiaojie Yuan break; 43903d0a073SXiaojie Yuan case CHIP_NAVI12: 44003d0a073SXiaojie Yuan navi12_reg_base_init(adev); 44103d0a073SXiaojie Yuan break; 442dccdbf3fSLikun Gao case CHIP_SIENNA_CICHLID: 443c8c959f6SJiansong Chen case CHIP_NAVY_FLOUNDER: 444dccdbf3fSLikun Gao sienna_cichlid_reg_base_init(adev); 445dccdbf3fSLikun Gao break; 446c6b6a421SHawking Zhang default: 447c6b6a421SHawking Zhang return -EINVAL; 448c6b6a421SHawking Zhang } 449c6b6a421SHawking Zhang 450b5c73856SXiaojie Yuan return 0; 451b5c73856SXiaojie Yuan } 452b5c73856SXiaojie Yuan 453c1299461SWenhui Sheng void nv_set_virt_ops(struct amdgpu_device *adev) 454c1299461SWenhui Sheng { 455c1299461SWenhui Sheng adev->virt.ops = &xgpu_nv_virt_ops; 456c1299461SWenhui Sheng } 457c1299461SWenhui Sheng 458b5c73856SXiaojie Yuan int nv_set_ip_blocks(struct amdgpu_device *adev) 459b5c73856SXiaojie Yuan { 460b5c73856SXiaojie Yuan int r; 461b5c73856SXiaojie Yuan 462122078deSMonk Liu adev->nbio.funcs = &nbio_v2_3_funcs; 463122078deSMonk Liu adev->nbio.hdp_flush_reg = &nbio_v2_3_hdp_flush_reg; 464122078deSMonk Liu 465c652923aSJohn Clements if (adev->asic_type == CHIP_SIENNA_CICHLID) 466c652923aSJohn Clements adev->gmc.xgmi.supported = true; 467c652923aSJohn Clements 468b5c73856SXiaojie Yuan /* Set IP register base before any HW register access */ 469b5c73856SXiaojie Yuan r = nv_reg_base_init(adev); 470b5c73856SXiaojie Yuan if (r) 471b5c73856SXiaojie Yuan return r; 472b5c73856SXiaojie Yuan 473c6b6a421SHawking Zhang switch (adev->asic_type) { 474c6b6a421SHawking Zhang case CHIP_NAVI10: 475d1daf850SAlex Deucher case CHIP_NAVI14: 476c6b6a421SHawking Zhang amdgpu_device_ip_block_add(adev, &nv_common_ip_block); 477c6b6a421SHawking Zhang amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block); 478c6b6a421SHawking Zhang amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block); 479c6b6a421SHawking Zhang amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block); 480c6b6a421SHawking Zhang if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP && 4819530273eSEvan Quan !amdgpu_sriov_vf(adev)) 482c6b6a421SHawking Zhang amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 483c6b6a421SHawking Zhang if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) 484c6b6a421SHawking Zhang amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block); 485f8a7976bSAlex Deucher #if defined(CONFIG_DRM_AMD_DC) 486b4f199c7SHarry Wentland else if (amdgpu_device_has_dc_support(adev)) 487b4f199c7SHarry Wentland amdgpu_device_ip_block_add(adev, &dm_ip_block); 488f8a7976bSAlex Deucher #endif 489c6b6a421SHawking Zhang amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block); 490c6b6a421SHawking Zhang amdgpu_device_ip_block_add(adev, &sdma_v5_0_ip_block); 491c6b6a421SHawking Zhang if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT && 4929530273eSEvan Quan !amdgpu_sriov_vf(adev)) 493c6b6a421SHawking Zhang amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 494c6b6a421SHawking Zhang amdgpu_device_ip_block_add(adev, &vcn_v2_0_ip_block); 4955be45a26SLeo Liu amdgpu_device_ip_block_add(adev, &jpeg_v2_0_ip_block); 496c6b6a421SHawking Zhang if (adev->enable_mes) 497c6b6a421SHawking Zhang amdgpu_device_ip_block_add(adev, &mes_v10_1_ip_block); 498c6b6a421SHawking Zhang break; 49944e9e7c9SXiaojie Yuan case CHIP_NAVI12: 50044e9e7c9SXiaojie Yuan amdgpu_device_ip_block_add(adev, &nv_common_ip_block); 50144e9e7c9SXiaojie Yuan amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block); 50244e9e7c9SXiaojie Yuan amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block); 5036b66ae2eSXiaojie Yuan amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block); 50479bebabbSMonk Liu if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) 5057f47efebSXiaojie Yuan amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 50679902029SXiaojie Yuan if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) 50779902029SXiaojie Yuan amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block); 50820c14ee1SPetr Cvek #if defined(CONFIG_DRM_AMD_DC) 509078655d9SLeo Li else if (amdgpu_device_has_dc_support(adev)) 510078655d9SLeo Li amdgpu_device_ip_block_add(adev, &dm_ip_block); 51120c14ee1SPetr Cvek #endif 51244e9e7c9SXiaojie Yuan amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block); 51344e9e7c9SXiaojie Yuan amdgpu_device_ip_block_add(adev, &sdma_v5_0_ip_block); 5147f47efebSXiaojie Yuan if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT && 5159530273eSEvan Quan !amdgpu_sriov_vf(adev)) 5167f47efebSXiaojie Yuan amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 5171fbed280SBoyuan Zhang amdgpu_device_ip_block_add(adev, &vcn_v2_0_ip_block); 518fe442491SMonk Liu if (!amdgpu_sriov_vf(adev)) 5195be45a26SLeo Liu amdgpu_device_ip_block_add(adev, &jpeg_v2_0_ip_block); 52044e9e7c9SXiaojie Yuan break; 5212e1ba10eSLikun Gao case CHIP_SIENNA_CICHLID: 5222e1ba10eSLikun Gao amdgpu_device_ip_block_add(adev, &nv_common_ip_block); 5230b3df16bSLikun Gao amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block); 524757b3af8SLikun Gao amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block); 52556304e72SLikun Gao if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) 5265aa02350SLikun Gao amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block); 527b07e5c60SLikun Gao if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP && 52838d5bbefSshaoyunl is_support_sw_smu(adev) && !amdgpu_sriov_vf(adev)) 529b07e5c60SLikun Gao amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 5309a986760SLikun Gao if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) 5319a986760SLikun Gao amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block); 532464ab91aSBhawanpreet Lakha #if defined(CONFIG_DRM_AMD_DC) 533464ab91aSBhawanpreet Lakha else if (amdgpu_device_has_dc_support(adev)) 534464ab91aSBhawanpreet Lakha amdgpu_device_ip_block_add(adev, &dm_ip_block); 535464ab91aSBhawanpreet Lakha #endif 536933c8a93SLikun Gao amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block); 537157e72e8SLikun Gao amdgpu_device_ip_block_add(adev, &sdma_v5_2_ip_block); 538b8f10585SLeo Liu amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block); 539c45fbe1bSJack Zhang if (!amdgpu_sriov_vf(adev)) 5404d72dd12SLeo Liu amdgpu_device_ip_block_add(adev, &jpeg_v3_0_ip_block); 541c45fbe1bSJack Zhang 542a346ef86SJack Xiao if (adev->enable_mes) 543a346ef86SJack Xiao amdgpu_device_ip_block_add(adev, &mes_v10_1_ip_block); 5442e1ba10eSLikun Gao break; 5458515e0a4SJiansong Chen case CHIP_NAVY_FLOUNDER: 5468515e0a4SJiansong Chen amdgpu_device_ip_block_add(adev, &nv_common_ip_block); 547fc8f07daSJiansong Chen amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block); 548026c396bSJiansong Chen amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block); 5497420eab2SJiansong Chen if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) 5507420eab2SJiansong Chen amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block); 5517420eab2SJiansong Chen if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP && 5527420eab2SJiansong Chen is_support_sw_smu(adev)) 5537420eab2SJiansong Chen amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 5545404f073SJiansong Chen if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) 5555404f073SJiansong Chen amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block); 556a6c5308fSBhawanpreet Lakha #if defined(CONFIG_DRM_AMD_DC) 557a6c5308fSBhawanpreet Lakha else if (amdgpu_device_has_dc_support(adev)) 558a6c5308fSBhawanpreet Lakha amdgpu_device_ip_block_add(adev, &dm_ip_block); 559a6c5308fSBhawanpreet Lakha #endif 560885eb3faSJiansong Chen amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block); 561df2d15dfSJiansong Chen amdgpu_device_ip_block_add(adev, &sdma_v5_2_ip_block); 562290b4ad5SBoyuan Zhang amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block); 563290b4ad5SBoyuan Zhang amdgpu_device_ip_block_add(adev, &jpeg_v3_0_ip_block); 564f4497d10SJiansong Chen if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT && 565f4497d10SJiansong Chen is_support_sw_smu(adev)) 566f4497d10SJiansong Chen amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 5678515e0a4SJiansong Chen break; 568c6b6a421SHawking Zhang default: 569c6b6a421SHawking Zhang return -EINVAL; 570c6b6a421SHawking Zhang } 571c6b6a421SHawking Zhang 572c6b6a421SHawking Zhang return 0; 573c6b6a421SHawking Zhang } 574c6b6a421SHawking Zhang 575c6b6a421SHawking Zhang static uint32_t nv_get_rev_id(struct amdgpu_device *adev) 576c6b6a421SHawking Zhang { 577bebc0762SHawking Zhang return adev->nbio.funcs->get_rev_id(adev); 578c6b6a421SHawking Zhang } 579c6b6a421SHawking Zhang 580c6b6a421SHawking Zhang static void nv_flush_hdp(struct amdgpu_device *adev, struct amdgpu_ring *ring) 581c6b6a421SHawking Zhang { 582bebc0762SHawking Zhang adev->nbio.funcs->hdp_flush(adev, ring); 583c6b6a421SHawking Zhang } 584c6b6a421SHawking Zhang 585c6b6a421SHawking Zhang static void nv_invalidate_hdp(struct amdgpu_device *adev, 586c6b6a421SHawking Zhang struct amdgpu_ring *ring) 587c6b6a421SHawking Zhang { 588c6b6a421SHawking Zhang if (!ring || !ring->funcs->emit_wreg) { 58978f0aef1SStanley.Yang WREG32_SOC15_NO_KIQ(HDP, 0, mmHDP_READ_CACHE_INVALIDATE, 1); 590c6b6a421SHawking Zhang } else { 591c6b6a421SHawking Zhang amdgpu_ring_emit_wreg(ring, SOC15_REG_OFFSET( 592c6b6a421SHawking Zhang HDP, 0, mmHDP_READ_CACHE_INVALIDATE), 1); 593c6b6a421SHawking Zhang } 594c6b6a421SHawking Zhang } 595c6b6a421SHawking Zhang 596c6b6a421SHawking Zhang static bool nv_need_full_reset(struct amdgpu_device *adev) 597c6b6a421SHawking Zhang { 598c6b6a421SHawking Zhang return true; 599c6b6a421SHawking Zhang } 600c6b6a421SHawking Zhang 601c6b6a421SHawking Zhang static bool nv_need_reset_on_init(struct amdgpu_device *adev) 602c6b6a421SHawking Zhang { 603c6b6a421SHawking Zhang u32 sol_reg; 604c6b6a421SHawking Zhang 605c6b6a421SHawking Zhang if (adev->flags & AMD_IS_APU) 606c6b6a421SHawking Zhang return false; 607c6b6a421SHawking Zhang 608c6b6a421SHawking Zhang /* Check sOS sign of life register to confirm sys driver and sOS 609c6b6a421SHawking Zhang * are already been loaded. 610c6b6a421SHawking Zhang */ 611c6b6a421SHawking Zhang sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81); 612c6b6a421SHawking Zhang if (sol_reg) 613c6b6a421SHawking Zhang return true; 6143967ae6dSAlex Deucher 615c6b6a421SHawking Zhang return false; 616c6b6a421SHawking Zhang } 617c6b6a421SHawking Zhang 6182af81531SKevin Wang static uint64_t nv_get_pcie_replay_count(struct amdgpu_device *adev) 6192af81531SKevin Wang { 6202af81531SKevin Wang 6212af81531SKevin Wang /* TODO 6222af81531SKevin Wang * dummy implement for pcie_replay_count sysfs interface 6232af81531SKevin Wang * */ 6242af81531SKevin Wang 6252af81531SKevin Wang return 0; 6262af81531SKevin Wang } 6272af81531SKevin Wang 628c6b6a421SHawking Zhang static void nv_init_doorbell_index(struct amdgpu_device *adev) 629c6b6a421SHawking Zhang { 630c6b6a421SHawking Zhang adev->doorbell_index.kiq = AMDGPU_NAVI10_DOORBELL_KIQ; 631c6b6a421SHawking Zhang adev->doorbell_index.mec_ring0 = AMDGPU_NAVI10_DOORBELL_MEC_RING0; 632c6b6a421SHawking Zhang adev->doorbell_index.mec_ring1 = AMDGPU_NAVI10_DOORBELL_MEC_RING1; 633c6b6a421SHawking Zhang adev->doorbell_index.mec_ring2 = AMDGPU_NAVI10_DOORBELL_MEC_RING2; 634c6b6a421SHawking Zhang adev->doorbell_index.mec_ring3 = AMDGPU_NAVI10_DOORBELL_MEC_RING3; 635c6b6a421SHawking Zhang adev->doorbell_index.mec_ring4 = AMDGPU_NAVI10_DOORBELL_MEC_RING4; 636c6b6a421SHawking Zhang adev->doorbell_index.mec_ring5 = AMDGPU_NAVI10_DOORBELL_MEC_RING5; 637c6b6a421SHawking Zhang adev->doorbell_index.mec_ring6 = AMDGPU_NAVI10_DOORBELL_MEC_RING6; 638c6b6a421SHawking Zhang adev->doorbell_index.mec_ring7 = AMDGPU_NAVI10_DOORBELL_MEC_RING7; 639c6b6a421SHawking Zhang adev->doorbell_index.userqueue_start = AMDGPU_NAVI10_DOORBELL_USERQUEUE_START; 640c6b6a421SHawking Zhang adev->doorbell_index.userqueue_end = AMDGPU_NAVI10_DOORBELL_USERQUEUE_END; 641c6b6a421SHawking Zhang adev->doorbell_index.gfx_ring0 = AMDGPU_NAVI10_DOORBELL_GFX_RING0; 642c6b6a421SHawking Zhang adev->doorbell_index.gfx_ring1 = AMDGPU_NAVI10_DOORBELL_GFX_RING1; 64320519232SJack Xiao adev->doorbell_index.mes_ring = AMDGPU_NAVI10_DOORBELL_MES_RING; 644c6b6a421SHawking Zhang adev->doorbell_index.sdma_engine[0] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE0; 645c6b6a421SHawking Zhang adev->doorbell_index.sdma_engine[1] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE1; 646157e72e8SLikun Gao adev->doorbell_index.sdma_engine[2] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE2; 647157e72e8SLikun Gao adev->doorbell_index.sdma_engine[3] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE3; 648c6b6a421SHawking Zhang adev->doorbell_index.ih = AMDGPU_NAVI10_DOORBELL_IH; 649c6b6a421SHawking Zhang adev->doorbell_index.vcn.vcn_ring0_1 = AMDGPU_NAVI10_DOORBELL64_VCN0_1; 650c6b6a421SHawking Zhang adev->doorbell_index.vcn.vcn_ring2_3 = AMDGPU_NAVI10_DOORBELL64_VCN2_3; 651c6b6a421SHawking Zhang adev->doorbell_index.vcn.vcn_ring4_5 = AMDGPU_NAVI10_DOORBELL64_VCN4_5; 652c6b6a421SHawking Zhang adev->doorbell_index.vcn.vcn_ring6_7 = AMDGPU_NAVI10_DOORBELL64_VCN6_7; 653c6b6a421SHawking Zhang adev->doorbell_index.first_non_cp = AMDGPU_NAVI10_DOORBELL64_FIRST_NON_CP; 654c6b6a421SHawking Zhang adev->doorbell_index.last_non_cp = AMDGPU_NAVI10_DOORBELL64_LAST_NON_CP; 655c6b6a421SHawking Zhang 656c6b6a421SHawking Zhang adev->doorbell_index.max_assignment = AMDGPU_NAVI10_DOORBELL_MAX_ASSIGNMENT << 1; 657c6b6a421SHawking Zhang adev->doorbell_index.sdma_doorbell_range = 20; 658c6b6a421SHawking Zhang } 659c6b6a421SHawking Zhang 660a7173731SAlex Deucher static void nv_pre_asic_init(struct amdgpu_device *adev) 661a7173731SAlex Deucher { 662a7173731SAlex Deucher } 663a7173731SAlex Deucher 664c6b6a421SHawking Zhang static const struct amdgpu_asic_funcs nv_asic_funcs = 665c6b6a421SHawking Zhang { 666c6b6a421SHawking Zhang .read_disabled_bios = &nv_read_disabled_bios, 667c6b6a421SHawking Zhang .read_bios_from_rom = &nv_read_bios_from_rom, 668c6b6a421SHawking Zhang .read_register = &nv_read_register, 669c6b6a421SHawking Zhang .reset = &nv_asic_reset, 6702ddc6c3eSAlex Deucher .reset_method = &nv_asic_reset_method, 671c6b6a421SHawking Zhang .set_vga_state = &nv_vga_set_state, 672c6b6a421SHawking Zhang .get_xclk = &nv_get_xclk, 673c6b6a421SHawking Zhang .set_uvd_clocks = &nv_set_uvd_clocks, 674c6b6a421SHawking Zhang .set_vce_clocks = &nv_set_vce_clocks, 675c6b6a421SHawking Zhang .get_config_memsize = &nv_get_config_memsize, 676c6b6a421SHawking Zhang .flush_hdp = &nv_flush_hdp, 677c6b6a421SHawking Zhang .invalidate_hdp = &nv_invalidate_hdp, 678c6b6a421SHawking Zhang .init_doorbell_index = &nv_init_doorbell_index, 679c6b6a421SHawking Zhang .need_full_reset = &nv_need_full_reset, 680c6b6a421SHawking Zhang .need_reset_on_init = &nv_need_reset_on_init, 6812af81531SKevin Wang .get_pcie_replay_count = &nv_get_pcie_replay_count, 682ac742616SAlex Deucher .supports_baco = &nv_asic_supports_baco, 683a7173731SAlex Deucher .pre_asic_init = &nv_pre_asic_init, 684c6b6a421SHawking Zhang }; 685c6b6a421SHawking Zhang 686c6b6a421SHawking Zhang static int nv_common_early_init(void *handle) 687c6b6a421SHawking Zhang { 688923c087aSYong Zhao #define MMIO_REG_HOLE_OFFSET (0x80000 - PAGE_SIZE) 689c6b6a421SHawking Zhang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 690c6b6a421SHawking Zhang 691923c087aSYong Zhao adev->rmmio_remap.reg_offset = MMIO_REG_HOLE_OFFSET; 692923c087aSYong Zhao adev->rmmio_remap.bus_addr = adev->rmmio_base + MMIO_REG_HOLE_OFFSET; 693c6b6a421SHawking Zhang adev->smc_rreg = NULL; 694c6b6a421SHawking Zhang adev->smc_wreg = NULL; 695c6b6a421SHawking Zhang adev->pcie_rreg = &nv_pcie_rreg; 696c6b6a421SHawking Zhang adev->pcie_wreg = &nv_pcie_wreg; 6974922f1bcSJohn Clements adev->pcie_rreg64 = &nv_pcie_rreg64; 6984922f1bcSJohn Clements adev->pcie_wreg64 = &nv_pcie_wreg64; 699c6b6a421SHawking Zhang 700c6b6a421SHawking Zhang /* TODO: will add them during VCN v2 implementation */ 701c6b6a421SHawking Zhang adev->uvd_ctx_rreg = NULL; 702c6b6a421SHawking Zhang adev->uvd_ctx_wreg = NULL; 703c6b6a421SHawking Zhang 704c6b6a421SHawking Zhang adev->didt_rreg = &nv_didt_rreg; 705c6b6a421SHawking Zhang adev->didt_wreg = &nv_didt_wreg; 706c6b6a421SHawking Zhang 707c6b6a421SHawking Zhang adev->asic_funcs = &nv_asic_funcs; 708c6b6a421SHawking Zhang 709c6b6a421SHawking Zhang adev->rev_id = nv_get_rev_id(adev); 710c6b6a421SHawking Zhang adev->external_rev_id = 0xff; 711c6b6a421SHawking Zhang switch (adev->asic_type) { 712c6b6a421SHawking Zhang case CHIP_NAVI10: 713c6b6a421SHawking Zhang adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 714c6b6a421SHawking Zhang AMD_CG_SUPPORT_GFX_CGCG | 715c6b6a421SHawking Zhang AMD_CG_SUPPORT_IH_CG | 716c6b6a421SHawking Zhang AMD_CG_SUPPORT_HDP_MGCG | 717c6b6a421SHawking Zhang AMD_CG_SUPPORT_HDP_LS | 718c6b6a421SHawking Zhang AMD_CG_SUPPORT_SDMA_MGCG | 719c6b6a421SHawking Zhang AMD_CG_SUPPORT_SDMA_LS | 720c6b6a421SHawking Zhang AMD_CG_SUPPORT_MC_MGCG | 721c6b6a421SHawking Zhang AMD_CG_SUPPORT_MC_LS | 722c6b6a421SHawking Zhang AMD_CG_SUPPORT_ATHUB_MGCG | 723c6b6a421SHawking Zhang AMD_CG_SUPPORT_ATHUB_LS | 724c6b6a421SHawking Zhang AMD_CG_SUPPORT_VCN_MGCG | 725099d66e4SLeo Liu AMD_CG_SUPPORT_JPEG_MGCG | 726c6b6a421SHawking Zhang AMD_CG_SUPPORT_BIF_MGCG | 727c6b6a421SHawking Zhang AMD_CG_SUPPORT_BIF_LS; 728157710eaSLeo Liu adev->pg_flags = AMD_PG_SUPPORT_VCN | 729c12d410fSHuang Rui AMD_PG_SUPPORT_VCN_DPG | 730099d66e4SLeo Liu AMD_PG_SUPPORT_JPEG | 731a201b6acSHuang Rui AMD_PG_SUPPORT_ATHUB; 732c6b6a421SHawking Zhang adev->external_rev_id = adev->rev_id + 0x1; 733c6b6a421SHawking Zhang break; 7345e71e011SXiaojie Yuan case CHIP_NAVI14: 735d0c39f8cSXiaojie Yuan adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 736d0c39f8cSXiaojie Yuan AMD_CG_SUPPORT_GFX_CGCG | 737d0c39f8cSXiaojie Yuan AMD_CG_SUPPORT_IH_CG | 738d0c39f8cSXiaojie Yuan AMD_CG_SUPPORT_HDP_MGCG | 739d0c39f8cSXiaojie Yuan AMD_CG_SUPPORT_HDP_LS | 740d0c39f8cSXiaojie Yuan AMD_CG_SUPPORT_SDMA_MGCG | 741d0c39f8cSXiaojie Yuan AMD_CG_SUPPORT_SDMA_LS | 742d0c39f8cSXiaojie Yuan AMD_CG_SUPPORT_MC_MGCG | 743d0c39f8cSXiaojie Yuan AMD_CG_SUPPORT_MC_LS | 744d0c39f8cSXiaojie Yuan AMD_CG_SUPPORT_ATHUB_MGCG | 745d0c39f8cSXiaojie Yuan AMD_CG_SUPPORT_ATHUB_LS | 746d0c39f8cSXiaojie Yuan AMD_CG_SUPPORT_VCN_MGCG | 747099d66e4SLeo Liu AMD_CG_SUPPORT_JPEG_MGCG | 748d0c39f8cSXiaojie Yuan AMD_CG_SUPPORT_BIF_MGCG | 749d0c39f8cSXiaojie Yuan AMD_CG_SUPPORT_BIF_LS; 7500377b088SXiaojie Yuan adev->pg_flags = AMD_PG_SUPPORT_VCN | 751099d66e4SLeo Liu AMD_PG_SUPPORT_JPEG | 7520377b088SXiaojie Yuan AMD_PG_SUPPORT_VCN_DPG; 75335ef88faStiancyin adev->external_rev_id = adev->rev_id + 20; 7545e71e011SXiaojie Yuan break; 75574b5e509SXiaojie Yuan case CHIP_NAVI12: 756dca009e7SXiaojie Yuan adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 757dca009e7SXiaojie Yuan AMD_CG_SUPPORT_GFX_MGLS | 758dca009e7SXiaojie Yuan AMD_CG_SUPPORT_GFX_CGCG | 759dca009e7SXiaojie Yuan AMD_CG_SUPPORT_GFX_CP_LS | 7605211c37aSXiaojie Yuan AMD_CG_SUPPORT_GFX_RLC_LS | 761fbe0bc57SXiaojie Yuan AMD_CG_SUPPORT_IH_CG | 7625211c37aSXiaojie Yuan AMD_CG_SUPPORT_HDP_MGCG | 763358ab97fSXiaojie Yuan AMD_CG_SUPPORT_HDP_LS | 764358ab97fSXiaojie Yuan AMD_CG_SUPPORT_SDMA_MGCG | 7658b797b3dSXiaojie Yuan AMD_CG_SUPPORT_SDMA_LS | 7668b797b3dSXiaojie Yuan AMD_CG_SUPPORT_MC_MGCG | 767ca51678dSXiaojie Yuan AMD_CG_SUPPORT_MC_LS | 768ca51678dSXiaojie Yuan AMD_CG_SUPPORT_ATHUB_MGCG | 76965872e59SXiaojie Yuan AMD_CG_SUPPORT_ATHUB_LS | 770099d66e4SLeo Liu AMD_CG_SUPPORT_VCN_MGCG | 771099d66e4SLeo Liu AMD_CG_SUPPORT_JPEG_MGCG; 772c1653ea0SXiaojie Yuan adev->pg_flags = AMD_PG_SUPPORT_VCN | 7735ef3b8acSXiaojie Yuan AMD_PG_SUPPORT_VCN_DPG | 774099d66e4SLeo Liu AMD_PG_SUPPORT_JPEG | 7751b0443b1SLikun Gao AMD_PG_SUPPORT_ATHUB; 776df5e984cSTiecheng Zhou /* guest vm gets 0xffffffff when reading RCC_DEV0_EPF0_STRAP0, 777df5e984cSTiecheng Zhou * as a consequence, the rev_id and external_rev_id are wrong. 778df5e984cSTiecheng Zhou * workaround it by hardcoding rev_id to 0 (default value). 779df5e984cSTiecheng Zhou */ 780df5e984cSTiecheng Zhou if (amdgpu_sriov_vf(adev)) 781df5e984cSTiecheng Zhou adev->rev_id = 0; 78274b5e509SXiaojie Yuan adev->external_rev_id = adev->rev_id + 0xa; 78374b5e509SXiaojie Yuan break; 784117910edSLikun Gao case CHIP_SIENNA_CICHLID: 78500194defSLikun Gao adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 78600194defSLikun Gao AMD_CG_SUPPORT_GFX_CGCG | 78700194defSLikun Gao AMD_CG_SUPPORT_GFX_3D_CGCG | 78898f8ea29SLikun Gao AMD_CG_SUPPORT_MC_MGCG | 78900194defSLikun Gao AMD_CG_SUPPORT_VCN_MGCG | 790ca36461fSKenneth Feng AMD_CG_SUPPORT_JPEG_MGCG | 791ca36461fSKenneth Feng AMD_CG_SUPPORT_HDP_MGCG | 7923a32c25aSKenneth Feng AMD_CG_SUPPORT_HDP_LS | 793bcc8367fSKenneth Feng AMD_CG_SUPPORT_IH_CG | 794bcc8367fSKenneth Feng AMD_CG_SUPPORT_MC_LS; 795b467c4f5SLeo Liu adev->pg_flags = AMD_PG_SUPPORT_VCN | 796d00b0fa9SBoyuan Zhang AMD_PG_SUPPORT_VCN_DPG | 797b794616dSKenneth Feng AMD_PG_SUPPORT_JPEG | 7981b0443b1SLikun Gao AMD_PG_SUPPORT_ATHUB | 7991b0443b1SLikun Gao AMD_PG_SUPPORT_MMHUB; 800c45fbe1bSJack Zhang if (amdgpu_sriov_vf(adev)) { 801c45fbe1bSJack Zhang /* hypervisor control CG and PG enablement */ 802c45fbe1bSJack Zhang adev->cg_flags = 0; 803c45fbe1bSJack Zhang adev->pg_flags = 0; 804c45fbe1bSJack Zhang } 805117910edSLikun Gao adev->external_rev_id = adev->rev_id + 0x28; 806117910edSLikun Gao break; 807543aa259SJiansong Chen case CHIP_NAVY_FLOUNDER: 80840582e67SJiansong Chen adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 80940582e67SJiansong Chen AMD_CG_SUPPORT_GFX_CGCG | 81040582e67SJiansong Chen AMD_CG_SUPPORT_GFX_3D_CGCG | 81140582e67SJiansong Chen AMD_CG_SUPPORT_VCN_MGCG | 81292c73756SJiansong Chen AMD_CG_SUPPORT_JPEG_MGCG | 81392c73756SJiansong Chen AMD_CG_SUPPORT_MC_MGCG | 8144759f887SJiansong Chen AMD_CG_SUPPORT_MC_LS | 8154759f887SJiansong Chen AMD_CG_SUPPORT_HDP_MGCG | 81685e7151bSJiansong Chen AMD_CG_SUPPORT_HDP_LS | 81785e7151bSJiansong Chen AMD_CG_SUPPORT_IH_CG; 818c6e9dd0eSBoyuan Zhang adev->pg_flags = AMD_PG_SUPPORT_VCN | 81900740df9SBoyuan Zhang AMD_PG_SUPPORT_VCN_DPG | 82047fc894aSJiansong Chen AMD_PG_SUPPORT_JPEG | 82147fc894aSJiansong Chen AMD_PG_SUPPORT_ATHUB | 82247fc894aSJiansong Chen AMD_PG_SUPPORT_MMHUB; 823543aa259SJiansong Chen adev->external_rev_id = adev->rev_id + 0x32; 824543aa259SJiansong Chen break; 825543aa259SJiansong Chen 826c6b6a421SHawking Zhang default: 827c6b6a421SHawking Zhang /* FIXME: not supported yet */ 828c6b6a421SHawking Zhang return -EINVAL; 829c6b6a421SHawking Zhang } 830c6b6a421SHawking Zhang 831b05b6903SJiange Zhao if (amdgpu_sriov_vf(adev)) { 832b05b6903SJiange Zhao amdgpu_virt_init_setting(adev); 833b05b6903SJiange Zhao xgpu_nv_mailbox_set_irq_funcs(adev); 834b05b6903SJiange Zhao } 835b05b6903SJiange Zhao 836c6b6a421SHawking Zhang return 0; 837c6b6a421SHawking Zhang } 838c6b6a421SHawking Zhang 839c6b6a421SHawking Zhang static int nv_common_late_init(void *handle) 840c6b6a421SHawking Zhang { 841b05b6903SJiange Zhao struct amdgpu_device *adev = (struct amdgpu_device *)handle; 842b05b6903SJiange Zhao 843b05b6903SJiange Zhao if (amdgpu_sriov_vf(adev)) 844b05b6903SJiange Zhao xgpu_nv_mailbox_get_irq(adev); 845b05b6903SJiange Zhao 846c6b6a421SHawking Zhang return 0; 847c6b6a421SHawking Zhang } 848c6b6a421SHawking Zhang 849c6b6a421SHawking Zhang static int nv_common_sw_init(void *handle) 850c6b6a421SHawking Zhang { 851b05b6903SJiange Zhao struct amdgpu_device *adev = (struct amdgpu_device *)handle; 852b05b6903SJiange Zhao 853b05b6903SJiange Zhao if (amdgpu_sriov_vf(adev)) 854b05b6903SJiange Zhao xgpu_nv_mailbox_add_irq_id(adev); 855b05b6903SJiange Zhao 856c6b6a421SHawking Zhang return 0; 857c6b6a421SHawking Zhang } 858c6b6a421SHawking Zhang 859c6b6a421SHawking Zhang static int nv_common_sw_fini(void *handle) 860c6b6a421SHawking Zhang { 861c6b6a421SHawking Zhang return 0; 862c6b6a421SHawking Zhang } 863c6b6a421SHawking Zhang 864c6b6a421SHawking Zhang static int nv_common_hw_init(void *handle) 865c6b6a421SHawking Zhang { 866c6b6a421SHawking Zhang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 867c6b6a421SHawking Zhang 868c6b6a421SHawking Zhang /* enable pcie gen2/3 link */ 869c6b6a421SHawking Zhang nv_pcie_gen3_enable(adev); 870c6b6a421SHawking Zhang /* enable aspm */ 871c6b6a421SHawking Zhang nv_program_aspm(adev); 872c6b6a421SHawking Zhang /* setup nbio registers */ 873bebc0762SHawking Zhang adev->nbio.funcs->init_registers(adev); 874923c087aSYong Zhao /* remap HDP registers to a hole in mmio space, 875923c087aSYong Zhao * for the purpose of expose those registers 876923c087aSYong Zhao * to process space 877923c087aSYong Zhao */ 878923c087aSYong Zhao if (adev->nbio.funcs->remap_hdp_registers) 879923c087aSYong Zhao adev->nbio.funcs->remap_hdp_registers(adev); 880c6b6a421SHawking Zhang /* enable the doorbell aperture */ 881c6b6a421SHawking Zhang nv_enable_doorbell_aperture(adev, true); 882c6b6a421SHawking Zhang 883c6b6a421SHawking Zhang return 0; 884c6b6a421SHawking Zhang } 885c6b6a421SHawking Zhang 886c6b6a421SHawking Zhang static int nv_common_hw_fini(void *handle) 887c6b6a421SHawking Zhang { 888c6b6a421SHawking Zhang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 889c6b6a421SHawking Zhang 890c6b6a421SHawking Zhang /* disable the doorbell aperture */ 891c6b6a421SHawking Zhang nv_enable_doorbell_aperture(adev, false); 892c6b6a421SHawking Zhang 893c6b6a421SHawking Zhang return 0; 894c6b6a421SHawking Zhang } 895c6b6a421SHawking Zhang 896c6b6a421SHawking Zhang static int nv_common_suspend(void *handle) 897c6b6a421SHawking Zhang { 898c6b6a421SHawking Zhang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 899c6b6a421SHawking Zhang 900c6b6a421SHawking Zhang return nv_common_hw_fini(adev); 901c6b6a421SHawking Zhang } 902c6b6a421SHawking Zhang 903c6b6a421SHawking Zhang static int nv_common_resume(void *handle) 904c6b6a421SHawking Zhang { 905c6b6a421SHawking Zhang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 906c6b6a421SHawking Zhang 907c6b6a421SHawking Zhang return nv_common_hw_init(adev); 908c6b6a421SHawking Zhang } 909c6b6a421SHawking Zhang 910c6b6a421SHawking Zhang static bool nv_common_is_idle(void *handle) 911c6b6a421SHawking Zhang { 912c6b6a421SHawking Zhang return true; 913c6b6a421SHawking Zhang } 914c6b6a421SHawking Zhang 915c6b6a421SHawking Zhang static int nv_common_wait_for_idle(void *handle) 916c6b6a421SHawking Zhang { 917c6b6a421SHawking Zhang return 0; 918c6b6a421SHawking Zhang } 919c6b6a421SHawking Zhang 920c6b6a421SHawking Zhang static int nv_common_soft_reset(void *handle) 921c6b6a421SHawking Zhang { 922c6b6a421SHawking Zhang return 0; 923c6b6a421SHawking Zhang } 924c6b6a421SHawking Zhang 925c6b6a421SHawking Zhang static void nv_update_hdp_mem_power_gating(struct amdgpu_device *adev, 926c6b6a421SHawking Zhang bool enable) 927c6b6a421SHawking Zhang { 928c6b6a421SHawking Zhang uint32_t hdp_clk_cntl, hdp_clk_cntl1; 929c6b6a421SHawking Zhang uint32_t hdp_mem_pwr_cntl; 930c6b6a421SHawking Zhang 931c6b6a421SHawking Zhang if (!(adev->cg_flags & (AMD_CG_SUPPORT_HDP_LS | 932c6b6a421SHawking Zhang AMD_CG_SUPPORT_HDP_DS | 933c6b6a421SHawking Zhang AMD_CG_SUPPORT_HDP_SD))) 934c6b6a421SHawking Zhang return; 935c6b6a421SHawking Zhang 936c6b6a421SHawking Zhang hdp_clk_cntl = hdp_clk_cntl1 = RREG32_SOC15(HDP, 0, mmHDP_CLK_CNTL); 937c6b6a421SHawking Zhang hdp_mem_pwr_cntl = RREG32_SOC15(HDP, 0, mmHDP_MEM_POWER_CTRL); 938c6b6a421SHawking Zhang 939c6b6a421SHawking Zhang /* Before doing clock/power mode switch, 940c6b6a421SHawking Zhang * forced on IPH & RC clock */ 941c6b6a421SHawking Zhang hdp_clk_cntl = REG_SET_FIELD(hdp_clk_cntl, HDP_CLK_CNTL, 942c6b6a421SHawking Zhang IPH_MEM_CLK_SOFT_OVERRIDE, 1); 943c6b6a421SHawking Zhang hdp_clk_cntl = REG_SET_FIELD(hdp_clk_cntl, HDP_CLK_CNTL, 944c6b6a421SHawking Zhang RC_MEM_CLK_SOFT_OVERRIDE, 1); 945c6b6a421SHawking Zhang WREG32_SOC15(HDP, 0, mmHDP_CLK_CNTL, hdp_clk_cntl); 946c6b6a421SHawking Zhang 947c6b6a421SHawking Zhang /* HDP 5.0 doesn't support dynamic power mode switch, 948c6b6a421SHawking Zhang * disable clock and power gating before any changing */ 949c6b6a421SHawking Zhang hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, 950c6b6a421SHawking Zhang IPH_MEM_POWER_CTRL_EN, 0); 951c6b6a421SHawking Zhang hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, 952c6b6a421SHawking Zhang IPH_MEM_POWER_LS_EN, 0); 953c6b6a421SHawking Zhang hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, 954c6b6a421SHawking Zhang IPH_MEM_POWER_DS_EN, 0); 955c6b6a421SHawking Zhang hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, 956c6b6a421SHawking Zhang IPH_MEM_POWER_SD_EN, 0); 957c6b6a421SHawking Zhang hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, 958c6b6a421SHawking Zhang RC_MEM_POWER_CTRL_EN, 0); 959c6b6a421SHawking Zhang hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, 960c6b6a421SHawking Zhang RC_MEM_POWER_LS_EN, 0); 961c6b6a421SHawking Zhang hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, 962c6b6a421SHawking Zhang RC_MEM_POWER_DS_EN, 0); 963c6b6a421SHawking Zhang hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, 964c6b6a421SHawking Zhang RC_MEM_POWER_SD_EN, 0); 965c6b6a421SHawking Zhang WREG32_SOC15(HDP, 0, mmHDP_MEM_POWER_CTRL, hdp_mem_pwr_cntl); 966c6b6a421SHawking Zhang 967c6b6a421SHawking Zhang /* only one clock gating mode (LS/DS/SD) can be enabled */ 968c6b6a421SHawking Zhang if (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS) { 969c6b6a421SHawking Zhang hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, 970c6b6a421SHawking Zhang HDP_MEM_POWER_CTRL, 971c6b6a421SHawking Zhang IPH_MEM_POWER_LS_EN, enable); 972c6b6a421SHawking Zhang hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, 973c6b6a421SHawking Zhang HDP_MEM_POWER_CTRL, 974c6b6a421SHawking Zhang RC_MEM_POWER_LS_EN, enable); 975c6b6a421SHawking Zhang } else if (adev->cg_flags & AMD_CG_SUPPORT_HDP_DS) { 976c6b6a421SHawking Zhang hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, 977c6b6a421SHawking Zhang HDP_MEM_POWER_CTRL, 978c6b6a421SHawking Zhang IPH_MEM_POWER_DS_EN, enable); 979c6b6a421SHawking Zhang hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, 980c6b6a421SHawking Zhang HDP_MEM_POWER_CTRL, 981c6b6a421SHawking Zhang RC_MEM_POWER_DS_EN, enable); 982c6b6a421SHawking Zhang } else if (adev->cg_flags & AMD_CG_SUPPORT_HDP_SD) { 983c6b6a421SHawking Zhang hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, 984c6b6a421SHawking Zhang HDP_MEM_POWER_CTRL, 985c6b6a421SHawking Zhang IPH_MEM_POWER_SD_EN, enable); 986c6b6a421SHawking Zhang /* RC should not use shut down mode, fallback to ds */ 987c6b6a421SHawking Zhang hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, 988c6b6a421SHawking Zhang HDP_MEM_POWER_CTRL, 989c6b6a421SHawking Zhang RC_MEM_POWER_DS_EN, enable); 990c6b6a421SHawking Zhang } 991c6b6a421SHawking Zhang 99291c6adf8SKenneth Feng /* confirmed that IPH_MEM_POWER_CTRL_EN and RC_MEM_POWER_CTRL_EN have to 99391c6adf8SKenneth Feng * be set for SRAM LS/DS/SD */ 99491c6adf8SKenneth Feng if (adev->cg_flags & (AMD_CG_SUPPORT_HDP_LS | AMD_CG_SUPPORT_HDP_DS | 99591c6adf8SKenneth Feng AMD_CG_SUPPORT_HDP_SD)) { 99691c6adf8SKenneth Feng hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, 99791c6adf8SKenneth Feng IPH_MEM_POWER_CTRL_EN, 1); 99891c6adf8SKenneth Feng hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, 99991c6adf8SKenneth Feng RC_MEM_POWER_CTRL_EN, 1); 100091c6adf8SKenneth Feng } 100191c6adf8SKenneth Feng 1002c6b6a421SHawking Zhang WREG32_SOC15(HDP, 0, mmHDP_MEM_POWER_CTRL, hdp_mem_pwr_cntl); 1003c6b6a421SHawking Zhang 1004c6b6a421SHawking Zhang /* restore IPH & RC clock override after clock/power mode changing */ 1005c6b6a421SHawking Zhang WREG32_SOC15(HDP, 0, mmHDP_CLK_CNTL, hdp_clk_cntl1); 1006c6b6a421SHawking Zhang } 1007c6b6a421SHawking Zhang 1008c6b6a421SHawking Zhang static void nv_update_hdp_clock_gating(struct amdgpu_device *adev, 1009c6b6a421SHawking Zhang bool enable) 1010c6b6a421SHawking Zhang { 1011c6b6a421SHawking Zhang uint32_t hdp_clk_cntl; 1012c6b6a421SHawking Zhang 1013c6b6a421SHawking Zhang if (!(adev->cg_flags & AMD_CG_SUPPORT_HDP_MGCG)) 1014c6b6a421SHawking Zhang return; 1015c6b6a421SHawking Zhang 1016c6b6a421SHawking Zhang hdp_clk_cntl = RREG32_SOC15(HDP, 0, mmHDP_CLK_CNTL); 1017c6b6a421SHawking Zhang 1018c6b6a421SHawking Zhang if (enable) { 1019c6b6a421SHawking Zhang hdp_clk_cntl &= 1020c6b6a421SHawking Zhang ~(uint32_t) 1021c6b6a421SHawking Zhang (HDP_CLK_CNTL__IPH_MEM_CLK_SOFT_OVERRIDE_MASK | 1022c6b6a421SHawking Zhang HDP_CLK_CNTL__RC_MEM_CLK_SOFT_OVERRIDE_MASK | 1023c6b6a421SHawking Zhang HDP_CLK_CNTL__DBUS_CLK_SOFT_OVERRIDE_MASK | 1024c6b6a421SHawking Zhang HDP_CLK_CNTL__DYN_CLK_SOFT_OVERRIDE_MASK | 1025c6b6a421SHawking Zhang HDP_CLK_CNTL__XDP_REG_CLK_SOFT_OVERRIDE_MASK | 1026c6b6a421SHawking Zhang HDP_CLK_CNTL__HDP_REG_CLK_SOFT_OVERRIDE_MASK); 1027c6b6a421SHawking Zhang } else { 1028c6b6a421SHawking Zhang hdp_clk_cntl |= HDP_CLK_CNTL__IPH_MEM_CLK_SOFT_OVERRIDE_MASK | 1029c6b6a421SHawking Zhang HDP_CLK_CNTL__RC_MEM_CLK_SOFT_OVERRIDE_MASK | 1030c6b6a421SHawking Zhang HDP_CLK_CNTL__DBUS_CLK_SOFT_OVERRIDE_MASK | 1031c6b6a421SHawking Zhang HDP_CLK_CNTL__DYN_CLK_SOFT_OVERRIDE_MASK | 1032c6b6a421SHawking Zhang HDP_CLK_CNTL__XDP_REG_CLK_SOFT_OVERRIDE_MASK | 1033c6b6a421SHawking Zhang HDP_CLK_CNTL__HDP_REG_CLK_SOFT_OVERRIDE_MASK; 1034c6b6a421SHawking Zhang } 1035c6b6a421SHawking Zhang 1036c6b6a421SHawking Zhang WREG32_SOC15(HDP, 0, mmHDP_CLK_CNTL, hdp_clk_cntl); 1037c6b6a421SHawking Zhang } 1038c6b6a421SHawking Zhang 1039c6b6a421SHawking Zhang static int nv_common_set_clockgating_state(void *handle, 1040c6b6a421SHawking Zhang enum amd_clockgating_state state) 1041c6b6a421SHawking Zhang { 1042c6b6a421SHawking Zhang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1043c6b6a421SHawking Zhang 1044c6b6a421SHawking Zhang if (amdgpu_sriov_vf(adev)) 1045c6b6a421SHawking Zhang return 0; 1046c6b6a421SHawking Zhang 1047c6b6a421SHawking Zhang switch (adev->asic_type) { 1048c6b6a421SHawking Zhang case CHIP_NAVI10: 10495e71e011SXiaojie Yuan case CHIP_NAVI14: 10507e17e58bSXiaojie Yuan case CHIP_NAVI12: 1051117910edSLikun Gao case CHIP_SIENNA_CICHLID: 1052543aa259SJiansong Chen case CHIP_NAVY_FLOUNDER: 1053bebc0762SHawking Zhang adev->nbio.funcs->update_medium_grain_clock_gating(adev, 1054a9d4fe2fSNirmoy Das state == AMD_CG_STATE_GATE); 1055bebc0762SHawking Zhang adev->nbio.funcs->update_medium_grain_light_sleep(adev, 1056a9d4fe2fSNirmoy Das state == AMD_CG_STATE_GATE); 1057c6b6a421SHawking Zhang nv_update_hdp_mem_power_gating(adev, 1058a9d4fe2fSNirmoy Das state == AMD_CG_STATE_GATE); 1059c6b6a421SHawking Zhang nv_update_hdp_clock_gating(adev, 1060a9d4fe2fSNirmoy Das state == AMD_CG_STATE_GATE); 1061c6b6a421SHawking Zhang break; 1062c6b6a421SHawking Zhang default: 1063c6b6a421SHawking Zhang break; 1064c6b6a421SHawking Zhang } 1065c6b6a421SHawking Zhang return 0; 1066c6b6a421SHawking Zhang } 1067c6b6a421SHawking Zhang 1068c6b6a421SHawking Zhang static int nv_common_set_powergating_state(void *handle, 1069c6b6a421SHawking Zhang enum amd_powergating_state state) 1070c6b6a421SHawking Zhang { 1071c6b6a421SHawking Zhang /* TODO */ 1072c6b6a421SHawking Zhang return 0; 1073c6b6a421SHawking Zhang } 1074c6b6a421SHawking Zhang 1075c6b6a421SHawking Zhang static void nv_common_get_clockgating_state(void *handle, u32 *flags) 1076c6b6a421SHawking Zhang { 1077c6b6a421SHawking Zhang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1078c6b6a421SHawking Zhang uint32_t tmp; 1079c6b6a421SHawking Zhang 1080c6b6a421SHawking Zhang if (amdgpu_sriov_vf(adev)) 1081c6b6a421SHawking Zhang *flags = 0; 1082c6b6a421SHawking Zhang 1083bebc0762SHawking Zhang adev->nbio.funcs->get_clockgating_state(adev, flags); 1084c6b6a421SHawking Zhang 1085c6b6a421SHawking Zhang /* AMD_CG_SUPPORT_HDP_MGCG */ 1086c6b6a421SHawking Zhang tmp = RREG32_SOC15(HDP, 0, mmHDP_CLK_CNTL); 1087c6b6a421SHawking Zhang if (!(tmp & (HDP_CLK_CNTL__IPH_MEM_CLK_SOFT_OVERRIDE_MASK | 1088c6b6a421SHawking Zhang HDP_CLK_CNTL__RC_MEM_CLK_SOFT_OVERRIDE_MASK | 1089c6b6a421SHawking Zhang HDP_CLK_CNTL__DBUS_CLK_SOFT_OVERRIDE_MASK | 1090c6b6a421SHawking Zhang HDP_CLK_CNTL__DYN_CLK_SOFT_OVERRIDE_MASK | 1091c6b6a421SHawking Zhang HDP_CLK_CNTL__XDP_REG_CLK_SOFT_OVERRIDE_MASK | 1092c6b6a421SHawking Zhang HDP_CLK_CNTL__HDP_REG_CLK_SOFT_OVERRIDE_MASK))) 1093c6b6a421SHawking Zhang *flags |= AMD_CG_SUPPORT_HDP_MGCG; 1094c6b6a421SHawking Zhang 1095c6b6a421SHawking Zhang /* AMD_CG_SUPPORT_HDP_LS/DS/SD */ 1096c6b6a421SHawking Zhang tmp = RREG32_SOC15(HDP, 0, mmHDP_MEM_POWER_CTRL); 1097c6b6a421SHawking Zhang if (tmp & HDP_MEM_POWER_CTRL__IPH_MEM_POWER_LS_EN_MASK) 1098c6b6a421SHawking Zhang *flags |= AMD_CG_SUPPORT_HDP_LS; 1099c6b6a421SHawking Zhang else if (tmp & HDP_MEM_POWER_CTRL__IPH_MEM_POWER_DS_EN_MASK) 1100c6b6a421SHawking Zhang *flags |= AMD_CG_SUPPORT_HDP_DS; 1101c6b6a421SHawking Zhang else if (tmp & HDP_MEM_POWER_CTRL__IPH_MEM_POWER_SD_EN_MASK) 1102c6b6a421SHawking Zhang *flags |= AMD_CG_SUPPORT_HDP_SD; 1103c6b6a421SHawking Zhang 1104c6b6a421SHawking Zhang return; 1105c6b6a421SHawking Zhang } 1106c6b6a421SHawking Zhang 1107c6b6a421SHawking Zhang static const struct amd_ip_funcs nv_common_ip_funcs = { 1108c6b6a421SHawking Zhang .name = "nv_common", 1109c6b6a421SHawking Zhang .early_init = nv_common_early_init, 1110c6b6a421SHawking Zhang .late_init = nv_common_late_init, 1111c6b6a421SHawking Zhang .sw_init = nv_common_sw_init, 1112c6b6a421SHawking Zhang .sw_fini = nv_common_sw_fini, 1113c6b6a421SHawking Zhang .hw_init = nv_common_hw_init, 1114c6b6a421SHawking Zhang .hw_fini = nv_common_hw_fini, 1115c6b6a421SHawking Zhang .suspend = nv_common_suspend, 1116c6b6a421SHawking Zhang .resume = nv_common_resume, 1117c6b6a421SHawking Zhang .is_idle = nv_common_is_idle, 1118c6b6a421SHawking Zhang .wait_for_idle = nv_common_wait_for_idle, 1119c6b6a421SHawking Zhang .soft_reset = nv_common_soft_reset, 1120c6b6a421SHawking Zhang .set_clockgating_state = nv_common_set_clockgating_state, 1121c6b6a421SHawking Zhang .set_powergating_state = nv_common_set_powergating_state, 1122c6b6a421SHawking Zhang .get_clockgating_state = nv_common_get_clockgating_state, 1123c6b6a421SHawking Zhang }; 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