1c6b6a421SHawking Zhang /* 2c6b6a421SHawking Zhang * Copyright 2019 Advanced Micro Devices, Inc. 3c6b6a421SHawking Zhang * 4c6b6a421SHawking Zhang * Permission is hereby granted, free of charge, to any person obtaining a 5c6b6a421SHawking Zhang * copy of this software and associated documentation files (the "Software"), 6c6b6a421SHawking Zhang * to deal in the Software without restriction, including without limitation 7c6b6a421SHawking Zhang * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8c6b6a421SHawking Zhang * and/or sell copies of the Software, and to permit persons to whom the 9c6b6a421SHawking Zhang * Software is furnished to do so, subject to the following conditions: 10c6b6a421SHawking Zhang * 11c6b6a421SHawking Zhang * The above copyright notice and this permission notice shall be included in 12c6b6a421SHawking Zhang * all copies or substantial portions of the Software. 13c6b6a421SHawking Zhang * 14c6b6a421SHawking Zhang * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15c6b6a421SHawking Zhang * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16c6b6a421SHawking Zhang * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17c6b6a421SHawking Zhang * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18c6b6a421SHawking Zhang * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19c6b6a421SHawking Zhang * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20c6b6a421SHawking Zhang * OTHER DEALINGS IN THE SOFTWARE. 21c6b6a421SHawking Zhang * 22c6b6a421SHawking Zhang */ 23c6b6a421SHawking Zhang #include <linux/firmware.h> 24c6b6a421SHawking Zhang #include <linux/slab.h> 25c6b6a421SHawking Zhang #include <linux/module.h> 26e9eea902SAlex Deucher #include <linux/pci.h> 27e9eea902SAlex Deucher 28c6b6a421SHawking Zhang #include "amdgpu.h" 29c6b6a421SHawking Zhang #include "amdgpu_atombios.h" 30c6b6a421SHawking Zhang #include "amdgpu_ih.h" 31c6b6a421SHawking Zhang #include "amdgpu_uvd.h" 32c6b6a421SHawking Zhang #include "amdgpu_vce.h" 33c6b6a421SHawking Zhang #include "amdgpu_ucode.h" 34c6b6a421SHawking Zhang #include "amdgpu_psp.h" 35767acabdSKevin Wang #include "amdgpu_smu.h" 36c6b6a421SHawking Zhang #include "atom.h" 37c6b6a421SHawking Zhang #include "amd_pcie.h" 38c6b6a421SHawking Zhang 39c6b6a421SHawking Zhang #include "gc/gc_10_1_0_offset.h" 40c6b6a421SHawking Zhang #include "gc/gc_10_1_0_sh_mask.h" 41c6b6a421SHawking Zhang #include "hdp/hdp_5_0_0_offset.h" 42c6b6a421SHawking Zhang #include "hdp/hdp_5_0_0_sh_mask.h" 4329bc37b4SAlex Deucher #include "smuio/smuio_11_0_0_offset.h" 443967ae6dSAlex Deucher #include "mp/mp_11_0_offset.h" 45c6b6a421SHawking Zhang 46c6b6a421SHawking Zhang #include "soc15.h" 47c6b6a421SHawking Zhang #include "soc15_common.h" 48c6b6a421SHawking Zhang #include "gmc_v10_0.h" 49c6b6a421SHawking Zhang #include "gfxhub_v2_0.h" 50c6b6a421SHawking Zhang #include "mmhub_v2_0.h" 51bebc0762SHawking Zhang #include "nbio_v2_3.h" 52c6b6a421SHawking Zhang #include "nv.h" 53c6b6a421SHawking Zhang #include "navi10_ih.h" 54c6b6a421SHawking Zhang #include "gfx_v10_0.h" 55c6b6a421SHawking Zhang #include "sdma_v5_0.h" 56157e72e8SLikun Gao #include "sdma_v5_2.h" 57c6b6a421SHawking Zhang #include "vcn_v2_0.h" 585be45a26SLeo Liu #include "jpeg_v2_0.h" 59b8f10585SLeo Liu #include "vcn_v3_0.h" 604d72dd12SLeo Liu #include "jpeg_v3_0.h" 61c6b6a421SHawking Zhang #include "dce_virtual.h" 62c6b6a421SHawking Zhang #include "mes_v10_1.h" 63b05b6903SJiange Zhao #include "mxgpu_nv.h" 64c6b6a421SHawking Zhang 65c6b6a421SHawking Zhang static const struct amd_ip_funcs nv_common_ip_funcs; 66c6b6a421SHawking Zhang 67c6b6a421SHawking Zhang /* 68c6b6a421SHawking Zhang * Indirect registers accessor 69c6b6a421SHawking Zhang */ 70c6b6a421SHawking Zhang static u32 nv_pcie_rreg(struct amdgpu_device *adev, u32 reg) 71c6b6a421SHawking Zhang { 72705a2b5bSHawking Zhang unsigned long address, data; 73bebc0762SHawking Zhang address = adev->nbio.funcs->get_pcie_index_offset(adev); 74bebc0762SHawking Zhang data = adev->nbio.funcs->get_pcie_data_offset(adev); 75c6b6a421SHawking Zhang 76705a2b5bSHawking Zhang return amdgpu_device_indirect_rreg(adev, address, data, reg); 77c6b6a421SHawking Zhang } 78c6b6a421SHawking Zhang 79c6b6a421SHawking Zhang static void nv_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v) 80c6b6a421SHawking Zhang { 81705a2b5bSHawking Zhang unsigned long address, data; 82c6b6a421SHawking Zhang 83bebc0762SHawking Zhang address = adev->nbio.funcs->get_pcie_index_offset(adev); 84bebc0762SHawking Zhang data = adev->nbio.funcs->get_pcie_data_offset(adev); 85c6b6a421SHawking Zhang 86705a2b5bSHawking Zhang amdgpu_device_indirect_wreg(adev, address, data, reg, v); 87c6b6a421SHawking Zhang } 88c6b6a421SHawking Zhang 894922f1bcSJohn Clements static u64 nv_pcie_rreg64(struct amdgpu_device *adev, u32 reg) 904922f1bcSJohn Clements { 91705a2b5bSHawking Zhang unsigned long address, data; 924922f1bcSJohn Clements address = adev->nbio.funcs->get_pcie_index_offset(adev); 934922f1bcSJohn Clements data = adev->nbio.funcs->get_pcie_data_offset(adev); 944922f1bcSJohn Clements 95705a2b5bSHawking Zhang return amdgpu_device_indirect_rreg64(adev, address, data, reg); 964922f1bcSJohn Clements } 974922f1bcSJohn Clements 98*5de54343SHuang Rui static u32 nv_pcie_port_rreg(struct amdgpu_device *adev, u32 reg) 99*5de54343SHuang Rui { 100*5de54343SHuang Rui unsigned long flags, address, data; 101*5de54343SHuang Rui u32 r; 102*5de54343SHuang Rui address = adev->nbio.funcs->get_pcie_port_index_offset(adev); 103*5de54343SHuang Rui data = adev->nbio.funcs->get_pcie_port_data_offset(adev); 104*5de54343SHuang Rui 105*5de54343SHuang Rui spin_lock_irqsave(&adev->pcie_idx_lock, flags); 106*5de54343SHuang Rui WREG32(address, reg * 4); 107*5de54343SHuang Rui (void)RREG32(address); 108*5de54343SHuang Rui r = RREG32(data); 109*5de54343SHuang Rui spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); 110*5de54343SHuang Rui return r; 111*5de54343SHuang Rui } 112*5de54343SHuang Rui 1134922f1bcSJohn Clements static void nv_pcie_wreg64(struct amdgpu_device *adev, u32 reg, u64 v) 1144922f1bcSJohn Clements { 115705a2b5bSHawking Zhang unsigned long address, data; 1164922f1bcSJohn Clements 1174922f1bcSJohn Clements address = adev->nbio.funcs->get_pcie_index_offset(adev); 1184922f1bcSJohn Clements data = adev->nbio.funcs->get_pcie_data_offset(adev); 1194922f1bcSJohn Clements 120705a2b5bSHawking Zhang amdgpu_device_indirect_wreg64(adev, address, data, reg, v); 1214922f1bcSJohn Clements } 1224922f1bcSJohn Clements 123*5de54343SHuang Rui static void nv_pcie_port_wreg(struct amdgpu_device *adev, u32 reg, u32 v) 124*5de54343SHuang Rui { 125*5de54343SHuang Rui unsigned long flags, address, data; 126*5de54343SHuang Rui 127*5de54343SHuang Rui address = adev->nbio.funcs->get_pcie_port_index_offset(adev); 128*5de54343SHuang Rui data = adev->nbio.funcs->get_pcie_port_data_offset(adev); 129*5de54343SHuang Rui 130*5de54343SHuang Rui spin_lock_irqsave(&adev->pcie_idx_lock, flags); 131*5de54343SHuang Rui WREG32(address, reg * 4); 132*5de54343SHuang Rui (void)RREG32(address); 133*5de54343SHuang Rui WREG32(data, v); 134*5de54343SHuang Rui (void)RREG32(data); 135*5de54343SHuang Rui spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); 136*5de54343SHuang Rui } 137*5de54343SHuang Rui 138c6b6a421SHawking Zhang static u32 nv_didt_rreg(struct amdgpu_device *adev, u32 reg) 139c6b6a421SHawking Zhang { 140c6b6a421SHawking Zhang unsigned long flags, address, data; 141c6b6a421SHawking Zhang u32 r; 142c6b6a421SHawking Zhang 143c6b6a421SHawking Zhang address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX); 144c6b6a421SHawking Zhang data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA); 145c6b6a421SHawking Zhang 146c6b6a421SHawking Zhang spin_lock_irqsave(&adev->didt_idx_lock, flags); 147c6b6a421SHawking Zhang WREG32(address, (reg)); 148c6b6a421SHawking Zhang r = RREG32(data); 149c6b6a421SHawking Zhang spin_unlock_irqrestore(&adev->didt_idx_lock, flags); 150c6b6a421SHawking Zhang return r; 151c6b6a421SHawking Zhang } 152c6b6a421SHawking Zhang 153c6b6a421SHawking Zhang static void nv_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v) 154c6b6a421SHawking Zhang { 155c6b6a421SHawking Zhang unsigned long flags, address, data; 156c6b6a421SHawking Zhang 157c6b6a421SHawking Zhang address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX); 158c6b6a421SHawking Zhang data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA); 159c6b6a421SHawking Zhang 160c6b6a421SHawking Zhang spin_lock_irqsave(&adev->didt_idx_lock, flags); 161c6b6a421SHawking Zhang WREG32(address, (reg)); 162c6b6a421SHawking Zhang WREG32(data, (v)); 163c6b6a421SHawking Zhang spin_unlock_irqrestore(&adev->didt_idx_lock, flags); 164c6b6a421SHawking Zhang } 165c6b6a421SHawking Zhang 166c6b6a421SHawking Zhang static u32 nv_get_config_memsize(struct amdgpu_device *adev) 167c6b6a421SHawking Zhang { 168bebc0762SHawking Zhang return adev->nbio.funcs->get_memsize(adev); 169c6b6a421SHawking Zhang } 170c6b6a421SHawking Zhang 171c6b6a421SHawking Zhang static u32 nv_get_xclk(struct amdgpu_device *adev) 172c6b6a421SHawking Zhang { 173462a70d8STao Zhou return adev->clock.spll.reference_freq; 174c6b6a421SHawking Zhang } 175c6b6a421SHawking Zhang 176c6b6a421SHawking Zhang 177c6b6a421SHawking Zhang void nv_grbm_select(struct amdgpu_device *adev, 178c6b6a421SHawking Zhang u32 me, u32 pipe, u32 queue, u32 vmid) 179c6b6a421SHawking Zhang { 180c6b6a421SHawking Zhang u32 grbm_gfx_cntl = 0; 181c6b6a421SHawking Zhang grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, PIPEID, pipe); 182c6b6a421SHawking Zhang grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, MEID, me); 183c6b6a421SHawking Zhang grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, VMID, vmid); 184c6b6a421SHawking Zhang grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, QUEUEID, queue); 185c6b6a421SHawking Zhang 186c6b6a421SHawking Zhang WREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_CNTL), grbm_gfx_cntl); 187c6b6a421SHawking Zhang } 188c6b6a421SHawking Zhang 189c6b6a421SHawking Zhang static void nv_vga_set_state(struct amdgpu_device *adev, bool state) 190c6b6a421SHawking Zhang { 191c6b6a421SHawking Zhang /* todo */ 192c6b6a421SHawking Zhang } 193c6b6a421SHawking Zhang 194c6b6a421SHawking Zhang static bool nv_read_disabled_bios(struct amdgpu_device *adev) 195c6b6a421SHawking Zhang { 196c6b6a421SHawking Zhang /* todo */ 197c6b6a421SHawking Zhang return false; 198c6b6a421SHawking Zhang } 199c6b6a421SHawking Zhang 200c6b6a421SHawking Zhang static bool nv_read_bios_from_rom(struct amdgpu_device *adev, 201c6b6a421SHawking Zhang u8 *bios, u32 length_bytes) 202c6b6a421SHawking Zhang { 20329bc37b4SAlex Deucher u32 *dw_ptr; 20429bc37b4SAlex Deucher u32 i, length_dw; 20529bc37b4SAlex Deucher 20629bc37b4SAlex Deucher if (bios == NULL) 207c6b6a421SHawking Zhang return false; 20829bc37b4SAlex Deucher if (length_bytes == 0) 20929bc37b4SAlex Deucher return false; 21029bc37b4SAlex Deucher /* APU vbios image is part of sbios image */ 21129bc37b4SAlex Deucher if (adev->flags & AMD_IS_APU) 21229bc37b4SAlex Deucher return false; 21329bc37b4SAlex Deucher 21429bc37b4SAlex Deucher dw_ptr = (u32 *)bios; 21529bc37b4SAlex Deucher length_dw = ALIGN(length_bytes, 4) / 4; 21629bc37b4SAlex Deucher 21729bc37b4SAlex Deucher /* set rom index to 0 */ 21829bc37b4SAlex Deucher WREG32(SOC15_REG_OFFSET(SMUIO, 0, mmROM_INDEX), 0); 21929bc37b4SAlex Deucher /* read out the rom data */ 22029bc37b4SAlex Deucher for (i = 0; i < length_dw; i++) 22129bc37b4SAlex Deucher dw_ptr[i] = RREG32(SOC15_REG_OFFSET(SMUIO, 0, mmROM_DATA)); 22229bc37b4SAlex Deucher 22329bc37b4SAlex Deucher return true; 224c6b6a421SHawking Zhang } 225c6b6a421SHawking Zhang 226c6b6a421SHawking Zhang static struct soc15_allowed_register_entry nv_allowed_read_registers[] = { 227c6b6a421SHawking Zhang { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS)}, 228c6b6a421SHawking Zhang { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS2)}, 229c6b6a421SHawking Zhang { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE0)}, 230c6b6a421SHawking Zhang { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE1)}, 231c6b6a421SHawking Zhang { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE2)}, 232c6b6a421SHawking Zhang { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE3)}, 233c6b6a421SHawking Zhang { SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_STATUS_REG)}, 234c6b6a421SHawking Zhang { SOC15_REG_ENTRY(SDMA1, 0, mmSDMA1_STATUS_REG)}, 235c6b6a421SHawking Zhang { SOC15_REG_ENTRY(GC, 0, mmCP_STAT)}, 236c6b6a421SHawking Zhang { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT1)}, 237c6b6a421SHawking Zhang { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT2)}, 238c6b6a421SHawking Zhang { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT3)}, 239c6b6a421SHawking Zhang { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_BUSY_STAT)}, 240c6b6a421SHawking Zhang { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STALLED_STAT1)}, 241c6b6a421SHawking Zhang { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STATUS)}, 242664fe85aSMarek Olšák { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_BUSY_STAT)}, 243c6b6a421SHawking Zhang { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STALLED_STAT1)}, 244c6b6a421SHawking Zhang { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STATUS)}, 245c6b6a421SHawking Zhang { SOC15_REG_ENTRY(GC, 0, mmGB_ADDR_CONFIG)}, 246c6b6a421SHawking Zhang }; 247c6b6a421SHawking Zhang 248c6b6a421SHawking Zhang static uint32_t nv_read_indexed_register(struct amdgpu_device *adev, u32 se_num, 249c6b6a421SHawking Zhang u32 sh_num, u32 reg_offset) 250c6b6a421SHawking Zhang { 251c6b6a421SHawking Zhang uint32_t val; 252c6b6a421SHawking Zhang 253c6b6a421SHawking Zhang mutex_lock(&adev->grbm_idx_mutex); 254c6b6a421SHawking Zhang if (se_num != 0xffffffff || sh_num != 0xffffffff) 255c6b6a421SHawking Zhang amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff); 256c6b6a421SHawking Zhang 257c6b6a421SHawking Zhang val = RREG32(reg_offset); 258c6b6a421SHawking Zhang 259c6b6a421SHawking Zhang if (se_num != 0xffffffff || sh_num != 0xffffffff) 260c6b6a421SHawking Zhang amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 261c6b6a421SHawking Zhang mutex_unlock(&adev->grbm_idx_mutex); 262c6b6a421SHawking Zhang return val; 263c6b6a421SHawking Zhang } 264c6b6a421SHawking Zhang 265c6b6a421SHawking Zhang static uint32_t nv_get_register_value(struct amdgpu_device *adev, 266c6b6a421SHawking Zhang bool indexed, u32 se_num, 267c6b6a421SHawking Zhang u32 sh_num, u32 reg_offset) 268c6b6a421SHawking Zhang { 269c6b6a421SHawking Zhang if (indexed) { 270c6b6a421SHawking Zhang return nv_read_indexed_register(adev, se_num, sh_num, reg_offset); 271c6b6a421SHawking Zhang } else { 272c6b6a421SHawking Zhang if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG)) 273c6b6a421SHawking Zhang return adev->gfx.config.gb_addr_config; 274c6b6a421SHawking Zhang return RREG32(reg_offset); 275c6b6a421SHawking Zhang } 276c6b6a421SHawking Zhang } 277c6b6a421SHawking Zhang 278c6b6a421SHawking Zhang static int nv_read_register(struct amdgpu_device *adev, u32 se_num, 279c6b6a421SHawking Zhang u32 sh_num, u32 reg_offset, u32 *value) 280c6b6a421SHawking Zhang { 281c6b6a421SHawking Zhang uint32_t i; 282c6b6a421SHawking Zhang struct soc15_allowed_register_entry *en; 283c6b6a421SHawking Zhang 284c6b6a421SHawking Zhang *value = 0; 285c6b6a421SHawking Zhang for (i = 0; i < ARRAY_SIZE(nv_allowed_read_registers); i++) { 286c6b6a421SHawking Zhang en = &nv_allowed_read_registers[i]; 287fced3c3aSHuang Rui if ((i == 7 && (adev->sdma.num_instances == 1)) || /* some asics don't have SDMA1 */ 288fced3c3aSHuang Rui reg_offset != 289c6b6a421SHawking Zhang (adev->reg_offset[en->hwip][en->inst][en->seg] + en->reg_offset)) 290c6b6a421SHawking Zhang continue; 291c6b6a421SHawking Zhang 292c6b6a421SHawking Zhang *value = nv_get_register_value(adev, 293c6b6a421SHawking Zhang nv_allowed_read_registers[i].grbm_indexed, 294c6b6a421SHawking Zhang se_num, sh_num, reg_offset); 295c6b6a421SHawking Zhang return 0; 296c6b6a421SHawking Zhang } 297c6b6a421SHawking Zhang return -EINVAL; 298c6b6a421SHawking Zhang } 299c6b6a421SHawking Zhang 3003e2bb60aSKevin Wang static int nv_asic_mode1_reset(struct amdgpu_device *adev) 3013e2bb60aSKevin Wang { 3023e2bb60aSKevin Wang u32 i; 3033e2bb60aSKevin Wang int ret = 0; 3043e2bb60aSKevin Wang 3053e2bb60aSKevin Wang amdgpu_atombios_scratch_regs_engine_hung(adev, true); 3063e2bb60aSKevin Wang 3073e2bb60aSKevin Wang /* disable BM */ 3083e2bb60aSKevin Wang pci_clear_master(adev->pdev); 3093e2bb60aSKevin Wang 310c1dd4aa6SAndrey Grodzovsky amdgpu_device_cache_pci_state(adev->pdev); 3113e2bb60aSKevin Wang 312311531f0SWenhui Sheng if (amdgpu_dpm_is_mode1_reset_supported(adev)) { 313311531f0SWenhui Sheng dev_info(adev->dev, "GPU smu mode1 reset\n"); 314311531f0SWenhui Sheng ret = amdgpu_dpm_mode1_reset(adev); 315311531f0SWenhui Sheng } else { 316311531f0SWenhui Sheng dev_info(adev->dev, "GPU psp mode1 reset\n"); 3173e2bb60aSKevin Wang ret = psp_gpu_reset(adev); 318311531f0SWenhui Sheng } 319311531f0SWenhui Sheng 3203e2bb60aSKevin Wang if (ret) 3213e2bb60aSKevin Wang dev_err(adev->dev, "GPU mode1 reset failed\n"); 322c1dd4aa6SAndrey Grodzovsky amdgpu_device_load_pci_state(adev->pdev); 3233e2bb60aSKevin Wang 3243e2bb60aSKevin Wang /* wait for asic to come out of reset */ 3253e2bb60aSKevin Wang for (i = 0; i < adev->usec_timeout; i++) { 326bebc0762SHawking Zhang u32 memsize = adev->nbio.funcs->get_memsize(adev); 3273e2bb60aSKevin Wang 3283e2bb60aSKevin Wang if (memsize != 0xffffffff) 3293e2bb60aSKevin Wang break; 3303e2bb60aSKevin Wang udelay(1); 3313e2bb60aSKevin Wang } 3323e2bb60aSKevin Wang 3333e2bb60aSKevin Wang amdgpu_atombios_scratch_regs_engine_hung(adev, false); 3343e2bb60aSKevin Wang 3353e2bb60aSKevin Wang return ret; 3363e2bb60aSKevin Wang } 3372ddc6c3eSAlex Deucher 338ac742616SAlex Deucher static bool nv_asic_supports_baco(struct amdgpu_device *adev) 339ac742616SAlex Deucher { 340ac742616SAlex Deucher struct smu_context *smu = &adev->smu; 341ac742616SAlex Deucher 342ac742616SAlex Deucher if (smu_baco_is_support(smu)) 343ac742616SAlex Deucher return true; 344ac742616SAlex Deucher else 345ac742616SAlex Deucher return false; 346ac742616SAlex Deucher } 347ac742616SAlex Deucher 3482ddc6c3eSAlex Deucher static enum amd_reset_method 3492ddc6c3eSAlex Deucher nv_asic_reset_method(struct amdgpu_device *adev) 3502ddc6c3eSAlex Deucher { 3512ddc6c3eSAlex Deucher struct smu_context *smu = &adev->smu; 3522ddc6c3eSAlex Deucher 353273da6ffSWenhui Sheng if (amdgpu_reset_method == AMD_RESET_METHOD_MODE1 || 354273da6ffSWenhui Sheng amdgpu_reset_method == AMD_RESET_METHOD_BACO) 355273da6ffSWenhui Sheng return amdgpu_reset_method; 356273da6ffSWenhui Sheng 357273da6ffSWenhui Sheng if (amdgpu_reset_method != -1) 358273da6ffSWenhui Sheng dev_warn(adev->dev, "Specified reset method:%d isn't supported, using AUTO instead.\n", 359273da6ffSWenhui Sheng amdgpu_reset_method); 360273da6ffSWenhui Sheng 361ca6fd7a6SLikun Gao switch (adev->asic_type) { 362ca6fd7a6SLikun Gao case CHIP_SIENNA_CICHLID: 36322dd44f4SJiansong Chen case CHIP_NAVY_FLOUNDER: 364ca6fd7a6SLikun Gao return AMD_RESET_METHOD_MODE1; 365ca6fd7a6SLikun Gao default: 366311531f0SWenhui Sheng if (smu_baco_is_support(smu)) 3672ddc6c3eSAlex Deucher return AMD_RESET_METHOD_BACO; 3682ddc6c3eSAlex Deucher else 3692ddc6c3eSAlex Deucher return AMD_RESET_METHOD_MODE1; 3702ddc6c3eSAlex Deucher } 371ca6fd7a6SLikun Gao } 3722ddc6c3eSAlex Deucher 373c6b6a421SHawking Zhang static int nv_asic_reset(struct amdgpu_device *adev) 374c6b6a421SHawking Zhang { 375767acabdSKevin Wang int ret = 0; 376767acabdSKevin Wang struct smu_context *smu = &adev->smu; 377c6b6a421SHawking Zhang 378e3526257SMonk Liu if (nv_asic_reset_method(adev) == AMD_RESET_METHOD_BACO) { 37911043b7aSAlex Deucher dev_info(adev->dev, "BACO reset\n"); 380311531f0SWenhui Sheng 38111520f27SAlex Deucher ret = smu_baco_enter(smu); 38211520f27SAlex Deucher if (ret) 38311520f27SAlex Deucher return ret; 38411520f27SAlex Deucher ret = smu_baco_exit(smu); 38511520f27SAlex Deucher if (ret) 38611520f27SAlex Deucher return ret; 38711043b7aSAlex Deucher } else { 38811043b7aSAlex Deucher dev_info(adev->dev, "MODE1 reset\n"); 3893e2bb60aSKevin Wang ret = nv_asic_mode1_reset(adev); 39011043b7aSAlex Deucher } 391767acabdSKevin Wang 392767acabdSKevin Wang return ret; 393c6b6a421SHawking Zhang } 394c6b6a421SHawking Zhang 395c6b6a421SHawking Zhang static int nv_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk) 396c6b6a421SHawking Zhang { 397c6b6a421SHawking Zhang /* todo */ 398c6b6a421SHawking Zhang return 0; 399c6b6a421SHawking Zhang } 400c6b6a421SHawking Zhang 401c6b6a421SHawking Zhang static int nv_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk) 402c6b6a421SHawking Zhang { 403c6b6a421SHawking Zhang /* todo */ 404c6b6a421SHawking Zhang return 0; 405c6b6a421SHawking Zhang } 406c6b6a421SHawking Zhang 407c6b6a421SHawking Zhang static void nv_pcie_gen3_enable(struct amdgpu_device *adev) 408c6b6a421SHawking Zhang { 409c6b6a421SHawking Zhang if (pci_is_root_bus(adev->pdev->bus)) 410c6b6a421SHawking Zhang return; 411c6b6a421SHawking Zhang 412c6b6a421SHawking Zhang if (amdgpu_pcie_gen2 == 0) 413c6b6a421SHawking Zhang return; 414c6b6a421SHawking Zhang 415c6b6a421SHawking Zhang if (!(adev->pm.pcie_gen_mask & (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 | 416c6b6a421SHawking Zhang CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3))) 417c6b6a421SHawking Zhang return; 418c6b6a421SHawking Zhang 419c6b6a421SHawking Zhang /* todo */ 420c6b6a421SHawking Zhang } 421c6b6a421SHawking Zhang 422c6b6a421SHawking Zhang static void nv_program_aspm(struct amdgpu_device *adev) 423c6b6a421SHawking Zhang { 424c6b6a421SHawking Zhang 425c6b6a421SHawking Zhang if (amdgpu_aspm == 0) 426c6b6a421SHawking Zhang return; 427c6b6a421SHawking Zhang 428c6b6a421SHawking Zhang /* todo */ 429c6b6a421SHawking Zhang } 430c6b6a421SHawking Zhang 431c6b6a421SHawking Zhang static void nv_enable_doorbell_aperture(struct amdgpu_device *adev, 432c6b6a421SHawking Zhang bool enable) 433c6b6a421SHawking Zhang { 434bebc0762SHawking Zhang adev->nbio.funcs->enable_doorbell_aperture(adev, enable); 435bebc0762SHawking Zhang adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, enable); 436c6b6a421SHawking Zhang } 437c6b6a421SHawking Zhang 438c6b6a421SHawking Zhang static const struct amdgpu_ip_block_version nv_common_ip_block = 439c6b6a421SHawking Zhang { 440c6b6a421SHawking Zhang .type = AMD_IP_BLOCK_TYPE_COMMON, 441c6b6a421SHawking Zhang .major = 1, 442c6b6a421SHawking Zhang .minor = 0, 443c6b6a421SHawking Zhang .rev = 0, 444c6b6a421SHawking Zhang .funcs = &nv_common_ip_funcs, 445c6b6a421SHawking Zhang }; 446c6b6a421SHawking Zhang 447b5c73856SXiaojie Yuan static int nv_reg_base_init(struct amdgpu_device *adev) 448c6b6a421SHawking Zhang { 449b5c73856SXiaojie Yuan int r; 450b5c73856SXiaojie Yuan 451b5c73856SXiaojie Yuan if (amdgpu_discovery) { 452b5c73856SXiaojie Yuan r = amdgpu_discovery_reg_base_init(adev); 453b5c73856SXiaojie Yuan if (r) { 454b5c73856SXiaojie Yuan DRM_WARN("failed to init reg base from ip discovery table, " 455b5c73856SXiaojie Yuan "fallback to legacy init method\n"); 456b5c73856SXiaojie Yuan goto legacy_init; 457b5c73856SXiaojie Yuan } 458b5c73856SXiaojie Yuan 459b5c73856SXiaojie Yuan return 0; 460b5c73856SXiaojie Yuan } 461b5c73856SXiaojie Yuan 462b5c73856SXiaojie Yuan legacy_init: 463c6b6a421SHawking Zhang switch (adev->asic_type) { 464c6b6a421SHawking Zhang case CHIP_NAVI10: 465c6b6a421SHawking Zhang navi10_reg_base_init(adev); 466c6b6a421SHawking Zhang break; 467a0f6d926SXiaojie Yuan case CHIP_NAVI14: 468a0f6d926SXiaojie Yuan navi14_reg_base_init(adev); 469a0f6d926SXiaojie Yuan break; 47003d0a073SXiaojie Yuan case CHIP_NAVI12: 47103d0a073SXiaojie Yuan navi12_reg_base_init(adev); 47203d0a073SXiaojie Yuan break; 473dccdbf3fSLikun Gao case CHIP_SIENNA_CICHLID: 474c8c959f6SJiansong Chen case CHIP_NAVY_FLOUNDER: 475dccdbf3fSLikun Gao sienna_cichlid_reg_base_init(adev); 476dccdbf3fSLikun Gao break; 477026570e6SHuang Rui case CHIP_VANGOGH: 478026570e6SHuang Rui vangogh_reg_base_init(adev); 479026570e6SHuang Rui break; 480c6b6a421SHawking Zhang default: 481c6b6a421SHawking Zhang return -EINVAL; 482c6b6a421SHawking Zhang } 483c6b6a421SHawking Zhang 484b5c73856SXiaojie Yuan return 0; 485b5c73856SXiaojie Yuan } 486b5c73856SXiaojie Yuan 487c1299461SWenhui Sheng void nv_set_virt_ops(struct amdgpu_device *adev) 488c1299461SWenhui Sheng { 489c1299461SWenhui Sheng adev->virt.ops = &xgpu_nv_virt_ops; 490c1299461SWenhui Sheng } 491c1299461SWenhui Sheng 492b5c73856SXiaojie Yuan int nv_set_ip_blocks(struct amdgpu_device *adev) 493b5c73856SXiaojie Yuan { 494b5c73856SXiaojie Yuan int r; 495b5c73856SXiaojie Yuan 496122078deSMonk Liu adev->nbio.funcs = &nbio_v2_3_funcs; 497122078deSMonk Liu adev->nbio.hdp_flush_reg = &nbio_v2_3_hdp_flush_reg; 498122078deSMonk Liu 499c652923aSJohn Clements if (adev->asic_type == CHIP_SIENNA_CICHLID) 500c652923aSJohn Clements adev->gmc.xgmi.supported = true; 501c652923aSJohn Clements 502b5c73856SXiaojie Yuan /* Set IP register base before any HW register access */ 503b5c73856SXiaojie Yuan r = nv_reg_base_init(adev); 504b5c73856SXiaojie Yuan if (r) 505b5c73856SXiaojie Yuan return r; 506b5c73856SXiaojie Yuan 507c6b6a421SHawking Zhang switch (adev->asic_type) { 508c6b6a421SHawking Zhang case CHIP_NAVI10: 509d1daf850SAlex Deucher case CHIP_NAVI14: 510c6b6a421SHawking Zhang amdgpu_device_ip_block_add(adev, &nv_common_ip_block); 511c6b6a421SHawking Zhang amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block); 512c6b6a421SHawking Zhang amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block); 513c6b6a421SHawking Zhang amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block); 514c6b6a421SHawking Zhang if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP && 5159530273eSEvan Quan !amdgpu_sriov_vf(adev)) 516c6b6a421SHawking Zhang amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 517c6b6a421SHawking Zhang if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) 518c6b6a421SHawking Zhang amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block); 519f8a7976bSAlex Deucher #if defined(CONFIG_DRM_AMD_DC) 520b4f199c7SHarry Wentland else if (amdgpu_device_has_dc_support(adev)) 521b4f199c7SHarry Wentland amdgpu_device_ip_block_add(adev, &dm_ip_block); 522f8a7976bSAlex Deucher #endif 523c6b6a421SHawking Zhang amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block); 524c6b6a421SHawking Zhang amdgpu_device_ip_block_add(adev, &sdma_v5_0_ip_block); 525c6b6a421SHawking Zhang if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT && 5269530273eSEvan Quan !amdgpu_sriov_vf(adev)) 527c6b6a421SHawking Zhang amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 528c6b6a421SHawking Zhang amdgpu_device_ip_block_add(adev, &vcn_v2_0_ip_block); 5295be45a26SLeo Liu amdgpu_device_ip_block_add(adev, &jpeg_v2_0_ip_block); 530c6b6a421SHawking Zhang if (adev->enable_mes) 531c6b6a421SHawking Zhang amdgpu_device_ip_block_add(adev, &mes_v10_1_ip_block); 532c6b6a421SHawking Zhang break; 53344e9e7c9SXiaojie Yuan case CHIP_NAVI12: 53444e9e7c9SXiaojie Yuan amdgpu_device_ip_block_add(adev, &nv_common_ip_block); 53544e9e7c9SXiaojie Yuan amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block); 53644e9e7c9SXiaojie Yuan amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block); 5376b66ae2eSXiaojie Yuan amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block); 53879bebabbSMonk Liu if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) 5397f47efebSXiaojie Yuan amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 54079902029SXiaojie Yuan if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) 54179902029SXiaojie Yuan amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block); 54220c14ee1SPetr Cvek #if defined(CONFIG_DRM_AMD_DC) 543078655d9SLeo Li else if (amdgpu_device_has_dc_support(adev)) 544078655d9SLeo Li amdgpu_device_ip_block_add(adev, &dm_ip_block); 54520c14ee1SPetr Cvek #endif 54644e9e7c9SXiaojie Yuan amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block); 54744e9e7c9SXiaojie Yuan amdgpu_device_ip_block_add(adev, &sdma_v5_0_ip_block); 5487f47efebSXiaojie Yuan if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT && 5499530273eSEvan Quan !amdgpu_sriov_vf(adev)) 5507f47efebSXiaojie Yuan amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 5511fbed280SBoyuan Zhang amdgpu_device_ip_block_add(adev, &vcn_v2_0_ip_block); 552fe442491SMonk Liu if (!amdgpu_sriov_vf(adev)) 5535be45a26SLeo Liu amdgpu_device_ip_block_add(adev, &jpeg_v2_0_ip_block); 55444e9e7c9SXiaojie Yuan break; 5552e1ba10eSLikun Gao case CHIP_SIENNA_CICHLID: 5562e1ba10eSLikun Gao amdgpu_device_ip_block_add(adev, &nv_common_ip_block); 5570b3df16bSLikun Gao amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block); 558757b3af8SLikun Gao amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block); 55956304e72SLikun Gao if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) 5605aa02350SLikun Gao amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block); 561b07e5c60SLikun Gao if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP && 56238d5bbefSshaoyunl is_support_sw_smu(adev) && !amdgpu_sriov_vf(adev)) 563b07e5c60SLikun Gao amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 5649a986760SLikun Gao if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) 5659a986760SLikun Gao amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block); 566464ab91aSBhawanpreet Lakha #if defined(CONFIG_DRM_AMD_DC) 567464ab91aSBhawanpreet Lakha else if (amdgpu_device_has_dc_support(adev)) 568464ab91aSBhawanpreet Lakha amdgpu_device_ip_block_add(adev, &dm_ip_block); 569464ab91aSBhawanpreet Lakha #endif 570933c8a93SLikun Gao amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block); 571157e72e8SLikun Gao amdgpu_device_ip_block_add(adev, &sdma_v5_2_ip_block); 572b8f10585SLeo Liu amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block); 573c45fbe1bSJack Zhang if (!amdgpu_sriov_vf(adev)) 5744d72dd12SLeo Liu amdgpu_device_ip_block_add(adev, &jpeg_v3_0_ip_block); 575c45fbe1bSJack Zhang 576a346ef86SJack Xiao if (adev->enable_mes) 577a346ef86SJack Xiao amdgpu_device_ip_block_add(adev, &mes_v10_1_ip_block); 5782e1ba10eSLikun Gao break; 5798515e0a4SJiansong Chen case CHIP_NAVY_FLOUNDER: 5808515e0a4SJiansong Chen amdgpu_device_ip_block_add(adev, &nv_common_ip_block); 581fc8f07daSJiansong Chen amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block); 582026c396bSJiansong Chen amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block); 5837420eab2SJiansong Chen if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) 5847420eab2SJiansong Chen amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block); 5857420eab2SJiansong Chen if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP && 5867420eab2SJiansong Chen is_support_sw_smu(adev)) 5877420eab2SJiansong Chen amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 5885404f073SJiansong Chen if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) 5895404f073SJiansong Chen amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block); 590a6c5308fSBhawanpreet Lakha #if defined(CONFIG_DRM_AMD_DC) 591a6c5308fSBhawanpreet Lakha else if (amdgpu_device_has_dc_support(adev)) 592a6c5308fSBhawanpreet Lakha amdgpu_device_ip_block_add(adev, &dm_ip_block); 593a6c5308fSBhawanpreet Lakha #endif 594885eb3faSJiansong Chen amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block); 595df2d15dfSJiansong Chen amdgpu_device_ip_block_add(adev, &sdma_v5_2_ip_block); 596290b4ad5SBoyuan Zhang amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block); 597290b4ad5SBoyuan Zhang amdgpu_device_ip_block_add(adev, &jpeg_v3_0_ip_block); 598f4497d10SJiansong Chen if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT && 599f4497d10SJiansong Chen is_support_sw_smu(adev)) 600f4497d10SJiansong Chen amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 6018515e0a4SJiansong Chen break; 60288edbad6SHuang Rui case CHIP_VANGOGH: 60388edbad6SHuang Rui amdgpu_device_ip_block_add(adev, &nv_common_ip_block); 60488edbad6SHuang Rui amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block); 60588edbad6SHuang Rui amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block); 60688edbad6SHuang Rui if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) 60788edbad6SHuang Rui amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block); 60888edbad6SHuang Rui amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block); 60988edbad6SHuang Rui amdgpu_device_ip_block_add(adev, &sdma_v5_2_ip_block); 610b4e532d6SThong Thai amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block); 611b4e532d6SThong Thai amdgpu_device_ip_block_add(adev, &jpeg_v3_0_ip_block); 61288edbad6SHuang Rui break; 613c6b6a421SHawking Zhang default: 614c6b6a421SHawking Zhang return -EINVAL; 615c6b6a421SHawking Zhang } 616c6b6a421SHawking Zhang 617c6b6a421SHawking Zhang return 0; 618c6b6a421SHawking Zhang } 619c6b6a421SHawking Zhang 620c6b6a421SHawking Zhang static uint32_t nv_get_rev_id(struct amdgpu_device *adev) 621c6b6a421SHawking Zhang { 622bebc0762SHawking Zhang return adev->nbio.funcs->get_rev_id(adev); 623c6b6a421SHawking Zhang } 624c6b6a421SHawking Zhang 625c6b6a421SHawking Zhang static void nv_flush_hdp(struct amdgpu_device *adev, struct amdgpu_ring *ring) 626c6b6a421SHawking Zhang { 627bebc0762SHawking Zhang adev->nbio.funcs->hdp_flush(adev, ring); 628c6b6a421SHawking Zhang } 629c6b6a421SHawking Zhang 630c6b6a421SHawking Zhang static void nv_invalidate_hdp(struct amdgpu_device *adev, 631c6b6a421SHawking Zhang struct amdgpu_ring *ring) 632c6b6a421SHawking Zhang { 633c6b6a421SHawking Zhang if (!ring || !ring->funcs->emit_wreg) { 63478f0aef1SStanley.Yang WREG32_SOC15_NO_KIQ(HDP, 0, mmHDP_READ_CACHE_INVALIDATE, 1); 635c6b6a421SHawking Zhang } else { 636c6b6a421SHawking Zhang amdgpu_ring_emit_wreg(ring, SOC15_REG_OFFSET( 637c6b6a421SHawking Zhang HDP, 0, mmHDP_READ_CACHE_INVALIDATE), 1); 638c6b6a421SHawking Zhang } 639c6b6a421SHawking Zhang } 640c6b6a421SHawking Zhang 641c6b6a421SHawking Zhang static bool nv_need_full_reset(struct amdgpu_device *adev) 642c6b6a421SHawking Zhang { 643c6b6a421SHawking Zhang return true; 644c6b6a421SHawking Zhang } 645c6b6a421SHawking Zhang 646c6b6a421SHawking Zhang static bool nv_need_reset_on_init(struct amdgpu_device *adev) 647c6b6a421SHawking Zhang { 648c6b6a421SHawking Zhang u32 sol_reg; 649c6b6a421SHawking Zhang 650c6b6a421SHawking Zhang if (adev->flags & AMD_IS_APU) 651c6b6a421SHawking Zhang return false; 652c6b6a421SHawking Zhang 653c6b6a421SHawking Zhang /* Check sOS sign of life register to confirm sys driver and sOS 654c6b6a421SHawking Zhang * are already been loaded. 655c6b6a421SHawking Zhang */ 656c6b6a421SHawking Zhang sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81); 657c6b6a421SHawking Zhang if (sol_reg) 658c6b6a421SHawking Zhang return true; 6593967ae6dSAlex Deucher 660c6b6a421SHawking Zhang return false; 661c6b6a421SHawking Zhang } 662c6b6a421SHawking Zhang 6632af81531SKevin Wang static uint64_t nv_get_pcie_replay_count(struct amdgpu_device *adev) 6642af81531SKevin Wang { 6652af81531SKevin Wang 6662af81531SKevin Wang /* TODO 6672af81531SKevin Wang * dummy implement for pcie_replay_count sysfs interface 6682af81531SKevin Wang * */ 6692af81531SKevin Wang 6702af81531SKevin Wang return 0; 6712af81531SKevin Wang } 6722af81531SKevin Wang 673c6b6a421SHawking Zhang static void nv_init_doorbell_index(struct amdgpu_device *adev) 674c6b6a421SHawking Zhang { 675c6b6a421SHawking Zhang adev->doorbell_index.kiq = AMDGPU_NAVI10_DOORBELL_KIQ; 676c6b6a421SHawking Zhang adev->doorbell_index.mec_ring0 = AMDGPU_NAVI10_DOORBELL_MEC_RING0; 677c6b6a421SHawking Zhang adev->doorbell_index.mec_ring1 = AMDGPU_NAVI10_DOORBELL_MEC_RING1; 678c6b6a421SHawking Zhang adev->doorbell_index.mec_ring2 = AMDGPU_NAVI10_DOORBELL_MEC_RING2; 679c6b6a421SHawking Zhang adev->doorbell_index.mec_ring3 = AMDGPU_NAVI10_DOORBELL_MEC_RING3; 680c6b6a421SHawking Zhang adev->doorbell_index.mec_ring4 = AMDGPU_NAVI10_DOORBELL_MEC_RING4; 681c6b6a421SHawking Zhang adev->doorbell_index.mec_ring5 = AMDGPU_NAVI10_DOORBELL_MEC_RING5; 682c6b6a421SHawking Zhang adev->doorbell_index.mec_ring6 = AMDGPU_NAVI10_DOORBELL_MEC_RING6; 683c6b6a421SHawking Zhang adev->doorbell_index.mec_ring7 = AMDGPU_NAVI10_DOORBELL_MEC_RING7; 684c6b6a421SHawking Zhang adev->doorbell_index.userqueue_start = AMDGPU_NAVI10_DOORBELL_USERQUEUE_START; 685c6b6a421SHawking Zhang adev->doorbell_index.userqueue_end = AMDGPU_NAVI10_DOORBELL_USERQUEUE_END; 686c6b6a421SHawking Zhang adev->doorbell_index.gfx_ring0 = AMDGPU_NAVI10_DOORBELL_GFX_RING0; 687c6b6a421SHawking Zhang adev->doorbell_index.gfx_ring1 = AMDGPU_NAVI10_DOORBELL_GFX_RING1; 68820519232SJack Xiao adev->doorbell_index.mes_ring = AMDGPU_NAVI10_DOORBELL_MES_RING; 689c6b6a421SHawking Zhang adev->doorbell_index.sdma_engine[0] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE0; 690c6b6a421SHawking Zhang adev->doorbell_index.sdma_engine[1] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE1; 691157e72e8SLikun Gao adev->doorbell_index.sdma_engine[2] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE2; 692157e72e8SLikun Gao adev->doorbell_index.sdma_engine[3] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE3; 693c6b6a421SHawking Zhang adev->doorbell_index.ih = AMDGPU_NAVI10_DOORBELL_IH; 694c6b6a421SHawking Zhang adev->doorbell_index.vcn.vcn_ring0_1 = AMDGPU_NAVI10_DOORBELL64_VCN0_1; 695c6b6a421SHawking Zhang adev->doorbell_index.vcn.vcn_ring2_3 = AMDGPU_NAVI10_DOORBELL64_VCN2_3; 696c6b6a421SHawking Zhang adev->doorbell_index.vcn.vcn_ring4_5 = AMDGPU_NAVI10_DOORBELL64_VCN4_5; 697c6b6a421SHawking Zhang adev->doorbell_index.vcn.vcn_ring6_7 = AMDGPU_NAVI10_DOORBELL64_VCN6_7; 698c6b6a421SHawking Zhang adev->doorbell_index.first_non_cp = AMDGPU_NAVI10_DOORBELL64_FIRST_NON_CP; 699c6b6a421SHawking Zhang adev->doorbell_index.last_non_cp = AMDGPU_NAVI10_DOORBELL64_LAST_NON_CP; 700c6b6a421SHawking Zhang 701c6b6a421SHawking Zhang adev->doorbell_index.max_assignment = AMDGPU_NAVI10_DOORBELL_MAX_ASSIGNMENT << 1; 702c6b6a421SHawking Zhang adev->doorbell_index.sdma_doorbell_range = 20; 703c6b6a421SHawking Zhang } 704c6b6a421SHawking Zhang 705a7173731SAlex Deucher static void nv_pre_asic_init(struct amdgpu_device *adev) 706a7173731SAlex Deucher { 707a7173731SAlex Deucher } 708a7173731SAlex Deucher 709c6b6a421SHawking Zhang static const struct amdgpu_asic_funcs nv_asic_funcs = 710c6b6a421SHawking Zhang { 711c6b6a421SHawking Zhang .read_disabled_bios = &nv_read_disabled_bios, 712c6b6a421SHawking Zhang .read_bios_from_rom = &nv_read_bios_from_rom, 713c6b6a421SHawking Zhang .read_register = &nv_read_register, 714c6b6a421SHawking Zhang .reset = &nv_asic_reset, 7152ddc6c3eSAlex Deucher .reset_method = &nv_asic_reset_method, 716c6b6a421SHawking Zhang .set_vga_state = &nv_vga_set_state, 717c6b6a421SHawking Zhang .get_xclk = &nv_get_xclk, 718c6b6a421SHawking Zhang .set_uvd_clocks = &nv_set_uvd_clocks, 719c6b6a421SHawking Zhang .set_vce_clocks = &nv_set_vce_clocks, 720c6b6a421SHawking Zhang .get_config_memsize = &nv_get_config_memsize, 721c6b6a421SHawking Zhang .flush_hdp = &nv_flush_hdp, 722c6b6a421SHawking Zhang .invalidate_hdp = &nv_invalidate_hdp, 723c6b6a421SHawking Zhang .init_doorbell_index = &nv_init_doorbell_index, 724c6b6a421SHawking Zhang .need_full_reset = &nv_need_full_reset, 725c6b6a421SHawking Zhang .need_reset_on_init = &nv_need_reset_on_init, 7262af81531SKevin Wang .get_pcie_replay_count = &nv_get_pcie_replay_count, 727ac742616SAlex Deucher .supports_baco = &nv_asic_supports_baco, 728a7173731SAlex Deucher .pre_asic_init = &nv_pre_asic_init, 729c6b6a421SHawking Zhang }; 730c6b6a421SHawking Zhang 731c6b6a421SHawking Zhang static int nv_common_early_init(void *handle) 732c6b6a421SHawking Zhang { 733923c087aSYong Zhao #define MMIO_REG_HOLE_OFFSET (0x80000 - PAGE_SIZE) 734c6b6a421SHawking Zhang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 735c6b6a421SHawking Zhang 736923c087aSYong Zhao adev->rmmio_remap.reg_offset = MMIO_REG_HOLE_OFFSET; 737923c087aSYong Zhao adev->rmmio_remap.bus_addr = adev->rmmio_base + MMIO_REG_HOLE_OFFSET; 738c6b6a421SHawking Zhang adev->smc_rreg = NULL; 739c6b6a421SHawking Zhang adev->smc_wreg = NULL; 740c6b6a421SHawking Zhang adev->pcie_rreg = &nv_pcie_rreg; 741c6b6a421SHawking Zhang adev->pcie_wreg = &nv_pcie_wreg; 7424922f1bcSJohn Clements adev->pcie_rreg64 = &nv_pcie_rreg64; 7434922f1bcSJohn Clements adev->pcie_wreg64 = &nv_pcie_wreg64; 744*5de54343SHuang Rui adev->pciep_rreg = &nv_pcie_port_rreg; 745*5de54343SHuang Rui adev->pciep_wreg = &nv_pcie_port_wreg; 746c6b6a421SHawking Zhang 747c6b6a421SHawking Zhang /* TODO: will add them during VCN v2 implementation */ 748c6b6a421SHawking Zhang adev->uvd_ctx_rreg = NULL; 749c6b6a421SHawking Zhang adev->uvd_ctx_wreg = NULL; 750c6b6a421SHawking Zhang 751c6b6a421SHawking Zhang adev->didt_rreg = &nv_didt_rreg; 752c6b6a421SHawking Zhang adev->didt_wreg = &nv_didt_wreg; 753c6b6a421SHawking Zhang 754c6b6a421SHawking Zhang adev->asic_funcs = &nv_asic_funcs; 755c6b6a421SHawking Zhang 756c6b6a421SHawking Zhang adev->rev_id = nv_get_rev_id(adev); 757c6b6a421SHawking Zhang adev->external_rev_id = 0xff; 758c6b6a421SHawking Zhang switch (adev->asic_type) { 759c6b6a421SHawking Zhang case CHIP_NAVI10: 760c6b6a421SHawking Zhang adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 761c6b6a421SHawking Zhang AMD_CG_SUPPORT_GFX_CGCG | 762c6b6a421SHawking Zhang AMD_CG_SUPPORT_IH_CG | 763c6b6a421SHawking Zhang AMD_CG_SUPPORT_HDP_MGCG | 764c6b6a421SHawking Zhang AMD_CG_SUPPORT_HDP_LS | 765c6b6a421SHawking Zhang AMD_CG_SUPPORT_SDMA_MGCG | 766c6b6a421SHawking Zhang AMD_CG_SUPPORT_SDMA_LS | 767c6b6a421SHawking Zhang AMD_CG_SUPPORT_MC_MGCG | 768c6b6a421SHawking Zhang AMD_CG_SUPPORT_MC_LS | 769c6b6a421SHawking Zhang AMD_CG_SUPPORT_ATHUB_MGCG | 770c6b6a421SHawking Zhang AMD_CG_SUPPORT_ATHUB_LS | 771c6b6a421SHawking Zhang AMD_CG_SUPPORT_VCN_MGCG | 772099d66e4SLeo Liu AMD_CG_SUPPORT_JPEG_MGCG | 773c6b6a421SHawking Zhang AMD_CG_SUPPORT_BIF_MGCG | 774c6b6a421SHawking Zhang AMD_CG_SUPPORT_BIF_LS; 775157710eaSLeo Liu adev->pg_flags = AMD_PG_SUPPORT_VCN | 776c12d410fSHuang Rui AMD_PG_SUPPORT_VCN_DPG | 777099d66e4SLeo Liu AMD_PG_SUPPORT_JPEG | 778a201b6acSHuang Rui AMD_PG_SUPPORT_ATHUB; 779c6b6a421SHawking Zhang adev->external_rev_id = adev->rev_id + 0x1; 780c6b6a421SHawking Zhang break; 7815e71e011SXiaojie Yuan case CHIP_NAVI14: 782d0c39f8cSXiaojie Yuan adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 783d0c39f8cSXiaojie Yuan AMD_CG_SUPPORT_GFX_CGCG | 784d0c39f8cSXiaojie Yuan AMD_CG_SUPPORT_IH_CG | 785d0c39f8cSXiaojie Yuan AMD_CG_SUPPORT_HDP_MGCG | 786d0c39f8cSXiaojie Yuan AMD_CG_SUPPORT_HDP_LS | 787d0c39f8cSXiaojie Yuan AMD_CG_SUPPORT_SDMA_MGCG | 788d0c39f8cSXiaojie Yuan AMD_CG_SUPPORT_SDMA_LS | 789d0c39f8cSXiaojie Yuan AMD_CG_SUPPORT_MC_MGCG | 790d0c39f8cSXiaojie Yuan AMD_CG_SUPPORT_MC_LS | 791d0c39f8cSXiaojie Yuan AMD_CG_SUPPORT_ATHUB_MGCG | 792d0c39f8cSXiaojie Yuan AMD_CG_SUPPORT_ATHUB_LS | 793d0c39f8cSXiaojie Yuan AMD_CG_SUPPORT_VCN_MGCG | 794099d66e4SLeo Liu AMD_CG_SUPPORT_JPEG_MGCG | 795d0c39f8cSXiaojie Yuan AMD_CG_SUPPORT_BIF_MGCG | 796d0c39f8cSXiaojie Yuan AMD_CG_SUPPORT_BIF_LS; 7970377b088SXiaojie Yuan adev->pg_flags = AMD_PG_SUPPORT_VCN | 798099d66e4SLeo Liu AMD_PG_SUPPORT_JPEG | 7990377b088SXiaojie Yuan AMD_PG_SUPPORT_VCN_DPG; 80035ef88faStiancyin adev->external_rev_id = adev->rev_id + 20; 8015e71e011SXiaojie Yuan break; 80274b5e509SXiaojie Yuan case CHIP_NAVI12: 803dca009e7SXiaojie Yuan adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 804dca009e7SXiaojie Yuan AMD_CG_SUPPORT_GFX_MGLS | 805dca009e7SXiaojie Yuan AMD_CG_SUPPORT_GFX_CGCG | 806dca009e7SXiaojie Yuan AMD_CG_SUPPORT_GFX_CP_LS | 8075211c37aSXiaojie Yuan AMD_CG_SUPPORT_GFX_RLC_LS | 808fbe0bc57SXiaojie Yuan AMD_CG_SUPPORT_IH_CG | 8095211c37aSXiaojie Yuan AMD_CG_SUPPORT_HDP_MGCG | 810358ab97fSXiaojie Yuan AMD_CG_SUPPORT_HDP_LS | 811358ab97fSXiaojie Yuan AMD_CG_SUPPORT_SDMA_MGCG | 8128b797b3dSXiaojie Yuan AMD_CG_SUPPORT_SDMA_LS | 8138b797b3dSXiaojie Yuan AMD_CG_SUPPORT_MC_MGCG | 814ca51678dSXiaojie Yuan AMD_CG_SUPPORT_MC_LS | 815ca51678dSXiaojie Yuan AMD_CG_SUPPORT_ATHUB_MGCG | 81665872e59SXiaojie Yuan AMD_CG_SUPPORT_ATHUB_LS | 817099d66e4SLeo Liu AMD_CG_SUPPORT_VCN_MGCG | 818099d66e4SLeo Liu AMD_CG_SUPPORT_JPEG_MGCG; 819c1653ea0SXiaojie Yuan adev->pg_flags = AMD_PG_SUPPORT_VCN | 8205ef3b8acSXiaojie Yuan AMD_PG_SUPPORT_VCN_DPG | 821099d66e4SLeo Liu AMD_PG_SUPPORT_JPEG | 8221b0443b1SLikun Gao AMD_PG_SUPPORT_ATHUB; 823df5e984cSTiecheng Zhou /* guest vm gets 0xffffffff when reading RCC_DEV0_EPF0_STRAP0, 824df5e984cSTiecheng Zhou * as a consequence, the rev_id and external_rev_id are wrong. 825df5e984cSTiecheng Zhou * workaround it by hardcoding rev_id to 0 (default value). 826df5e984cSTiecheng Zhou */ 827df5e984cSTiecheng Zhou if (amdgpu_sriov_vf(adev)) 828df5e984cSTiecheng Zhou adev->rev_id = 0; 82974b5e509SXiaojie Yuan adev->external_rev_id = adev->rev_id + 0xa; 83074b5e509SXiaojie Yuan break; 831117910edSLikun Gao case CHIP_SIENNA_CICHLID: 83200194defSLikun Gao adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 83300194defSLikun Gao AMD_CG_SUPPORT_GFX_CGCG | 83400194defSLikun Gao AMD_CG_SUPPORT_GFX_3D_CGCG | 83598f8ea29SLikun Gao AMD_CG_SUPPORT_MC_MGCG | 83600194defSLikun Gao AMD_CG_SUPPORT_VCN_MGCG | 837ca36461fSKenneth Feng AMD_CG_SUPPORT_JPEG_MGCG | 838ca36461fSKenneth Feng AMD_CG_SUPPORT_HDP_MGCG | 8393a32c25aSKenneth Feng AMD_CG_SUPPORT_HDP_LS | 840bcc8367fSKenneth Feng AMD_CG_SUPPORT_IH_CG | 841bcc8367fSKenneth Feng AMD_CG_SUPPORT_MC_LS; 842b467c4f5SLeo Liu adev->pg_flags = AMD_PG_SUPPORT_VCN | 843d00b0fa9SBoyuan Zhang AMD_PG_SUPPORT_VCN_DPG | 844b794616dSKenneth Feng AMD_PG_SUPPORT_JPEG | 8451b0443b1SLikun Gao AMD_PG_SUPPORT_ATHUB | 8461b0443b1SLikun Gao AMD_PG_SUPPORT_MMHUB; 847c45fbe1bSJack Zhang if (amdgpu_sriov_vf(adev)) { 848c45fbe1bSJack Zhang /* hypervisor control CG and PG enablement */ 849c45fbe1bSJack Zhang adev->cg_flags = 0; 850c45fbe1bSJack Zhang adev->pg_flags = 0; 851c45fbe1bSJack Zhang } 852117910edSLikun Gao adev->external_rev_id = adev->rev_id + 0x28; 853117910edSLikun Gao break; 854543aa259SJiansong Chen case CHIP_NAVY_FLOUNDER: 85540582e67SJiansong Chen adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 85640582e67SJiansong Chen AMD_CG_SUPPORT_GFX_CGCG | 85740582e67SJiansong Chen AMD_CG_SUPPORT_GFX_3D_CGCG | 85840582e67SJiansong Chen AMD_CG_SUPPORT_VCN_MGCG | 85992c73756SJiansong Chen AMD_CG_SUPPORT_JPEG_MGCG | 86092c73756SJiansong Chen AMD_CG_SUPPORT_MC_MGCG | 8614759f887SJiansong Chen AMD_CG_SUPPORT_MC_LS | 8624759f887SJiansong Chen AMD_CG_SUPPORT_HDP_MGCG | 86385e7151bSJiansong Chen AMD_CG_SUPPORT_HDP_LS | 86485e7151bSJiansong Chen AMD_CG_SUPPORT_IH_CG; 865c6e9dd0eSBoyuan Zhang adev->pg_flags = AMD_PG_SUPPORT_VCN | 86600740df9SBoyuan Zhang AMD_PG_SUPPORT_VCN_DPG | 86747fc894aSJiansong Chen AMD_PG_SUPPORT_JPEG | 86847fc894aSJiansong Chen AMD_PG_SUPPORT_ATHUB | 86947fc894aSJiansong Chen AMD_PG_SUPPORT_MMHUB; 870543aa259SJiansong Chen adev->external_rev_id = adev->rev_id + 0x32; 871543aa259SJiansong Chen break; 872543aa259SJiansong Chen 873026570e6SHuang Rui case CHIP_VANGOGH: 874026570e6SHuang Rui adev->cg_flags = 0; 875026570e6SHuang Rui adev->pg_flags = 0; 876026570e6SHuang Rui adev->external_rev_id = adev->rev_id + 0x01; 877026570e6SHuang Rui break; 878c6b6a421SHawking Zhang default: 879c6b6a421SHawking Zhang /* FIXME: not supported yet */ 880c6b6a421SHawking Zhang return -EINVAL; 881c6b6a421SHawking Zhang } 882c6b6a421SHawking Zhang 883b05b6903SJiange Zhao if (amdgpu_sriov_vf(adev)) { 884b05b6903SJiange Zhao amdgpu_virt_init_setting(adev); 885b05b6903SJiange Zhao xgpu_nv_mailbox_set_irq_funcs(adev); 886b05b6903SJiange Zhao } 887b05b6903SJiange Zhao 888c6b6a421SHawking Zhang return 0; 889c6b6a421SHawking Zhang } 890c6b6a421SHawking Zhang 891c6b6a421SHawking Zhang static int nv_common_late_init(void *handle) 892c6b6a421SHawking Zhang { 893b05b6903SJiange Zhao struct amdgpu_device *adev = (struct amdgpu_device *)handle; 894b05b6903SJiange Zhao 895b05b6903SJiange Zhao if (amdgpu_sriov_vf(adev)) 896b05b6903SJiange Zhao xgpu_nv_mailbox_get_irq(adev); 897b05b6903SJiange Zhao 898c6b6a421SHawking Zhang return 0; 899c6b6a421SHawking Zhang } 900c6b6a421SHawking Zhang 901c6b6a421SHawking Zhang static int nv_common_sw_init(void *handle) 902c6b6a421SHawking Zhang { 903b05b6903SJiange Zhao struct amdgpu_device *adev = (struct amdgpu_device *)handle; 904b05b6903SJiange Zhao 905b05b6903SJiange Zhao if (amdgpu_sriov_vf(adev)) 906b05b6903SJiange Zhao xgpu_nv_mailbox_add_irq_id(adev); 907b05b6903SJiange Zhao 908c6b6a421SHawking Zhang return 0; 909c6b6a421SHawking Zhang } 910c6b6a421SHawking Zhang 911c6b6a421SHawking Zhang static int nv_common_sw_fini(void *handle) 912c6b6a421SHawking Zhang { 913c6b6a421SHawking Zhang return 0; 914c6b6a421SHawking Zhang } 915c6b6a421SHawking Zhang 916c6b6a421SHawking Zhang static int nv_common_hw_init(void *handle) 917c6b6a421SHawking Zhang { 918c6b6a421SHawking Zhang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 919c6b6a421SHawking Zhang 920c6b6a421SHawking Zhang /* enable pcie gen2/3 link */ 921c6b6a421SHawking Zhang nv_pcie_gen3_enable(adev); 922c6b6a421SHawking Zhang /* enable aspm */ 923c6b6a421SHawking Zhang nv_program_aspm(adev); 924c6b6a421SHawking Zhang /* setup nbio registers */ 925bebc0762SHawking Zhang adev->nbio.funcs->init_registers(adev); 926923c087aSYong Zhao /* remap HDP registers to a hole in mmio space, 927923c087aSYong Zhao * for the purpose of expose those registers 928923c087aSYong Zhao * to process space 929923c087aSYong Zhao */ 930923c087aSYong Zhao if (adev->nbio.funcs->remap_hdp_registers) 931923c087aSYong Zhao adev->nbio.funcs->remap_hdp_registers(adev); 932c6b6a421SHawking Zhang /* enable the doorbell aperture */ 933c6b6a421SHawking Zhang nv_enable_doorbell_aperture(adev, true); 934c6b6a421SHawking Zhang 935c6b6a421SHawking Zhang return 0; 936c6b6a421SHawking Zhang } 937c6b6a421SHawking Zhang 938c6b6a421SHawking Zhang static int nv_common_hw_fini(void *handle) 939c6b6a421SHawking Zhang { 940c6b6a421SHawking Zhang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 941c6b6a421SHawking Zhang 942c6b6a421SHawking Zhang /* disable the doorbell aperture */ 943c6b6a421SHawking Zhang nv_enable_doorbell_aperture(adev, false); 944c6b6a421SHawking Zhang 945c6b6a421SHawking Zhang return 0; 946c6b6a421SHawking Zhang } 947c6b6a421SHawking Zhang 948c6b6a421SHawking Zhang static int nv_common_suspend(void *handle) 949c6b6a421SHawking Zhang { 950c6b6a421SHawking Zhang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 951c6b6a421SHawking Zhang 952c6b6a421SHawking Zhang return nv_common_hw_fini(adev); 953c6b6a421SHawking Zhang } 954c6b6a421SHawking Zhang 955c6b6a421SHawking Zhang static int nv_common_resume(void *handle) 956c6b6a421SHawking Zhang { 957c6b6a421SHawking Zhang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 958c6b6a421SHawking Zhang 959c6b6a421SHawking Zhang return nv_common_hw_init(adev); 960c6b6a421SHawking Zhang } 961c6b6a421SHawking Zhang 962c6b6a421SHawking Zhang static bool nv_common_is_idle(void *handle) 963c6b6a421SHawking Zhang { 964c6b6a421SHawking Zhang return true; 965c6b6a421SHawking Zhang } 966c6b6a421SHawking Zhang 967c6b6a421SHawking Zhang static int nv_common_wait_for_idle(void *handle) 968c6b6a421SHawking Zhang { 969c6b6a421SHawking Zhang return 0; 970c6b6a421SHawking Zhang } 971c6b6a421SHawking Zhang 972c6b6a421SHawking Zhang static int nv_common_soft_reset(void *handle) 973c6b6a421SHawking Zhang { 974c6b6a421SHawking Zhang return 0; 975c6b6a421SHawking Zhang } 976c6b6a421SHawking Zhang 977c6b6a421SHawking Zhang static void nv_update_hdp_mem_power_gating(struct amdgpu_device *adev, 978c6b6a421SHawking Zhang bool enable) 979c6b6a421SHawking Zhang { 980c6b6a421SHawking Zhang uint32_t hdp_clk_cntl, hdp_clk_cntl1; 981c6b6a421SHawking Zhang uint32_t hdp_mem_pwr_cntl; 982c6b6a421SHawking Zhang 983c6b6a421SHawking Zhang if (!(adev->cg_flags & (AMD_CG_SUPPORT_HDP_LS | 984c6b6a421SHawking Zhang AMD_CG_SUPPORT_HDP_DS | 985c6b6a421SHawking Zhang AMD_CG_SUPPORT_HDP_SD))) 986c6b6a421SHawking Zhang return; 987c6b6a421SHawking Zhang 988c6b6a421SHawking Zhang hdp_clk_cntl = hdp_clk_cntl1 = RREG32_SOC15(HDP, 0, mmHDP_CLK_CNTL); 989c6b6a421SHawking Zhang hdp_mem_pwr_cntl = RREG32_SOC15(HDP, 0, mmHDP_MEM_POWER_CTRL); 990c6b6a421SHawking Zhang 991c6b6a421SHawking Zhang /* Before doing clock/power mode switch, 992c6b6a421SHawking Zhang * forced on IPH & RC clock */ 993c6b6a421SHawking Zhang hdp_clk_cntl = REG_SET_FIELD(hdp_clk_cntl, HDP_CLK_CNTL, 994c6b6a421SHawking Zhang IPH_MEM_CLK_SOFT_OVERRIDE, 1); 995c6b6a421SHawking Zhang hdp_clk_cntl = REG_SET_FIELD(hdp_clk_cntl, HDP_CLK_CNTL, 996c6b6a421SHawking Zhang RC_MEM_CLK_SOFT_OVERRIDE, 1); 997c6b6a421SHawking Zhang WREG32_SOC15(HDP, 0, mmHDP_CLK_CNTL, hdp_clk_cntl); 998c6b6a421SHawking Zhang 999c6b6a421SHawking Zhang /* HDP 5.0 doesn't support dynamic power mode switch, 1000c6b6a421SHawking Zhang * disable clock and power gating before any changing */ 1001c6b6a421SHawking Zhang hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, 1002c6b6a421SHawking Zhang IPH_MEM_POWER_CTRL_EN, 0); 1003c6b6a421SHawking Zhang hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, 1004c6b6a421SHawking Zhang IPH_MEM_POWER_LS_EN, 0); 1005c6b6a421SHawking Zhang hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, 1006c6b6a421SHawking Zhang IPH_MEM_POWER_DS_EN, 0); 1007c6b6a421SHawking Zhang hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, 1008c6b6a421SHawking Zhang IPH_MEM_POWER_SD_EN, 0); 1009c6b6a421SHawking Zhang hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, 1010c6b6a421SHawking Zhang RC_MEM_POWER_CTRL_EN, 0); 1011c6b6a421SHawking Zhang hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, 1012c6b6a421SHawking Zhang RC_MEM_POWER_LS_EN, 0); 1013c6b6a421SHawking Zhang hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, 1014c6b6a421SHawking Zhang RC_MEM_POWER_DS_EN, 0); 1015c6b6a421SHawking Zhang hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, 1016c6b6a421SHawking Zhang RC_MEM_POWER_SD_EN, 0); 1017c6b6a421SHawking Zhang WREG32_SOC15(HDP, 0, mmHDP_MEM_POWER_CTRL, hdp_mem_pwr_cntl); 1018c6b6a421SHawking Zhang 1019c6b6a421SHawking Zhang /* only one clock gating mode (LS/DS/SD) can be enabled */ 1020c6b6a421SHawking Zhang if (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS) { 1021c6b6a421SHawking Zhang hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, 1022c6b6a421SHawking Zhang HDP_MEM_POWER_CTRL, 1023c6b6a421SHawking Zhang IPH_MEM_POWER_LS_EN, enable); 1024c6b6a421SHawking Zhang hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, 1025c6b6a421SHawking Zhang HDP_MEM_POWER_CTRL, 1026c6b6a421SHawking Zhang RC_MEM_POWER_LS_EN, enable); 1027c6b6a421SHawking Zhang } else if (adev->cg_flags & AMD_CG_SUPPORT_HDP_DS) { 1028c6b6a421SHawking Zhang hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, 1029c6b6a421SHawking Zhang HDP_MEM_POWER_CTRL, 1030c6b6a421SHawking Zhang IPH_MEM_POWER_DS_EN, enable); 1031c6b6a421SHawking Zhang hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, 1032c6b6a421SHawking Zhang HDP_MEM_POWER_CTRL, 1033c6b6a421SHawking Zhang RC_MEM_POWER_DS_EN, enable); 1034c6b6a421SHawking Zhang } else if (adev->cg_flags & AMD_CG_SUPPORT_HDP_SD) { 1035c6b6a421SHawking Zhang hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, 1036c6b6a421SHawking Zhang HDP_MEM_POWER_CTRL, 1037c6b6a421SHawking Zhang IPH_MEM_POWER_SD_EN, enable); 1038c6b6a421SHawking Zhang /* RC should not use shut down mode, fallback to ds */ 1039c6b6a421SHawking Zhang hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, 1040c6b6a421SHawking Zhang HDP_MEM_POWER_CTRL, 1041c6b6a421SHawking Zhang RC_MEM_POWER_DS_EN, enable); 1042c6b6a421SHawking Zhang } 1043c6b6a421SHawking Zhang 104491c6adf8SKenneth Feng /* confirmed that IPH_MEM_POWER_CTRL_EN and RC_MEM_POWER_CTRL_EN have to 104591c6adf8SKenneth Feng * be set for SRAM LS/DS/SD */ 104691c6adf8SKenneth Feng if (adev->cg_flags & (AMD_CG_SUPPORT_HDP_LS | AMD_CG_SUPPORT_HDP_DS | 104791c6adf8SKenneth Feng AMD_CG_SUPPORT_HDP_SD)) { 104891c6adf8SKenneth Feng hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, 104991c6adf8SKenneth Feng IPH_MEM_POWER_CTRL_EN, 1); 105091c6adf8SKenneth Feng hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, 105191c6adf8SKenneth Feng RC_MEM_POWER_CTRL_EN, 1); 105291c6adf8SKenneth Feng } 105391c6adf8SKenneth Feng 1054c6b6a421SHawking Zhang WREG32_SOC15(HDP, 0, mmHDP_MEM_POWER_CTRL, hdp_mem_pwr_cntl); 1055c6b6a421SHawking Zhang 1056c6b6a421SHawking Zhang /* restore IPH & RC clock override after clock/power mode changing */ 1057c6b6a421SHawking Zhang WREG32_SOC15(HDP, 0, mmHDP_CLK_CNTL, hdp_clk_cntl1); 1058c6b6a421SHawking Zhang } 1059c6b6a421SHawking Zhang 1060c6b6a421SHawking Zhang static void nv_update_hdp_clock_gating(struct amdgpu_device *adev, 1061c6b6a421SHawking Zhang bool enable) 1062c6b6a421SHawking Zhang { 1063c6b6a421SHawking Zhang uint32_t hdp_clk_cntl; 1064c6b6a421SHawking Zhang 1065c6b6a421SHawking Zhang if (!(adev->cg_flags & AMD_CG_SUPPORT_HDP_MGCG)) 1066c6b6a421SHawking Zhang return; 1067c6b6a421SHawking Zhang 1068c6b6a421SHawking Zhang hdp_clk_cntl = RREG32_SOC15(HDP, 0, mmHDP_CLK_CNTL); 1069c6b6a421SHawking Zhang 1070c6b6a421SHawking Zhang if (enable) { 1071c6b6a421SHawking Zhang hdp_clk_cntl &= 1072c6b6a421SHawking Zhang ~(uint32_t) 1073c6b6a421SHawking Zhang (HDP_CLK_CNTL__IPH_MEM_CLK_SOFT_OVERRIDE_MASK | 1074c6b6a421SHawking Zhang HDP_CLK_CNTL__RC_MEM_CLK_SOFT_OVERRIDE_MASK | 1075c6b6a421SHawking Zhang HDP_CLK_CNTL__DBUS_CLK_SOFT_OVERRIDE_MASK | 1076c6b6a421SHawking Zhang HDP_CLK_CNTL__DYN_CLK_SOFT_OVERRIDE_MASK | 1077c6b6a421SHawking Zhang HDP_CLK_CNTL__XDP_REG_CLK_SOFT_OVERRIDE_MASK | 1078c6b6a421SHawking Zhang HDP_CLK_CNTL__HDP_REG_CLK_SOFT_OVERRIDE_MASK); 1079c6b6a421SHawking Zhang } else { 1080c6b6a421SHawking Zhang hdp_clk_cntl |= HDP_CLK_CNTL__IPH_MEM_CLK_SOFT_OVERRIDE_MASK | 1081c6b6a421SHawking Zhang HDP_CLK_CNTL__RC_MEM_CLK_SOFT_OVERRIDE_MASK | 1082c6b6a421SHawking Zhang HDP_CLK_CNTL__DBUS_CLK_SOFT_OVERRIDE_MASK | 1083c6b6a421SHawking Zhang HDP_CLK_CNTL__DYN_CLK_SOFT_OVERRIDE_MASK | 1084c6b6a421SHawking Zhang HDP_CLK_CNTL__XDP_REG_CLK_SOFT_OVERRIDE_MASK | 1085c6b6a421SHawking Zhang HDP_CLK_CNTL__HDP_REG_CLK_SOFT_OVERRIDE_MASK; 1086c6b6a421SHawking Zhang } 1087c6b6a421SHawking Zhang 1088c6b6a421SHawking Zhang WREG32_SOC15(HDP, 0, mmHDP_CLK_CNTL, hdp_clk_cntl); 1089c6b6a421SHawking Zhang } 1090c6b6a421SHawking Zhang 1091c6b6a421SHawking Zhang static int nv_common_set_clockgating_state(void *handle, 1092c6b6a421SHawking Zhang enum amd_clockgating_state state) 1093c6b6a421SHawking Zhang { 1094c6b6a421SHawking Zhang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1095c6b6a421SHawking Zhang 1096c6b6a421SHawking Zhang if (amdgpu_sriov_vf(adev)) 1097c6b6a421SHawking Zhang return 0; 1098c6b6a421SHawking Zhang 1099c6b6a421SHawking Zhang switch (adev->asic_type) { 1100c6b6a421SHawking Zhang case CHIP_NAVI10: 11015e71e011SXiaojie Yuan case CHIP_NAVI14: 11027e17e58bSXiaojie Yuan case CHIP_NAVI12: 1103117910edSLikun Gao case CHIP_SIENNA_CICHLID: 1104543aa259SJiansong Chen case CHIP_NAVY_FLOUNDER: 1105bebc0762SHawking Zhang adev->nbio.funcs->update_medium_grain_clock_gating(adev, 1106a9d4fe2fSNirmoy Das state == AMD_CG_STATE_GATE); 1107bebc0762SHawking Zhang adev->nbio.funcs->update_medium_grain_light_sleep(adev, 1108a9d4fe2fSNirmoy Das state == AMD_CG_STATE_GATE); 1109c6b6a421SHawking Zhang nv_update_hdp_mem_power_gating(adev, 1110a9d4fe2fSNirmoy Das state == AMD_CG_STATE_GATE); 1111c6b6a421SHawking Zhang nv_update_hdp_clock_gating(adev, 1112a9d4fe2fSNirmoy Das state == AMD_CG_STATE_GATE); 1113c6b6a421SHawking Zhang break; 1114c6b6a421SHawking Zhang default: 1115c6b6a421SHawking Zhang break; 1116c6b6a421SHawking Zhang } 1117c6b6a421SHawking Zhang return 0; 1118c6b6a421SHawking Zhang } 1119c6b6a421SHawking Zhang 1120c6b6a421SHawking Zhang static int nv_common_set_powergating_state(void *handle, 1121c6b6a421SHawking Zhang enum amd_powergating_state state) 1122c6b6a421SHawking Zhang { 1123c6b6a421SHawking Zhang /* TODO */ 1124c6b6a421SHawking Zhang return 0; 1125c6b6a421SHawking Zhang } 1126c6b6a421SHawking Zhang 1127c6b6a421SHawking Zhang static void nv_common_get_clockgating_state(void *handle, u32 *flags) 1128c6b6a421SHawking Zhang { 1129c6b6a421SHawking Zhang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1130c6b6a421SHawking Zhang uint32_t tmp; 1131c6b6a421SHawking Zhang 1132c6b6a421SHawking Zhang if (amdgpu_sriov_vf(adev)) 1133c6b6a421SHawking Zhang *flags = 0; 1134c6b6a421SHawking Zhang 1135bebc0762SHawking Zhang adev->nbio.funcs->get_clockgating_state(adev, flags); 1136c6b6a421SHawking Zhang 1137c6b6a421SHawking Zhang /* AMD_CG_SUPPORT_HDP_MGCG */ 1138c6b6a421SHawking Zhang tmp = RREG32_SOC15(HDP, 0, mmHDP_CLK_CNTL); 1139c6b6a421SHawking Zhang if (!(tmp & (HDP_CLK_CNTL__IPH_MEM_CLK_SOFT_OVERRIDE_MASK | 1140c6b6a421SHawking Zhang HDP_CLK_CNTL__RC_MEM_CLK_SOFT_OVERRIDE_MASK | 1141c6b6a421SHawking Zhang HDP_CLK_CNTL__DBUS_CLK_SOFT_OVERRIDE_MASK | 1142c6b6a421SHawking Zhang HDP_CLK_CNTL__DYN_CLK_SOFT_OVERRIDE_MASK | 1143c6b6a421SHawking Zhang HDP_CLK_CNTL__XDP_REG_CLK_SOFT_OVERRIDE_MASK | 1144c6b6a421SHawking Zhang HDP_CLK_CNTL__HDP_REG_CLK_SOFT_OVERRIDE_MASK))) 1145c6b6a421SHawking Zhang *flags |= AMD_CG_SUPPORT_HDP_MGCG; 1146c6b6a421SHawking Zhang 1147c6b6a421SHawking Zhang /* AMD_CG_SUPPORT_HDP_LS/DS/SD */ 1148c6b6a421SHawking Zhang tmp = RREG32_SOC15(HDP, 0, mmHDP_MEM_POWER_CTRL); 1149c6b6a421SHawking Zhang if (tmp & HDP_MEM_POWER_CTRL__IPH_MEM_POWER_LS_EN_MASK) 1150c6b6a421SHawking Zhang *flags |= AMD_CG_SUPPORT_HDP_LS; 1151c6b6a421SHawking Zhang else if (tmp & HDP_MEM_POWER_CTRL__IPH_MEM_POWER_DS_EN_MASK) 1152c6b6a421SHawking Zhang *flags |= AMD_CG_SUPPORT_HDP_DS; 1153c6b6a421SHawking Zhang else if (tmp & HDP_MEM_POWER_CTRL__IPH_MEM_POWER_SD_EN_MASK) 1154c6b6a421SHawking Zhang *flags |= AMD_CG_SUPPORT_HDP_SD; 1155c6b6a421SHawking Zhang 1156c6b6a421SHawking Zhang return; 1157c6b6a421SHawking Zhang } 1158c6b6a421SHawking Zhang 1159c6b6a421SHawking Zhang static const struct amd_ip_funcs nv_common_ip_funcs = { 1160c6b6a421SHawking Zhang .name = "nv_common", 1161c6b6a421SHawking Zhang .early_init = nv_common_early_init, 1162c6b6a421SHawking Zhang .late_init = nv_common_late_init, 1163c6b6a421SHawking Zhang .sw_init = nv_common_sw_init, 1164c6b6a421SHawking Zhang .sw_fini = nv_common_sw_fini, 1165c6b6a421SHawking Zhang .hw_init = nv_common_hw_init, 1166c6b6a421SHawking Zhang .hw_fini = nv_common_hw_fini, 1167c6b6a421SHawking Zhang .suspend = nv_common_suspend, 1168c6b6a421SHawking Zhang .resume = nv_common_resume, 1169c6b6a421SHawking Zhang .is_idle = nv_common_is_idle, 1170c6b6a421SHawking Zhang .wait_for_idle = nv_common_wait_for_idle, 1171c6b6a421SHawking Zhang .soft_reset = nv_common_soft_reset, 1172c6b6a421SHawking Zhang .set_clockgating_state = nv_common_set_clockgating_state, 1173c6b6a421SHawking Zhang .set_powergating_state = nv_common_set_powergating_state, 1174c6b6a421SHawking Zhang .get_clockgating_state = nv_common_get_clockgating_state, 1175c6b6a421SHawking Zhang }; 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