1c6b6a421SHawking Zhang /* 2c6b6a421SHawking Zhang * Copyright 2019 Advanced Micro Devices, Inc. 3c6b6a421SHawking Zhang * 4c6b6a421SHawking Zhang * Permission is hereby granted, free of charge, to any person obtaining a 5c6b6a421SHawking Zhang * copy of this software and associated documentation files (the "Software"), 6c6b6a421SHawking Zhang * to deal in the Software without restriction, including without limitation 7c6b6a421SHawking Zhang * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8c6b6a421SHawking Zhang * and/or sell copies of the Software, and to permit persons to whom the 9c6b6a421SHawking Zhang * Software is furnished to do so, subject to the following conditions: 10c6b6a421SHawking Zhang * 11c6b6a421SHawking Zhang * The above copyright notice and this permission notice shall be included in 12c6b6a421SHawking Zhang * all copies or substantial portions of the Software. 13c6b6a421SHawking Zhang * 14c6b6a421SHawking Zhang * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15c6b6a421SHawking Zhang * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16c6b6a421SHawking Zhang * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17c6b6a421SHawking Zhang * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18c6b6a421SHawking Zhang * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19c6b6a421SHawking Zhang * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20c6b6a421SHawking Zhang * OTHER DEALINGS IN THE SOFTWARE. 21c6b6a421SHawking Zhang * 22c6b6a421SHawking Zhang */ 23c6b6a421SHawking Zhang #include <linux/firmware.h> 24c6b6a421SHawking Zhang #include <linux/slab.h> 25c6b6a421SHawking Zhang #include <linux/module.h> 26e9eea902SAlex Deucher #include <linux/pci.h> 27e9eea902SAlex Deucher 286f786950SAlex Deucher #include <drm/amdgpu_drm.h> 296f786950SAlex Deucher 30c6b6a421SHawking Zhang #include "amdgpu.h" 31c6b6a421SHawking Zhang #include "amdgpu_atombios.h" 32c6b6a421SHawking Zhang #include "amdgpu_ih.h" 33c6b6a421SHawking Zhang #include "amdgpu_uvd.h" 34c6b6a421SHawking Zhang #include "amdgpu_vce.h" 35c6b6a421SHawking Zhang #include "amdgpu_ucode.h" 36c6b6a421SHawking Zhang #include "amdgpu_psp.h" 37c6b6a421SHawking Zhang #include "atom.h" 38c6b6a421SHawking Zhang #include "amd_pcie.h" 39c6b6a421SHawking Zhang 40c6b6a421SHawking Zhang #include "gc/gc_10_1_0_offset.h" 41c6b6a421SHawking Zhang #include "gc/gc_10_1_0_sh_mask.h" 423967ae6dSAlex Deucher #include "mp/mp_11_0_offset.h" 43c6b6a421SHawking Zhang 44c6b6a421SHawking Zhang #include "soc15.h" 45c6b6a421SHawking Zhang #include "soc15_common.h" 46c6b6a421SHawking Zhang #include "gmc_v10_0.h" 47c6b6a421SHawking Zhang #include "gfxhub_v2_0.h" 48c6b6a421SHawking Zhang #include "mmhub_v2_0.h" 49bebc0762SHawking Zhang #include "nbio_v2_3.h" 50a7e91bd7SHuang Rui #include "nbio_v7_2.h" 51bf087285SLikun Gao #include "hdp_v5_0.h" 52c6b6a421SHawking Zhang #include "nv.h" 53c6b6a421SHawking Zhang #include "navi10_ih.h" 54c6b6a421SHawking Zhang #include "gfx_v10_0.h" 55c6b6a421SHawking Zhang #include "sdma_v5_0.h" 56157e72e8SLikun Gao #include "sdma_v5_2.h" 57c6b6a421SHawking Zhang #include "vcn_v2_0.h" 585be45a26SLeo Liu #include "jpeg_v2_0.h" 59b8f10585SLeo Liu #include "vcn_v3_0.h" 604d72dd12SLeo Liu #include "jpeg_v3_0.h" 61733ee71aSRyan Taylor #include "amdgpu_vkms.h" 62c6b6a421SHawking Zhang #include "mes_v10_1.h" 63b05b6903SJiange Zhao #include "mxgpu_nv.h" 640bf7f2dcSLikun Gao #include "smuio_v11_0.h" 650bf7f2dcSLikun Gao #include "smuio_v11_0_6.h" 66c6b6a421SHawking Zhang 67c6b6a421SHawking Zhang static const struct amd_ip_funcs nv_common_ip_funcs; 68c6b6a421SHawking Zhang 693b246e8bSAlex Deucher /* Navi */ 703b246e8bSAlex Deucher static const struct amdgpu_video_codec_info nv_video_codecs_encode_array[] = 713b246e8bSAlex Deucher { 729075096bSVeerabadhran Gopalakrishnan {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 2304, 0)}, 739075096bSVeerabadhran Gopalakrishnan {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 4096, 2304, 0)}, 743b246e8bSAlex Deucher }; 753b246e8bSAlex Deucher 763b246e8bSAlex Deucher static const struct amdgpu_video_codecs nv_video_codecs_encode = 773b246e8bSAlex Deucher { 783b246e8bSAlex Deucher .codec_count = ARRAY_SIZE(nv_video_codecs_encode_array), 793b246e8bSAlex Deucher .codec_array = nv_video_codecs_encode_array, 803b246e8bSAlex Deucher }; 813b246e8bSAlex Deucher 823b246e8bSAlex Deucher /* Navi1x */ 833b246e8bSAlex Deucher static const struct amdgpu_video_codec_info nv_video_codecs_decode_array[] = 843b246e8bSAlex Deucher { 859075096bSVeerabadhran Gopalakrishnan {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 4096, 4906, 3)}, 869075096bSVeerabadhran Gopalakrishnan {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 4096, 4906, 5)}, 879075096bSVeerabadhran Gopalakrishnan {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4906, 52)}, 889075096bSVeerabadhran Gopalakrishnan {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 4096, 4906, 4)}, 899075096bSVeerabadhran Gopalakrishnan {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)}, 909075096bSVeerabadhran Gopalakrishnan {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)}, 919075096bSVeerabadhran Gopalakrishnan {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)}, 923b246e8bSAlex Deucher }; 933b246e8bSAlex Deucher 943b246e8bSAlex Deucher static const struct amdgpu_video_codecs nv_video_codecs_decode = 953b246e8bSAlex Deucher { 963b246e8bSAlex Deucher .codec_count = ARRAY_SIZE(nv_video_codecs_decode_array), 973b246e8bSAlex Deucher .codec_array = nv_video_codecs_decode_array, 983b246e8bSAlex Deucher }; 993b246e8bSAlex Deucher 1003b246e8bSAlex Deucher /* Sienna Cichlid */ 1013b246e8bSAlex Deucher static const struct amdgpu_video_codec_info sc_video_codecs_decode_array[] = 1023b246e8bSAlex Deucher { 1039075096bSVeerabadhran Gopalakrishnan {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 4096, 4906, 3)}, 1049075096bSVeerabadhran Gopalakrishnan {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 4096, 4906, 5)}, 1059075096bSVeerabadhran Gopalakrishnan {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4906, 52)}, 1069075096bSVeerabadhran Gopalakrishnan {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 4096, 4906, 4)}, 1079075096bSVeerabadhran Gopalakrishnan {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)}, 1089075096bSVeerabadhran Gopalakrishnan {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)}, 1099075096bSVeerabadhran Gopalakrishnan {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)}, 1109075096bSVeerabadhran Gopalakrishnan {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, 8192, 4352, 0)}, 1113b246e8bSAlex Deucher }; 1123b246e8bSAlex Deucher 1133b246e8bSAlex Deucher static const struct amdgpu_video_codecs sc_video_codecs_decode = 1143b246e8bSAlex Deucher { 1153b246e8bSAlex Deucher .codec_count = ARRAY_SIZE(sc_video_codecs_decode_array), 1163b246e8bSAlex Deucher .codec_array = sc_video_codecs_decode_array, 1173b246e8bSAlex Deucher }; 1183b246e8bSAlex Deucher 119ed9d2053SBokun Zhang /* SRIOV Sienna Cichlid, not const since data is controlled by host */ 120ed9d2053SBokun Zhang static struct amdgpu_video_codec_info sriov_sc_video_codecs_encode_array[] = 121ed9d2053SBokun Zhang { 1229075096bSVeerabadhran Gopalakrishnan {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 2304, 0)}, 1239075096bSVeerabadhran Gopalakrishnan {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 4096, 2304, 0)}, 124ed9d2053SBokun Zhang }; 125ed9d2053SBokun Zhang 126ed9d2053SBokun Zhang static struct amdgpu_video_codec_info sriov_sc_video_codecs_decode_array[] = 127ed9d2053SBokun Zhang { 1289075096bSVeerabadhran Gopalakrishnan {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 4096, 4906, 3)}, 1299075096bSVeerabadhran Gopalakrishnan {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 4096, 4906, 5)}, 1309075096bSVeerabadhran Gopalakrishnan {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4906, 52)}, 1319075096bSVeerabadhran Gopalakrishnan {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 4096, 4906, 4)}, 1329075096bSVeerabadhran Gopalakrishnan {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)}, 1339075096bSVeerabadhran Gopalakrishnan {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)}, 1349075096bSVeerabadhran Gopalakrishnan {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)}, 1359075096bSVeerabadhran Gopalakrishnan {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, 8192, 4352, 0)}, 136ed9d2053SBokun Zhang }; 137ed9d2053SBokun Zhang 138ed9d2053SBokun Zhang static struct amdgpu_video_codecs sriov_sc_video_codecs_encode = 139ed9d2053SBokun Zhang { 140ed9d2053SBokun Zhang .codec_count = ARRAY_SIZE(sriov_sc_video_codecs_encode_array), 141ed9d2053SBokun Zhang .codec_array = sriov_sc_video_codecs_encode_array, 142ed9d2053SBokun Zhang }; 143ed9d2053SBokun Zhang 144ed9d2053SBokun Zhang static struct amdgpu_video_codecs sriov_sc_video_codecs_decode = 145ed9d2053SBokun Zhang { 146ed9d2053SBokun Zhang .codec_count = ARRAY_SIZE(sriov_sc_video_codecs_decode_array), 147ed9d2053SBokun Zhang .codec_array = sriov_sc_video_codecs_decode_array, 148ed9d2053SBokun Zhang }; 149ed9d2053SBokun Zhang 150b3a24461SVeerabadhran Gopalakrishnan /* Beige Goby*/ 151b3a24461SVeerabadhran Gopalakrishnan static const struct amdgpu_video_codec_info bg_video_codecs_decode_array[] = { 152b3a24461SVeerabadhran Gopalakrishnan {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4906, 52)}, 153b3a24461SVeerabadhran Gopalakrishnan {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)}, 154b3a24461SVeerabadhran Gopalakrishnan {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)}, 155b3a24461SVeerabadhran Gopalakrishnan }; 156b3a24461SVeerabadhran Gopalakrishnan 157b3a24461SVeerabadhran Gopalakrishnan static const struct amdgpu_video_codecs bg_video_codecs_decode = { 158b3a24461SVeerabadhran Gopalakrishnan .codec_count = ARRAY_SIZE(bg_video_codecs_decode_array), 159b3a24461SVeerabadhran Gopalakrishnan .codec_array = bg_video_codecs_decode_array, 160b3a24461SVeerabadhran Gopalakrishnan }; 161b3a24461SVeerabadhran Gopalakrishnan 162b3a24461SVeerabadhran Gopalakrishnan static const struct amdgpu_video_codecs bg_video_codecs_encode = { 163b3a24461SVeerabadhran Gopalakrishnan .codec_count = 0, 164b3a24461SVeerabadhran Gopalakrishnan .codec_array = NULL, 165b3a24461SVeerabadhran Gopalakrishnan }; 166b3a24461SVeerabadhran Gopalakrishnan 16755439817SVeerabadhran Gopalakrishnan /* Yellow Carp*/ 16855439817SVeerabadhran Gopalakrishnan static const struct amdgpu_video_codec_info yc_video_codecs_decode_array[] = { 16955439817SVeerabadhran Gopalakrishnan {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4906, 52)}, 17055439817SVeerabadhran Gopalakrishnan {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)}, 17155439817SVeerabadhran Gopalakrishnan {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)}, 17255439817SVeerabadhran Gopalakrishnan {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)}, 17355439817SVeerabadhran Gopalakrishnan }; 17455439817SVeerabadhran Gopalakrishnan 17555439817SVeerabadhran Gopalakrishnan static const struct amdgpu_video_codecs yc_video_codecs_decode = { 176f72ac409SVeerabadhran Gopalakrishnan .codec_count = ARRAY_SIZE(yc_video_codecs_decode_array), 177f72ac409SVeerabadhran Gopalakrishnan .codec_array = yc_video_codecs_decode_array, 17855439817SVeerabadhran Gopalakrishnan }; 17955439817SVeerabadhran Gopalakrishnan 1803b246e8bSAlex Deucher static int nv_query_video_codecs(struct amdgpu_device *adev, bool encode, 1813b246e8bSAlex Deucher const struct amdgpu_video_codecs **codecs) 1823b246e8bSAlex Deucher { 1831d789535SAlex Deucher switch (adev->ip_versions[UVD_HWIP][0]) { 1843e67f4f2SAlex Deucher case IP_VERSION(3, 0, 0): 185*4d395f93SGuchun Chen case IP_VERSION(3, 0, 64): 186ed9d2053SBokun Zhang if (amdgpu_sriov_vf(adev)) { 187ed9d2053SBokun Zhang if (encode) 188ed9d2053SBokun Zhang *codecs = &sriov_sc_video_codecs_encode; 189ed9d2053SBokun Zhang else 190ed9d2053SBokun Zhang *codecs = &sriov_sc_video_codecs_decode; 191ed9d2053SBokun Zhang } else { 192ed9d2053SBokun Zhang if (encode) 193ed9d2053SBokun Zhang *codecs = &nv_video_codecs_encode; 194ed9d2053SBokun Zhang else 195ed9d2053SBokun Zhang *codecs = &sc_video_codecs_decode; 196ed9d2053SBokun Zhang } 197ed9d2053SBokun Zhang return 0; 1983e67f4f2SAlex Deucher case IP_VERSION(3, 0, 16): 1993e67f4f2SAlex Deucher case IP_VERSION(3, 0, 2): 2003b246e8bSAlex Deucher if (encode) 2013b246e8bSAlex Deucher *codecs = &nv_video_codecs_encode; 2023b246e8bSAlex Deucher else 2033b246e8bSAlex Deucher *codecs = &sc_video_codecs_decode; 2043b246e8bSAlex Deucher return 0; 2053e67f4f2SAlex Deucher case IP_VERSION(3, 1, 1): 20655439817SVeerabadhran Gopalakrishnan if (encode) 20755439817SVeerabadhran Gopalakrishnan *codecs = &nv_video_codecs_encode; 20855439817SVeerabadhran Gopalakrishnan else 20955439817SVeerabadhran Gopalakrishnan *codecs = &yc_video_codecs_decode; 21055439817SVeerabadhran Gopalakrishnan return 0; 2113e67f4f2SAlex Deucher case IP_VERSION(3, 0, 33): 212b3a24461SVeerabadhran Gopalakrishnan if (encode) 213b3a24461SVeerabadhran Gopalakrishnan *codecs = &bg_video_codecs_encode; 214b3a24461SVeerabadhran Gopalakrishnan else 215b3a24461SVeerabadhran Gopalakrishnan *codecs = &bg_video_codecs_decode; 216b3a24461SVeerabadhran Gopalakrishnan return 0; 2173e67f4f2SAlex Deucher case IP_VERSION(2, 0, 0): 2183e67f4f2SAlex Deucher case IP_VERSION(2, 0, 2): 2193b246e8bSAlex Deucher if (encode) 2203b246e8bSAlex Deucher *codecs = &nv_video_codecs_encode; 2213b246e8bSAlex Deucher else 2223b246e8bSAlex Deucher *codecs = &nv_video_codecs_decode; 2233b246e8bSAlex Deucher return 0; 2243b246e8bSAlex Deucher default: 2253b246e8bSAlex Deucher return -EINVAL; 2263b246e8bSAlex Deucher } 2273b246e8bSAlex Deucher } 2283b246e8bSAlex Deucher 229c6b6a421SHawking Zhang /* 230c6b6a421SHawking Zhang * Indirect registers accessor 231c6b6a421SHawking Zhang */ 232c6b6a421SHawking Zhang static u32 nv_pcie_rreg(struct amdgpu_device *adev, u32 reg) 233c6b6a421SHawking Zhang { 234705a2b5bSHawking Zhang unsigned long address, data; 235bebc0762SHawking Zhang address = adev->nbio.funcs->get_pcie_index_offset(adev); 236bebc0762SHawking Zhang data = adev->nbio.funcs->get_pcie_data_offset(adev); 237c6b6a421SHawking Zhang 238705a2b5bSHawking Zhang return amdgpu_device_indirect_rreg(adev, address, data, reg); 239c6b6a421SHawking Zhang } 240c6b6a421SHawking Zhang 241c6b6a421SHawking Zhang static void nv_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v) 242c6b6a421SHawking Zhang { 243705a2b5bSHawking Zhang unsigned long address, data; 244c6b6a421SHawking Zhang 245bebc0762SHawking Zhang address = adev->nbio.funcs->get_pcie_index_offset(adev); 246bebc0762SHawking Zhang data = adev->nbio.funcs->get_pcie_data_offset(adev); 247c6b6a421SHawking Zhang 248705a2b5bSHawking Zhang amdgpu_device_indirect_wreg(adev, address, data, reg, v); 249c6b6a421SHawking Zhang } 250c6b6a421SHawking Zhang 2514922f1bcSJohn Clements static u64 nv_pcie_rreg64(struct amdgpu_device *adev, u32 reg) 2524922f1bcSJohn Clements { 253705a2b5bSHawking Zhang unsigned long address, data; 2544922f1bcSJohn Clements address = adev->nbio.funcs->get_pcie_index_offset(adev); 2554922f1bcSJohn Clements data = adev->nbio.funcs->get_pcie_data_offset(adev); 2564922f1bcSJohn Clements 257705a2b5bSHawking Zhang return amdgpu_device_indirect_rreg64(adev, address, data, reg); 2584922f1bcSJohn Clements } 2594922f1bcSJohn Clements 2605de54343SHuang Rui static u32 nv_pcie_port_rreg(struct amdgpu_device *adev, u32 reg) 2615de54343SHuang Rui { 2625de54343SHuang Rui unsigned long flags, address, data; 2635de54343SHuang Rui u32 r; 2645de54343SHuang Rui address = adev->nbio.funcs->get_pcie_port_index_offset(adev); 2655de54343SHuang Rui data = adev->nbio.funcs->get_pcie_port_data_offset(adev); 2665de54343SHuang Rui 2675de54343SHuang Rui spin_lock_irqsave(&adev->pcie_idx_lock, flags); 2685de54343SHuang Rui WREG32(address, reg * 4); 2695de54343SHuang Rui (void)RREG32(address); 2705de54343SHuang Rui r = RREG32(data); 2715de54343SHuang Rui spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); 2725de54343SHuang Rui return r; 2735de54343SHuang Rui } 2745de54343SHuang Rui 2754922f1bcSJohn Clements static void nv_pcie_wreg64(struct amdgpu_device *adev, u32 reg, u64 v) 2764922f1bcSJohn Clements { 277705a2b5bSHawking Zhang unsigned long address, data; 2784922f1bcSJohn Clements 2794922f1bcSJohn Clements address = adev->nbio.funcs->get_pcie_index_offset(adev); 2804922f1bcSJohn Clements data = adev->nbio.funcs->get_pcie_data_offset(adev); 2814922f1bcSJohn Clements 282705a2b5bSHawking Zhang amdgpu_device_indirect_wreg64(adev, address, data, reg, v); 2834922f1bcSJohn Clements } 2844922f1bcSJohn Clements 2855de54343SHuang Rui static void nv_pcie_port_wreg(struct amdgpu_device *adev, u32 reg, u32 v) 2865de54343SHuang Rui { 2875de54343SHuang Rui unsigned long flags, address, data; 2885de54343SHuang Rui 2895de54343SHuang Rui address = adev->nbio.funcs->get_pcie_port_index_offset(adev); 2905de54343SHuang Rui data = adev->nbio.funcs->get_pcie_port_data_offset(adev); 2915de54343SHuang Rui 2925de54343SHuang Rui spin_lock_irqsave(&adev->pcie_idx_lock, flags); 2935de54343SHuang Rui WREG32(address, reg * 4); 2945de54343SHuang Rui (void)RREG32(address); 2955de54343SHuang Rui WREG32(data, v); 2965de54343SHuang Rui (void)RREG32(data); 2975de54343SHuang Rui spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); 2985de54343SHuang Rui } 2995de54343SHuang Rui 300c6b6a421SHawking Zhang static u32 nv_didt_rreg(struct amdgpu_device *adev, u32 reg) 301c6b6a421SHawking Zhang { 302c6b6a421SHawking Zhang unsigned long flags, address, data; 303c6b6a421SHawking Zhang u32 r; 304c6b6a421SHawking Zhang 305c6b6a421SHawking Zhang address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX); 306c6b6a421SHawking Zhang data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA); 307c6b6a421SHawking Zhang 308c6b6a421SHawking Zhang spin_lock_irqsave(&adev->didt_idx_lock, flags); 309c6b6a421SHawking Zhang WREG32(address, (reg)); 310c6b6a421SHawking Zhang r = RREG32(data); 311c6b6a421SHawking Zhang spin_unlock_irqrestore(&adev->didt_idx_lock, flags); 312c6b6a421SHawking Zhang return r; 313c6b6a421SHawking Zhang } 314c6b6a421SHawking Zhang 315c6b6a421SHawking Zhang static void nv_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v) 316c6b6a421SHawking Zhang { 317c6b6a421SHawking Zhang unsigned long flags, address, data; 318c6b6a421SHawking Zhang 319c6b6a421SHawking Zhang address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX); 320c6b6a421SHawking Zhang data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA); 321c6b6a421SHawking Zhang 322c6b6a421SHawking Zhang spin_lock_irqsave(&adev->didt_idx_lock, flags); 323c6b6a421SHawking Zhang WREG32(address, (reg)); 324c6b6a421SHawking Zhang WREG32(data, (v)); 325c6b6a421SHawking Zhang spin_unlock_irqrestore(&adev->didt_idx_lock, flags); 326c6b6a421SHawking Zhang } 327c6b6a421SHawking Zhang 328c6b6a421SHawking Zhang static u32 nv_get_config_memsize(struct amdgpu_device *adev) 329c6b6a421SHawking Zhang { 330bebc0762SHawking Zhang return adev->nbio.funcs->get_memsize(adev); 331c6b6a421SHawking Zhang } 332c6b6a421SHawking Zhang 333c6b6a421SHawking Zhang static u32 nv_get_xclk(struct amdgpu_device *adev) 334c6b6a421SHawking Zhang { 335462a70d8STao Zhou return adev->clock.spll.reference_freq; 336c6b6a421SHawking Zhang } 337c6b6a421SHawking Zhang 338c6b6a421SHawking Zhang 339c6b6a421SHawking Zhang void nv_grbm_select(struct amdgpu_device *adev, 340c6b6a421SHawking Zhang u32 me, u32 pipe, u32 queue, u32 vmid) 341c6b6a421SHawking Zhang { 342c6b6a421SHawking Zhang u32 grbm_gfx_cntl = 0; 343c6b6a421SHawking Zhang grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, PIPEID, pipe); 344c6b6a421SHawking Zhang grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, MEID, me); 345c6b6a421SHawking Zhang grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, VMID, vmid); 346c6b6a421SHawking Zhang grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, QUEUEID, queue); 347c6b6a421SHawking Zhang 348f2958a8bSPeng Ju Zhou WREG32_SOC15(GC, 0, mmGRBM_GFX_CNTL, grbm_gfx_cntl); 349c6b6a421SHawking Zhang } 350c6b6a421SHawking Zhang 351c6b6a421SHawking Zhang static void nv_vga_set_state(struct amdgpu_device *adev, bool state) 352c6b6a421SHawking Zhang { 353c6b6a421SHawking Zhang /* todo */ 354c6b6a421SHawking Zhang } 355c6b6a421SHawking Zhang 356c6b6a421SHawking Zhang static bool nv_read_disabled_bios(struct amdgpu_device *adev) 357c6b6a421SHawking Zhang { 358c6b6a421SHawking Zhang /* todo */ 359c6b6a421SHawking Zhang return false; 360c6b6a421SHawking Zhang } 361c6b6a421SHawking Zhang 362c6b6a421SHawking Zhang static bool nv_read_bios_from_rom(struct amdgpu_device *adev, 363c6b6a421SHawking Zhang u8 *bios, u32 length_bytes) 364c6b6a421SHawking Zhang { 36529bc37b4SAlex Deucher u32 *dw_ptr; 36629bc37b4SAlex Deucher u32 i, length_dw; 3670bf7f2dcSLikun Gao u32 rom_index_offset, rom_data_offset; 36829bc37b4SAlex Deucher 36929bc37b4SAlex Deucher if (bios == NULL) 370c6b6a421SHawking Zhang return false; 37129bc37b4SAlex Deucher if (length_bytes == 0) 37229bc37b4SAlex Deucher return false; 37329bc37b4SAlex Deucher /* APU vbios image is part of sbios image */ 37429bc37b4SAlex Deucher if (adev->flags & AMD_IS_APU) 37529bc37b4SAlex Deucher return false; 37629bc37b4SAlex Deucher 37729bc37b4SAlex Deucher dw_ptr = (u32 *)bios; 37829bc37b4SAlex Deucher length_dw = ALIGN(length_bytes, 4) / 4; 37929bc37b4SAlex Deucher 3800bf7f2dcSLikun Gao rom_index_offset = 3810bf7f2dcSLikun Gao adev->smuio.funcs->get_rom_index_offset(adev); 3820bf7f2dcSLikun Gao rom_data_offset = 3830bf7f2dcSLikun Gao adev->smuio.funcs->get_rom_data_offset(adev); 3840bf7f2dcSLikun Gao 38529bc37b4SAlex Deucher /* set rom index to 0 */ 3860bf7f2dcSLikun Gao WREG32(rom_index_offset, 0); 38729bc37b4SAlex Deucher /* read out the rom data */ 38829bc37b4SAlex Deucher for (i = 0; i < length_dw; i++) 3890bf7f2dcSLikun Gao dw_ptr[i] = RREG32(rom_data_offset); 39029bc37b4SAlex Deucher 39129bc37b4SAlex Deucher return true; 392c6b6a421SHawking Zhang } 393c6b6a421SHawking Zhang 394c6b6a421SHawking Zhang static struct soc15_allowed_register_entry nv_allowed_read_registers[] = { 395c6b6a421SHawking Zhang { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS)}, 396c6b6a421SHawking Zhang { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS2)}, 397c6b6a421SHawking Zhang { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE0)}, 398c6b6a421SHawking Zhang { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE1)}, 399c6b6a421SHawking Zhang { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE2)}, 400c6b6a421SHawking Zhang { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE3)}, 401c6b6a421SHawking Zhang { SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_STATUS_REG)}, 402c6b6a421SHawking Zhang { SOC15_REG_ENTRY(SDMA1, 0, mmSDMA1_STATUS_REG)}, 403c6b6a421SHawking Zhang { SOC15_REG_ENTRY(GC, 0, mmCP_STAT)}, 404c6b6a421SHawking Zhang { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT1)}, 405c6b6a421SHawking Zhang { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT2)}, 406c6b6a421SHawking Zhang { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT3)}, 407c6b6a421SHawking Zhang { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_BUSY_STAT)}, 408c6b6a421SHawking Zhang { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STALLED_STAT1)}, 409c6b6a421SHawking Zhang { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STATUS)}, 410664fe85aSMarek Olšák { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_BUSY_STAT)}, 411c6b6a421SHawking Zhang { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STALLED_STAT1)}, 412c6b6a421SHawking Zhang { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STATUS)}, 413c6b6a421SHawking Zhang { SOC15_REG_ENTRY(GC, 0, mmGB_ADDR_CONFIG)}, 414c6b6a421SHawking Zhang }; 415c6b6a421SHawking Zhang 416c6b6a421SHawking Zhang static uint32_t nv_read_indexed_register(struct amdgpu_device *adev, u32 se_num, 417c6b6a421SHawking Zhang u32 sh_num, u32 reg_offset) 418c6b6a421SHawking Zhang { 419c6b6a421SHawking Zhang uint32_t val; 420c6b6a421SHawking Zhang 421c6b6a421SHawking Zhang mutex_lock(&adev->grbm_idx_mutex); 422c6b6a421SHawking Zhang if (se_num != 0xffffffff || sh_num != 0xffffffff) 423c6b6a421SHawking Zhang amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff); 424c6b6a421SHawking Zhang 425c6b6a421SHawking Zhang val = RREG32(reg_offset); 426c6b6a421SHawking Zhang 427c6b6a421SHawking Zhang if (se_num != 0xffffffff || sh_num != 0xffffffff) 428c6b6a421SHawking Zhang amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 429c6b6a421SHawking Zhang mutex_unlock(&adev->grbm_idx_mutex); 430c6b6a421SHawking Zhang return val; 431c6b6a421SHawking Zhang } 432c6b6a421SHawking Zhang 433c6b6a421SHawking Zhang static uint32_t nv_get_register_value(struct amdgpu_device *adev, 434c6b6a421SHawking Zhang bool indexed, u32 se_num, 435c6b6a421SHawking Zhang u32 sh_num, u32 reg_offset) 436c6b6a421SHawking Zhang { 437c6b6a421SHawking Zhang if (indexed) { 438c6b6a421SHawking Zhang return nv_read_indexed_register(adev, se_num, sh_num, reg_offset); 439c6b6a421SHawking Zhang } else { 440c6b6a421SHawking Zhang if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG)) 441c6b6a421SHawking Zhang return adev->gfx.config.gb_addr_config; 442c6b6a421SHawking Zhang return RREG32(reg_offset); 443c6b6a421SHawking Zhang } 444c6b6a421SHawking Zhang } 445c6b6a421SHawking Zhang 446c6b6a421SHawking Zhang static int nv_read_register(struct amdgpu_device *adev, u32 se_num, 447c6b6a421SHawking Zhang u32 sh_num, u32 reg_offset, u32 *value) 448c6b6a421SHawking Zhang { 449c6b6a421SHawking Zhang uint32_t i; 450c6b6a421SHawking Zhang struct soc15_allowed_register_entry *en; 451c6b6a421SHawking Zhang 452c6b6a421SHawking Zhang *value = 0; 453c6b6a421SHawking Zhang for (i = 0; i < ARRAY_SIZE(nv_allowed_read_registers); i++) { 454c6b6a421SHawking Zhang en = &nv_allowed_read_registers[i]; 455fced3c3aSHuang Rui if ((i == 7 && (adev->sdma.num_instances == 1)) || /* some asics don't have SDMA1 */ 456fced3c3aSHuang Rui reg_offset != 457c6b6a421SHawking Zhang (adev->reg_offset[en->hwip][en->inst][en->seg] + en->reg_offset)) 458c6b6a421SHawking Zhang continue; 459c6b6a421SHawking Zhang 460c6b6a421SHawking Zhang *value = nv_get_register_value(adev, 461c6b6a421SHawking Zhang nv_allowed_read_registers[i].grbm_indexed, 462c6b6a421SHawking Zhang se_num, sh_num, reg_offset); 463c6b6a421SHawking Zhang return 0; 464c6b6a421SHawking Zhang } 465c6b6a421SHawking Zhang return -EINVAL; 466c6b6a421SHawking Zhang } 467c6b6a421SHawking Zhang 468b913ec62SAlex Deucher static int nv_asic_mode2_reset(struct amdgpu_device *adev) 469b913ec62SAlex Deucher { 470b913ec62SAlex Deucher u32 i; 471b913ec62SAlex Deucher int ret = 0; 472b913ec62SAlex Deucher 473b913ec62SAlex Deucher amdgpu_atombios_scratch_regs_engine_hung(adev, true); 474b913ec62SAlex Deucher 475b913ec62SAlex Deucher /* disable BM */ 476b913ec62SAlex Deucher pci_clear_master(adev->pdev); 477b913ec62SAlex Deucher 478b913ec62SAlex Deucher amdgpu_device_cache_pci_state(adev->pdev); 479b913ec62SAlex Deucher 480b913ec62SAlex Deucher ret = amdgpu_dpm_mode2_reset(adev); 481b913ec62SAlex Deucher if (ret) 482b913ec62SAlex Deucher dev_err(adev->dev, "GPU mode2 reset failed\n"); 483b913ec62SAlex Deucher 484b913ec62SAlex Deucher amdgpu_device_load_pci_state(adev->pdev); 485b913ec62SAlex Deucher 486b913ec62SAlex Deucher /* wait for asic to come out of reset */ 487b913ec62SAlex Deucher for (i = 0; i < adev->usec_timeout; i++) { 488b913ec62SAlex Deucher u32 memsize = adev->nbio.funcs->get_memsize(adev); 489b913ec62SAlex Deucher 490b913ec62SAlex Deucher if (memsize != 0xffffffff) 491b913ec62SAlex Deucher break; 492b913ec62SAlex Deucher udelay(1); 493b913ec62SAlex Deucher } 494b913ec62SAlex Deucher 495b913ec62SAlex Deucher amdgpu_atombios_scratch_regs_engine_hung(adev, false); 496b913ec62SAlex Deucher 497b913ec62SAlex Deucher return ret; 498b913ec62SAlex Deucher } 499b913ec62SAlex Deucher 5002ddc6c3eSAlex Deucher static enum amd_reset_method 5012ddc6c3eSAlex Deucher nv_asic_reset_method(struct amdgpu_device *adev) 5022ddc6c3eSAlex Deucher { 503273da6ffSWenhui Sheng if (amdgpu_reset_method == AMD_RESET_METHOD_MODE1 || 50416086355SAlex Deucher amdgpu_reset_method == AMD_RESET_METHOD_MODE2 || 505f172865aSAlex Deucher amdgpu_reset_method == AMD_RESET_METHOD_BACO || 506f172865aSAlex Deucher amdgpu_reset_method == AMD_RESET_METHOD_PCI) 507273da6ffSWenhui Sheng return amdgpu_reset_method; 508273da6ffSWenhui Sheng 509273da6ffSWenhui Sheng if (amdgpu_reset_method != -1) 510273da6ffSWenhui Sheng dev_warn(adev->dev, "Specified reset method:%d isn't supported, using AUTO instead.\n", 511273da6ffSWenhui Sheng amdgpu_reset_method); 512273da6ffSWenhui Sheng 5131d789535SAlex Deucher switch (adev->ip_versions[MP1_HWIP][0]) { 5143e67f4f2SAlex Deucher case IP_VERSION(11, 5, 0): 5153e67f4f2SAlex Deucher case IP_VERSION(13, 0, 1): 5163e67f4f2SAlex Deucher case IP_VERSION(13, 0, 3): 51716086355SAlex Deucher return AMD_RESET_METHOD_MODE2; 5183e67f4f2SAlex Deucher case IP_VERSION(11, 0, 7): 5193e67f4f2SAlex Deucher case IP_VERSION(11, 0, 11): 5203e67f4f2SAlex Deucher case IP_VERSION(11, 0, 12): 5213e67f4f2SAlex Deucher case IP_VERSION(11, 0, 13): 522ca6fd7a6SLikun Gao return AMD_RESET_METHOD_MODE1; 523ca6fd7a6SLikun Gao default: 524181e772fSEvan Quan if (amdgpu_dpm_is_baco_supported(adev)) 5252ddc6c3eSAlex Deucher return AMD_RESET_METHOD_BACO; 5262ddc6c3eSAlex Deucher else 5272ddc6c3eSAlex Deucher return AMD_RESET_METHOD_MODE1; 5282ddc6c3eSAlex Deucher } 529ca6fd7a6SLikun Gao } 5302ddc6c3eSAlex Deucher 531c6b6a421SHawking Zhang static int nv_asic_reset(struct amdgpu_device *adev) 532c6b6a421SHawking Zhang { 533767acabdSKevin Wang int ret = 0; 534c6b6a421SHawking Zhang 53516086355SAlex Deucher switch (nv_asic_reset_method(adev)) { 536f172865aSAlex Deucher case AMD_RESET_METHOD_PCI: 537f172865aSAlex Deucher dev_info(adev->dev, "PCI reset\n"); 538f172865aSAlex Deucher ret = amdgpu_device_pci_reset(adev); 539f172865aSAlex Deucher break; 54016086355SAlex Deucher case AMD_RESET_METHOD_BACO: 54111043b7aSAlex Deucher dev_info(adev->dev, "BACO reset\n"); 542181e772fSEvan Quan ret = amdgpu_dpm_baco_reset(adev); 54316086355SAlex Deucher break; 54416086355SAlex Deucher case AMD_RESET_METHOD_MODE2: 54516086355SAlex Deucher dev_info(adev->dev, "MODE2 reset\n"); 546b913ec62SAlex Deucher ret = nv_asic_mode2_reset(adev); 54716086355SAlex Deucher break; 54816086355SAlex Deucher default: 54911043b7aSAlex Deucher dev_info(adev->dev, "MODE1 reset\n"); 5505c03e584SFeifei Xu ret = amdgpu_device_mode1_reset(adev); 55116086355SAlex Deucher break; 55211043b7aSAlex Deucher } 553767acabdSKevin Wang 554767acabdSKevin Wang return ret; 555c6b6a421SHawking Zhang } 556c6b6a421SHawking Zhang 557c6b6a421SHawking Zhang static int nv_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk) 558c6b6a421SHawking Zhang { 559c6b6a421SHawking Zhang /* todo */ 560c6b6a421SHawking Zhang return 0; 561c6b6a421SHawking Zhang } 562c6b6a421SHawking Zhang 563c6b6a421SHawking Zhang static int nv_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk) 564c6b6a421SHawking Zhang { 565c6b6a421SHawking Zhang /* todo */ 566c6b6a421SHawking Zhang return 0; 567c6b6a421SHawking Zhang } 568c6b6a421SHawking Zhang 569c6b6a421SHawking Zhang static void nv_pcie_gen3_enable(struct amdgpu_device *adev) 570c6b6a421SHawking Zhang { 571c6b6a421SHawking Zhang if (pci_is_root_bus(adev->pdev->bus)) 572c6b6a421SHawking Zhang return; 573c6b6a421SHawking Zhang 574c6b6a421SHawking Zhang if (amdgpu_pcie_gen2 == 0) 575c6b6a421SHawking Zhang return; 576c6b6a421SHawking Zhang 577c6b6a421SHawking Zhang if (!(adev->pm.pcie_gen_mask & (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 | 578c6b6a421SHawking Zhang CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3))) 579c6b6a421SHawking Zhang return; 580c6b6a421SHawking Zhang 581c6b6a421SHawking Zhang /* todo */ 582c6b6a421SHawking Zhang } 583c6b6a421SHawking Zhang 584c6b6a421SHawking Zhang static void nv_program_aspm(struct amdgpu_device *adev) 585c6b6a421SHawking Zhang { 5860064b0ceSKenneth Feng if (!amdgpu_aspm) 587c6b6a421SHawking Zhang return; 588c6b6a421SHawking Zhang 5893273f8b9SKenneth Feng if (!(adev->flags & AMD_IS_APU) && 590e1edaeafSLikun Gao (adev->nbio.funcs->program_aspm)) 591e1edaeafSLikun Gao adev->nbio.funcs->program_aspm(adev); 592e1edaeafSLikun Gao 593c6b6a421SHawking Zhang } 594c6b6a421SHawking Zhang 595c6b6a421SHawking Zhang static void nv_enable_doorbell_aperture(struct amdgpu_device *adev, 596c6b6a421SHawking Zhang bool enable) 597c6b6a421SHawking Zhang { 598bebc0762SHawking Zhang adev->nbio.funcs->enable_doorbell_aperture(adev, enable); 599bebc0762SHawking Zhang adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, enable); 600c6b6a421SHawking Zhang } 601c6b6a421SHawking Zhang 602a1f62df7SAlex Deucher const struct amdgpu_ip_block_version nv_common_ip_block = 603c6b6a421SHawking Zhang { 604c6b6a421SHawking Zhang .type = AMD_IP_BLOCK_TYPE_COMMON, 605c6b6a421SHawking Zhang .major = 1, 606c6b6a421SHawking Zhang .minor = 0, 607c6b6a421SHawking Zhang .rev = 0, 608c6b6a421SHawking Zhang .funcs = &nv_common_ip_funcs, 609c6b6a421SHawking Zhang }; 610c6b6a421SHawking Zhang 611c1299461SWenhui Sheng void nv_set_virt_ops(struct amdgpu_device *adev) 612c1299461SWenhui Sheng { 613c1299461SWenhui Sheng adev->virt.ops = &xgpu_nv_virt_ops; 614c1299461SWenhui Sheng } 615c1299461SWenhui Sheng 616c6b6a421SHawking Zhang static uint32_t nv_get_rev_id(struct amdgpu_device *adev) 617c6b6a421SHawking Zhang { 618bebc0762SHawking Zhang return adev->nbio.funcs->get_rev_id(adev); 619c6b6a421SHawking Zhang } 620c6b6a421SHawking Zhang 621c6b6a421SHawking Zhang static bool nv_need_full_reset(struct amdgpu_device *adev) 622c6b6a421SHawking Zhang { 623c6b6a421SHawking Zhang return true; 624c6b6a421SHawking Zhang } 625c6b6a421SHawking Zhang 626c6b6a421SHawking Zhang static bool nv_need_reset_on_init(struct amdgpu_device *adev) 627c6b6a421SHawking Zhang { 628c6b6a421SHawking Zhang u32 sol_reg; 629c6b6a421SHawking Zhang 630c6b6a421SHawking Zhang if (adev->flags & AMD_IS_APU) 631c6b6a421SHawking Zhang return false; 632c6b6a421SHawking Zhang 633c6b6a421SHawking Zhang /* Check sOS sign of life register to confirm sys driver and sOS 634c6b6a421SHawking Zhang * are already been loaded. 635c6b6a421SHawking Zhang */ 636c6b6a421SHawking Zhang sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81); 637c6b6a421SHawking Zhang if (sol_reg) 638c6b6a421SHawking Zhang return true; 6393967ae6dSAlex Deucher 640c6b6a421SHawking Zhang return false; 641c6b6a421SHawking Zhang } 642c6b6a421SHawking Zhang 6432af81531SKevin Wang static uint64_t nv_get_pcie_replay_count(struct amdgpu_device *adev) 6442af81531SKevin Wang { 6452af81531SKevin Wang 6462af81531SKevin Wang /* TODO 6472af81531SKevin Wang * dummy implement for pcie_replay_count sysfs interface 6482af81531SKevin Wang * */ 6492af81531SKevin Wang 6502af81531SKevin Wang return 0; 6512af81531SKevin Wang } 6522af81531SKevin Wang 653c6b6a421SHawking Zhang static void nv_init_doorbell_index(struct amdgpu_device *adev) 654c6b6a421SHawking Zhang { 655c6b6a421SHawking Zhang adev->doorbell_index.kiq = AMDGPU_NAVI10_DOORBELL_KIQ; 656c6b6a421SHawking Zhang adev->doorbell_index.mec_ring0 = AMDGPU_NAVI10_DOORBELL_MEC_RING0; 657c6b6a421SHawking Zhang adev->doorbell_index.mec_ring1 = AMDGPU_NAVI10_DOORBELL_MEC_RING1; 658c6b6a421SHawking Zhang adev->doorbell_index.mec_ring2 = AMDGPU_NAVI10_DOORBELL_MEC_RING2; 659c6b6a421SHawking Zhang adev->doorbell_index.mec_ring3 = AMDGPU_NAVI10_DOORBELL_MEC_RING3; 660c6b6a421SHawking Zhang adev->doorbell_index.mec_ring4 = AMDGPU_NAVI10_DOORBELL_MEC_RING4; 661c6b6a421SHawking Zhang adev->doorbell_index.mec_ring5 = AMDGPU_NAVI10_DOORBELL_MEC_RING5; 662c6b6a421SHawking Zhang adev->doorbell_index.mec_ring6 = AMDGPU_NAVI10_DOORBELL_MEC_RING6; 663c6b6a421SHawking Zhang adev->doorbell_index.mec_ring7 = AMDGPU_NAVI10_DOORBELL_MEC_RING7; 664c6b6a421SHawking Zhang adev->doorbell_index.userqueue_start = AMDGPU_NAVI10_DOORBELL_USERQUEUE_START; 665c6b6a421SHawking Zhang adev->doorbell_index.userqueue_end = AMDGPU_NAVI10_DOORBELL_USERQUEUE_END; 666c6b6a421SHawking Zhang adev->doorbell_index.gfx_ring0 = AMDGPU_NAVI10_DOORBELL_GFX_RING0; 667c6b6a421SHawking Zhang adev->doorbell_index.gfx_ring1 = AMDGPU_NAVI10_DOORBELL_GFX_RING1; 66820519232SJack Xiao adev->doorbell_index.mes_ring = AMDGPU_NAVI10_DOORBELL_MES_RING; 669c6b6a421SHawking Zhang adev->doorbell_index.sdma_engine[0] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE0; 670c6b6a421SHawking Zhang adev->doorbell_index.sdma_engine[1] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE1; 671157e72e8SLikun Gao adev->doorbell_index.sdma_engine[2] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE2; 672157e72e8SLikun Gao adev->doorbell_index.sdma_engine[3] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE3; 673c6b6a421SHawking Zhang adev->doorbell_index.ih = AMDGPU_NAVI10_DOORBELL_IH; 674c6b6a421SHawking Zhang adev->doorbell_index.vcn.vcn_ring0_1 = AMDGPU_NAVI10_DOORBELL64_VCN0_1; 675c6b6a421SHawking Zhang adev->doorbell_index.vcn.vcn_ring2_3 = AMDGPU_NAVI10_DOORBELL64_VCN2_3; 676c6b6a421SHawking Zhang adev->doorbell_index.vcn.vcn_ring4_5 = AMDGPU_NAVI10_DOORBELL64_VCN4_5; 677c6b6a421SHawking Zhang adev->doorbell_index.vcn.vcn_ring6_7 = AMDGPU_NAVI10_DOORBELL64_VCN6_7; 678c6b6a421SHawking Zhang adev->doorbell_index.first_non_cp = AMDGPU_NAVI10_DOORBELL64_FIRST_NON_CP; 679c6b6a421SHawking Zhang adev->doorbell_index.last_non_cp = AMDGPU_NAVI10_DOORBELL64_LAST_NON_CP; 680c6b6a421SHawking Zhang 681c6b6a421SHawking Zhang adev->doorbell_index.max_assignment = AMDGPU_NAVI10_DOORBELL_MAX_ASSIGNMENT << 1; 682c6b6a421SHawking Zhang adev->doorbell_index.sdma_doorbell_range = 20; 683c6b6a421SHawking Zhang } 684c6b6a421SHawking Zhang 685a7173731SAlex Deucher static void nv_pre_asic_init(struct amdgpu_device *adev) 686a7173731SAlex Deucher { 687a7173731SAlex Deucher } 688a7173731SAlex Deucher 68927747293SEvan Quan static int nv_update_umd_stable_pstate(struct amdgpu_device *adev, 69027747293SEvan Quan bool enter) 69127747293SEvan Quan { 69227747293SEvan Quan if (enter) 69327747293SEvan Quan amdgpu_gfx_rlc_enter_safe_mode(adev); 69427747293SEvan Quan else 69527747293SEvan Quan amdgpu_gfx_rlc_exit_safe_mode(adev); 69627747293SEvan Quan 69727747293SEvan Quan if (adev->gfx.funcs->update_perfmon_mgcg) 69827747293SEvan Quan adev->gfx.funcs->update_perfmon_mgcg(adev, !enter); 69927747293SEvan Quan 7003273f8b9SKenneth Feng if (!(adev->flags & AMD_IS_APU) && 701e1edaeafSLikun Gao (adev->nbio.funcs->enable_aspm)) 70227747293SEvan Quan adev->nbio.funcs->enable_aspm(adev, !enter); 70327747293SEvan Quan 70427747293SEvan Quan return 0; 70527747293SEvan Quan } 70627747293SEvan Quan 707c6b6a421SHawking Zhang static const struct amdgpu_asic_funcs nv_asic_funcs = 708c6b6a421SHawking Zhang { 709c6b6a421SHawking Zhang .read_disabled_bios = &nv_read_disabled_bios, 710c6b6a421SHawking Zhang .read_bios_from_rom = &nv_read_bios_from_rom, 711c6b6a421SHawking Zhang .read_register = &nv_read_register, 712c6b6a421SHawking Zhang .reset = &nv_asic_reset, 7132ddc6c3eSAlex Deucher .reset_method = &nv_asic_reset_method, 714c6b6a421SHawking Zhang .set_vga_state = &nv_vga_set_state, 715c6b6a421SHawking Zhang .get_xclk = &nv_get_xclk, 716c6b6a421SHawking Zhang .set_uvd_clocks = &nv_set_uvd_clocks, 717c6b6a421SHawking Zhang .set_vce_clocks = &nv_set_vce_clocks, 718c6b6a421SHawking Zhang .get_config_memsize = &nv_get_config_memsize, 719c6b6a421SHawking Zhang .init_doorbell_index = &nv_init_doorbell_index, 720c6b6a421SHawking Zhang .need_full_reset = &nv_need_full_reset, 721c6b6a421SHawking Zhang .need_reset_on_init = &nv_need_reset_on_init, 7222af81531SKevin Wang .get_pcie_replay_count = &nv_get_pcie_replay_count, 723181e772fSEvan Quan .supports_baco = &amdgpu_dpm_is_baco_supported, 724a7173731SAlex Deucher .pre_asic_init = &nv_pre_asic_init, 72527747293SEvan Quan .update_umd_stable_pstate = &nv_update_umd_stable_pstate, 7263b246e8bSAlex Deucher .query_video_codecs = &nv_query_video_codecs, 727c6b6a421SHawking Zhang }; 728c6b6a421SHawking Zhang 729c6b6a421SHawking Zhang static int nv_common_early_init(void *handle) 730c6b6a421SHawking Zhang { 731923c087aSYong Zhao #define MMIO_REG_HOLE_OFFSET (0x80000 - PAGE_SIZE) 732c6b6a421SHawking Zhang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 733c6b6a421SHawking Zhang 734923c087aSYong Zhao adev->rmmio_remap.reg_offset = MMIO_REG_HOLE_OFFSET; 735923c087aSYong Zhao adev->rmmio_remap.bus_addr = adev->rmmio_base + MMIO_REG_HOLE_OFFSET; 736c6b6a421SHawking Zhang adev->smc_rreg = NULL; 737c6b6a421SHawking Zhang adev->smc_wreg = NULL; 738c6b6a421SHawking Zhang adev->pcie_rreg = &nv_pcie_rreg; 739c6b6a421SHawking Zhang adev->pcie_wreg = &nv_pcie_wreg; 7404922f1bcSJohn Clements adev->pcie_rreg64 = &nv_pcie_rreg64; 7414922f1bcSJohn Clements adev->pcie_wreg64 = &nv_pcie_wreg64; 7425de54343SHuang Rui adev->pciep_rreg = &nv_pcie_port_rreg; 7435de54343SHuang Rui adev->pciep_wreg = &nv_pcie_port_wreg; 744c6b6a421SHawking Zhang 745c6b6a421SHawking Zhang /* TODO: will add them during VCN v2 implementation */ 746c6b6a421SHawking Zhang adev->uvd_ctx_rreg = NULL; 747c6b6a421SHawking Zhang adev->uvd_ctx_wreg = NULL; 748c6b6a421SHawking Zhang 749c6b6a421SHawking Zhang adev->didt_rreg = &nv_didt_rreg; 750c6b6a421SHawking Zhang adev->didt_wreg = &nv_didt_wreg; 751c6b6a421SHawking Zhang 752c6b6a421SHawking Zhang adev->asic_funcs = &nv_asic_funcs; 753c6b6a421SHawking Zhang 754c6b6a421SHawking Zhang adev->rev_id = nv_get_rev_id(adev); 755c6b6a421SHawking Zhang adev->external_rev_id = 0xff; 7563e67f4f2SAlex Deucher /* TODO: split the GC and PG flags based on the relevant IP version for which 7573e67f4f2SAlex Deucher * they are relevant. 7583e67f4f2SAlex Deucher */ 7591d789535SAlex Deucher switch (adev->ip_versions[GC_HWIP][0]) { 7603e67f4f2SAlex Deucher case IP_VERSION(10, 1, 10): 761c6b6a421SHawking Zhang adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 762c6b6a421SHawking Zhang AMD_CG_SUPPORT_GFX_CGCG | 763c6b6a421SHawking Zhang AMD_CG_SUPPORT_IH_CG | 764c6b6a421SHawking Zhang AMD_CG_SUPPORT_HDP_MGCG | 765c6b6a421SHawking Zhang AMD_CG_SUPPORT_HDP_LS | 766c6b6a421SHawking Zhang AMD_CG_SUPPORT_SDMA_MGCG | 767c6b6a421SHawking Zhang AMD_CG_SUPPORT_SDMA_LS | 768c6b6a421SHawking Zhang AMD_CG_SUPPORT_MC_MGCG | 769c6b6a421SHawking Zhang AMD_CG_SUPPORT_MC_LS | 770c6b6a421SHawking Zhang AMD_CG_SUPPORT_ATHUB_MGCG | 771c6b6a421SHawking Zhang AMD_CG_SUPPORT_ATHUB_LS | 772c6b6a421SHawking Zhang AMD_CG_SUPPORT_VCN_MGCG | 773099d66e4SLeo Liu AMD_CG_SUPPORT_JPEG_MGCG | 774c6b6a421SHawking Zhang AMD_CG_SUPPORT_BIF_MGCG | 775c6b6a421SHawking Zhang AMD_CG_SUPPORT_BIF_LS; 776157710eaSLeo Liu adev->pg_flags = AMD_PG_SUPPORT_VCN | 777c12d410fSHuang Rui AMD_PG_SUPPORT_VCN_DPG | 778099d66e4SLeo Liu AMD_PG_SUPPORT_JPEG | 779a201b6acSHuang Rui AMD_PG_SUPPORT_ATHUB; 780c6b6a421SHawking Zhang adev->external_rev_id = adev->rev_id + 0x1; 781c6b6a421SHawking Zhang break; 7823e67f4f2SAlex Deucher case IP_VERSION(10, 1, 1): 783d0c39f8cSXiaojie Yuan adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 784d0c39f8cSXiaojie Yuan AMD_CG_SUPPORT_GFX_CGCG | 785d0c39f8cSXiaojie Yuan AMD_CG_SUPPORT_IH_CG | 786d0c39f8cSXiaojie Yuan AMD_CG_SUPPORT_HDP_MGCG | 787d0c39f8cSXiaojie Yuan AMD_CG_SUPPORT_HDP_LS | 788d0c39f8cSXiaojie Yuan AMD_CG_SUPPORT_SDMA_MGCG | 789d0c39f8cSXiaojie Yuan AMD_CG_SUPPORT_SDMA_LS | 790d0c39f8cSXiaojie Yuan AMD_CG_SUPPORT_MC_MGCG | 791d0c39f8cSXiaojie Yuan AMD_CG_SUPPORT_MC_LS | 792d0c39f8cSXiaojie Yuan AMD_CG_SUPPORT_ATHUB_MGCG | 793d0c39f8cSXiaojie Yuan AMD_CG_SUPPORT_ATHUB_LS | 794d0c39f8cSXiaojie Yuan AMD_CG_SUPPORT_VCN_MGCG | 795099d66e4SLeo Liu AMD_CG_SUPPORT_JPEG_MGCG | 796d0c39f8cSXiaojie Yuan AMD_CG_SUPPORT_BIF_MGCG | 797d0c39f8cSXiaojie Yuan AMD_CG_SUPPORT_BIF_LS; 7980377b088SXiaojie Yuan adev->pg_flags = AMD_PG_SUPPORT_VCN | 799099d66e4SLeo Liu AMD_PG_SUPPORT_JPEG | 8000377b088SXiaojie Yuan AMD_PG_SUPPORT_VCN_DPG; 80135ef88faStiancyin adev->external_rev_id = adev->rev_id + 20; 8025e71e011SXiaojie Yuan break; 8033e67f4f2SAlex Deucher case IP_VERSION(10, 1, 2): 804dca009e7SXiaojie Yuan adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 805dca009e7SXiaojie Yuan AMD_CG_SUPPORT_GFX_MGLS | 806dca009e7SXiaojie Yuan AMD_CG_SUPPORT_GFX_CGCG | 807dca009e7SXiaojie Yuan AMD_CG_SUPPORT_GFX_CP_LS | 8085211c37aSXiaojie Yuan AMD_CG_SUPPORT_GFX_RLC_LS | 809fbe0bc57SXiaojie Yuan AMD_CG_SUPPORT_IH_CG | 8105211c37aSXiaojie Yuan AMD_CG_SUPPORT_HDP_MGCG | 811358ab97fSXiaojie Yuan AMD_CG_SUPPORT_HDP_LS | 812358ab97fSXiaojie Yuan AMD_CG_SUPPORT_SDMA_MGCG | 8138b797b3dSXiaojie Yuan AMD_CG_SUPPORT_SDMA_LS | 8148b797b3dSXiaojie Yuan AMD_CG_SUPPORT_MC_MGCG | 815ca51678dSXiaojie Yuan AMD_CG_SUPPORT_MC_LS | 816ca51678dSXiaojie Yuan AMD_CG_SUPPORT_ATHUB_MGCG | 81765872e59SXiaojie Yuan AMD_CG_SUPPORT_ATHUB_LS | 818099d66e4SLeo Liu AMD_CG_SUPPORT_VCN_MGCG | 819099d66e4SLeo Liu AMD_CG_SUPPORT_JPEG_MGCG; 820c1653ea0SXiaojie Yuan adev->pg_flags = AMD_PG_SUPPORT_VCN | 8215ef3b8acSXiaojie Yuan AMD_PG_SUPPORT_VCN_DPG | 822099d66e4SLeo Liu AMD_PG_SUPPORT_JPEG | 8231b0443b1SLikun Gao AMD_PG_SUPPORT_ATHUB; 824df5e984cSTiecheng Zhou /* guest vm gets 0xffffffff when reading RCC_DEV0_EPF0_STRAP0, 825df5e984cSTiecheng Zhou * as a consequence, the rev_id and external_rev_id are wrong. 826df5e984cSTiecheng Zhou * workaround it by hardcoding rev_id to 0 (default value). 827df5e984cSTiecheng Zhou */ 828df5e984cSTiecheng Zhou if (amdgpu_sriov_vf(adev)) 829df5e984cSTiecheng Zhou adev->rev_id = 0; 83074b5e509SXiaojie Yuan adev->external_rev_id = adev->rev_id + 0xa; 83174b5e509SXiaojie Yuan break; 8323e67f4f2SAlex Deucher case IP_VERSION(10, 3, 0): 83300194defSLikun Gao adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 83400194defSLikun Gao AMD_CG_SUPPORT_GFX_CGCG | 8351d712be9SKenneth Feng AMD_CG_SUPPORT_GFX_CGLS | 83600194defSLikun Gao AMD_CG_SUPPORT_GFX_3D_CGCG | 83798f8ea29SLikun Gao AMD_CG_SUPPORT_MC_MGCG | 83800194defSLikun Gao AMD_CG_SUPPORT_VCN_MGCG | 839ca36461fSKenneth Feng AMD_CG_SUPPORT_JPEG_MGCG | 840ca36461fSKenneth Feng AMD_CG_SUPPORT_HDP_MGCG | 8413a32c25aSKenneth Feng AMD_CG_SUPPORT_HDP_LS | 842bcc8367fSKenneth Feng AMD_CG_SUPPORT_IH_CG | 843bcc8367fSKenneth Feng AMD_CG_SUPPORT_MC_LS; 844b467c4f5SLeo Liu adev->pg_flags = AMD_PG_SUPPORT_VCN | 845d00b0fa9SBoyuan Zhang AMD_PG_SUPPORT_VCN_DPG | 846b794616dSKenneth Feng AMD_PG_SUPPORT_JPEG | 8471b0443b1SLikun Gao AMD_PG_SUPPORT_ATHUB | 8481b0443b1SLikun Gao AMD_PG_SUPPORT_MMHUB; 849c45fbe1bSJack Zhang if (amdgpu_sriov_vf(adev)) { 850c45fbe1bSJack Zhang /* hypervisor control CG and PG enablement */ 851c45fbe1bSJack Zhang adev->cg_flags = 0; 852c45fbe1bSJack Zhang adev->pg_flags = 0; 853c45fbe1bSJack Zhang } 854117910edSLikun Gao adev->external_rev_id = adev->rev_id + 0x28; 855117910edSLikun Gao break; 8563e67f4f2SAlex Deucher case IP_VERSION(10, 3, 2): 85740582e67SJiansong Chen adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 85840582e67SJiansong Chen AMD_CG_SUPPORT_GFX_CGCG | 8591d712be9SKenneth Feng AMD_CG_SUPPORT_GFX_CGLS | 86040582e67SJiansong Chen AMD_CG_SUPPORT_GFX_3D_CGCG | 86140582e67SJiansong Chen AMD_CG_SUPPORT_VCN_MGCG | 86292c73756SJiansong Chen AMD_CG_SUPPORT_JPEG_MGCG | 86392c73756SJiansong Chen AMD_CG_SUPPORT_MC_MGCG | 8644759f887SJiansong Chen AMD_CG_SUPPORT_MC_LS | 8654759f887SJiansong Chen AMD_CG_SUPPORT_HDP_MGCG | 86685e7151bSJiansong Chen AMD_CG_SUPPORT_HDP_LS | 86785e7151bSJiansong Chen AMD_CG_SUPPORT_IH_CG; 868c6e9dd0eSBoyuan Zhang adev->pg_flags = AMD_PG_SUPPORT_VCN | 86900740df9SBoyuan Zhang AMD_PG_SUPPORT_VCN_DPG | 87047fc894aSJiansong Chen AMD_PG_SUPPORT_JPEG | 87147fc894aSJiansong Chen AMD_PG_SUPPORT_ATHUB | 87247fc894aSJiansong Chen AMD_PG_SUPPORT_MMHUB; 873543aa259SJiansong Chen adev->external_rev_id = adev->rev_id + 0x32; 874543aa259SJiansong Chen break; 8753e67f4f2SAlex Deucher case IP_VERSION(10, 3, 1): 87651a7e938SJinzhou.Su adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 87751a7e938SJinzhou.Su AMD_CG_SUPPORT_GFX_MGLS | 87851a7e938SJinzhou.Su AMD_CG_SUPPORT_GFX_CP_LS | 87951a7e938SJinzhou.Su AMD_CG_SUPPORT_GFX_RLC_LS | 88051a7e938SJinzhou.Su AMD_CG_SUPPORT_GFX_CGCG | 881ac0dc4c5SHuang Rui AMD_CG_SUPPORT_GFX_CGLS | 882ac0dc4c5SHuang Rui AMD_CG_SUPPORT_GFX_3D_CGCG | 88307f9c22fSBoyuan Zhang AMD_CG_SUPPORT_GFX_3D_CGLS | 8840ebce667SJinzhou.Su AMD_CG_SUPPORT_MC_MGCG | 8850ebce667SJinzhou.Su AMD_CG_SUPPORT_MC_LS | 886a3964ec4SJinzhou.Su AMD_CG_SUPPORT_GFX_FGCG | 88707f9c22fSBoyuan Zhang AMD_CG_SUPPORT_VCN_MGCG | 888ef9bcfdeSJinzhou Su AMD_CG_SUPPORT_SDMA_MGCG | 889ec0f72cbSJinzhou Su AMD_CG_SUPPORT_SDMA_LS | 89007f9c22fSBoyuan Zhang AMD_CG_SUPPORT_JPEG_MGCG; 89107f9c22fSBoyuan Zhang adev->pg_flags = AMD_PG_SUPPORT_GFX_PG | 89207f9c22fSBoyuan Zhang AMD_PG_SUPPORT_VCN | 89307f9c22fSBoyuan Zhang AMD_PG_SUPPORT_VCN_DPG | 89407f9c22fSBoyuan Zhang AMD_PG_SUPPORT_JPEG; 895c345c89bSHuang Rui if (adev->apu_flags & AMD_APU_IS_VANGOGH) 896026570e6SHuang Rui adev->external_rev_id = adev->rev_id + 0x01; 897026570e6SHuang Rui break; 8983e67f4f2SAlex Deucher case IP_VERSION(10, 3, 4): 899583e5a5eSTao Zhou adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 900583e5a5eSTao Zhou AMD_CG_SUPPORT_GFX_CGCG | 9011d712be9SKenneth Feng AMD_CG_SUPPORT_GFX_CGLS | 902583e5a5eSTao Zhou AMD_CG_SUPPORT_GFX_3D_CGCG | 903583e5a5eSTao Zhou AMD_CG_SUPPORT_VCN_MGCG | 904135333a0STao Zhou AMD_CG_SUPPORT_JPEG_MGCG | 905135333a0STao Zhou AMD_CG_SUPPORT_MC_MGCG | 9062c70c332STao Zhou AMD_CG_SUPPORT_MC_LS | 9072c70c332STao Zhou AMD_CG_SUPPORT_HDP_MGCG | 9088e3bfb99STao Zhou AMD_CG_SUPPORT_HDP_LS | 9098e3bfb99STao Zhou AMD_CG_SUPPORT_IH_CG; 910d5bc1579SJames Zhu adev->pg_flags = AMD_PG_SUPPORT_VCN | 911cc6161aaSJames Zhu AMD_PG_SUPPORT_VCN_DPG | 91273da8e86STao Zhou AMD_PG_SUPPORT_JPEG | 91373da8e86STao Zhou AMD_PG_SUPPORT_ATHUB | 91473da8e86STao Zhou AMD_PG_SUPPORT_MMHUB; 915550c58e0STao Zhou adev->external_rev_id = adev->rev_id + 0x3c; 916550c58e0STao Zhou break; 9173e67f4f2SAlex Deucher case IP_VERSION(10, 3, 5): 918bc6bd46bSTao Zhou adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 919bc6bd46bSTao Zhou AMD_CG_SUPPORT_GFX_CGCG | 920d69d278fSTao Zhou AMD_CG_SUPPORT_GFX_CGLS | 9215d36b865STao Zhou AMD_CG_SUPPORT_GFX_3D_CGCG | 9225d36b865STao Zhou AMD_CG_SUPPORT_MC_MGCG | 923170c193fSTao Zhou AMD_CG_SUPPORT_MC_LS | 924170c193fSTao Zhou AMD_CG_SUPPORT_HDP_MGCG | 925a764bef3STao Zhou AMD_CG_SUPPORT_HDP_LS | 926e47e4c0eSVeerabadhran Gopalakrishnan AMD_CG_SUPPORT_IH_CG | 927e47e4c0eSVeerabadhran Gopalakrishnan AMD_CG_SUPPORT_VCN_MGCG; 928f703d4b6SVeerabadhran Gopalakrishnan adev->pg_flags = AMD_PG_SUPPORT_VCN | 929147de218STao Zhou AMD_PG_SUPPORT_VCN_DPG | 930147de218STao Zhou AMD_PG_SUPPORT_ATHUB | 931147de218STao Zhou AMD_PG_SUPPORT_MMHUB; 9328573035aSChengming Gui adev->external_rev_id = adev->rev_id + 0x46; 9338573035aSChengming Gui break; 9343e67f4f2SAlex Deucher case IP_VERSION(10, 3, 3): 9359c6c48e6SAaron Liu adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 9369c6c48e6SAaron Liu AMD_CG_SUPPORT_GFX_MGLS | 9379c6c48e6SAaron Liu AMD_CG_SUPPORT_GFX_CGCG | 9389c6c48e6SAaron Liu AMD_CG_SUPPORT_GFX_CGLS | 9399c6c48e6SAaron Liu AMD_CG_SUPPORT_GFX_3D_CGCG | 9409c6c48e6SAaron Liu AMD_CG_SUPPORT_GFX_3D_CGLS | 9419c6c48e6SAaron Liu AMD_CG_SUPPORT_GFX_RLC_LS | 9429c6c48e6SAaron Liu AMD_CG_SUPPORT_GFX_CP_LS | 94383ae09b5SAaron Liu AMD_CG_SUPPORT_GFX_FGCG | 94483ae09b5SAaron Liu AMD_CG_SUPPORT_MC_MGCG | 945f1e9aa65SAaron Liu AMD_CG_SUPPORT_MC_LS | 9466bd95572SAaron Liu AMD_CG_SUPPORT_SDMA_LS | 9476bd95572SAaron Liu AMD_CG_SUPPORT_HDP_MGCG | 948b7dd14c7SAaron Liu AMD_CG_SUPPORT_HDP_LS | 949b7dd14c7SAaron Liu AMD_CG_SUPPORT_ATHUB_MGCG | 950db72c3faSAaron Liu AMD_CG_SUPPORT_ATHUB_LS | 951948b1216SAaron Liu AMD_CG_SUPPORT_IH_CG | 952948b1216SAaron Liu AMD_CG_SUPPORT_VCN_MGCG | 953948b1216SAaron Liu AMD_CG_SUPPORT_JPEG_MGCG; 95454f4f6f3SJames Zhu adev->pg_flags = AMD_PG_SUPPORT_GFX_PG | 955948b1216SAaron Liu AMD_PG_SUPPORT_VCN | 956948b1216SAaron Liu AMD_PG_SUPPORT_VCN_DPG | 957948b1216SAaron Liu AMD_PG_SUPPORT_JPEG; 958e97c8d86SAaron Liu if (adev->pdev->device == 0x1681) 9595efacdf0SAaron Liu adev->external_rev_id = 0x20; 960e97c8d86SAaron Liu else 961e7990721SAaron Liu adev->external_rev_id = adev->rev_id + 0x01; 962e7990721SAaron Liu break; 9633e67f4f2SAlex Deucher case IP_VERSION(10, 1, 3): 964b515937bSTao Zhou adev->cg_flags = 0; 965b515937bSTao Zhou adev->pg_flags = 0; 966b515937bSTao Zhou adev->external_rev_id = adev->rev_id + 0x82; 967b515937bSTao Zhou break; 968c6b6a421SHawking Zhang default: 969c6b6a421SHawking Zhang /* FIXME: not supported yet */ 970c6b6a421SHawking Zhang return -EINVAL; 971c6b6a421SHawking Zhang } 972c6b6a421SHawking Zhang 9737bd939d0SLikun GAO if (adev->harvest_ip_mask & AMD_HARVEST_IP_VCN_MASK) 9747bd939d0SLikun GAO adev->pg_flags &= ~(AMD_PG_SUPPORT_VCN | 9757bd939d0SLikun GAO AMD_PG_SUPPORT_VCN_DPG | 9767bd939d0SLikun GAO AMD_PG_SUPPORT_JPEG); 9777bd939d0SLikun GAO 978b05b6903SJiange Zhao if (amdgpu_sriov_vf(adev)) { 979b05b6903SJiange Zhao amdgpu_virt_init_setting(adev); 980b05b6903SJiange Zhao xgpu_nv_mailbox_set_irq_funcs(adev); 981b05b6903SJiange Zhao } 982b05b6903SJiange Zhao 983c6b6a421SHawking Zhang return 0; 984c6b6a421SHawking Zhang } 985c6b6a421SHawking Zhang 986c6b6a421SHawking Zhang static int nv_common_late_init(void *handle) 987c6b6a421SHawking Zhang { 988b05b6903SJiange Zhao struct amdgpu_device *adev = (struct amdgpu_device *)handle; 989b05b6903SJiange Zhao 990ed9d2053SBokun Zhang if (amdgpu_sriov_vf(adev)) { 991b05b6903SJiange Zhao xgpu_nv_mailbox_get_irq(adev); 992ed9d2053SBokun Zhang amdgpu_virt_update_sriov_video_codec(adev, 993ed9d2053SBokun Zhang sriov_sc_video_codecs_encode_array, ARRAY_SIZE(sriov_sc_video_codecs_encode_array), 994ed9d2053SBokun Zhang sriov_sc_video_codecs_decode_array, ARRAY_SIZE(sriov_sc_video_codecs_decode_array)); 995ed9d2053SBokun Zhang } 996b05b6903SJiange Zhao 997c6b6a421SHawking Zhang return 0; 998c6b6a421SHawking Zhang } 999c6b6a421SHawking Zhang 1000c6b6a421SHawking Zhang static int nv_common_sw_init(void *handle) 1001c6b6a421SHawking Zhang { 1002b05b6903SJiange Zhao struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1003b05b6903SJiange Zhao 1004b05b6903SJiange Zhao if (amdgpu_sriov_vf(adev)) 1005b05b6903SJiange Zhao xgpu_nv_mailbox_add_irq_id(adev); 1006b05b6903SJiange Zhao 1007c6b6a421SHawking Zhang return 0; 1008c6b6a421SHawking Zhang } 1009c6b6a421SHawking Zhang 1010c6b6a421SHawking Zhang static int nv_common_sw_fini(void *handle) 1011c6b6a421SHawking Zhang { 1012c6b6a421SHawking Zhang return 0; 1013c6b6a421SHawking Zhang } 1014c6b6a421SHawking Zhang 1015c6b6a421SHawking Zhang static int nv_common_hw_init(void *handle) 1016c6b6a421SHawking Zhang { 1017c6b6a421SHawking Zhang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1018c6b6a421SHawking Zhang 10195a5da8aeSEvan Quan if (adev->nbio.funcs->apply_lc_spc_mode_wa) 10205a5da8aeSEvan Quan adev->nbio.funcs->apply_lc_spc_mode_wa(adev); 10215a5da8aeSEvan Quan 1022adcf949eSEvan Quan if (adev->nbio.funcs->apply_l1_link_width_reconfig_wa) 1023adcf949eSEvan Quan adev->nbio.funcs->apply_l1_link_width_reconfig_wa(adev); 1024adcf949eSEvan Quan 1025c6b6a421SHawking Zhang /* enable pcie gen2/3 link */ 1026c6b6a421SHawking Zhang nv_pcie_gen3_enable(adev); 1027c6b6a421SHawking Zhang /* enable aspm */ 1028c6b6a421SHawking Zhang nv_program_aspm(adev); 1029c6b6a421SHawking Zhang /* setup nbio registers */ 1030bebc0762SHawking Zhang adev->nbio.funcs->init_registers(adev); 1031923c087aSYong Zhao /* remap HDP registers to a hole in mmio space, 1032923c087aSYong Zhao * for the purpose of expose those registers 1033923c087aSYong Zhao * to process space 1034923c087aSYong Zhao */ 1035923c087aSYong Zhao if (adev->nbio.funcs->remap_hdp_registers) 1036923c087aSYong Zhao adev->nbio.funcs->remap_hdp_registers(adev); 1037c6b6a421SHawking Zhang /* enable the doorbell aperture */ 1038c6b6a421SHawking Zhang nv_enable_doorbell_aperture(adev, true); 1039c6b6a421SHawking Zhang 1040c6b6a421SHawking Zhang return 0; 1041c6b6a421SHawking Zhang } 1042c6b6a421SHawking Zhang 1043c6b6a421SHawking Zhang static int nv_common_hw_fini(void *handle) 1044c6b6a421SHawking Zhang { 1045c6b6a421SHawking Zhang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1046c6b6a421SHawking Zhang 1047c6b6a421SHawking Zhang /* disable the doorbell aperture */ 1048c6b6a421SHawking Zhang nv_enable_doorbell_aperture(adev, false); 1049c6b6a421SHawking Zhang 1050c6b6a421SHawking Zhang return 0; 1051c6b6a421SHawking Zhang } 1052c6b6a421SHawking Zhang 1053c6b6a421SHawking Zhang static int nv_common_suspend(void *handle) 1054c6b6a421SHawking Zhang { 1055c6b6a421SHawking Zhang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1056c6b6a421SHawking Zhang 1057c6b6a421SHawking Zhang return nv_common_hw_fini(adev); 1058c6b6a421SHawking Zhang } 1059c6b6a421SHawking Zhang 1060c6b6a421SHawking Zhang static int nv_common_resume(void *handle) 1061c6b6a421SHawking Zhang { 1062c6b6a421SHawking Zhang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1063c6b6a421SHawking Zhang 1064c6b6a421SHawking Zhang return nv_common_hw_init(adev); 1065c6b6a421SHawking Zhang } 1066c6b6a421SHawking Zhang 1067c6b6a421SHawking Zhang static bool nv_common_is_idle(void *handle) 1068c6b6a421SHawking Zhang { 1069c6b6a421SHawking Zhang return true; 1070c6b6a421SHawking Zhang } 1071c6b6a421SHawking Zhang 1072c6b6a421SHawking Zhang static int nv_common_wait_for_idle(void *handle) 1073c6b6a421SHawking Zhang { 1074c6b6a421SHawking Zhang return 0; 1075c6b6a421SHawking Zhang } 1076c6b6a421SHawking Zhang 1077c6b6a421SHawking Zhang static int nv_common_soft_reset(void *handle) 1078c6b6a421SHawking Zhang { 1079c6b6a421SHawking Zhang return 0; 1080c6b6a421SHawking Zhang } 1081c6b6a421SHawking Zhang 1082c6b6a421SHawking Zhang static int nv_common_set_clockgating_state(void *handle, 1083c6b6a421SHawking Zhang enum amd_clockgating_state state) 1084c6b6a421SHawking Zhang { 1085c6b6a421SHawking Zhang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1086c6b6a421SHawking Zhang 1087c6b6a421SHawking Zhang if (amdgpu_sriov_vf(adev)) 1088c6b6a421SHawking Zhang return 0; 1089c6b6a421SHawking Zhang 10901d789535SAlex Deucher switch (adev->ip_versions[NBIO_HWIP][0]) { 10913e67f4f2SAlex Deucher case IP_VERSION(2, 3, 0): 10923e67f4f2SAlex Deucher case IP_VERSION(2, 3, 1): 10933e67f4f2SAlex Deucher case IP_VERSION(2, 3, 2): 10943e67f4f2SAlex Deucher case IP_VERSION(3, 3, 0): 10953e67f4f2SAlex Deucher case IP_VERSION(3, 3, 1): 10963e67f4f2SAlex Deucher case IP_VERSION(3, 3, 2): 10973e67f4f2SAlex Deucher case IP_VERSION(3, 3, 3): 1098bebc0762SHawking Zhang adev->nbio.funcs->update_medium_grain_clock_gating(adev, 1099a9d4fe2fSNirmoy Das state == AMD_CG_STATE_GATE); 1100bebc0762SHawking Zhang adev->nbio.funcs->update_medium_grain_light_sleep(adev, 1101a9d4fe2fSNirmoy Das state == AMD_CG_STATE_GATE); 1102bf087285SLikun Gao adev->hdp.funcs->update_clock_gating(adev, 1103a9d4fe2fSNirmoy Das state == AMD_CG_STATE_GATE); 11041001f2a1SLikun Gao adev->smuio.funcs->update_rom_clock_gating(adev, 11051001f2a1SLikun Gao state == AMD_CG_STATE_GATE); 1106c6b6a421SHawking Zhang break; 1107c6b6a421SHawking Zhang default: 1108c6b6a421SHawking Zhang break; 1109c6b6a421SHawking Zhang } 1110c6b6a421SHawking Zhang return 0; 1111c6b6a421SHawking Zhang } 1112c6b6a421SHawking Zhang 1113c6b6a421SHawking Zhang static int nv_common_set_powergating_state(void *handle, 1114c6b6a421SHawking Zhang enum amd_powergating_state state) 1115c6b6a421SHawking Zhang { 1116c6b6a421SHawking Zhang /* TODO */ 1117c6b6a421SHawking Zhang return 0; 1118c6b6a421SHawking Zhang } 1119c6b6a421SHawking Zhang 1120c6b6a421SHawking Zhang static void nv_common_get_clockgating_state(void *handle, u32 *flags) 1121c6b6a421SHawking Zhang { 1122c6b6a421SHawking Zhang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1123c6b6a421SHawking Zhang 1124c6b6a421SHawking Zhang if (amdgpu_sriov_vf(adev)) 1125c6b6a421SHawking Zhang *flags = 0; 1126c6b6a421SHawking Zhang 1127bebc0762SHawking Zhang adev->nbio.funcs->get_clockgating_state(adev, flags); 1128c6b6a421SHawking Zhang 1129bf087285SLikun Gao adev->hdp.funcs->get_clock_gating_state(adev, flags); 1130c6b6a421SHawking Zhang 11311001f2a1SLikun Gao adev->smuio.funcs->get_clock_gating_state(adev, flags); 11321001f2a1SLikun Gao 1133c6b6a421SHawking Zhang return; 1134c6b6a421SHawking Zhang } 1135c6b6a421SHawking Zhang 1136c6b6a421SHawking Zhang static const struct amd_ip_funcs nv_common_ip_funcs = { 1137c6b6a421SHawking Zhang .name = "nv_common", 1138c6b6a421SHawking Zhang .early_init = nv_common_early_init, 1139c6b6a421SHawking Zhang .late_init = nv_common_late_init, 1140c6b6a421SHawking Zhang .sw_init = nv_common_sw_init, 1141c6b6a421SHawking Zhang .sw_fini = nv_common_sw_fini, 1142c6b6a421SHawking Zhang .hw_init = nv_common_hw_init, 1143c6b6a421SHawking Zhang .hw_fini = nv_common_hw_fini, 1144c6b6a421SHawking Zhang .suspend = nv_common_suspend, 1145c6b6a421SHawking Zhang .resume = nv_common_resume, 1146c6b6a421SHawking Zhang .is_idle = nv_common_is_idle, 1147c6b6a421SHawking Zhang .wait_for_idle = nv_common_wait_for_idle, 1148c6b6a421SHawking Zhang .soft_reset = nv_common_soft_reset, 1149c6b6a421SHawking Zhang .set_clockgating_state = nv_common_set_clockgating_state, 1150c6b6a421SHawking Zhang .set_powergating_state = nv_common_set_powergating_state, 1151c6b6a421SHawking Zhang .get_clockgating_state = nv_common_get_clockgating_state, 1152c6b6a421SHawking Zhang }; 1153