1c6b6a421SHawking Zhang /* 2c6b6a421SHawking Zhang * Copyright 2019 Advanced Micro Devices, Inc. 3c6b6a421SHawking Zhang * 4c6b6a421SHawking Zhang * Permission is hereby granted, free of charge, to any person obtaining a 5c6b6a421SHawking Zhang * copy of this software and associated documentation files (the "Software"), 6c6b6a421SHawking Zhang * to deal in the Software without restriction, including without limitation 7c6b6a421SHawking Zhang * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8c6b6a421SHawking Zhang * and/or sell copies of the Software, and to permit persons to whom the 9c6b6a421SHawking Zhang * Software is furnished to do so, subject to the following conditions: 10c6b6a421SHawking Zhang * 11c6b6a421SHawking Zhang * The above copyright notice and this permission notice shall be included in 12c6b6a421SHawking Zhang * all copies or substantial portions of the Software. 13c6b6a421SHawking Zhang * 14c6b6a421SHawking Zhang * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15c6b6a421SHawking Zhang * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16c6b6a421SHawking Zhang * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17c6b6a421SHawking Zhang * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18c6b6a421SHawking Zhang * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19c6b6a421SHawking Zhang * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20c6b6a421SHawking Zhang * OTHER DEALINGS IN THE SOFTWARE. 21c6b6a421SHawking Zhang * 22c6b6a421SHawking Zhang */ 23c6b6a421SHawking Zhang #include <linux/firmware.h> 24c6b6a421SHawking Zhang #include <linux/slab.h> 25c6b6a421SHawking Zhang #include <linux/module.h> 26e9eea902SAlex Deucher #include <linux/pci.h> 27e9eea902SAlex Deucher 286f786950SAlex Deucher #include <drm/amdgpu_drm.h> 296f786950SAlex Deucher 30c6b6a421SHawking Zhang #include "amdgpu.h" 31c6b6a421SHawking Zhang #include "amdgpu_atombios.h" 32c6b6a421SHawking Zhang #include "amdgpu_ih.h" 33c6b6a421SHawking Zhang #include "amdgpu_uvd.h" 34c6b6a421SHawking Zhang #include "amdgpu_vce.h" 35c6b6a421SHawking Zhang #include "amdgpu_ucode.h" 36c6b6a421SHawking Zhang #include "amdgpu_psp.h" 37c6b6a421SHawking Zhang #include "atom.h" 38c6b6a421SHawking Zhang #include "amd_pcie.h" 39c6b6a421SHawking Zhang 40c6b6a421SHawking Zhang #include "gc/gc_10_1_0_offset.h" 41c6b6a421SHawking Zhang #include "gc/gc_10_1_0_sh_mask.h" 423967ae6dSAlex Deucher #include "mp/mp_11_0_offset.h" 43c6b6a421SHawking Zhang 44c6b6a421SHawking Zhang #include "soc15.h" 45c6b6a421SHawking Zhang #include "soc15_common.h" 46c6b6a421SHawking Zhang #include "gmc_v10_0.h" 47c6b6a421SHawking Zhang #include "gfxhub_v2_0.h" 48c6b6a421SHawking Zhang #include "mmhub_v2_0.h" 49bebc0762SHawking Zhang #include "nbio_v2_3.h" 50a7e91bd7SHuang Rui #include "nbio_v7_2.h" 51bf087285SLikun Gao #include "hdp_v5_0.h" 52c6b6a421SHawking Zhang #include "nv.h" 53c6b6a421SHawking Zhang #include "navi10_ih.h" 54c6b6a421SHawking Zhang #include "gfx_v10_0.h" 55c6b6a421SHawking Zhang #include "sdma_v5_0.h" 56157e72e8SLikun Gao #include "sdma_v5_2.h" 57c6b6a421SHawking Zhang #include "vcn_v2_0.h" 585be45a26SLeo Liu #include "jpeg_v2_0.h" 59b8f10585SLeo Liu #include "vcn_v3_0.h" 604d72dd12SLeo Liu #include "jpeg_v3_0.h" 61c6b6a421SHawking Zhang #include "dce_virtual.h" 62c6b6a421SHawking Zhang #include "mes_v10_1.h" 63b05b6903SJiange Zhao #include "mxgpu_nv.h" 640bf7f2dcSLikun Gao #include "smuio_v11_0.h" 650bf7f2dcSLikun Gao #include "smuio_v11_0_6.h" 66c6b6a421SHawking Zhang 67c6b6a421SHawking Zhang static const struct amd_ip_funcs nv_common_ip_funcs; 68c6b6a421SHawking Zhang 693b246e8bSAlex Deucher /* Navi */ 703b246e8bSAlex Deucher static const struct amdgpu_video_codec_info nv_video_codecs_encode_array[] = 713b246e8bSAlex Deucher { 723b246e8bSAlex Deucher { 736f786950SAlex Deucher .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 743b246e8bSAlex Deucher .max_width = 4096, 753b246e8bSAlex Deucher .max_height = 2304, 763b246e8bSAlex Deucher .max_pixels_per_frame = 4096 * 2304, 773b246e8bSAlex Deucher .max_level = 0, 783b246e8bSAlex Deucher }, 793b246e8bSAlex Deucher { 806f786950SAlex Deucher .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 813b246e8bSAlex Deucher .max_width = 4096, 823b246e8bSAlex Deucher .max_height = 2304, 833b246e8bSAlex Deucher .max_pixels_per_frame = 4096 * 2304, 843b246e8bSAlex Deucher .max_level = 0, 853b246e8bSAlex Deucher }, 863b246e8bSAlex Deucher }; 873b246e8bSAlex Deucher 883b246e8bSAlex Deucher static const struct amdgpu_video_codecs nv_video_codecs_encode = 893b246e8bSAlex Deucher { 903b246e8bSAlex Deucher .codec_count = ARRAY_SIZE(nv_video_codecs_encode_array), 913b246e8bSAlex Deucher .codec_array = nv_video_codecs_encode_array, 923b246e8bSAlex Deucher }; 933b246e8bSAlex Deucher 943b246e8bSAlex Deucher /* Navi1x */ 953b246e8bSAlex Deucher static const struct amdgpu_video_codec_info nv_video_codecs_decode_array[] = 963b246e8bSAlex Deucher { 973b246e8bSAlex Deucher { 986f786950SAlex Deucher .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 993b246e8bSAlex Deucher .max_width = 4096, 1003b246e8bSAlex Deucher .max_height = 4096, 1013b246e8bSAlex Deucher .max_pixels_per_frame = 4096 * 4096, 1023b246e8bSAlex Deucher .max_level = 3, 1033b246e8bSAlex Deucher }, 1043b246e8bSAlex Deucher { 1056f786950SAlex Deucher .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 1063b246e8bSAlex Deucher .max_width = 4096, 1073b246e8bSAlex Deucher .max_height = 4096, 1083b246e8bSAlex Deucher .max_pixels_per_frame = 4096 * 4096, 1093b246e8bSAlex Deucher .max_level = 5, 1103b246e8bSAlex Deucher }, 1113b246e8bSAlex Deucher { 1126f786950SAlex Deucher .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 1133b246e8bSAlex Deucher .max_width = 4096, 1143b246e8bSAlex Deucher .max_height = 4096, 1153b246e8bSAlex Deucher .max_pixels_per_frame = 4096 * 4096, 1163b246e8bSAlex Deucher .max_level = 52, 1173b246e8bSAlex Deucher }, 1183b246e8bSAlex Deucher { 1196f786950SAlex Deucher .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 1203b246e8bSAlex Deucher .max_width = 4096, 1213b246e8bSAlex Deucher .max_height = 4096, 1223b246e8bSAlex Deucher .max_pixels_per_frame = 4096 * 4096, 1233b246e8bSAlex Deucher .max_level = 4, 1243b246e8bSAlex Deucher }, 1253b246e8bSAlex Deucher { 1266f786950SAlex Deucher .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 1273b246e8bSAlex Deucher .max_width = 8192, 1283b246e8bSAlex Deucher .max_height = 4352, 1293b246e8bSAlex Deucher .max_pixels_per_frame = 8192 * 4352, 1303b246e8bSAlex Deucher .max_level = 186, 1313b246e8bSAlex Deucher }, 1323b246e8bSAlex Deucher { 1336f786950SAlex Deucher .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 1343b246e8bSAlex Deucher .max_width = 4096, 1353b246e8bSAlex Deucher .max_height = 4096, 1363b246e8bSAlex Deucher .max_pixels_per_frame = 4096 * 4096, 1373b246e8bSAlex Deucher .max_level = 0, 1383b246e8bSAlex Deucher }, 1393b246e8bSAlex Deucher { 1406f786950SAlex Deucher .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 1413b246e8bSAlex Deucher .max_width = 8192, 1423b246e8bSAlex Deucher .max_height = 4352, 1433b246e8bSAlex Deucher .max_pixels_per_frame = 8192 * 4352, 1443b246e8bSAlex Deucher .max_level = 0, 1453b246e8bSAlex Deucher }, 1463b246e8bSAlex Deucher }; 1473b246e8bSAlex Deucher 1483b246e8bSAlex Deucher static const struct amdgpu_video_codecs nv_video_codecs_decode = 1493b246e8bSAlex Deucher { 1503b246e8bSAlex Deucher .codec_count = ARRAY_SIZE(nv_video_codecs_decode_array), 1513b246e8bSAlex Deucher .codec_array = nv_video_codecs_decode_array, 1523b246e8bSAlex Deucher }; 1533b246e8bSAlex Deucher 1543b246e8bSAlex Deucher /* Sienna Cichlid */ 1553b246e8bSAlex Deucher static const struct amdgpu_video_codec_info sc_video_codecs_decode_array[] = 1563b246e8bSAlex Deucher { 1573b246e8bSAlex Deucher { 1586f786950SAlex Deucher .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 1593b246e8bSAlex Deucher .max_width = 4096, 1603b246e8bSAlex Deucher .max_height = 4096, 1613b246e8bSAlex Deucher .max_pixels_per_frame = 4096 * 4096, 1623b246e8bSAlex Deucher .max_level = 3, 1633b246e8bSAlex Deucher }, 1643b246e8bSAlex Deucher { 1656f786950SAlex Deucher .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 1663b246e8bSAlex Deucher .max_width = 4096, 1673b246e8bSAlex Deucher .max_height = 4096, 1683b246e8bSAlex Deucher .max_pixels_per_frame = 4096 * 4096, 1693b246e8bSAlex Deucher .max_level = 5, 1703b246e8bSAlex Deucher }, 1713b246e8bSAlex Deucher { 1726f786950SAlex Deucher .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 1733b246e8bSAlex Deucher .max_width = 4096, 1743b246e8bSAlex Deucher .max_height = 4096, 1753b246e8bSAlex Deucher .max_pixels_per_frame = 4096 * 4096, 1763b246e8bSAlex Deucher .max_level = 52, 1773b246e8bSAlex Deucher }, 1783b246e8bSAlex Deucher { 1796f786950SAlex Deucher .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 1803b246e8bSAlex Deucher .max_width = 4096, 1813b246e8bSAlex Deucher .max_height = 4096, 1823b246e8bSAlex Deucher .max_pixels_per_frame = 4096 * 4096, 1833b246e8bSAlex Deucher .max_level = 4, 1843b246e8bSAlex Deucher }, 1853b246e8bSAlex Deucher { 1866f786950SAlex Deucher .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 1873b246e8bSAlex Deucher .max_width = 8192, 1883b246e8bSAlex Deucher .max_height = 4352, 1893b246e8bSAlex Deucher .max_pixels_per_frame = 8192 * 4352, 1903b246e8bSAlex Deucher .max_level = 186, 1913b246e8bSAlex Deucher }, 1923b246e8bSAlex Deucher { 1936f786950SAlex Deucher .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 1943b246e8bSAlex Deucher .max_width = 4096, 1953b246e8bSAlex Deucher .max_height = 4096, 1963b246e8bSAlex Deucher .max_pixels_per_frame = 4096 * 4096, 1973b246e8bSAlex Deucher .max_level = 0, 1983b246e8bSAlex Deucher }, 1993b246e8bSAlex Deucher { 2006f786950SAlex Deucher .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 2013b246e8bSAlex Deucher .max_width = 8192, 2023b246e8bSAlex Deucher .max_height = 4352, 2033b246e8bSAlex Deucher .max_pixels_per_frame = 8192 * 4352, 2043b246e8bSAlex Deucher .max_level = 0, 2053b246e8bSAlex Deucher }, 2063b246e8bSAlex Deucher { 2076f786950SAlex Deucher .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, 2083b246e8bSAlex Deucher .max_width = 8192, 2093b246e8bSAlex Deucher .max_height = 4352, 2103b246e8bSAlex Deucher .max_pixels_per_frame = 8192 * 4352, 2113b246e8bSAlex Deucher .max_level = 0, 2123b246e8bSAlex Deucher }, 2133b246e8bSAlex Deucher }; 2143b246e8bSAlex Deucher 2153b246e8bSAlex Deucher static const struct amdgpu_video_codecs sc_video_codecs_decode = 2163b246e8bSAlex Deucher { 2173b246e8bSAlex Deucher .codec_count = ARRAY_SIZE(sc_video_codecs_decode_array), 2183b246e8bSAlex Deucher .codec_array = sc_video_codecs_decode_array, 2193b246e8bSAlex Deucher }; 2203b246e8bSAlex Deucher 2213b246e8bSAlex Deucher static int nv_query_video_codecs(struct amdgpu_device *adev, bool encode, 2223b246e8bSAlex Deucher const struct amdgpu_video_codecs **codecs) 2233b246e8bSAlex Deucher { 2243b246e8bSAlex Deucher switch (adev->asic_type) { 2253b246e8bSAlex Deucher case CHIP_SIENNA_CICHLID: 2263b246e8bSAlex Deucher case CHIP_NAVY_FLOUNDER: 2273b246e8bSAlex Deucher case CHIP_DIMGREY_CAVEFISH: 2283b246e8bSAlex Deucher case CHIP_VANGOGH: 2293b246e8bSAlex Deucher if (encode) 2303b246e8bSAlex Deucher *codecs = &nv_video_codecs_encode; 2313b246e8bSAlex Deucher else 2323b246e8bSAlex Deucher *codecs = &sc_video_codecs_decode; 2333b246e8bSAlex Deucher return 0; 2343b246e8bSAlex Deucher case CHIP_NAVI10: 2353b246e8bSAlex Deucher case CHIP_NAVI14: 2363b246e8bSAlex Deucher case CHIP_NAVI12: 2373b246e8bSAlex Deucher if (encode) 2383b246e8bSAlex Deucher *codecs = &nv_video_codecs_encode; 2393b246e8bSAlex Deucher else 2403b246e8bSAlex Deucher *codecs = &nv_video_codecs_decode; 2413b246e8bSAlex Deucher return 0; 2423b246e8bSAlex Deucher default: 2433b246e8bSAlex Deucher return -EINVAL; 2443b246e8bSAlex Deucher } 2453b246e8bSAlex Deucher } 2463b246e8bSAlex Deucher 247c6b6a421SHawking Zhang /* 248c6b6a421SHawking Zhang * Indirect registers accessor 249c6b6a421SHawking Zhang */ 250c6b6a421SHawking Zhang static u32 nv_pcie_rreg(struct amdgpu_device *adev, u32 reg) 251c6b6a421SHawking Zhang { 252705a2b5bSHawking Zhang unsigned long address, data; 253bebc0762SHawking Zhang address = adev->nbio.funcs->get_pcie_index_offset(adev); 254bebc0762SHawking Zhang data = adev->nbio.funcs->get_pcie_data_offset(adev); 255c6b6a421SHawking Zhang 256705a2b5bSHawking Zhang return amdgpu_device_indirect_rreg(adev, address, data, reg); 257c6b6a421SHawking Zhang } 258c6b6a421SHawking Zhang 259c6b6a421SHawking Zhang static void nv_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v) 260c6b6a421SHawking Zhang { 261705a2b5bSHawking Zhang unsigned long address, data; 262c6b6a421SHawking Zhang 263bebc0762SHawking Zhang address = adev->nbio.funcs->get_pcie_index_offset(adev); 264bebc0762SHawking Zhang data = adev->nbio.funcs->get_pcie_data_offset(adev); 265c6b6a421SHawking Zhang 266705a2b5bSHawking Zhang amdgpu_device_indirect_wreg(adev, address, data, reg, v); 267c6b6a421SHawking Zhang } 268c6b6a421SHawking Zhang 2694922f1bcSJohn Clements static u64 nv_pcie_rreg64(struct amdgpu_device *adev, u32 reg) 2704922f1bcSJohn Clements { 271705a2b5bSHawking Zhang unsigned long address, data; 2724922f1bcSJohn Clements address = adev->nbio.funcs->get_pcie_index_offset(adev); 2734922f1bcSJohn Clements data = adev->nbio.funcs->get_pcie_data_offset(adev); 2744922f1bcSJohn Clements 275705a2b5bSHawking Zhang return amdgpu_device_indirect_rreg64(adev, address, data, reg); 2764922f1bcSJohn Clements } 2774922f1bcSJohn Clements 2785de54343SHuang Rui static u32 nv_pcie_port_rreg(struct amdgpu_device *adev, u32 reg) 2795de54343SHuang Rui { 2805de54343SHuang Rui unsigned long flags, address, data; 2815de54343SHuang Rui u32 r; 2825de54343SHuang Rui address = adev->nbio.funcs->get_pcie_port_index_offset(adev); 2835de54343SHuang Rui data = adev->nbio.funcs->get_pcie_port_data_offset(adev); 2845de54343SHuang Rui 2855de54343SHuang Rui spin_lock_irqsave(&adev->pcie_idx_lock, flags); 2865de54343SHuang Rui WREG32(address, reg * 4); 2875de54343SHuang Rui (void)RREG32(address); 2885de54343SHuang Rui r = RREG32(data); 2895de54343SHuang Rui spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); 2905de54343SHuang Rui return r; 2915de54343SHuang Rui } 2925de54343SHuang Rui 2934922f1bcSJohn Clements static void nv_pcie_wreg64(struct amdgpu_device *adev, u32 reg, u64 v) 2944922f1bcSJohn Clements { 295705a2b5bSHawking Zhang unsigned long address, data; 2964922f1bcSJohn Clements 2974922f1bcSJohn Clements address = adev->nbio.funcs->get_pcie_index_offset(adev); 2984922f1bcSJohn Clements data = adev->nbio.funcs->get_pcie_data_offset(adev); 2994922f1bcSJohn Clements 300705a2b5bSHawking Zhang amdgpu_device_indirect_wreg64(adev, address, data, reg, v); 3014922f1bcSJohn Clements } 3024922f1bcSJohn Clements 3035de54343SHuang Rui static void nv_pcie_port_wreg(struct amdgpu_device *adev, u32 reg, u32 v) 3045de54343SHuang Rui { 3055de54343SHuang Rui unsigned long flags, address, data; 3065de54343SHuang Rui 3075de54343SHuang Rui address = adev->nbio.funcs->get_pcie_port_index_offset(adev); 3085de54343SHuang Rui data = adev->nbio.funcs->get_pcie_port_data_offset(adev); 3095de54343SHuang Rui 3105de54343SHuang Rui spin_lock_irqsave(&adev->pcie_idx_lock, flags); 3115de54343SHuang Rui WREG32(address, reg * 4); 3125de54343SHuang Rui (void)RREG32(address); 3135de54343SHuang Rui WREG32(data, v); 3145de54343SHuang Rui (void)RREG32(data); 3155de54343SHuang Rui spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); 3165de54343SHuang Rui } 3175de54343SHuang Rui 318c6b6a421SHawking Zhang static u32 nv_didt_rreg(struct amdgpu_device *adev, u32 reg) 319c6b6a421SHawking Zhang { 320c6b6a421SHawking Zhang unsigned long flags, address, data; 321c6b6a421SHawking Zhang u32 r; 322c6b6a421SHawking Zhang 323c6b6a421SHawking Zhang address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX); 324c6b6a421SHawking Zhang data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA); 325c6b6a421SHawking Zhang 326c6b6a421SHawking Zhang spin_lock_irqsave(&adev->didt_idx_lock, flags); 327c6b6a421SHawking Zhang WREG32(address, (reg)); 328c6b6a421SHawking Zhang r = RREG32(data); 329c6b6a421SHawking Zhang spin_unlock_irqrestore(&adev->didt_idx_lock, flags); 330c6b6a421SHawking Zhang return r; 331c6b6a421SHawking Zhang } 332c6b6a421SHawking Zhang 333c6b6a421SHawking Zhang static void nv_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v) 334c6b6a421SHawking Zhang { 335c6b6a421SHawking Zhang unsigned long flags, address, data; 336c6b6a421SHawking Zhang 337c6b6a421SHawking Zhang address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX); 338c6b6a421SHawking Zhang data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA); 339c6b6a421SHawking Zhang 340c6b6a421SHawking Zhang spin_lock_irqsave(&adev->didt_idx_lock, flags); 341c6b6a421SHawking Zhang WREG32(address, (reg)); 342c6b6a421SHawking Zhang WREG32(data, (v)); 343c6b6a421SHawking Zhang spin_unlock_irqrestore(&adev->didt_idx_lock, flags); 344c6b6a421SHawking Zhang } 345c6b6a421SHawking Zhang 346c6b6a421SHawking Zhang static u32 nv_get_config_memsize(struct amdgpu_device *adev) 347c6b6a421SHawking Zhang { 348bebc0762SHawking Zhang return adev->nbio.funcs->get_memsize(adev); 349c6b6a421SHawking Zhang } 350c6b6a421SHawking Zhang 351c6b6a421SHawking Zhang static u32 nv_get_xclk(struct amdgpu_device *adev) 352c6b6a421SHawking Zhang { 353462a70d8STao Zhou return adev->clock.spll.reference_freq; 354c6b6a421SHawking Zhang } 355c6b6a421SHawking Zhang 356c6b6a421SHawking Zhang 357c6b6a421SHawking Zhang void nv_grbm_select(struct amdgpu_device *adev, 358c6b6a421SHawking Zhang u32 me, u32 pipe, u32 queue, u32 vmid) 359c6b6a421SHawking Zhang { 360c6b6a421SHawking Zhang u32 grbm_gfx_cntl = 0; 361c6b6a421SHawking Zhang grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, PIPEID, pipe); 362c6b6a421SHawking Zhang grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, MEID, me); 363c6b6a421SHawking Zhang grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, VMID, vmid); 364c6b6a421SHawking Zhang grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, QUEUEID, queue); 365c6b6a421SHawking Zhang 366c6b6a421SHawking Zhang WREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_CNTL), grbm_gfx_cntl); 367c6b6a421SHawking Zhang } 368c6b6a421SHawking Zhang 369c6b6a421SHawking Zhang static void nv_vga_set_state(struct amdgpu_device *adev, bool state) 370c6b6a421SHawking Zhang { 371c6b6a421SHawking Zhang /* todo */ 372c6b6a421SHawking Zhang } 373c6b6a421SHawking Zhang 374c6b6a421SHawking Zhang static bool nv_read_disabled_bios(struct amdgpu_device *adev) 375c6b6a421SHawking Zhang { 376c6b6a421SHawking Zhang /* todo */ 377c6b6a421SHawking Zhang return false; 378c6b6a421SHawking Zhang } 379c6b6a421SHawking Zhang 380c6b6a421SHawking Zhang static bool nv_read_bios_from_rom(struct amdgpu_device *adev, 381c6b6a421SHawking Zhang u8 *bios, u32 length_bytes) 382c6b6a421SHawking Zhang { 38329bc37b4SAlex Deucher u32 *dw_ptr; 38429bc37b4SAlex Deucher u32 i, length_dw; 3850bf7f2dcSLikun Gao u32 rom_index_offset, rom_data_offset; 38629bc37b4SAlex Deucher 38729bc37b4SAlex Deucher if (bios == NULL) 388c6b6a421SHawking Zhang return false; 38929bc37b4SAlex Deucher if (length_bytes == 0) 39029bc37b4SAlex Deucher return false; 39129bc37b4SAlex Deucher /* APU vbios image is part of sbios image */ 39229bc37b4SAlex Deucher if (adev->flags & AMD_IS_APU) 39329bc37b4SAlex Deucher return false; 39429bc37b4SAlex Deucher 39529bc37b4SAlex Deucher dw_ptr = (u32 *)bios; 39629bc37b4SAlex Deucher length_dw = ALIGN(length_bytes, 4) / 4; 39729bc37b4SAlex Deucher 3980bf7f2dcSLikun Gao rom_index_offset = 3990bf7f2dcSLikun Gao adev->smuio.funcs->get_rom_index_offset(adev); 4000bf7f2dcSLikun Gao rom_data_offset = 4010bf7f2dcSLikun Gao adev->smuio.funcs->get_rom_data_offset(adev); 4020bf7f2dcSLikun Gao 40329bc37b4SAlex Deucher /* set rom index to 0 */ 4040bf7f2dcSLikun Gao WREG32(rom_index_offset, 0); 40529bc37b4SAlex Deucher /* read out the rom data */ 40629bc37b4SAlex Deucher for (i = 0; i < length_dw; i++) 4070bf7f2dcSLikun Gao dw_ptr[i] = RREG32(rom_data_offset); 40829bc37b4SAlex Deucher 40929bc37b4SAlex Deucher return true; 410c6b6a421SHawking Zhang } 411c6b6a421SHawking Zhang 412c6b6a421SHawking Zhang static struct soc15_allowed_register_entry nv_allowed_read_registers[] = { 413c6b6a421SHawking Zhang { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS)}, 414c6b6a421SHawking Zhang { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS2)}, 415c6b6a421SHawking Zhang { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE0)}, 416c6b6a421SHawking Zhang { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE1)}, 417c6b6a421SHawking Zhang { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE2)}, 418c6b6a421SHawking Zhang { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE3)}, 419c6b6a421SHawking Zhang { SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_STATUS_REG)}, 420c6b6a421SHawking Zhang { SOC15_REG_ENTRY(SDMA1, 0, mmSDMA1_STATUS_REG)}, 421c6b6a421SHawking Zhang { SOC15_REG_ENTRY(GC, 0, mmCP_STAT)}, 422c6b6a421SHawking Zhang { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT1)}, 423c6b6a421SHawking Zhang { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT2)}, 424c6b6a421SHawking Zhang { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT3)}, 425c6b6a421SHawking Zhang { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_BUSY_STAT)}, 426c6b6a421SHawking Zhang { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STALLED_STAT1)}, 427c6b6a421SHawking Zhang { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STATUS)}, 428664fe85aSMarek Olšák { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_BUSY_STAT)}, 429c6b6a421SHawking Zhang { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STALLED_STAT1)}, 430c6b6a421SHawking Zhang { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STATUS)}, 431c6b6a421SHawking Zhang { SOC15_REG_ENTRY(GC, 0, mmGB_ADDR_CONFIG)}, 432c6b6a421SHawking Zhang }; 433c6b6a421SHawking Zhang 434c6b6a421SHawking Zhang static uint32_t nv_read_indexed_register(struct amdgpu_device *adev, u32 se_num, 435c6b6a421SHawking Zhang u32 sh_num, u32 reg_offset) 436c6b6a421SHawking Zhang { 437c6b6a421SHawking Zhang uint32_t val; 438c6b6a421SHawking Zhang 439c6b6a421SHawking Zhang mutex_lock(&adev->grbm_idx_mutex); 440c6b6a421SHawking Zhang if (se_num != 0xffffffff || sh_num != 0xffffffff) 441c6b6a421SHawking Zhang amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff); 442c6b6a421SHawking Zhang 443c6b6a421SHawking Zhang val = RREG32(reg_offset); 444c6b6a421SHawking Zhang 445c6b6a421SHawking Zhang if (se_num != 0xffffffff || sh_num != 0xffffffff) 446c6b6a421SHawking Zhang amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 447c6b6a421SHawking Zhang mutex_unlock(&adev->grbm_idx_mutex); 448c6b6a421SHawking Zhang return val; 449c6b6a421SHawking Zhang } 450c6b6a421SHawking Zhang 451c6b6a421SHawking Zhang static uint32_t nv_get_register_value(struct amdgpu_device *adev, 452c6b6a421SHawking Zhang bool indexed, u32 se_num, 453c6b6a421SHawking Zhang u32 sh_num, u32 reg_offset) 454c6b6a421SHawking Zhang { 455c6b6a421SHawking Zhang if (indexed) { 456c6b6a421SHawking Zhang return nv_read_indexed_register(adev, se_num, sh_num, reg_offset); 457c6b6a421SHawking Zhang } else { 458c6b6a421SHawking Zhang if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG)) 459c6b6a421SHawking Zhang return adev->gfx.config.gb_addr_config; 460c6b6a421SHawking Zhang return RREG32(reg_offset); 461c6b6a421SHawking Zhang } 462c6b6a421SHawking Zhang } 463c6b6a421SHawking Zhang 464c6b6a421SHawking Zhang static int nv_read_register(struct amdgpu_device *adev, u32 se_num, 465c6b6a421SHawking Zhang u32 sh_num, u32 reg_offset, u32 *value) 466c6b6a421SHawking Zhang { 467c6b6a421SHawking Zhang uint32_t i; 468c6b6a421SHawking Zhang struct soc15_allowed_register_entry *en; 469c6b6a421SHawking Zhang 470c6b6a421SHawking Zhang *value = 0; 471c6b6a421SHawking Zhang for (i = 0; i < ARRAY_SIZE(nv_allowed_read_registers); i++) { 472c6b6a421SHawking Zhang en = &nv_allowed_read_registers[i]; 473fced3c3aSHuang Rui if ((i == 7 && (adev->sdma.num_instances == 1)) || /* some asics don't have SDMA1 */ 474fced3c3aSHuang Rui reg_offset != 475c6b6a421SHawking Zhang (adev->reg_offset[en->hwip][en->inst][en->seg] + en->reg_offset)) 476c6b6a421SHawking Zhang continue; 477c6b6a421SHawking Zhang 478c6b6a421SHawking Zhang *value = nv_get_register_value(adev, 479c6b6a421SHawking Zhang nv_allowed_read_registers[i].grbm_indexed, 480c6b6a421SHawking Zhang se_num, sh_num, reg_offset); 481c6b6a421SHawking Zhang return 0; 482c6b6a421SHawking Zhang } 483c6b6a421SHawking Zhang return -EINVAL; 484c6b6a421SHawking Zhang } 485c6b6a421SHawking Zhang 486b913ec62SAlex Deucher static int nv_asic_mode2_reset(struct amdgpu_device *adev) 487b913ec62SAlex Deucher { 488b913ec62SAlex Deucher u32 i; 489b913ec62SAlex Deucher int ret = 0; 490b913ec62SAlex Deucher 491b913ec62SAlex Deucher amdgpu_atombios_scratch_regs_engine_hung(adev, true); 492b913ec62SAlex Deucher 493b913ec62SAlex Deucher /* disable BM */ 494b913ec62SAlex Deucher pci_clear_master(adev->pdev); 495b913ec62SAlex Deucher 496b913ec62SAlex Deucher amdgpu_device_cache_pci_state(adev->pdev); 497b913ec62SAlex Deucher 498b913ec62SAlex Deucher ret = amdgpu_dpm_mode2_reset(adev); 499b913ec62SAlex Deucher if (ret) 500b913ec62SAlex Deucher dev_err(adev->dev, "GPU mode2 reset failed\n"); 501b913ec62SAlex Deucher 502b913ec62SAlex Deucher amdgpu_device_load_pci_state(adev->pdev); 503b913ec62SAlex Deucher 504b913ec62SAlex Deucher /* wait for asic to come out of reset */ 505b913ec62SAlex Deucher for (i = 0; i < adev->usec_timeout; i++) { 506b913ec62SAlex Deucher u32 memsize = adev->nbio.funcs->get_memsize(adev); 507b913ec62SAlex Deucher 508b913ec62SAlex Deucher if (memsize != 0xffffffff) 509b913ec62SAlex Deucher break; 510b913ec62SAlex Deucher udelay(1); 511b913ec62SAlex Deucher } 512b913ec62SAlex Deucher 513b913ec62SAlex Deucher amdgpu_atombios_scratch_regs_engine_hung(adev, false); 514b913ec62SAlex Deucher 515b913ec62SAlex Deucher return ret; 516b913ec62SAlex Deucher } 517b913ec62SAlex Deucher 5182ddc6c3eSAlex Deucher static enum amd_reset_method 5192ddc6c3eSAlex Deucher nv_asic_reset_method(struct amdgpu_device *adev) 5202ddc6c3eSAlex Deucher { 521273da6ffSWenhui Sheng if (amdgpu_reset_method == AMD_RESET_METHOD_MODE1 || 52216086355SAlex Deucher amdgpu_reset_method == AMD_RESET_METHOD_MODE2 || 523f172865aSAlex Deucher amdgpu_reset_method == AMD_RESET_METHOD_BACO || 524f172865aSAlex Deucher amdgpu_reset_method == AMD_RESET_METHOD_PCI) 525273da6ffSWenhui Sheng return amdgpu_reset_method; 526273da6ffSWenhui Sheng 527273da6ffSWenhui Sheng if (amdgpu_reset_method != -1) 528273da6ffSWenhui Sheng dev_warn(adev->dev, "Specified reset method:%d isn't supported, using AUTO instead.\n", 529273da6ffSWenhui Sheng amdgpu_reset_method); 530273da6ffSWenhui Sheng 531ca6fd7a6SLikun Gao switch (adev->asic_type) { 53216086355SAlex Deucher case CHIP_VANGOGH: 53316086355SAlex Deucher return AMD_RESET_METHOD_MODE2; 534ca6fd7a6SLikun Gao case CHIP_SIENNA_CICHLID: 53522dd44f4SJiansong Chen case CHIP_NAVY_FLOUNDER: 53615ed44c0STao Zhou case CHIP_DIMGREY_CAVEFISH: 537ca6fd7a6SLikun Gao return AMD_RESET_METHOD_MODE1; 538ca6fd7a6SLikun Gao default: 539181e772fSEvan Quan if (amdgpu_dpm_is_baco_supported(adev)) 5402ddc6c3eSAlex Deucher return AMD_RESET_METHOD_BACO; 5412ddc6c3eSAlex Deucher else 5422ddc6c3eSAlex Deucher return AMD_RESET_METHOD_MODE1; 5432ddc6c3eSAlex Deucher } 544ca6fd7a6SLikun Gao } 5452ddc6c3eSAlex Deucher 546c6b6a421SHawking Zhang static int nv_asic_reset(struct amdgpu_device *adev) 547c6b6a421SHawking Zhang { 548767acabdSKevin Wang int ret = 0; 549c6b6a421SHawking Zhang 55016086355SAlex Deucher switch (nv_asic_reset_method(adev)) { 551f172865aSAlex Deucher case AMD_RESET_METHOD_PCI: 552f172865aSAlex Deucher dev_info(adev->dev, "PCI reset\n"); 553f172865aSAlex Deucher ret = amdgpu_device_pci_reset(adev); 554f172865aSAlex Deucher break; 55516086355SAlex Deucher case AMD_RESET_METHOD_BACO: 55611043b7aSAlex Deucher dev_info(adev->dev, "BACO reset\n"); 557181e772fSEvan Quan ret = amdgpu_dpm_baco_reset(adev); 55816086355SAlex Deucher break; 55916086355SAlex Deucher case AMD_RESET_METHOD_MODE2: 56016086355SAlex Deucher dev_info(adev->dev, "MODE2 reset\n"); 561b913ec62SAlex Deucher ret = nv_asic_mode2_reset(adev); 56216086355SAlex Deucher break; 56316086355SAlex Deucher default: 56411043b7aSAlex Deucher dev_info(adev->dev, "MODE1 reset\n"); 5655c03e584SFeifei Xu ret = amdgpu_device_mode1_reset(adev); 56616086355SAlex Deucher break; 56711043b7aSAlex Deucher } 568767acabdSKevin Wang 569767acabdSKevin Wang return ret; 570c6b6a421SHawking Zhang } 571c6b6a421SHawking Zhang 572c6b6a421SHawking Zhang static int nv_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk) 573c6b6a421SHawking Zhang { 574c6b6a421SHawking Zhang /* todo */ 575c6b6a421SHawking Zhang return 0; 576c6b6a421SHawking Zhang } 577c6b6a421SHawking Zhang 578c6b6a421SHawking Zhang static int nv_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk) 579c6b6a421SHawking Zhang { 580c6b6a421SHawking Zhang /* todo */ 581c6b6a421SHawking Zhang return 0; 582c6b6a421SHawking Zhang } 583c6b6a421SHawking Zhang 584c6b6a421SHawking Zhang static void nv_pcie_gen3_enable(struct amdgpu_device *adev) 585c6b6a421SHawking Zhang { 586c6b6a421SHawking Zhang if (pci_is_root_bus(adev->pdev->bus)) 587c6b6a421SHawking Zhang return; 588c6b6a421SHawking Zhang 589c6b6a421SHawking Zhang if (amdgpu_pcie_gen2 == 0) 590c6b6a421SHawking Zhang return; 591c6b6a421SHawking Zhang 592c6b6a421SHawking Zhang if (!(adev->pm.pcie_gen_mask & (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 | 593c6b6a421SHawking Zhang CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3))) 594c6b6a421SHawking Zhang return; 595c6b6a421SHawking Zhang 596c6b6a421SHawking Zhang /* todo */ 597c6b6a421SHawking Zhang } 598c6b6a421SHawking Zhang 599c6b6a421SHawking Zhang static void nv_program_aspm(struct amdgpu_device *adev) 600c6b6a421SHawking Zhang { 601e1edaeafSLikun Gao if (amdgpu_aspm != 1) 602c6b6a421SHawking Zhang return; 603c6b6a421SHawking Zhang 6043273f8b9SKenneth Feng if (!(adev->flags & AMD_IS_APU) && 605e1edaeafSLikun Gao (adev->nbio.funcs->program_aspm)) 606e1edaeafSLikun Gao adev->nbio.funcs->program_aspm(adev); 607e1edaeafSLikun Gao 608c6b6a421SHawking Zhang } 609c6b6a421SHawking Zhang 610c6b6a421SHawking Zhang static void nv_enable_doorbell_aperture(struct amdgpu_device *adev, 611c6b6a421SHawking Zhang bool enable) 612c6b6a421SHawking Zhang { 613bebc0762SHawking Zhang adev->nbio.funcs->enable_doorbell_aperture(adev, enable); 614bebc0762SHawking Zhang adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, enable); 615c6b6a421SHawking Zhang } 616c6b6a421SHawking Zhang 617c6b6a421SHawking Zhang static const struct amdgpu_ip_block_version nv_common_ip_block = 618c6b6a421SHawking Zhang { 619c6b6a421SHawking Zhang .type = AMD_IP_BLOCK_TYPE_COMMON, 620c6b6a421SHawking Zhang .major = 1, 621c6b6a421SHawking Zhang .minor = 0, 622c6b6a421SHawking Zhang .rev = 0, 623c6b6a421SHawking Zhang .funcs = &nv_common_ip_funcs, 624c6b6a421SHawking Zhang }; 625c6b6a421SHawking Zhang 626*32358093SLikun Gao static bool nv_is_headless_sku(struct pci_dev *pdev) 627*32358093SLikun Gao { 628*32358093SLikun Gao if ((pdev->device == 0x731E && 629*32358093SLikun Gao (pdev->revision == 0xC6 || pdev->revision == 0xC7)) || 630*32358093SLikun Gao (pdev->device == 0x7340 && pdev->revision == 0xC9) || 631*32358093SLikun Gao (pdev->device == 0x7360 && pdev->revision == 0xC7)) 632*32358093SLikun Gao return true; 633*32358093SLikun Gao return false; 634*32358093SLikun Gao } 635*32358093SLikun Gao 636b5c73856SXiaojie Yuan static int nv_reg_base_init(struct amdgpu_device *adev) 637c6b6a421SHawking Zhang { 638b5c73856SXiaojie Yuan int r; 639b5c73856SXiaojie Yuan 640b5c73856SXiaojie Yuan if (amdgpu_discovery) { 641b5c73856SXiaojie Yuan r = amdgpu_discovery_reg_base_init(adev); 642b5c73856SXiaojie Yuan if (r) { 643b5c73856SXiaojie Yuan DRM_WARN("failed to init reg base from ip discovery table, " 644b5c73856SXiaojie Yuan "fallback to legacy init method\n"); 645b5c73856SXiaojie Yuan goto legacy_init; 646b5c73856SXiaojie Yuan } 647b5c73856SXiaojie Yuan 6487bd939d0SLikun GAO amdgpu_discovery_harvest_ip(adev); 649*32358093SLikun Gao if (nv_is_headless_sku(adev->pdev)) { 650*32358093SLikun Gao adev->harvest_ip_mask |= AMD_HARVEST_IP_VCN_MASK; 651*32358093SLikun Gao adev->harvest_ip_mask |= AMD_HARVEST_IP_JPEG_MASK; 652*32358093SLikun Gao } 6537bd939d0SLikun GAO 654b5c73856SXiaojie Yuan return 0; 655b5c73856SXiaojie Yuan } 656b5c73856SXiaojie Yuan 657b5c73856SXiaojie Yuan legacy_init: 658c6b6a421SHawking Zhang switch (adev->asic_type) { 659c6b6a421SHawking Zhang case CHIP_NAVI10: 660c6b6a421SHawking Zhang navi10_reg_base_init(adev); 661c6b6a421SHawking Zhang break; 662a0f6d926SXiaojie Yuan case CHIP_NAVI14: 663a0f6d926SXiaojie Yuan navi14_reg_base_init(adev); 664a0f6d926SXiaojie Yuan break; 66503d0a073SXiaojie Yuan case CHIP_NAVI12: 66603d0a073SXiaojie Yuan navi12_reg_base_init(adev); 66703d0a073SXiaojie Yuan break; 668dccdbf3fSLikun Gao case CHIP_SIENNA_CICHLID: 669c8c959f6SJiansong Chen case CHIP_NAVY_FLOUNDER: 670dccdbf3fSLikun Gao sienna_cichlid_reg_base_init(adev); 671dccdbf3fSLikun Gao break; 672026570e6SHuang Rui case CHIP_VANGOGH: 673026570e6SHuang Rui vangogh_reg_base_init(adev); 674026570e6SHuang Rui break; 675038d757bSTao Zhou case CHIP_DIMGREY_CAVEFISH: 676038d757bSTao Zhou dimgrey_cavefish_reg_base_init(adev); 677038d757bSTao Zhou break; 678c6b6a421SHawking Zhang default: 679c6b6a421SHawking Zhang return -EINVAL; 680c6b6a421SHawking Zhang } 681c6b6a421SHawking Zhang 682b5c73856SXiaojie Yuan return 0; 683b5c73856SXiaojie Yuan } 684b5c73856SXiaojie Yuan 685c1299461SWenhui Sheng void nv_set_virt_ops(struct amdgpu_device *adev) 686c1299461SWenhui Sheng { 687c1299461SWenhui Sheng adev->virt.ops = &xgpu_nv_virt_ops; 688c1299461SWenhui Sheng } 689c1299461SWenhui Sheng 690b5c73856SXiaojie Yuan int nv_set_ip_blocks(struct amdgpu_device *adev) 691b5c73856SXiaojie Yuan { 692b5c73856SXiaojie Yuan int r; 693b5c73856SXiaojie Yuan 694a7e91bd7SHuang Rui if (adev->flags & AMD_IS_APU) { 695a7e91bd7SHuang Rui adev->nbio.funcs = &nbio_v7_2_funcs; 696a7e91bd7SHuang Rui adev->nbio.hdp_flush_reg = &nbio_v7_2_hdp_flush_reg; 697a7e91bd7SHuang Rui } else { 698122078deSMonk Liu adev->nbio.funcs = &nbio_v2_3_funcs; 699122078deSMonk Liu adev->nbio.hdp_flush_reg = &nbio_v2_3_hdp_flush_reg; 700a7e91bd7SHuang Rui } 701bf087285SLikun Gao adev->hdp.funcs = &hdp_v5_0_funcs; 702122078deSMonk Liu 7030bf7f2dcSLikun Gao if (adev->asic_type >= CHIP_SIENNA_CICHLID) 7040bf7f2dcSLikun Gao adev->smuio.funcs = &smuio_v11_0_6_funcs; 7050bf7f2dcSLikun Gao else 7060bf7f2dcSLikun Gao adev->smuio.funcs = &smuio_v11_0_funcs; 7070bf7f2dcSLikun Gao 708c652923aSJohn Clements if (adev->asic_type == CHIP_SIENNA_CICHLID) 709c652923aSJohn Clements adev->gmc.xgmi.supported = true; 710c652923aSJohn Clements 711b5c73856SXiaojie Yuan /* Set IP register base before any HW register access */ 712b5c73856SXiaojie Yuan r = nv_reg_base_init(adev); 713b5c73856SXiaojie Yuan if (r) 714b5c73856SXiaojie Yuan return r; 715b5c73856SXiaojie Yuan 716c6b6a421SHawking Zhang switch (adev->asic_type) { 717c6b6a421SHawking Zhang case CHIP_NAVI10: 718d1daf850SAlex Deucher case CHIP_NAVI14: 719c6b6a421SHawking Zhang amdgpu_device_ip_block_add(adev, &nv_common_ip_block); 720c6b6a421SHawking Zhang amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block); 721c6b6a421SHawking Zhang amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block); 722c6b6a421SHawking Zhang amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block); 723c6b6a421SHawking Zhang if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP && 7249530273eSEvan Quan !amdgpu_sriov_vf(adev)) 725c6b6a421SHawking Zhang amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 726c6b6a421SHawking Zhang if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) 727c6b6a421SHawking Zhang amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block); 728f8a7976bSAlex Deucher #if defined(CONFIG_DRM_AMD_DC) 7298301f6b9STianci.Yin else if (amdgpu_device_has_dc_support(adev)) 730b4f199c7SHarry Wentland amdgpu_device_ip_block_add(adev, &dm_ip_block); 731f8a7976bSAlex Deucher #endif 732c6b6a421SHawking Zhang amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block); 733c6b6a421SHawking Zhang amdgpu_device_ip_block_add(adev, &sdma_v5_0_ip_block); 734c6b6a421SHawking Zhang if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT && 7359530273eSEvan Quan !amdgpu_sriov_vf(adev)) 736c6b6a421SHawking Zhang amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 737c6b6a421SHawking Zhang amdgpu_device_ip_block_add(adev, &vcn_v2_0_ip_block); 7385be45a26SLeo Liu amdgpu_device_ip_block_add(adev, &jpeg_v2_0_ip_block); 739c6b6a421SHawking Zhang if (adev->enable_mes) 740c6b6a421SHawking Zhang amdgpu_device_ip_block_add(adev, &mes_v10_1_ip_block); 741c6b6a421SHawking Zhang break; 74244e9e7c9SXiaojie Yuan case CHIP_NAVI12: 74344e9e7c9SXiaojie Yuan amdgpu_device_ip_block_add(adev, &nv_common_ip_block); 74444e9e7c9SXiaojie Yuan amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block); 74544e9e7c9SXiaojie Yuan amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block); 7466b66ae2eSXiaojie Yuan amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block); 74779bebabbSMonk Liu if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) 7487f47efebSXiaojie Yuan amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 74979902029SXiaojie Yuan if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) 75079902029SXiaojie Yuan amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block); 75120c14ee1SPetr Cvek #if defined(CONFIG_DRM_AMD_DC) 752078655d9SLeo Li else if (amdgpu_device_has_dc_support(adev)) 753078655d9SLeo Li amdgpu_device_ip_block_add(adev, &dm_ip_block); 75420c14ee1SPetr Cvek #endif 75544e9e7c9SXiaojie Yuan amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block); 75644e9e7c9SXiaojie Yuan amdgpu_device_ip_block_add(adev, &sdma_v5_0_ip_block); 7577f47efebSXiaojie Yuan if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT && 7589530273eSEvan Quan !amdgpu_sriov_vf(adev)) 7597f47efebSXiaojie Yuan amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 7601fbed280SBoyuan Zhang amdgpu_device_ip_block_add(adev, &vcn_v2_0_ip_block); 761fe442491SMonk Liu if (!amdgpu_sriov_vf(adev)) 7625be45a26SLeo Liu amdgpu_device_ip_block_add(adev, &jpeg_v2_0_ip_block); 76344e9e7c9SXiaojie Yuan break; 7642e1ba10eSLikun Gao case CHIP_SIENNA_CICHLID: 7652e1ba10eSLikun Gao amdgpu_device_ip_block_add(adev, &nv_common_ip_block); 7660b3df16bSLikun Gao amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block); 767757b3af8SLikun Gao amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block); 76856304e72SLikun Gao if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) 7695aa02350SLikun Gao amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block); 770b07e5c60SLikun Gao if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP && 771acf2740fSJane Jian is_support_sw_smu(adev)) 772b07e5c60SLikun Gao amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 7739a986760SLikun Gao if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) 7749a986760SLikun Gao amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block); 775464ab91aSBhawanpreet Lakha #if defined(CONFIG_DRM_AMD_DC) 776464ab91aSBhawanpreet Lakha else if (amdgpu_device_has_dc_support(adev)) 777464ab91aSBhawanpreet Lakha amdgpu_device_ip_block_add(adev, &dm_ip_block); 778464ab91aSBhawanpreet Lakha #endif 779933c8a93SLikun Gao amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block); 780157e72e8SLikun Gao amdgpu_device_ip_block_add(adev, &sdma_v5_2_ip_block); 781b8f10585SLeo Liu amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block); 782c45fbe1bSJack Zhang if (!amdgpu_sriov_vf(adev)) 7834d72dd12SLeo Liu amdgpu_device_ip_block_add(adev, &jpeg_v3_0_ip_block); 784a346ef86SJack Xiao if (adev->enable_mes) 785a346ef86SJack Xiao amdgpu_device_ip_block_add(adev, &mes_v10_1_ip_block); 7862e1ba10eSLikun Gao break; 7878515e0a4SJiansong Chen case CHIP_NAVY_FLOUNDER: 7888515e0a4SJiansong Chen amdgpu_device_ip_block_add(adev, &nv_common_ip_block); 789fc8f07daSJiansong Chen amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block); 790026c396bSJiansong Chen amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block); 7917420eab2SJiansong Chen if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) 7927420eab2SJiansong Chen amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block); 7937420eab2SJiansong Chen if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP && 7947420eab2SJiansong Chen is_support_sw_smu(adev)) 7957420eab2SJiansong Chen amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 7965404f073SJiansong Chen if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) 7975404f073SJiansong Chen amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block); 798a6c5308fSBhawanpreet Lakha #if defined(CONFIG_DRM_AMD_DC) 799a6c5308fSBhawanpreet Lakha else if (amdgpu_device_has_dc_support(adev)) 800a6c5308fSBhawanpreet Lakha amdgpu_device_ip_block_add(adev, &dm_ip_block); 801a6c5308fSBhawanpreet Lakha #endif 802885eb3faSJiansong Chen amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block); 803df2d15dfSJiansong Chen amdgpu_device_ip_block_add(adev, &sdma_v5_2_ip_block); 804290b4ad5SBoyuan Zhang amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block); 805290b4ad5SBoyuan Zhang amdgpu_device_ip_block_add(adev, &jpeg_v3_0_ip_block); 806f4497d10SJiansong Chen if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT && 807f4497d10SJiansong Chen is_support_sw_smu(adev)) 808f4497d10SJiansong Chen amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 8098515e0a4SJiansong Chen break; 81088edbad6SHuang Rui case CHIP_VANGOGH: 81188edbad6SHuang Rui amdgpu_device_ip_block_add(adev, &nv_common_ip_block); 81288edbad6SHuang Rui amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block); 81388edbad6SHuang Rui amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block); 814ed3b7353SHuang Rui if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) 815ed3b7353SHuang Rui amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block); 816c821e0fbSHuang Rui amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 81788edbad6SHuang Rui if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) 81888edbad6SHuang Rui amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block); 81984b934bcSHuang Rui #if defined(CONFIG_DRM_AMD_DC) 82084b934bcSHuang Rui else if (amdgpu_device_has_dc_support(adev)) 82184b934bcSHuang Rui amdgpu_device_ip_block_add(adev, &dm_ip_block); 82284b934bcSHuang Rui #endif 82388edbad6SHuang Rui amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block); 82488edbad6SHuang Rui amdgpu_device_ip_block_add(adev, &sdma_v5_2_ip_block); 825b4e532d6SThong Thai amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block); 826b4e532d6SThong Thai amdgpu_device_ip_block_add(adev, &jpeg_v3_0_ip_block); 82788edbad6SHuang Rui break; 8282aa92b12STao Zhou case CHIP_DIMGREY_CAVEFISH: 8292aa92b12STao Zhou amdgpu_device_ip_block_add(adev, &nv_common_ip_block); 8303e02ad44STao Zhou amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block); 831771cc67eSTao Zhou amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block); 832aff39cdeSTao Zhou if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) 833aff39cdeSTao Zhou amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block); 834aff39cdeSTao Zhou if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP && 835aff39cdeSTao Zhou is_support_sw_smu(adev)) 836aff39cdeSTao Zhou amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 83776a2d9eaSTao Zhou if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) 83876a2d9eaSTao Zhou amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block); 8397cc656e2STao Zhou #if defined(CONFIG_DRM_AMD_DC) 8407cc656e2STao Zhou else if (amdgpu_device_has_dc_support(adev)) 8417cc656e2STao Zhou amdgpu_device_ip_block_add(adev, &dm_ip_block); 8427cc656e2STao Zhou #endif 843feb6329cSTao Zhou amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block); 84401069226STao Zhou amdgpu_device_ip_block_add(adev, &sdma_v5_2_ip_block); 8450afc770bSJames Zhu amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block); 846be6b1cd3SJames Zhu amdgpu_device_ip_block_add(adev, &jpeg_v3_0_ip_block); 8472aa92b12STao Zhou break; 848c6b6a421SHawking Zhang default: 849c6b6a421SHawking Zhang return -EINVAL; 850c6b6a421SHawking Zhang } 851c6b6a421SHawking Zhang 852c6b6a421SHawking Zhang return 0; 853c6b6a421SHawking Zhang } 854c6b6a421SHawking Zhang 855c6b6a421SHawking Zhang static uint32_t nv_get_rev_id(struct amdgpu_device *adev) 856c6b6a421SHawking Zhang { 857bebc0762SHawking Zhang return adev->nbio.funcs->get_rev_id(adev); 858c6b6a421SHawking Zhang } 859c6b6a421SHawking Zhang 860c6b6a421SHawking Zhang static bool nv_need_full_reset(struct amdgpu_device *adev) 861c6b6a421SHawking Zhang { 862c6b6a421SHawking Zhang return true; 863c6b6a421SHawking Zhang } 864c6b6a421SHawking Zhang 865c6b6a421SHawking Zhang static bool nv_need_reset_on_init(struct amdgpu_device *adev) 866c6b6a421SHawking Zhang { 867c6b6a421SHawking Zhang u32 sol_reg; 868c6b6a421SHawking Zhang 869c6b6a421SHawking Zhang if (adev->flags & AMD_IS_APU) 870c6b6a421SHawking Zhang return false; 871c6b6a421SHawking Zhang 872c6b6a421SHawking Zhang /* Check sOS sign of life register to confirm sys driver and sOS 873c6b6a421SHawking Zhang * are already been loaded. 874c6b6a421SHawking Zhang */ 875c6b6a421SHawking Zhang sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81); 876c6b6a421SHawking Zhang if (sol_reg) 877c6b6a421SHawking Zhang return true; 8783967ae6dSAlex Deucher 879c6b6a421SHawking Zhang return false; 880c6b6a421SHawking Zhang } 881c6b6a421SHawking Zhang 8822af81531SKevin Wang static uint64_t nv_get_pcie_replay_count(struct amdgpu_device *adev) 8832af81531SKevin Wang { 8842af81531SKevin Wang 8852af81531SKevin Wang /* TODO 8862af81531SKevin Wang * dummy implement for pcie_replay_count sysfs interface 8872af81531SKevin Wang * */ 8882af81531SKevin Wang 8892af81531SKevin Wang return 0; 8902af81531SKevin Wang } 8912af81531SKevin Wang 892c6b6a421SHawking Zhang static void nv_init_doorbell_index(struct amdgpu_device *adev) 893c6b6a421SHawking Zhang { 894c6b6a421SHawking Zhang adev->doorbell_index.kiq = AMDGPU_NAVI10_DOORBELL_KIQ; 895c6b6a421SHawking Zhang adev->doorbell_index.mec_ring0 = AMDGPU_NAVI10_DOORBELL_MEC_RING0; 896c6b6a421SHawking Zhang adev->doorbell_index.mec_ring1 = AMDGPU_NAVI10_DOORBELL_MEC_RING1; 897c6b6a421SHawking Zhang adev->doorbell_index.mec_ring2 = AMDGPU_NAVI10_DOORBELL_MEC_RING2; 898c6b6a421SHawking Zhang adev->doorbell_index.mec_ring3 = AMDGPU_NAVI10_DOORBELL_MEC_RING3; 899c6b6a421SHawking Zhang adev->doorbell_index.mec_ring4 = AMDGPU_NAVI10_DOORBELL_MEC_RING4; 900c6b6a421SHawking Zhang adev->doorbell_index.mec_ring5 = AMDGPU_NAVI10_DOORBELL_MEC_RING5; 901c6b6a421SHawking Zhang adev->doorbell_index.mec_ring6 = AMDGPU_NAVI10_DOORBELL_MEC_RING6; 902c6b6a421SHawking Zhang adev->doorbell_index.mec_ring7 = AMDGPU_NAVI10_DOORBELL_MEC_RING7; 903c6b6a421SHawking Zhang adev->doorbell_index.userqueue_start = AMDGPU_NAVI10_DOORBELL_USERQUEUE_START; 904c6b6a421SHawking Zhang adev->doorbell_index.userqueue_end = AMDGPU_NAVI10_DOORBELL_USERQUEUE_END; 905c6b6a421SHawking Zhang adev->doorbell_index.gfx_ring0 = AMDGPU_NAVI10_DOORBELL_GFX_RING0; 906c6b6a421SHawking Zhang adev->doorbell_index.gfx_ring1 = AMDGPU_NAVI10_DOORBELL_GFX_RING1; 90720519232SJack Xiao adev->doorbell_index.mes_ring = AMDGPU_NAVI10_DOORBELL_MES_RING; 908c6b6a421SHawking Zhang adev->doorbell_index.sdma_engine[0] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE0; 909c6b6a421SHawking Zhang adev->doorbell_index.sdma_engine[1] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE1; 910157e72e8SLikun Gao adev->doorbell_index.sdma_engine[2] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE2; 911157e72e8SLikun Gao adev->doorbell_index.sdma_engine[3] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE3; 912c6b6a421SHawking Zhang adev->doorbell_index.ih = AMDGPU_NAVI10_DOORBELL_IH; 913c6b6a421SHawking Zhang adev->doorbell_index.vcn.vcn_ring0_1 = AMDGPU_NAVI10_DOORBELL64_VCN0_1; 914c6b6a421SHawking Zhang adev->doorbell_index.vcn.vcn_ring2_3 = AMDGPU_NAVI10_DOORBELL64_VCN2_3; 915c6b6a421SHawking Zhang adev->doorbell_index.vcn.vcn_ring4_5 = AMDGPU_NAVI10_DOORBELL64_VCN4_5; 916c6b6a421SHawking Zhang adev->doorbell_index.vcn.vcn_ring6_7 = AMDGPU_NAVI10_DOORBELL64_VCN6_7; 917c6b6a421SHawking Zhang adev->doorbell_index.first_non_cp = AMDGPU_NAVI10_DOORBELL64_FIRST_NON_CP; 918c6b6a421SHawking Zhang adev->doorbell_index.last_non_cp = AMDGPU_NAVI10_DOORBELL64_LAST_NON_CP; 919c6b6a421SHawking Zhang 920c6b6a421SHawking Zhang adev->doorbell_index.max_assignment = AMDGPU_NAVI10_DOORBELL_MAX_ASSIGNMENT << 1; 921c6b6a421SHawking Zhang adev->doorbell_index.sdma_doorbell_range = 20; 922c6b6a421SHawking Zhang } 923c6b6a421SHawking Zhang 924a7173731SAlex Deucher static void nv_pre_asic_init(struct amdgpu_device *adev) 925a7173731SAlex Deucher { 926a7173731SAlex Deucher } 927a7173731SAlex Deucher 92827747293SEvan Quan static int nv_update_umd_stable_pstate(struct amdgpu_device *adev, 92927747293SEvan Quan bool enter) 93027747293SEvan Quan { 93127747293SEvan Quan if (enter) 93227747293SEvan Quan amdgpu_gfx_rlc_enter_safe_mode(adev); 93327747293SEvan Quan else 93427747293SEvan Quan amdgpu_gfx_rlc_exit_safe_mode(adev); 93527747293SEvan Quan 93627747293SEvan Quan if (adev->gfx.funcs->update_perfmon_mgcg) 93727747293SEvan Quan adev->gfx.funcs->update_perfmon_mgcg(adev, !enter); 93827747293SEvan Quan 9393273f8b9SKenneth Feng if (!(adev->flags & AMD_IS_APU) && 940e1edaeafSLikun Gao (adev->nbio.funcs->enable_aspm)) 94127747293SEvan Quan adev->nbio.funcs->enable_aspm(adev, !enter); 94227747293SEvan Quan 94327747293SEvan Quan return 0; 94427747293SEvan Quan } 94527747293SEvan Quan 946c6b6a421SHawking Zhang static const struct amdgpu_asic_funcs nv_asic_funcs = 947c6b6a421SHawking Zhang { 948c6b6a421SHawking Zhang .read_disabled_bios = &nv_read_disabled_bios, 949c6b6a421SHawking Zhang .read_bios_from_rom = &nv_read_bios_from_rom, 950c6b6a421SHawking Zhang .read_register = &nv_read_register, 951c6b6a421SHawking Zhang .reset = &nv_asic_reset, 9522ddc6c3eSAlex Deucher .reset_method = &nv_asic_reset_method, 953c6b6a421SHawking Zhang .set_vga_state = &nv_vga_set_state, 954c6b6a421SHawking Zhang .get_xclk = &nv_get_xclk, 955c6b6a421SHawking Zhang .set_uvd_clocks = &nv_set_uvd_clocks, 956c6b6a421SHawking Zhang .set_vce_clocks = &nv_set_vce_clocks, 957c6b6a421SHawking Zhang .get_config_memsize = &nv_get_config_memsize, 958c6b6a421SHawking Zhang .init_doorbell_index = &nv_init_doorbell_index, 959c6b6a421SHawking Zhang .need_full_reset = &nv_need_full_reset, 960c6b6a421SHawking Zhang .need_reset_on_init = &nv_need_reset_on_init, 9612af81531SKevin Wang .get_pcie_replay_count = &nv_get_pcie_replay_count, 962181e772fSEvan Quan .supports_baco = &amdgpu_dpm_is_baco_supported, 963a7173731SAlex Deucher .pre_asic_init = &nv_pre_asic_init, 96427747293SEvan Quan .update_umd_stable_pstate = &nv_update_umd_stable_pstate, 9653b246e8bSAlex Deucher .query_video_codecs = &nv_query_video_codecs, 966c6b6a421SHawking Zhang }; 967c6b6a421SHawking Zhang 968c6b6a421SHawking Zhang static int nv_common_early_init(void *handle) 969c6b6a421SHawking Zhang { 970923c087aSYong Zhao #define MMIO_REG_HOLE_OFFSET (0x80000 - PAGE_SIZE) 971c6b6a421SHawking Zhang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 972c6b6a421SHawking Zhang 973923c087aSYong Zhao adev->rmmio_remap.reg_offset = MMIO_REG_HOLE_OFFSET; 974923c087aSYong Zhao adev->rmmio_remap.bus_addr = adev->rmmio_base + MMIO_REG_HOLE_OFFSET; 975c6b6a421SHawking Zhang adev->smc_rreg = NULL; 976c6b6a421SHawking Zhang adev->smc_wreg = NULL; 977c6b6a421SHawking Zhang adev->pcie_rreg = &nv_pcie_rreg; 978c6b6a421SHawking Zhang adev->pcie_wreg = &nv_pcie_wreg; 9794922f1bcSJohn Clements adev->pcie_rreg64 = &nv_pcie_rreg64; 9804922f1bcSJohn Clements adev->pcie_wreg64 = &nv_pcie_wreg64; 9815de54343SHuang Rui adev->pciep_rreg = &nv_pcie_port_rreg; 9825de54343SHuang Rui adev->pciep_wreg = &nv_pcie_port_wreg; 983c6b6a421SHawking Zhang 984c6b6a421SHawking Zhang /* TODO: will add them during VCN v2 implementation */ 985c6b6a421SHawking Zhang adev->uvd_ctx_rreg = NULL; 986c6b6a421SHawking Zhang adev->uvd_ctx_wreg = NULL; 987c6b6a421SHawking Zhang 988c6b6a421SHawking Zhang adev->didt_rreg = &nv_didt_rreg; 989c6b6a421SHawking Zhang adev->didt_wreg = &nv_didt_wreg; 990c6b6a421SHawking Zhang 991c6b6a421SHawking Zhang adev->asic_funcs = &nv_asic_funcs; 992c6b6a421SHawking Zhang 993c6b6a421SHawking Zhang adev->rev_id = nv_get_rev_id(adev); 994c6b6a421SHawking Zhang adev->external_rev_id = 0xff; 995c6b6a421SHawking Zhang switch (adev->asic_type) { 996c6b6a421SHawking Zhang case CHIP_NAVI10: 997c6b6a421SHawking Zhang adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 998c6b6a421SHawking Zhang AMD_CG_SUPPORT_GFX_CGCG | 999c6b6a421SHawking Zhang AMD_CG_SUPPORT_IH_CG | 1000c6b6a421SHawking Zhang AMD_CG_SUPPORT_HDP_MGCG | 1001c6b6a421SHawking Zhang AMD_CG_SUPPORT_HDP_LS | 1002c6b6a421SHawking Zhang AMD_CG_SUPPORT_SDMA_MGCG | 1003c6b6a421SHawking Zhang AMD_CG_SUPPORT_SDMA_LS | 1004c6b6a421SHawking Zhang AMD_CG_SUPPORT_MC_MGCG | 1005c6b6a421SHawking Zhang AMD_CG_SUPPORT_MC_LS | 1006c6b6a421SHawking Zhang AMD_CG_SUPPORT_ATHUB_MGCG | 1007c6b6a421SHawking Zhang AMD_CG_SUPPORT_ATHUB_LS | 1008c6b6a421SHawking Zhang AMD_CG_SUPPORT_VCN_MGCG | 1009099d66e4SLeo Liu AMD_CG_SUPPORT_JPEG_MGCG | 1010c6b6a421SHawking Zhang AMD_CG_SUPPORT_BIF_MGCG | 1011c6b6a421SHawking Zhang AMD_CG_SUPPORT_BIF_LS; 1012157710eaSLeo Liu adev->pg_flags = AMD_PG_SUPPORT_VCN | 1013c12d410fSHuang Rui AMD_PG_SUPPORT_VCN_DPG | 1014099d66e4SLeo Liu AMD_PG_SUPPORT_JPEG | 1015a201b6acSHuang Rui AMD_PG_SUPPORT_ATHUB; 1016c6b6a421SHawking Zhang adev->external_rev_id = adev->rev_id + 0x1; 1017c6b6a421SHawking Zhang break; 10185e71e011SXiaojie Yuan case CHIP_NAVI14: 1019d0c39f8cSXiaojie Yuan adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 1020d0c39f8cSXiaojie Yuan AMD_CG_SUPPORT_GFX_CGCG | 1021d0c39f8cSXiaojie Yuan AMD_CG_SUPPORT_IH_CG | 1022d0c39f8cSXiaojie Yuan AMD_CG_SUPPORT_HDP_MGCG | 1023d0c39f8cSXiaojie Yuan AMD_CG_SUPPORT_HDP_LS | 1024d0c39f8cSXiaojie Yuan AMD_CG_SUPPORT_SDMA_MGCG | 1025d0c39f8cSXiaojie Yuan AMD_CG_SUPPORT_SDMA_LS | 1026d0c39f8cSXiaojie Yuan AMD_CG_SUPPORT_MC_MGCG | 1027d0c39f8cSXiaojie Yuan AMD_CG_SUPPORT_MC_LS | 1028d0c39f8cSXiaojie Yuan AMD_CG_SUPPORT_ATHUB_MGCG | 1029d0c39f8cSXiaojie Yuan AMD_CG_SUPPORT_ATHUB_LS | 1030d0c39f8cSXiaojie Yuan AMD_CG_SUPPORT_VCN_MGCG | 1031099d66e4SLeo Liu AMD_CG_SUPPORT_JPEG_MGCG | 1032d0c39f8cSXiaojie Yuan AMD_CG_SUPPORT_BIF_MGCG | 1033d0c39f8cSXiaojie Yuan AMD_CG_SUPPORT_BIF_LS; 10340377b088SXiaojie Yuan adev->pg_flags = AMD_PG_SUPPORT_VCN | 1035099d66e4SLeo Liu AMD_PG_SUPPORT_JPEG | 10360377b088SXiaojie Yuan AMD_PG_SUPPORT_VCN_DPG; 103735ef88faStiancyin adev->external_rev_id = adev->rev_id + 20; 10385e71e011SXiaojie Yuan break; 103974b5e509SXiaojie Yuan case CHIP_NAVI12: 1040dca009e7SXiaojie Yuan adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 1041dca009e7SXiaojie Yuan AMD_CG_SUPPORT_GFX_MGLS | 1042dca009e7SXiaojie Yuan AMD_CG_SUPPORT_GFX_CGCG | 1043dca009e7SXiaojie Yuan AMD_CG_SUPPORT_GFX_CP_LS | 10445211c37aSXiaojie Yuan AMD_CG_SUPPORT_GFX_RLC_LS | 1045fbe0bc57SXiaojie Yuan AMD_CG_SUPPORT_IH_CG | 10465211c37aSXiaojie Yuan AMD_CG_SUPPORT_HDP_MGCG | 1047358ab97fSXiaojie Yuan AMD_CG_SUPPORT_HDP_LS | 1048358ab97fSXiaojie Yuan AMD_CG_SUPPORT_SDMA_MGCG | 10498b797b3dSXiaojie Yuan AMD_CG_SUPPORT_SDMA_LS | 10508b797b3dSXiaojie Yuan AMD_CG_SUPPORT_MC_MGCG | 1051ca51678dSXiaojie Yuan AMD_CG_SUPPORT_MC_LS | 1052ca51678dSXiaojie Yuan AMD_CG_SUPPORT_ATHUB_MGCG | 105365872e59SXiaojie Yuan AMD_CG_SUPPORT_ATHUB_LS | 1054099d66e4SLeo Liu AMD_CG_SUPPORT_VCN_MGCG | 1055099d66e4SLeo Liu AMD_CG_SUPPORT_JPEG_MGCG; 1056c1653ea0SXiaojie Yuan adev->pg_flags = AMD_PG_SUPPORT_VCN | 10575ef3b8acSXiaojie Yuan AMD_PG_SUPPORT_VCN_DPG | 1058099d66e4SLeo Liu AMD_PG_SUPPORT_JPEG | 10591b0443b1SLikun Gao AMD_PG_SUPPORT_ATHUB; 1060df5e984cSTiecheng Zhou /* guest vm gets 0xffffffff when reading RCC_DEV0_EPF0_STRAP0, 1061df5e984cSTiecheng Zhou * as a consequence, the rev_id and external_rev_id are wrong. 1062df5e984cSTiecheng Zhou * workaround it by hardcoding rev_id to 0 (default value). 1063df5e984cSTiecheng Zhou */ 1064df5e984cSTiecheng Zhou if (amdgpu_sriov_vf(adev)) 1065df5e984cSTiecheng Zhou adev->rev_id = 0; 106674b5e509SXiaojie Yuan adev->external_rev_id = adev->rev_id + 0xa; 106774b5e509SXiaojie Yuan break; 1068117910edSLikun Gao case CHIP_SIENNA_CICHLID: 106900194defSLikun Gao adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 107000194defSLikun Gao AMD_CG_SUPPORT_GFX_CGCG | 10711d712be9SKenneth Feng AMD_CG_SUPPORT_GFX_CGLS | 107200194defSLikun Gao AMD_CG_SUPPORT_GFX_3D_CGCG | 107398f8ea29SLikun Gao AMD_CG_SUPPORT_MC_MGCG | 107400194defSLikun Gao AMD_CG_SUPPORT_VCN_MGCG | 1075ca36461fSKenneth Feng AMD_CG_SUPPORT_JPEG_MGCG | 1076ca36461fSKenneth Feng AMD_CG_SUPPORT_HDP_MGCG | 10773a32c25aSKenneth Feng AMD_CG_SUPPORT_HDP_LS | 1078bcc8367fSKenneth Feng AMD_CG_SUPPORT_IH_CG | 1079bcc8367fSKenneth Feng AMD_CG_SUPPORT_MC_LS; 1080b467c4f5SLeo Liu adev->pg_flags = AMD_PG_SUPPORT_VCN | 1081d00b0fa9SBoyuan Zhang AMD_PG_SUPPORT_VCN_DPG | 1082b794616dSKenneth Feng AMD_PG_SUPPORT_JPEG | 10831b0443b1SLikun Gao AMD_PG_SUPPORT_ATHUB | 10841b0443b1SLikun Gao AMD_PG_SUPPORT_MMHUB; 1085c45fbe1bSJack Zhang if (amdgpu_sriov_vf(adev)) { 1086c45fbe1bSJack Zhang /* hypervisor control CG and PG enablement */ 1087c45fbe1bSJack Zhang adev->cg_flags = 0; 1088c45fbe1bSJack Zhang adev->pg_flags = 0; 1089c45fbe1bSJack Zhang } 1090117910edSLikun Gao adev->external_rev_id = adev->rev_id + 0x28; 1091117910edSLikun Gao break; 1092543aa259SJiansong Chen case CHIP_NAVY_FLOUNDER: 109340582e67SJiansong Chen adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 109440582e67SJiansong Chen AMD_CG_SUPPORT_GFX_CGCG | 10951d712be9SKenneth Feng AMD_CG_SUPPORT_GFX_CGLS | 109640582e67SJiansong Chen AMD_CG_SUPPORT_GFX_3D_CGCG | 109740582e67SJiansong Chen AMD_CG_SUPPORT_VCN_MGCG | 109892c73756SJiansong Chen AMD_CG_SUPPORT_JPEG_MGCG | 109992c73756SJiansong Chen AMD_CG_SUPPORT_MC_MGCG | 11004759f887SJiansong Chen AMD_CG_SUPPORT_MC_LS | 11014759f887SJiansong Chen AMD_CG_SUPPORT_HDP_MGCG | 110285e7151bSJiansong Chen AMD_CG_SUPPORT_HDP_LS | 110385e7151bSJiansong Chen AMD_CG_SUPPORT_IH_CG; 1104c6e9dd0eSBoyuan Zhang adev->pg_flags = AMD_PG_SUPPORT_VCN | 110500740df9SBoyuan Zhang AMD_PG_SUPPORT_VCN_DPG | 110647fc894aSJiansong Chen AMD_PG_SUPPORT_JPEG | 110747fc894aSJiansong Chen AMD_PG_SUPPORT_ATHUB | 110847fc894aSJiansong Chen AMD_PG_SUPPORT_MMHUB; 1109543aa259SJiansong Chen adev->external_rev_id = adev->rev_id + 0x32; 1110543aa259SJiansong Chen break; 1111543aa259SJiansong Chen 1112026570e6SHuang Rui case CHIP_VANGOGH: 1113c345c89bSHuang Rui adev->apu_flags |= AMD_APU_IS_VANGOGH; 111451a7e938SJinzhou.Su adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 111551a7e938SJinzhou.Su AMD_CG_SUPPORT_GFX_MGLS | 111651a7e938SJinzhou.Su AMD_CG_SUPPORT_GFX_CP_LS | 111751a7e938SJinzhou.Su AMD_CG_SUPPORT_GFX_RLC_LS | 111851a7e938SJinzhou.Su AMD_CG_SUPPORT_GFX_CGCG | 1119ac0dc4c5SHuang Rui AMD_CG_SUPPORT_GFX_CGLS | 1120ac0dc4c5SHuang Rui AMD_CG_SUPPORT_GFX_3D_CGCG | 112107f9c22fSBoyuan Zhang AMD_CG_SUPPORT_GFX_3D_CGLS | 11220ebce667SJinzhou.Su AMD_CG_SUPPORT_MC_MGCG | 11230ebce667SJinzhou.Su AMD_CG_SUPPORT_MC_LS | 1124a3964ec4SJinzhou.Su AMD_CG_SUPPORT_GFX_FGCG | 112507f9c22fSBoyuan Zhang AMD_CG_SUPPORT_VCN_MGCG | 1126ef9bcfdeSJinzhou Su AMD_CG_SUPPORT_SDMA_MGCG | 1127ec0f72cbSJinzhou Su AMD_CG_SUPPORT_SDMA_LS | 112807f9c22fSBoyuan Zhang AMD_CG_SUPPORT_JPEG_MGCG; 112907f9c22fSBoyuan Zhang adev->pg_flags = AMD_PG_SUPPORT_GFX_PG | 113007f9c22fSBoyuan Zhang AMD_PG_SUPPORT_VCN | 113107f9c22fSBoyuan Zhang AMD_PG_SUPPORT_VCN_DPG | 113207f9c22fSBoyuan Zhang AMD_PG_SUPPORT_JPEG; 1133c345c89bSHuang Rui if (adev->apu_flags & AMD_APU_IS_VANGOGH) 1134026570e6SHuang Rui adev->external_rev_id = adev->rev_id + 0x01; 1135026570e6SHuang Rui break; 1136550c58e0STao Zhou case CHIP_DIMGREY_CAVEFISH: 1137583e5a5eSTao Zhou adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 1138583e5a5eSTao Zhou AMD_CG_SUPPORT_GFX_CGCG | 11391d712be9SKenneth Feng AMD_CG_SUPPORT_GFX_CGLS | 1140583e5a5eSTao Zhou AMD_CG_SUPPORT_GFX_3D_CGCG | 1141583e5a5eSTao Zhou AMD_CG_SUPPORT_VCN_MGCG | 1142135333a0STao Zhou AMD_CG_SUPPORT_JPEG_MGCG | 1143135333a0STao Zhou AMD_CG_SUPPORT_MC_MGCG | 11442c70c332STao Zhou AMD_CG_SUPPORT_MC_LS | 11452c70c332STao Zhou AMD_CG_SUPPORT_HDP_MGCG | 11468e3bfb99STao Zhou AMD_CG_SUPPORT_HDP_LS | 11478e3bfb99STao Zhou AMD_CG_SUPPORT_IH_CG; 1148d5bc1579SJames Zhu adev->pg_flags = AMD_PG_SUPPORT_VCN | 1149cc6161aaSJames Zhu AMD_PG_SUPPORT_VCN_DPG | 115073da8e86STao Zhou AMD_PG_SUPPORT_JPEG | 115173da8e86STao Zhou AMD_PG_SUPPORT_ATHUB | 115273da8e86STao Zhou AMD_PG_SUPPORT_MMHUB; 1153550c58e0STao Zhou adev->external_rev_id = adev->rev_id + 0x3c; 1154550c58e0STao Zhou break; 1155c6b6a421SHawking Zhang default: 1156c6b6a421SHawking Zhang /* FIXME: not supported yet */ 1157c6b6a421SHawking Zhang return -EINVAL; 1158c6b6a421SHawking Zhang } 1159c6b6a421SHawking Zhang 11607bd939d0SLikun GAO if (adev->harvest_ip_mask & AMD_HARVEST_IP_VCN_MASK) 11617bd939d0SLikun GAO adev->pg_flags &= ~(AMD_PG_SUPPORT_VCN | 11627bd939d0SLikun GAO AMD_PG_SUPPORT_VCN_DPG | 11637bd939d0SLikun GAO AMD_PG_SUPPORT_JPEG); 11647bd939d0SLikun GAO 1165b05b6903SJiange Zhao if (amdgpu_sriov_vf(adev)) { 1166b05b6903SJiange Zhao amdgpu_virt_init_setting(adev); 1167b05b6903SJiange Zhao xgpu_nv_mailbox_set_irq_funcs(adev); 1168b05b6903SJiange Zhao } 1169b05b6903SJiange Zhao 1170c6b6a421SHawking Zhang return 0; 1171c6b6a421SHawking Zhang } 1172c6b6a421SHawking Zhang 1173c6b6a421SHawking Zhang static int nv_common_late_init(void *handle) 1174c6b6a421SHawking Zhang { 1175b05b6903SJiange Zhao struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1176b05b6903SJiange Zhao 1177b05b6903SJiange Zhao if (amdgpu_sriov_vf(adev)) 1178b05b6903SJiange Zhao xgpu_nv_mailbox_get_irq(adev); 1179b05b6903SJiange Zhao 1180c6b6a421SHawking Zhang return 0; 1181c6b6a421SHawking Zhang } 1182c6b6a421SHawking Zhang 1183c6b6a421SHawking Zhang static int nv_common_sw_init(void *handle) 1184c6b6a421SHawking Zhang { 1185b05b6903SJiange Zhao struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1186b05b6903SJiange Zhao 1187b05b6903SJiange Zhao if (amdgpu_sriov_vf(adev)) 1188b05b6903SJiange Zhao xgpu_nv_mailbox_add_irq_id(adev); 1189b05b6903SJiange Zhao 1190c6b6a421SHawking Zhang return 0; 1191c6b6a421SHawking Zhang } 1192c6b6a421SHawking Zhang 1193c6b6a421SHawking Zhang static int nv_common_sw_fini(void *handle) 1194c6b6a421SHawking Zhang { 1195c6b6a421SHawking Zhang return 0; 1196c6b6a421SHawking Zhang } 1197c6b6a421SHawking Zhang 1198c6b6a421SHawking Zhang static int nv_common_hw_init(void *handle) 1199c6b6a421SHawking Zhang { 1200c6b6a421SHawking Zhang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1201c6b6a421SHawking Zhang 1202c6b6a421SHawking Zhang /* enable pcie gen2/3 link */ 1203c6b6a421SHawking Zhang nv_pcie_gen3_enable(adev); 1204c6b6a421SHawking Zhang /* enable aspm */ 1205c6b6a421SHawking Zhang nv_program_aspm(adev); 1206c6b6a421SHawking Zhang /* setup nbio registers */ 1207bebc0762SHawking Zhang adev->nbio.funcs->init_registers(adev); 1208923c087aSYong Zhao /* remap HDP registers to a hole in mmio space, 1209923c087aSYong Zhao * for the purpose of expose those registers 1210923c087aSYong Zhao * to process space 1211923c087aSYong Zhao */ 1212923c087aSYong Zhao if (adev->nbio.funcs->remap_hdp_registers) 1213923c087aSYong Zhao adev->nbio.funcs->remap_hdp_registers(adev); 1214c6b6a421SHawking Zhang /* enable the doorbell aperture */ 1215c6b6a421SHawking Zhang nv_enable_doorbell_aperture(adev, true); 1216c6b6a421SHawking Zhang 1217c6b6a421SHawking Zhang return 0; 1218c6b6a421SHawking Zhang } 1219c6b6a421SHawking Zhang 1220c6b6a421SHawking Zhang static int nv_common_hw_fini(void *handle) 1221c6b6a421SHawking Zhang { 1222c6b6a421SHawking Zhang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1223c6b6a421SHawking Zhang 1224c6b6a421SHawking Zhang /* disable the doorbell aperture */ 1225c6b6a421SHawking Zhang nv_enable_doorbell_aperture(adev, false); 1226c6b6a421SHawking Zhang 1227c6b6a421SHawking Zhang return 0; 1228c6b6a421SHawking Zhang } 1229c6b6a421SHawking Zhang 1230c6b6a421SHawking Zhang static int nv_common_suspend(void *handle) 1231c6b6a421SHawking Zhang { 1232c6b6a421SHawking Zhang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1233c6b6a421SHawking Zhang 1234c6b6a421SHawking Zhang return nv_common_hw_fini(adev); 1235c6b6a421SHawking Zhang } 1236c6b6a421SHawking Zhang 1237c6b6a421SHawking Zhang static int nv_common_resume(void *handle) 1238c6b6a421SHawking Zhang { 1239c6b6a421SHawking Zhang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1240c6b6a421SHawking Zhang 1241c6b6a421SHawking Zhang return nv_common_hw_init(adev); 1242c6b6a421SHawking Zhang } 1243c6b6a421SHawking Zhang 1244c6b6a421SHawking Zhang static bool nv_common_is_idle(void *handle) 1245c6b6a421SHawking Zhang { 1246c6b6a421SHawking Zhang return true; 1247c6b6a421SHawking Zhang } 1248c6b6a421SHawking Zhang 1249c6b6a421SHawking Zhang static int nv_common_wait_for_idle(void *handle) 1250c6b6a421SHawking Zhang { 1251c6b6a421SHawking Zhang return 0; 1252c6b6a421SHawking Zhang } 1253c6b6a421SHawking Zhang 1254c6b6a421SHawking Zhang static int nv_common_soft_reset(void *handle) 1255c6b6a421SHawking Zhang { 1256c6b6a421SHawking Zhang return 0; 1257c6b6a421SHawking Zhang } 1258c6b6a421SHawking Zhang 1259c6b6a421SHawking Zhang static int nv_common_set_clockgating_state(void *handle, 1260c6b6a421SHawking Zhang enum amd_clockgating_state state) 1261c6b6a421SHawking Zhang { 1262c6b6a421SHawking Zhang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1263c6b6a421SHawking Zhang 1264c6b6a421SHawking Zhang if (amdgpu_sriov_vf(adev)) 1265c6b6a421SHawking Zhang return 0; 1266c6b6a421SHawking Zhang 1267c6b6a421SHawking Zhang switch (adev->asic_type) { 1268c6b6a421SHawking Zhang case CHIP_NAVI10: 12695e71e011SXiaojie Yuan case CHIP_NAVI14: 12707e17e58bSXiaojie Yuan case CHIP_NAVI12: 1271117910edSLikun Gao case CHIP_SIENNA_CICHLID: 1272543aa259SJiansong Chen case CHIP_NAVY_FLOUNDER: 1273550c58e0STao Zhou case CHIP_DIMGREY_CAVEFISH: 1274bebc0762SHawking Zhang adev->nbio.funcs->update_medium_grain_clock_gating(adev, 1275a9d4fe2fSNirmoy Das state == AMD_CG_STATE_GATE); 1276bebc0762SHawking Zhang adev->nbio.funcs->update_medium_grain_light_sleep(adev, 1277a9d4fe2fSNirmoy Das state == AMD_CG_STATE_GATE); 1278bf087285SLikun Gao adev->hdp.funcs->update_clock_gating(adev, 1279a9d4fe2fSNirmoy Das state == AMD_CG_STATE_GATE); 12801001f2a1SLikun Gao adev->smuio.funcs->update_rom_clock_gating(adev, 12811001f2a1SLikun Gao state == AMD_CG_STATE_GATE); 1282c6b6a421SHawking Zhang break; 1283c6b6a421SHawking Zhang default: 1284c6b6a421SHawking Zhang break; 1285c6b6a421SHawking Zhang } 1286c6b6a421SHawking Zhang return 0; 1287c6b6a421SHawking Zhang } 1288c6b6a421SHawking Zhang 1289c6b6a421SHawking Zhang static int nv_common_set_powergating_state(void *handle, 1290c6b6a421SHawking Zhang enum amd_powergating_state state) 1291c6b6a421SHawking Zhang { 1292c6b6a421SHawking Zhang /* TODO */ 1293c6b6a421SHawking Zhang return 0; 1294c6b6a421SHawking Zhang } 1295c6b6a421SHawking Zhang 1296c6b6a421SHawking Zhang static void nv_common_get_clockgating_state(void *handle, u32 *flags) 1297c6b6a421SHawking Zhang { 1298c6b6a421SHawking Zhang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1299c6b6a421SHawking Zhang 1300c6b6a421SHawking Zhang if (amdgpu_sriov_vf(adev)) 1301c6b6a421SHawking Zhang *flags = 0; 1302c6b6a421SHawking Zhang 1303bebc0762SHawking Zhang adev->nbio.funcs->get_clockgating_state(adev, flags); 1304c6b6a421SHawking Zhang 1305bf087285SLikun Gao adev->hdp.funcs->get_clock_gating_state(adev, flags); 1306c6b6a421SHawking Zhang 13071001f2a1SLikun Gao adev->smuio.funcs->get_clock_gating_state(adev, flags); 13081001f2a1SLikun Gao 1309c6b6a421SHawking Zhang return; 1310c6b6a421SHawking Zhang } 1311c6b6a421SHawking Zhang 1312c6b6a421SHawking Zhang static const struct amd_ip_funcs nv_common_ip_funcs = { 1313c6b6a421SHawking Zhang .name = "nv_common", 1314c6b6a421SHawking Zhang .early_init = nv_common_early_init, 1315c6b6a421SHawking Zhang .late_init = nv_common_late_init, 1316c6b6a421SHawking Zhang .sw_init = nv_common_sw_init, 1317c6b6a421SHawking Zhang .sw_fini = nv_common_sw_fini, 1318c6b6a421SHawking Zhang .hw_init = nv_common_hw_init, 1319c6b6a421SHawking Zhang .hw_fini = nv_common_hw_fini, 1320c6b6a421SHawking Zhang .suspend = nv_common_suspend, 1321c6b6a421SHawking Zhang .resume = nv_common_resume, 1322c6b6a421SHawking Zhang .is_idle = nv_common_is_idle, 1323c6b6a421SHawking Zhang .wait_for_idle = nv_common_wait_for_idle, 1324c6b6a421SHawking Zhang .soft_reset = nv_common_soft_reset, 1325c6b6a421SHawking Zhang .set_clockgating_state = nv_common_set_clockgating_state, 1326c6b6a421SHawking Zhang .set_powergating_state = nv_common_set_powergating_state, 1327c6b6a421SHawking Zhang .get_clockgating_state = nv_common_get_clockgating_state, 1328c6b6a421SHawking Zhang }; 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