1c6b6a421SHawking Zhang /* 2c6b6a421SHawking Zhang * Copyright 2019 Advanced Micro Devices, Inc. 3c6b6a421SHawking Zhang * 4c6b6a421SHawking Zhang * Permission is hereby granted, free of charge, to any person obtaining a 5c6b6a421SHawking Zhang * copy of this software and associated documentation files (the "Software"), 6c6b6a421SHawking Zhang * to deal in the Software without restriction, including without limitation 7c6b6a421SHawking Zhang * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8c6b6a421SHawking Zhang * and/or sell copies of the Software, and to permit persons to whom the 9c6b6a421SHawking Zhang * Software is furnished to do so, subject to the following conditions: 10c6b6a421SHawking Zhang * 11c6b6a421SHawking Zhang * The above copyright notice and this permission notice shall be included in 12c6b6a421SHawking Zhang * all copies or substantial portions of the Software. 13c6b6a421SHawking Zhang * 14c6b6a421SHawking Zhang * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15c6b6a421SHawking Zhang * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16c6b6a421SHawking Zhang * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17c6b6a421SHawking Zhang * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18c6b6a421SHawking Zhang * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19c6b6a421SHawking Zhang * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20c6b6a421SHawking Zhang * OTHER DEALINGS IN THE SOFTWARE. 21c6b6a421SHawking Zhang * 22c6b6a421SHawking Zhang */ 23c6b6a421SHawking Zhang #include <linux/firmware.h> 24c6b6a421SHawking Zhang #include <linux/slab.h> 25c6b6a421SHawking Zhang #include <linux/module.h> 26e9eea902SAlex Deucher #include <linux/pci.h> 27e9eea902SAlex Deucher 28c6b6a421SHawking Zhang #include "amdgpu.h" 29c6b6a421SHawking Zhang #include "amdgpu_atombios.h" 30c6b6a421SHawking Zhang #include "amdgpu_ih.h" 31c6b6a421SHawking Zhang #include "amdgpu_uvd.h" 32c6b6a421SHawking Zhang #include "amdgpu_vce.h" 33c6b6a421SHawking Zhang #include "amdgpu_ucode.h" 34c6b6a421SHawking Zhang #include "amdgpu_psp.h" 35767acabdSKevin Wang #include "amdgpu_smu.h" 36c6b6a421SHawking Zhang #include "atom.h" 37c6b6a421SHawking Zhang #include "amd_pcie.h" 38c6b6a421SHawking Zhang 39c6b6a421SHawking Zhang #include "gc/gc_10_1_0_offset.h" 40c6b6a421SHawking Zhang #include "gc/gc_10_1_0_sh_mask.h" 41c6b6a421SHawking Zhang #include "hdp/hdp_5_0_0_offset.h" 42c6b6a421SHawking Zhang #include "hdp/hdp_5_0_0_sh_mask.h" 4329bc37b4SAlex Deucher #include "smuio/smuio_11_0_0_offset.h" 443967ae6dSAlex Deucher #include "mp/mp_11_0_offset.h" 45c6b6a421SHawking Zhang 46c6b6a421SHawking Zhang #include "soc15.h" 47c6b6a421SHawking Zhang #include "soc15_common.h" 48c6b6a421SHawking Zhang #include "gmc_v10_0.h" 49c6b6a421SHawking Zhang #include "gfxhub_v2_0.h" 50c6b6a421SHawking Zhang #include "mmhub_v2_0.h" 51bebc0762SHawking Zhang #include "nbio_v2_3.h" 52c6b6a421SHawking Zhang #include "nv.h" 53c6b6a421SHawking Zhang #include "navi10_ih.h" 54c6b6a421SHawking Zhang #include "gfx_v10_0.h" 55c6b6a421SHawking Zhang #include "sdma_v5_0.h" 56c6b6a421SHawking Zhang #include "vcn_v2_0.h" 575be45a26SLeo Liu #include "jpeg_v2_0.h" 58c6b6a421SHawking Zhang #include "dce_virtual.h" 59c6b6a421SHawking Zhang #include "mes_v10_1.h" 60b05b6903SJiange Zhao #include "mxgpu_nv.h" 61c6b6a421SHawking Zhang 62c6b6a421SHawking Zhang static const struct amd_ip_funcs nv_common_ip_funcs; 63c6b6a421SHawking Zhang 64c6b6a421SHawking Zhang /* 65c6b6a421SHawking Zhang * Indirect registers accessor 66c6b6a421SHawking Zhang */ 67c6b6a421SHawking Zhang static u32 nv_pcie_rreg(struct amdgpu_device *adev, u32 reg) 68c6b6a421SHawking Zhang { 69c6b6a421SHawking Zhang unsigned long flags, address, data; 70c6b6a421SHawking Zhang u32 r; 71bebc0762SHawking Zhang address = adev->nbio.funcs->get_pcie_index_offset(adev); 72bebc0762SHawking Zhang data = adev->nbio.funcs->get_pcie_data_offset(adev); 73c6b6a421SHawking Zhang 74c6b6a421SHawking Zhang spin_lock_irqsave(&adev->pcie_idx_lock, flags); 75c6b6a421SHawking Zhang WREG32(address, reg); 76c6b6a421SHawking Zhang (void)RREG32(address); 77c6b6a421SHawking Zhang r = RREG32(data); 78c6b6a421SHawking Zhang spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); 79c6b6a421SHawking Zhang return r; 80c6b6a421SHawking Zhang } 81c6b6a421SHawking Zhang 82c6b6a421SHawking Zhang static void nv_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v) 83c6b6a421SHawking Zhang { 84c6b6a421SHawking Zhang unsigned long flags, address, data; 85c6b6a421SHawking Zhang 86bebc0762SHawking Zhang address = adev->nbio.funcs->get_pcie_index_offset(adev); 87bebc0762SHawking Zhang data = adev->nbio.funcs->get_pcie_data_offset(adev); 88c6b6a421SHawking Zhang 89c6b6a421SHawking Zhang spin_lock_irqsave(&adev->pcie_idx_lock, flags); 90c6b6a421SHawking Zhang WREG32(address, reg); 91c6b6a421SHawking Zhang (void)RREG32(address); 92c6b6a421SHawking Zhang WREG32(data, v); 93c6b6a421SHawking Zhang (void)RREG32(data); 94c6b6a421SHawking Zhang spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); 95c6b6a421SHawking Zhang } 96c6b6a421SHawking Zhang 97c6b6a421SHawking Zhang static u32 nv_didt_rreg(struct amdgpu_device *adev, u32 reg) 98c6b6a421SHawking Zhang { 99c6b6a421SHawking Zhang unsigned long flags, address, data; 100c6b6a421SHawking Zhang u32 r; 101c6b6a421SHawking Zhang 102c6b6a421SHawking Zhang address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX); 103c6b6a421SHawking Zhang data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA); 104c6b6a421SHawking Zhang 105c6b6a421SHawking Zhang spin_lock_irqsave(&adev->didt_idx_lock, flags); 106c6b6a421SHawking Zhang WREG32(address, (reg)); 107c6b6a421SHawking Zhang r = RREG32(data); 108c6b6a421SHawking Zhang spin_unlock_irqrestore(&adev->didt_idx_lock, flags); 109c6b6a421SHawking Zhang return r; 110c6b6a421SHawking Zhang } 111c6b6a421SHawking Zhang 112c6b6a421SHawking Zhang static void nv_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v) 113c6b6a421SHawking Zhang { 114c6b6a421SHawking Zhang unsigned long flags, address, data; 115c6b6a421SHawking Zhang 116c6b6a421SHawking Zhang address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX); 117c6b6a421SHawking Zhang data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA); 118c6b6a421SHawking Zhang 119c6b6a421SHawking Zhang spin_lock_irqsave(&adev->didt_idx_lock, flags); 120c6b6a421SHawking Zhang WREG32(address, (reg)); 121c6b6a421SHawking Zhang WREG32(data, (v)); 122c6b6a421SHawking Zhang spin_unlock_irqrestore(&adev->didt_idx_lock, flags); 123c6b6a421SHawking Zhang } 124c6b6a421SHawking Zhang 125c6b6a421SHawking Zhang static u32 nv_get_config_memsize(struct amdgpu_device *adev) 126c6b6a421SHawking Zhang { 127bebc0762SHawking Zhang return adev->nbio.funcs->get_memsize(adev); 128c6b6a421SHawking Zhang } 129c6b6a421SHawking Zhang 130c6b6a421SHawking Zhang static u32 nv_get_xclk(struct amdgpu_device *adev) 131c6b6a421SHawking Zhang { 132462a70d8STao Zhou return adev->clock.spll.reference_freq; 133c6b6a421SHawking Zhang } 134c6b6a421SHawking Zhang 135c6b6a421SHawking Zhang 136c6b6a421SHawking Zhang void nv_grbm_select(struct amdgpu_device *adev, 137c6b6a421SHawking Zhang u32 me, u32 pipe, u32 queue, u32 vmid) 138c6b6a421SHawking Zhang { 139c6b6a421SHawking Zhang u32 grbm_gfx_cntl = 0; 140c6b6a421SHawking Zhang grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, PIPEID, pipe); 141c6b6a421SHawking Zhang grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, MEID, me); 142c6b6a421SHawking Zhang grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, VMID, vmid); 143c6b6a421SHawking Zhang grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, QUEUEID, queue); 144c6b6a421SHawking Zhang 145c6b6a421SHawking Zhang WREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_CNTL), grbm_gfx_cntl); 146c6b6a421SHawking Zhang } 147c6b6a421SHawking Zhang 148c6b6a421SHawking Zhang static void nv_vga_set_state(struct amdgpu_device *adev, bool state) 149c6b6a421SHawking Zhang { 150c6b6a421SHawking Zhang /* todo */ 151c6b6a421SHawking Zhang } 152c6b6a421SHawking Zhang 153c6b6a421SHawking Zhang static bool nv_read_disabled_bios(struct amdgpu_device *adev) 154c6b6a421SHawking Zhang { 155c6b6a421SHawking Zhang /* todo */ 156c6b6a421SHawking Zhang return false; 157c6b6a421SHawking Zhang } 158c6b6a421SHawking Zhang 159c6b6a421SHawking Zhang static bool nv_read_bios_from_rom(struct amdgpu_device *adev, 160c6b6a421SHawking Zhang u8 *bios, u32 length_bytes) 161c6b6a421SHawking Zhang { 16229bc37b4SAlex Deucher u32 *dw_ptr; 16329bc37b4SAlex Deucher u32 i, length_dw; 16429bc37b4SAlex Deucher 16529bc37b4SAlex Deucher if (bios == NULL) 166c6b6a421SHawking Zhang return false; 16729bc37b4SAlex Deucher if (length_bytes == 0) 16829bc37b4SAlex Deucher return false; 16929bc37b4SAlex Deucher /* APU vbios image is part of sbios image */ 17029bc37b4SAlex Deucher if (adev->flags & AMD_IS_APU) 17129bc37b4SAlex Deucher return false; 17229bc37b4SAlex Deucher 17329bc37b4SAlex Deucher dw_ptr = (u32 *)bios; 17429bc37b4SAlex Deucher length_dw = ALIGN(length_bytes, 4) / 4; 17529bc37b4SAlex Deucher 17629bc37b4SAlex Deucher /* set rom index to 0 */ 17729bc37b4SAlex Deucher WREG32(SOC15_REG_OFFSET(SMUIO, 0, mmROM_INDEX), 0); 17829bc37b4SAlex Deucher /* read out the rom data */ 17929bc37b4SAlex Deucher for (i = 0; i < length_dw; i++) 18029bc37b4SAlex Deucher dw_ptr[i] = RREG32(SOC15_REG_OFFSET(SMUIO, 0, mmROM_DATA)); 18129bc37b4SAlex Deucher 18229bc37b4SAlex Deucher return true; 183c6b6a421SHawking Zhang } 184c6b6a421SHawking Zhang 185c6b6a421SHawking Zhang static struct soc15_allowed_register_entry nv_allowed_read_registers[] = { 186c6b6a421SHawking Zhang { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS)}, 187c6b6a421SHawking Zhang { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS2)}, 188c6b6a421SHawking Zhang { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE0)}, 189c6b6a421SHawking Zhang { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE1)}, 190c6b6a421SHawking Zhang { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE2)}, 191c6b6a421SHawking Zhang { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE3)}, 192c6b6a421SHawking Zhang { SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_STATUS_REG)}, 193c6b6a421SHawking Zhang { SOC15_REG_ENTRY(SDMA1, 0, mmSDMA1_STATUS_REG)}, 194c6b6a421SHawking Zhang { SOC15_REG_ENTRY(GC, 0, mmCP_STAT)}, 195c6b6a421SHawking Zhang { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT1)}, 196c6b6a421SHawking Zhang { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT2)}, 197c6b6a421SHawking Zhang { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT3)}, 198c6b6a421SHawking Zhang { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_BUSY_STAT)}, 199c6b6a421SHawking Zhang { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STALLED_STAT1)}, 200c6b6a421SHawking Zhang { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STATUS)}, 201664fe85aSMarek Olšák { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_BUSY_STAT)}, 202c6b6a421SHawking Zhang { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STALLED_STAT1)}, 203c6b6a421SHawking Zhang { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STATUS)}, 204c6b6a421SHawking Zhang { SOC15_REG_ENTRY(GC, 0, mmGB_ADDR_CONFIG)}, 205c6b6a421SHawking Zhang }; 206c6b6a421SHawking Zhang 207c6b6a421SHawking Zhang static uint32_t nv_read_indexed_register(struct amdgpu_device *adev, u32 se_num, 208c6b6a421SHawking Zhang u32 sh_num, u32 reg_offset) 209c6b6a421SHawking Zhang { 210c6b6a421SHawking Zhang uint32_t val; 211c6b6a421SHawking Zhang 212c6b6a421SHawking Zhang mutex_lock(&adev->grbm_idx_mutex); 213c6b6a421SHawking Zhang if (se_num != 0xffffffff || sh_num != 0xffffffff) 214c6b6a421SHawking Zhang amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff); 215c6b6a421SHawking Zhang 216c6b6a421SHawking Zhang val = RREG32(reg_offset); 217c6b6a421SHawking Zhang 218c6b6a421SHawking Zhang if (se_num != 0xffffffff || sh_num != 0xffffffff) 219c6b6a421SHawking Zhang amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 220c6b6a421SHawking Zhang mutex_unlock(&adev->grbm_idx_mutex); 221c6b6a421SHawking Zhang return val; 222c6b6a421SHawking Zhang } 223c6b6a421SHawking Zhang 224c6b6a421SHawking Zhang static uint32_t nv_get_register_value(struct amdgpu_device *adev, 225c6b6a421SHawking Zhang bool indexed, u32 se_num, 226c6b6a421SHawking Zhang u32 sh_num, u32 reg_offset) 227c6b6a421SHawking Zhang { 228c6b6a421SHawking Zhang if (indexed) { 229c6b6a421SHawking Zhang return nv_read_indexed_register(adev, se_num, sh_num, reg_offset); 230c6b6a421SHawking Zhang } else { 231c6b6a421SHawking Zhang if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG)) 232c6b6a421SHawking Zhang return adev->gfx.config.gb_addr_config; 233c6b6a421SHawking Zhang return RREG32(reg_offset); 234c6b6a421SHawking Zhang } 235c6b6a421SHawking Zhang } 236c6b6a421SHawking Zhang 237c6b6a421SHawking Zhang static int nv_read_register(struct amdgpu_device *adev, u32 se_num, 238c6b6a421SHawking Zhang u32 sh_num, u32 reg_offset, u32 *value) 239c6b6a421SHawking Zhang { 240c6b6a421SHawking Zhang uint32_t i; 241c6b6a421SHawking Zhang struct soc15_allowed_register_entry *en; 242c6b6a421SHawking Zhang 243c6b6a421SHawking Zhang *value = 0; 244c6b6a421SHawking Zhang for (i = 0; i < ARRAY_SIZE(nv_allowed_read_registers); i++) { 245c6b6a421SHawking Zhang en = &nv_allowed_read_registers[i]; 246c6b6a421SHawking Zhang if (reg_offset != 247c6b6a421SHawking Zhang (adev->reg_offset[en->hwip][en->inst][en->seg] + en->reg_offset)) 248c6b6a421SHawking Zhang continue; 249c6b6a421SHawking Zhang 250c6b6a421SHawking Zhang *value = nv_get_register_value(adev, 251c6b6a421SHawking Zhang nv_allowed_read_registers[i].grbm_indexed, 252c6b6a421SHawking Zhang se_num, sh_num, reg_offset); 253c6b6a421SHawking Zhang return 0; 254c6b6a421SHawking Zhang } 255c6b6a421SHawking Zhang return -EINVAL; 256c6b6a421SHawking Zhang } 257c6b6a421SHawking Zhang 2583e2bb60aSKevin Wang static int nv_asic_mode1_reset(struct amdgpu_device *adev) 2593e2bb60aSKevin Wang { 2603e2bb60aSKevin Wang u32 i; 2613e2bb60aSKevin Wang int ret = 0; 2623e2bb60aSKevin Wang 2633e2bb60aSKevin Wang amdgpu_atombios_scratch_regs_engine_hung(adev, true); 2643e2bb60aSKevin Wang 2653e2bb60aSKevin Wang dev_info(adev->dev, "GPU mode1 reset\n"); 2663e2bb60aSKevin Wang 2673e2bb60aSKevin Wang /* disable BM */ 2683e2bb60aSKevin Wang pci_clear_master(adev->pdev); 2693e2bb60aSKevin Wang 2703e2bb60aSKevin Wang pci_save_state(adev->pdev); 2713e2bb60aSKevin Wang 2723e2bb60aSKevin Wang ret = psp_gpu_reset(adev); 2733e2bb60aSKevin Wang if (ret) 2743e2bb60aSKevin Wang dev_err(adev->dev, "GPU mode1 reset failed\n"); 2753e2bb60aSKevin Wang 2763e2bb60aSKevin Wang pci_restore_state(adev->pdev); 2773e2bb60aSKevin Wang 2783e2bb60aSKevin Wang /* wait for asic to come out of reset */ 2793e2bb60aSKevin Wang for (i = 0; i < adev->usec_timeout; i++) { 280bebc0762SHawking Zhang u32 memsize = adev->nbio.funcs->get_memsize(adev); 2813e2bb60aSKevin Wang 2823e2bb60aSKevin Wang if (memsize != 0xffffffff) 2833e2bb60aSKevin Wang break; 2843e2bb60aSKevin Wang udelay(1); 2853e2bb60aSKevin Wang } 2863e2bb60aSKevin Wang 2873e2bb60aSKevin Wang amdgpu_atombios_scratch_regs_engine_hung(adev, false); 2883e2bb60aSKevin Wang 2893e2bb60aSKevin Wang return ret; 2903e2bb60aSKevin Wang } 2912ddc6c3eSAlex Deucher 292ac742616SAlex Deucher static bool nv_asic_supports_baco(struct amdgpu_device *adev) 293ac742616SAlex Deucher { 294ac742616SAlex Deucher struct smu_context *smu = &adev->smu; 295ac742616SAlex Deucher 296ac742616SAlex Deucher if (smu_baco_is_support(smu)) 297ac742616SAlex Deucher return true; 298ac742616SAlex Deucher else 299ac742616SAlex Deucher return false; 300ac742616SAlex Deucher } 301ac742616SAlex Deucher 3022ddc6c3eSAlex Deucher static enum amd_reset_method 3032ddc6c3eSAlex Deucher nv_asic_reset_method(struct amdgpu_device *adev) 3042ddc6c3eSAlex Deucher { 3052ddc6c3eSAlex Deucher struct smu_context *smu = &adev->smu; 3062ddc6c3eSAlex Deucher 307b4def374SJiange Zhao if (!amdgpu_sriov_vf(adev) && smu_baco_is_support(smu)) 3082ddc6c3eSAlex Deucher return AMD_RESET_METHOD_BACO; 3092ddc6c3eSAlex Deucher else 3102ddc6c3eSAlex Deucher return AMD_RESET_METHOD_MODE1; 3112ddc6c3eSAlex Deucher } 3122ddc6c3eSAlex Deucher 313c6b6a421SHawking Zhang static int nv_asic_reset(struct amdgpu_device *adev) 314c6b6a421SHawking Zhang { 315767acabdSKevin Wang int ret = 0; 316767acabdSKevin Wang struct smu_context *smu = &adev->smu; 317c6b6a421SHawking Zhang 318e3526257SMonk Liu if (nv_asic_reset_method(adev) == AMD_RESET_METHOD_BACO) { 31911520f27SAlex Deucher ret = smu_baco_enter(smu); 32011520f27SAlex Deucher if (ret) 32111520f27SAlex Deucher return ret; 32211520f27SAlex Deucher ret = smu_baco_exit(smu); 32311520f27SAlex Deucher if (ret) 32411520f27SAlex Deucher return ret; 325e3526257SMonk Liu } else { 3263e2bb60aSKevin Wang ret = nv_asic_mode1_reset(adev); 327e3526257SMonk Liu } 328767acabdSKevin Wang 329767acabdSKevin Wang return ret; 330c6b6a421SHawking Zhang } 331c6b6a421SHawking Zhang 332c6b6a421SHawking Zhang static int nv_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk) 333c6b6a421SHawking Zhang { 334c6b6a421SHawking Zhang /* todo */ 335c6b6a421SHawking Zhang return 0; 336c6b6a421SHawking Zhang } 337c6b6a421SHawking Zhang 338c6b6a421SHawking Zhang static int nv_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk) 339c6b6a421SHawking Zhang { 340c6b6a421SHawking Zhang /* todo */ 341c6b6a421SHawking Zhang return 0; 342c6b6a421SHawking Zhang } 343c6b6a421SHawking Zhang 344c6b6a421SHawking Zhang static void nv_pcie_gen3_enable(struct amdgpu_device *adev) 345c6b6a421SHawking Zhang { 346c6b6a421SHawking Zhang if (pci_is_root_bus(adev->pdev->bus)) 347c6b6a421SHawking Zhang return; 348c6b6a421SHawking Zhang 349c6b6a421SHawking Zhang if (amdgpu_pcie_gen2 == 0) 350c6b6a421SHawking Zhang return; 351c6b6a421SHawking Zhang 352c6b6a421SHawking Zhang if (!(adev->pm.pcie_gen_mask & (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 | 353c6b6a421SHawking Zhang CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3))) 354c6b6a421SHawking Zhang return; 355c6b6a421SHawking Zhang 356c6b6a421SHawking Zhang /* todo */ 357c6b6a421SHawking Zhang } 358c6b6a421SHawking Zhang 359c6b6a421SHawking Zhang static void nv_program_aspm(struct amdgpu_device *adev) 360c6b6a421SHawking Zhang { 361c6b6a421SHawking Zhang 362c6b6a421SHawking Zhang if (amdgpu_aspm == 0) 363c6b6a421SHawking Zhang return; 364c6b6a421SHawking Zhang 365c6b6a421SHawking Zhang /* todo */ 366c6b6a421SHawking Zhang } 367c6b6a421SHawking Zhang 368c6b6a421SHawking Zhang static void nv_enable_doorbell_aperture(struct amdgpu_device *adev, 369c6b6a421SHawking Zhang bool enable) 370c6b6a421SHawking Zhang { 371bebc0762SHawking Zhang adev->nbio.funcs->enable_doorbell_aperture(adev, enable); 372bebc0762SHawking Zhang adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, enable); 373c6b6a421SHawking Zhang } 374c6b6a421SHawking Zhang 375c6b6a421SHawking Zhang static const struct amdgpu_ip_block_version nv_common_ip_block = 376c6b6a421SHawking Zhang { 377c6b6a421SHawking Zhang .type = AMD_IP_BLOCK_TYPE_COMMON, 378c6b6a421SHawking Zhang .major = 1, 379c6b6a421SHawking Zhang .minor = 0, 380c6b6a421SHawking Zhang .rev = 0, 381c6b6a421SHawking Zhang .funcs = &nv_common_ip_funcs, 382c6b6a421SHawking Zhang }; 383c6b6a421SHawking Zhang 384b5c73856SXiaojie Yuan static int nv_reg_base_init(struct amdgpu_device *adev) 385c6b6a421SHawking Zhang { 386b5c73856SXiaojie Yuan int r; 387b5c73856SXiaojie Yuan 388b5c73856SXiaojie Yuan if (amdgpu_discovery) { 389b5c73856SXiaojie Yuan r = amdgpu_discovery_reg_base_init(adev); 390b5c73856SXiaojie Yuan if (r) { 391b5c73856SXiaojie Yuan DRM_WARN("failed to init reg base from ip discovery table, " 392b5c73856SXiaojie Yuan "fallback to legacy init method\n"); 393b5c73856SXiaojie Yuan goto legacy_init; 394b5c73856SXiaojie Yuan } 395b5c73856SXiaojie Yuan 396b5c73856SXiaojie Yuan return 0; 397b5c73856SXiaojie Yuan } 398b5c73856SXiaojie Yuan 399b5c73856SXiaojie Yuan legacy_init: 400c6b6a421SHawking Zhang switch (adev->asic_type) { 401c6b6a421SHawking Zhang case CHIP_NAVI10: 402c6b6a421SHawking Zhang navi10_reg_base_init(adev); 403c6b6a421SHawking Zhang break; 404a0f6d926SXiaojie Yuan case CHIP_NAVI14: 405a0f6d926SXiaojie Yuan navi14_reg_base_init(adev); 406a0f6d926SXiaojie Yuan break; 40703d0a073SXiaojie Yuan case CHIP_NAVI12: 40803d0a073SXiaojie Yuan navi12_reg_base_init(adev); 40903d0a073SXiaojie Yuan break; 410dccdbf3fSLikun Gao case CHIP_SIENNA_CICHLID: 411dccdbf3fSLikun Gao sienna_cichlid_reg_base_init(adev); 412dccdbf3fSLikun Gao break; 413c6b6a421SHawking Zhang default: 414c6b6a421SHawking Zhang return -EINVAL; 415c6b6a421SHawking Zhang } 416c6b6a421SHawking Zhang 417b5c73856SXiaojie Yuan return 0; 418b5c73856SXiaojie Yuan } 419b5c73856SXiaojie Yuan 420b5c73856SXiaojie Yuan int nv_set_ip_blocks(struct amdgpu_device *adev) 421b5c73856SXiaojie Yuan { 422b5c73856SXiaojie Yuan int r; 423b5c73856SXiaojie Yuan 424122078deSMonk Liu adev->nbio.funcs = &nbio_v2_3_funcs; 425122078deSMonk Liu adev->nbio.hdp_flush_reg = &nbio_v2_3_hdp_flush_reg; 426122078deSMonk Liu 427122078deSMonk Liu if (amdgpu_sriov_vf(adev)) { 428122078deSMonk Liu adev->virt.ops = &xgpu_nv_virt_ops; 429122078deSMonk Liu /* try send GPU_INIT_DATA request to host */ 430122078deSMonk Liu amdgpu_virt_request_init_data(adev); 431122078deSMonk Liu } 432122078deSMonk Liu 433b5c73856SXiaojie Yuan /* Set IP register base before any HW register access */ 434b5c73856SXiaojie Yuan r = nv_reg_base_init(adev); 435b5c73856SXiaojie Yuan if (r) 436b5c73856SXiaojie Yuan return r; 437b5c73856SXiaojie Yuan 438c6b6a421SHawking Zhang switch (adev->asic_type) { 439c6b6a421SHawking Zhang case CHIP_NAVI10: 440d1daf850SAlex Deucher case CHIP_NAVI14: 441c6b6a421SHawking Zhang amdgpu_device_ip_block_add(adev, &nv_common_ip_block); 442c6b6a421SHawking Zhang amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block); 443c6b6a421SHawking Zhang amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block); 444c6b6a421SHawking Zhang amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block); 445c6b6a421SHawking Zhang if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP && 4469530273eSEvan Quan !amdgpu_sriov_vf(adev)) 447c6b6a421SHawking Zhang amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 448c6b6a421SHawking Zhang if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) 449c6b6a421SHawking Zhang amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block); 450f8a7976bSAlex Deucher #if defined(CONFIG_DRM_AMD_DC) 451b4f199c7SHarry Wentland else if (amdgpu_device_has_dc_support(adev)) 452b4f199c7SHarry Wentland amdgpu_device_ip_block_add(adev, &dm_ip_block); 453f8a7976bSAlex Deucher #endif 454c6b6a421SHawking Zhang amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block); 455c6b6a421SHawking Zhang amdgpu_device_ip_block_add(adev, &sdma_v5_0_ip_block); 456c6b6a421SHawking Zhang if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT && 4579530273eSEvan Quan !amdgpu_sriov_vf(adev)) 458c6b6a421SHawking Zhang amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 459c6b6a421SHawking Zhang amdgpu_device_ip_block_add(adev, &vcn_v2_0_ip_block); 4605be45a26SLeo Liu amdgpu_device_ip_block_add(adev, &jpeg_v2_0_ip_block); 461c6b6a421SHawking Zhang if (adev->enable_mes) 462c6b6a421SHawking Zhang amdgpu_device_ip_block_add(adev, &mes_v10_1_ip_block); 463c6b6a421SHawking Zhang break; 46444e9e7c9SXiaojie Yuan case CHIP_NAVI12: 46544e9e7c9SXiaojie Yuan amdgpu_device_ip_block_add(adev, &nv_common_ip_block); 46644e9e7c9SXiaojie Yuan amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block); 46744e9e7c9SXiaojie Yuan amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block); 4686b66ae2eSXiaojie Yuan amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block); 46979bebabbSMonk Liu if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) 4707f47efebSXiaojie Yuan amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 47179902029SXiaojie Yuan if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) 47279902029SXiaojie Yuan amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block); 47320c14ee1SPetr Cvek #if defined(CONFIG_DRM_AMD_DC) 474078655d9SLeo Li else if (amdgpu_device_has_dc_support(adev)) 475078655d9SLeo Li amdgpu_device_ip_block_add(adev, &dm_ip_block); 47620c14ee1SPetr Cvek #endif 47744e9e7c9SXiaojie Yuan amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block); 47844e9e7c9SXiaojie Yuan amdgpu_device_ip_block_add(adev, &sdma_v5_0_ip_block); 4797f47efebSXiaojie Yuan if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT && 4809530273eSEvan Quan !amdgpu_sriov_vf(adev)) 4817f47efebSXiaojie Yuan amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 4821fbed280SBoyuan Zhang amdgpu_device_ip_block_add(adev, &vcn_v2_0_ip_block); 483fe442491SMonk Liu if (!amdgpu_sriov_vf(adev)) 4845be45a26SLeo Liu amdgpu_device_ip_block_add(adev, &jpeg_v2_0_ip_block); 48544e9e7c9SXiaojie Yuan break; 4862e1ba10eSLikun Gao case CHIP_SIENNA_CICHLID: 4872e1ba10eSLikun Gao amdgpu_device_ip_block_add(adev, &nv_common_ip_block); 4882e1ba10eSLikun Gao break; 489c6b6a421SHawking Zhang default: 490c6b6a421SHawking Zhang return -EINVAL; 491c6b6a421SHawking Zhang } 492c6b6a421SHawking Zhang 493c6b6a421SHawking Zhang return 0; 494c6b6a421SHawking Zhang } 495c6b6a421SHawking Zhang 496c6b6a421SHawking Zhang static uint32_t nv_get_rev_id(struct amdgpu_device *adev) 497c6b6a421SHawking Zhang { 498bebc0762SHawking Zhang return adev->nbio.funcs->get_rev_id(adev); 499c6b6a421SHawking Zhang } 500c6b6a421SHawking Zhang 501c6b6a421SHawking Zhang static void nv_flush_hdp(struct amdgpu_device *adev, struct amdgpu_ring *ring) 502c6b6a421SHawking Zhang { 503bebc0762SHawking Zhang adev->nbio.funcs->hdp_flush(adev, ring); 504c6b6a421SHawking Zhang } 505c6b6a421SHawking Zhang 506c6b6a421SHawking Zhang static void nv_invalidate_hdp(struct amdgpu_device *adev, 507c6b6a421SHawking Zhang struct amdgpu_ring *ring) 508c6b6a421SHawking Zhang { 509c6b6a421SHawking Zhang if (!ring || !ring->funcs->emit_wreg) { 510c6b6a421SHawking Zhang WREG32_SOC15_NO_KIQ(NBIO, 0, mmHDP_READ_CACHE_INVALIDATE, 1); 511c6b6a421SHawking Zhang } else { 512c6b6a421SHawking Zhang amdgpu_ring_emit_wreg(ring, SOC15_REG_OFFSET( 513c6b6a421SHawking Zhang HDP, 0, mmHDP_READ_CACHE_INVALIDATE), 1); 514c6b6a421SHawking Zhang } 515c6b6a421SHawking Zhang } 516c6b6a421SHawking Zhang 517c6b6a421SHawking Zhang static bool nv_need_full_reset(struct amdgpu_device *adev) 518c6b6a421SHawking Zhang { 519c6b6a421SHawking Zhang return true; 520c6b6a421SHawking Zhang } 521c6b6a421SHawking Zhang 522c6b6a421SHawking Zhang static bool nv_need_reset_on_init(struct amdgpu_device *adev) 523c6b6a421SHawking Zhang { 524c6b6a421SHawking Zhang u32 sol_reg; 525c6b6a421SHawking Zhang 526c6b6a421SHawking Zhang if (adev->flags & AMD_IS_APU) 527c6b6a421SHawking Zhang return false; 528c6b6a421SHawking Zhang 529c6b6a421SHawking Zhang /* Check sOS sign of life register to confirm sys driver and sOS 530c6b6a421SHawking Zhang * are already been loaded. 531c6b6a421SHawking Zhang */ 532c6b6a421SHawking Zhang sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81); 533c6b6a421SHawking Zhang if (sol_reg) 534c6b6a421SHawking Zhang return true; 5353967ae6dSAlex Deucher 536c6b6a421SHawking Zhang return false; 537c6b6a421SHawking Zhang } 538c6b6a421SHawking Zhang 5392af81531SKevin Wang static uint64_t nv_get_pcie_replay_count(struct amdgpu_device *adev) 5402af81531SKevin Wang { 5412af81531SKevin Wang 5422af81531SKevin Wang /* TODO 5432af81531SKevin Wang * dummy implement for pcie_replay_count sysfs interface 5442af81531SKevin Wang * */ 5452af81531SKevin Wang 5462af81531SKevin Wang return 0; 5472af81531SKevin Wang } 5482af81531SKevin Wang 549c6b6a421SHawking Zhang static void nv_init_doorbell_index(struct amdgpu_device *adev) 550c6b6a421SHawking Zhang { 551c6b6a421SHawking Zhang adev->doorbell_index.kiq = AMDGPU_NAVI10_DOORBELL_KIQ; 552c6b6a421SHawking Zhang adev->doorbell_index.mec_ring0 = AMDGPU_NAVI10_DOORBELL_MEC_RING0; 553c6b6a421SHawking Zhang adev->doorbell_index.mec_ring1 = AMDGPU_NAVI10_DOORBELL_MEC_RING1; 554c6b6a421SHawking Zhang adev->doorbell_index.mec_ring2 = AMDGPU_NAVI10_DOORBELL_MEC_RING2; 555c6b6a421SHawking Zhang adev->doorbell_index.mec_ring3 = AMDGPU_NAVI10_DOORBELL_MEC_RING3; 556c6b6a421SHawking Zhang adev->doorbell_index.mec_ring4 = AMDGPU_NAVI10_DOORBELL_MEC_RING4; 557c6b6a421SHawking Zhang adev->doorbell_index.mec_ring5 = AMDGPU_NAVI10_DOORBELL_MEC_RING5; 558c6b6a421SHawking Zhang adev->doorbell_index.mec_ring6 = AMDGPU_NAVI10_DOORBELL_MEC_RING6; 559c6b6a421SHawking Zhang adev->doorbell_index.mec_ring7 = AMDGPU_NAVI10_DOORBELL_MEC_RING7; 560c6b6a421SHawking Zhang adev->doorbell_index.userqueue_start = AMDGPU_NAVI10_DOORBELL_USERQUEUE_START; 561c6b6a421SHawking Zhang adev->doorbell_index.userqueue_end = AMDGPU_NAVI10_DOORBELL_USERQUEUE_END; 562c6b6a421SHawking Zhang adev->doorbell_index.gfx_ring0 = AMDGPU_NAVI10_DOORBELL_GFX_RING0; 563c6b6a421SHawking Zhang adev->doorbell_index.gfx_ring1 = AMDGPU_NAVI10_DOORBELL_GFX_RING1; 564c6b6a421SHawking Zhang adev->doorbell_index.sdma_engine[0] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE0; 565c6b6a421SHawking Zhang adev->doorbell_index.sdma_engine[1] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE1; 566c6b6a421SHawking Zhang adev->doorbell_index.ih = AMDGPU_NAVI10_DOORBELL_IH; 567c6b6a421SHawking Zhang adev->doorbell_index.vcn.vcn_ring0_1 = AMDGPU_NAVI10_DOORBELL64_VCN0_1; 568c6b6a421SHawking Zhang adev->doorbell_index.vcn.vcn_ring2_3 = AMDGPU_NAVI10_DOORBELL64_VCN2_3; 569c6b6a421SHawking Zhang adev->doorbell_index.vcn.vcn_ring4_5 = AMDGPU_NAVI10_DOORBELL64_VCN4_5; 570c6b6a421SHawking Zhang adev->doorbell_index.vcn.vcn_ring6_7 = AMDGPU_NAVI10_DOORBELL64_VCN6_7; 571c6b6a421SHawking Zhang adev->doorbell_index.first_non_cp = AMDGPU_NAVI10_DOORBELL64_FIRST_NON_CP; 572c6b6a421SHawking Zhang adev->doorbell_index.last_non_cp = AMDGPU_NAVI10_DOORBELL64_LAST_NON_CP; 573c6b6a421SHawking Zhang 574c6b6a421SHawking Zhang adev->doorbell_index.max_assignment = AMDGPU_NAVI10_DOORBELL_MAX_ASSIGNMENT << 1; 575c6b6a421SHawking Zhang adev->doorbell_index.sdma_doorbell_range = 20; 576c6b6a421SHawking Zhang } 577c6b6a421SHawking Zhang 578c6b6a421SHawking Zhang static const struct amdgpu_asic_funcs nv_asic_funcs = 579c6b6a421SHawking Zhang { 580c6b6a421SHawking Zhang .read_disabled_bios = &nv_read_disabled_bios, 581c6b6a421SHawking Zhang .read_bios_from_rom = &nv_read_bios_from_rom, 582c6b6a421SHawking Zhang .read_register = &nv_read_register, 583c6b6a421SHawking Zhang .reset = &nv_asic_reset, 5842ddc6c3eSAlex Deucher .reset_method = &nv_asic_reset_method, 585c6b6a421SHawking Zhang .set_vga_state = &nv_vga_set_state, 586c6b6a421SHawking Zhang .get_xclk = &nv_get_xclk, 587c6b6a421SHawking Zhang .set_uvd_clocks = &nv_set_uvd_clocks, 588c6b6a421SHawking Zhang .set_vce_clocks = &nv_set_vce_clocks, 589c6b6a421SHawking Zhang .get_config_memsize = &nv_get_config_memsize, 590c6b6a421SHawking Zhang .flush_hdp = &nv_flush_hdp, 591c6b6a421SHawking Zhang .invalidate_hdp = &nv_invalidate_hdp, 592c6b6a421SHawking Zhang .init_doorbell_index = &nv_init_doorbell_index, 593c6b6a421SHawking Zhang .need_full_reset = &nv_need_full_reset, 594c6b6a421SHawking Zhang .need_reset_on_init = &nv_need_reset_on_init, 5952af81531SKevin Wang .get_pcie_replay_count = &nv_get_pcie_replay_count, 596ac742616SAlex Deucher .supports_baco = &nv_asic_supports_baco, 597c6b6a421SHawking Zhang }; 598c6b6a421SHawking Zhang 599c6b6a421SHawking Zhang static int nv_common_early_init(void *handle) 600c6b6a421SHawking Zhang { 601923c087aSYong Zhao #define MMIO_REG_HOLE_OFFSET (0x80000 - PAGE_SIZE) 602c6b6a421SHawking Zhang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 603c6b6a421SHawking Zhang 604923c087aSYong Zhao adev->rmmio_remap.reg_offset = MMIO_REG_HOLE_OFFSET; 605923c087aSYong Zhao adev->rmmio_remap.bus_addr = adev->rmmio_base + MMIO_REG_HOLE_OFFSET; 606c6b6a421SHawking Zhang adev->smc_rreg = NULL; 607c6b6a421SHawking Zhang adev->smc_wreg = NULL; 608c6b6a421SHawking Zhang adev->pcie_rreg = &nv_pcie_rreg; 609c6b6a421SHawking Zhang adev->pcie_wreg = &nv_pcie_wreg; 610c6b6a421SHawking Zhang 611c6b6a421SHawking Zhang /* TODO: will add them during VCN v2 implementation */ 612c6b6a421SHawking Zhang adev->uvd_ctx_rreg = NULL; 613c6b6a421SHawking Zhang adev->uvd_ctx_wreg = NULL; 614c6b6a421SHawking Zhang 615c6b6a421SHawking Zhang adev->didt_rreg = &nv_didt_rreg; 616c6b6a421SHawking Zhang adev->didt_wreg = &nv_didt_wreg; 617c6b6a421SHawking Zhang 618c6b6a421SHawking Zhang adev->asic_funcs = &nv_asic_funcs; 619c6b6a421SHawking Zhang 620c6b6a421SHawking Zhang adev->rev_id = nv_get_rev_id(adev); 621c6b6a421SHawking Zhang adev->external_rev_id = 0xff; 622c6b6a421SHawking Zhang switch (adev->asic_type) { 623c6b6a421SHawking Zhang case CHIP_NAVI10: 624c6b6a421SHawking Zhang adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 625c6b6a421SHawking Zhang AMD_CG_SUPPORT_GFX_CGCG | 626c6b6a421SHawking Zhang AMD_CG_SUPPORT_IH_CG | 627c6b6a421SHawking Zhang AMD_CG_SUPPORT_HDP_MGCG | 628c6b6a421SHawking Zhang AMD_CG_SUPPORT_HDP_LS | 629c6b6a421SHawking Zhang AMD_CG_SUPPORT_SDMA_MGCG | 630c6b6a421SHawking Zhang AMD_CG_SUPPORT_SDMA_LS | 631c6b6a421SHawking Zhang AMD_CG_SUPPORT_MC_MGCG | 632c6b6a421SHawking Zhang AMD_CG_SUPPORT_MC_LS | 633c6b6a421SHawking Zhang AMD_CG_SUPPORT_ATHUB_MGCG | 634c6b6a421SHawking Zhang AMD_CG_SUPPORT_ATHUB_LS | 635c6b6a421SHawking Zhang AMD_CG_SUPPORT_VCN_MGCG | 636099d66e4SLeo Liu AMD_CG_SUPPORT_JPEG_MGCG | 637c6b6a421SHawking Zhang AMD_CG_SUPPORT_BIF_MGCG | 638c6b6a421SHawking Zhang AMD_CG_SUPPORT_BIF_LS; 639157710eaSLeo Liu adev->pg_flags = AMD_PG_SUPPORT_VCN | 640c12d410fSHuang Rui AMD_PG_SUPPORT_VCN_DPG | 641099d66e4SLeo Liu AMD_PG_SUPPORT_JPEG | 642a201b6acSHuang Rui AMD_PG_SUPPORT_ATHUB; 643c6b6a421SHawking Zhang adev->external_rev_id = adev->rev_id + 0x1; 644c6b6a421SHawking Zhang break; 6455e71e011SXiaojie Yuan case CHIP_NAVI14: 646d0c39f8cSXiaojie Yuan adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 647d0c39f8cSXiaojie Yuan AMD_CG_SUPPORT_GFX_CGCG | 648d0c39f8cSXiaojie Yuan AMD_CG_SUPPORT_IH_CG | 649d0c39f8cSXiaojie Yuan AMD_CG_SUPPORT_HDP_MGCG | 650d0c39f8cSXiaojie Yuan AMD_CG_SUPPORT_HDP_LS | 651d0c39f8cSXiaojie Yuan AMD_CG_SUPPORT_SDMA_MGCG | 652d0c39f8cSXiaojie Yuan AMD_CG_SUPPORT_SDMA_LS | 653d0c39f8cSXiaojie Yuan AMD_CG_SUPPORT_MC_MGCG | 654d0c39f8cSXiaojie Yuan AMD_CG_SUPPORT_MC_LS | 655d0c39f8cSXiaojie Yuan AMD_CG_SUPPORT_ATHUB_MGCG | 656d0c39f8cSXiaojie Yuan AMD_CG_SUPPORT_ATHUB_LS | 657d0c39f8cSXiaojie Yuan AMD_CG_SUPPORT_VCN_MGCG | 658099d66e4SLeo Liu AMD_CG_SUPPORT_JPEG_MGCG | 659d0c39f8cSXiaojie Yuan AMD_CG_SUPPORT_BIF_MGCG | 660d0c39f8cSXiaojie Yuan AMD_CG_SUPPORT_BIF_LS; 6610377b088SXiaojie Yuan adev->pg_flags = AMD_PG_SUPPORT_VCN | 662099d66e4SLeo Liu AMD_PG_SUPPORT_JPEG | 6630377b088SXiaojie Yuan AMD_PG_SUPPORT_VCN_DPG; 66435ef88faStiancyin adev->external_rev_id = adev->rev_id + 20; 6655e71e011SXiaojie Yuan break; 66674b5e509SXiaojie Yuan case CHIP_NAVI12: 667dca009e7SXiaojie Yuan adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 668dca009e7SXiaojie Yuan AMD_CG_SUPPORT_GFX_MGLS | 669dca009e7SXiaojie Yuan AMD_CG_SUPPORT_GFX_CGCG | 670dca009e7SXiaojie Yuan AMD_CG_SUPPORT_GFX_CP_LS | 6715211c37aSXiaojie Yuan AMD_CG_SUPPORT_GFX_RLC_LS | 672fbe0bc57SXiaojie Yuan AMD_CG_SUPPORT_IH_CG | 6735211c37aSXiaojie Yuan AMD_CG_SUPPORT_HDP_MGCG | 674358ab97fSXiaojie Yuan AMD_CG_SUPPORT_HDP_LS | 675358ab97fSXiaojie Yuan AMD_CG_SUPPORT_SDMA_MGCG | 6768b797b3dSXiaojie Yuan AMD_CG_SUPPORT_SDMA_LS | 6778b797b3dSXiaojie Yuan AMD_CG_SUPPORT_MC_MGCG | 678ca51678dSXiaojie Yuan AMD_CG_SUPPORT_MC_LS | 679ca51678dSXiaojie Yuan AMD_CG_SUPPORT_ATHUB_MGCG | 68065872e59SXiaojie Yuan AMD_CG_SUPPORT_ATHUB_LS | 681099d66e4SLeo Liu AMD_CG_SUPPORT_VCN_MGCG | 682099d66e4SLeo Liu AMD_CG_SUPPORT_JPEG_MGCG; 683c1653ea0SXiaojie Yuan adev->pg_flags = AMD_PG_SUPPORT_VCN | 6845ef3b8acSXiaojie Yuan AMD_PG_SUPPORT_VCN_DPG | 685099d66e4SLeo Liu AMD_PG_SUPPORT_JPEG | 6865ef3b8acSXiaojie Yuan AMD_PG_SUPPORT_ATHUB; 687df5e984cSTiecheng Zhou /* guest vm gets 0xffffffff when reading RCC_DEV0_EPF0_STRAP0, 688df5e984cSTiecheng Zhou * as a consequence, the rev_id and external_rev_id are wrong. 689df5e984cSTiecheng Zhou * workaround it by hardcoding rev_id to 0 (default value). 690df5e984cSTiecheng Zhou */ 691df5e984cSTiecheng Zhou if (amdgpu_sriov_vf(adev)) 692df5e984cSTiecheng Zhou adev->rev_id = 0; 69374b5e509SXiaojie Yuan adev->external_rev_id = adev->rev_id + 0xa; 69474b5e509SXiaojie Yuan break; 695117910edSLikun Gao case CHIP_SIENNA_CICHLID: 696117910edSLikun Gao adev->cg_flags = 0; 697117910edSLikun Gao adev->pg_flags = 0; 698117910edSLikun Gao adev->external_rev_id = adev->rev_id + 0x28; 699117910edSLikun Gao break; 700c6b6a421SHawking Zhang default: 701c6b6a421SHawking Zhang /* FIXME: not supported yet */ 702c6b6a421SHawking Zhang return -EINVAL; 703c6b6a421SHawking Zhang } 704c6b6a421SHawking Zhang 705b05b6903SJiange Zhao if (amdgpu_sriov_vf(adev)) { 706b05b6903SJiange Zhao amdgpu_virt_init_setting(adev); 707b05b6903SJiange Zhao xgpu_nv_mailbox_set_irq_funcs(adev); 708b05b6903SJiange Zhao } 709b05b6903SJiange Zhao 710c6b6a421SHawking Zhang return 0; 711c6b6a421SHawking Zhang } 712c6b6a421SHawking Zhang 713c6b6a421SHawking Zhang static int nv_common_late_init(void *handle) 714c6b6a421SHawking Zhang { 715b05b6903SJiange Zhao struct amdgpu_device *adev = (struct amdgpu_device *)handle; 716b05b6903SJiange Zhao 717b05b6903SJiange Zhao if (amdgpu_sriov_vf(adev)) 718b05b6903SJiange Zhao xgpu_nv_mailbox_get_irq(adev); 719b05b6903SJiange Zhao 720c6b6a421SHawking Zhang return 0; 721c6b6a421SHawking Zhang } 722c6b6a421SHawking Zhang 723c6b6a421SHawking Zhang static int nv_common_sw_init(void *handle) 724c6b6a421SHawking Zhang { 725b05b6903SJiange Zhao struct amdgpu_device *adev = (struct amdgpu_device *)handle; 726b05b6903SJiange Zhao 727b05b6903SJiange Zhao if (amdgpu_sriov_vf(adev)) 728b05b6903SJiange Zhao xgpu_nv_mailbox_add_irq_id(adev); 729b05b6903SJiange Zhao 730c6b6a421SHawking Zhang return 0; 731c6b6a421SHawking Zhang } 732c6b6a421SHawking Zhang 733c6b6a421SHawking Zhang static int nv_common_sw_fini(void *handle) 734c6b6a421SHawking Zhang { 735c6b6a421SHawking Zhang return 0; 736c6b6a421SHawking Zhang } 737c6b6a421SHawking Zhang 738c6b6a421SHawking Zhang static int nv_common_hw_init(void *handle) 739c6b6a421SHawking Zhang { 740c6b6a421SHawking Zhang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 741c6b6a421SHawking Zhang 742c6b6a421SHawking Zhang /* enable pcie gen2/3 link */ 743c6b6a421SHawking Zhang nv_pcie_gen3_enable(adev); 744c6b6a421SHawking Zhang /* enable aspm */ 745c6b6a421SHawking Zhang nv_program_aspm(adev); 746c6b6a421SHawking Zhang /* setup nbio registers */ 747bebc0762SHawking Zhang adev->nbio.funcs->init_registers(adev); 748923c087aSYong Zhao /* remap HDP registers to a hole in mmio space, 749923c087aSYong Zhao * for the purpose of expose those registers 750923c087aSYong Zhao * to process space 751923c087aSYong Zhao */ 752923c087aSYong Zhao if (adev->nbio.funcs->remap_hdp_registers) 753923c087aSYong Zhao adev->nbio.funcs->remap_hdp_registers(adev); 754c6b6a421SHawking Zhang /* enable the doorbell aperture */ 755c6b6a421SHawking Zhang nv_enable_doorbell_aperture(adev, true); 756c6b6a421SHawking Zhang 757c6b6a421SHawking Zhang return 0; 758c6b6a421SHawking Zhang } 759c6b6a421SHawking Zhang 760c6b6a421SHawking Zhang static int nv_common_hw_fini(void *handle) 761c6b6a421SHawking Zhang { 762c6b6a421SHawking Zhang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 763c6b6a421SHawking Zhang 764c6b6a421SHawking Zhang /* disable the doorbell aperture */ 765c6b6a421SHawking Zhang nv_enable_doorbell_aperture(adev, false); 766c6b6a421SHawking Zhang 767c6b6a421SHawking Zhang return 0; 768c6b6a421SHawking Zhang } 769c6b6a421SHawking Zhang 770c6b6a421SHawking Zhang static int nv_common_suspend(void *handle) 771c6b6a421SHawking Zhang { 772c6b6a421SHawking Zhang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 773c6b6a421SHawking Zhang 774c6b6a421SHawking Zhang return nv_common_hw_fini(adev); 775c6b6a421SHawking Zhang } 776c6b6a421SHawking Zhang 777c6b6a421SHawking Zhang static int nv_common_resume(void *handle) 778c6b6a421SHawking Zhang { 779c6b6a421SHawking Zhang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 780c6b6a421SHawking Zhang 781c6b6a421SHawking Zhang return nv_common_hw_init(adev); 782c6b6a421SHawking Zhang } 783c6b6a421SHawking Zhang 784c6b6a421SHawking Zhang static bool nv_common_is_idle(void *handle) 785c6b6a421SHawking Zhang { 786c6b6a421SHawking Zhang return true; 787c6b6a421SHawking Zhang } 788c6b6a421SHawking Zhang 789c6b6a421SHawking Zhang static int nv_common_wait_for_idle(void *handle) 790c6b6a421SHawking Zhang { 791c6b6a421SHawking Zhang return 0; 792c6b6a421SHawking Zhang } 793c6b6a421SHawking Zhang 794c6b6a421SHawking Zhang static int nv_common_soft_reset(void *handle) 795c6b6a421SHawking Zhang { 796c6b6a421SHawking Zhang return 0; 797c6b6a421SHawking Zhang } 798c6b6a421SHawking Zhang 799c6b6a421SHawking Zhang static void nv_update_hdp_mem_power_gating(struct amdgpu_device *adev, 800c6b6a421SHawking Zhang bool enable) 801c6b6a421SHawking Zhang { 802c6b6a421SHawking Zhang uint32_t hdp_clk_cntl, hdp_clk_cntl1; 803c6b6a421SHawking Zhang uint32_t hdp_mem_pwr_cntl; 804c6b6a421SHawking Zhang 805c6b6a421SHawking Zhang if (!(adev->cg_flags & (AMD_CG_SUPPORT_HDP_LS | 806c6b6a421SHawking Zhang AMD_CG_SUPPORT_HDP_DS | 807c6b6a421SHawking Zhang AMD_CG_SUPPORT_HDP_SD))) 808c6b6a421SHawking Zhang return; 809c6b6a421SHawking Zhang 810c6b6a421SHawking Zhang hdp_clk_cntl = hdp_clk_cntl1 = RREG32_SOC15(HDP, 0, mmHDP_CLK_CNTL); 811c6b6a421SHawking Zhang hdp_mem_pwr_cntl = RREG32_SOC15(HDP, 0, mmHDP_MEM_POWER_CTRL); 812c6b6a421SHawking Zhang 813c6b6a421SHawking Zhang /* Before doing clock/power mode switch, 814c6b6a421SHawking Zhang * forced on IPH & RC clock */ 815c6b6a421SHawking Zhang hdp_clk_cntl = REG_SET_FIELD(hdp_clk_cntl, HDP_CLK_CNTL, 816c6b6a421SHawking Zhang IPH_MEM_CLK_SOFT_OVERRIDE, 1); 817c6b6a421SHawking Zhang hdp_clk_cntl = REG_SET_FIELD(hdp_clk_cntl, HDP_CLK_CNTL, 818c6b6a421SHawking Zhang RC_MEM_CLK_SOFT_OVERRIDE, 1); 819c6b6a421SHawking Zhang WREG32_SOC15(HDP, 0, mmHDP_CLK_CNTL, hdp_clk_cntl); 820c6b6a421SHawking Zhang 821c6b6a421SHawking Zhang /* HDP 5.0 doesn't support dynamic power mode switch, 822c6b6a421SHawking Zhang * disable clock and power gating before any changing */ 823c6b6a421SHawking Zhang hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, 824c6b6a421SHawking Zhang IPH_MEM_POWER_CTRL_EN, 0); 825c6b6a421SHawking Zhang hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, 826c6b6a421SHawking Zhang IPH_MEM_POWER_LS_EN, 0); 827c6b6a421SHawking Zhang hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, 828c6b6a421SHawking Zhang IPH_MEM_POWER_DS_EN, 0); 829c6b6a421SHawking Zhang hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, 830c6b6a421SHawking Zhang IPH_MEM_POWER_SD_EN, 0); 831c6b6a421SHawking Zhang hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, 832c6b6a421SHawking Zhang RC_MEM_POWER_CTRL_EN, 0); 833c6b6a421SHawking Zhang hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, 834c6b6a421SHawking Zhang RC_MEM_POWER_LS_EN, 0); 835c6b6a421SHawking Zhang hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, 836c6b6a421SHawking Zhang RC_MEM_POWER_DS_EN, 0); 837c6b6a421SHawking Zhang hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, 838c6b6a421SHawking Zhang RC_MEM_POWER_SD_EN, 0); 839c6b6a421SHawking Zhang WREG32_SOC15(HDP, 0, mmHDP_MEM_POWER_CTRL, hdp_mem_pwr_cntl); 840c6b6a421SHawking Zhang 841c6b6a421SHawking Zhang /* only one clock gating mode (LS/DS/SD) can be enabled */ 842c6b6a421SHawking Zhang if (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS) { 843c6b6a421SHawking Zhang hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, 844c6b6a421SHawking Zhang HDP_MEM_POWER_CTRL, 845c6b6a421SHawking Zhang IPH_MEM_POWER_LS_EN, enable); 846c6b6a421SHawking Zhang hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, 847c6b6a421SHawking Zhang HDP_MEM_POWER_CTRL, 848c6b6a421SHawking Zhang RC_MEM_POWER_LS_EN, enable); 849c6b6a421SHawking Zhang } else if (adev->cg_flags & AMD_CG_SUPPORT_HDP_DS) { 850c6b6a421SHawking Zhang hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, 851c6b6a421SHawking Zhang HDP_MEM_POWER_CTRL, 852c6b6a421SHawking Zhang IPH_MEM_POWER_DS_EN, enable); 853c6b6a421SHawking Zhang hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, 854c6b6a421SHawking Zhang HDP_MEM_POWER_CTRL, 855c6b6a421SHawking Zhang RC_MEM_POWER_DS_EN, enable); 856c6b6a421SHawking Zhang } else if (adev->cg_flags & AMD_CG_SUPPORT_HDP_SD) { 857c6b6a421SHawking Zhang hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, 858c6b6a421SHawking Zhang HDP_MEM_POWER_CTRL, 859c6b6a421SHawking Zhang IPH_MEM_POWER_SD_EN, enable); 860c6b6a421SHawking Zhang /* RC should not use shut down mode, fallback to ds */ 861c6b6a421SHawking Zhang hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, 862c6b6a421SHawking Zhang HDP_MEM_POWER_CTRL, 863c6b6a421SHawking Zhang RC_MEM_POWER_DS_EN, enable); 864c6b6a421SHawking Zhang } 865c6b6a421SHawking Zhang 866c6b6a421SHawking Zhang WREG32_SOC15(HDP, 0, mmHDP_MEM_POWER_CTRL, hdp_mem_pwr_cntl); 867c6b6a421SHawking Zhang 868c6b6a421SHawking Zhang /* restore IPH & RC clock override after clock/power mode changing */ 869c6b6a421SHawking Zhang WREG32_SOC15(HDP, 0, mmHDP_CLK_CNTL, hdp_clk_cntl1); 870c6b6a421SHawking Zhang } 871c6b6a421SHawking Zhang 872c6b6a421SHawking Zhang static void nv_update_hdp_clock_gating(struct amdgpu_device *adev, 873c6b6a421SHawking Zhang bool enable) 874c6b6a421SHawking Zhang { 875c6b6a421SHawking Zhang uint32_t hdp_clk_cntl; 876c6b6a421SHawking Zhang 877c6b6a421SHawking Zhang if (!(adev->cg_flags & AMD_CG_SUPPORT_HDP_MGCG)) 878c6b6a421SHawking Zhang return; 879c6b6a421SHawking Zhang 880c6b6a421SHawking Zhang hdp_clk_cntl = RREG32_SOC15(HDP, 0, mmHDP_CLK_CNTL); 881c6b6a421SHawking Zhang 882c6b6a421SHawking Zhang if (enable) { 883c6b6a421SHawking Zhang hdp_clk_cntl &= 884c6b6a421SHawking Zhang ~(uint32_t) 885c6b6a421SHawking Zhang (HDP_CLK_CNTL__IPH_MEM_CLK_SOFT_OVERRIDE_MASK | 886c6b6a421SHawking Zhang HDP_CLK_CNTL__RC_MEM_CLK_SOFT_OVERRIDE_MASK | 887c6b6a421SHawking Zhang HDP_CLK_CNTL__DBUS_CLK_SOFT_OVERRIDE_MASK | 888c6b6a421SHawking Zhang HDP_CLK_CNTL__DYN_CLK_SOFT_OVERRIDE_MASK | 889c6b6a421SHawking Zhang HDP_CLK_CNTL__XDP_REG_CLK_SOFT_OVERRIDE_MASK | 890c6b6a421SHawking Zhang HDP_CLK_CNTL__HDP_REG_CLK_SOFT_OVERRIDE_MASK); 891c6b6a421SHawking Zhang } else { 892c6b6a421SHawking Zhang hdp_clk_cntl |= HDP_CLK_CNTL__IPH_MEM_CLK_SOFT_OVERRIDE_MASK | 893c6b6a421SHawking Zhang HDP_CLK_CNTL__RC_MEM_CLK_SOFT_OVERRIDE_MASK | 894c6b6a421SHawking Zhang HDP_CLK_CNTL__DBUS_CLK_SOFT_OVERRIDE_MASK | 895c6b6a421SHawking Zhang HDP_CLK_CNTL__DYN_CLK_SOFT_OVERRIDE_MASK | 896c6b6a421SHawking Zhang HDP_CLK_CNTL__XDP_REG_CLK_SOFT_OVERRIDE_MASK | 897c6b6a421SHawking Zhang HDP_CLK_CNTL__HDP_REG_CLK_SOFT_OVERRIDE_MASK; 898c6b6a421SHawking Zhang } 899c6b6a421SHawking Zhang 900c6b6a421SHawking Zhang WREG32_SOC15(HDP, 0, mmHDP_CLK_CNTL, hdp_clk_cntl); 901c6b6a421SHawking Zhang } 902c6b6a421SHawking Zhang 903c6b6a421SHawking Zhang static int nv_common_set_clockgating_state(void *handle, 904c6b6a421SHawking Zhang enum amd_clockgating_state state) 905c6b6a421SHawking Zhang { 906c6b6a421SHawking Zhang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 907c6b6a421SHawking Zhang 908c6b6a421SHawking Zhang if (amdgpu_sriov_vf(adev)) 909c6b6a421SHawking Zhang return 0; 910c6b6a421SHawking Zhang 911c6b6a421SHawking Zhang switch (adev->asic_type) { 912c6b6a421SHawking Zhang case CHIP_NAVI10: 9135e71e011SXiaojie Yuan case CHIP_NAVI14: 9147e17e58bSXiaojie Yuan case CHIP_NAVI12: 915117910edSLikun Gao case CHIP_SIENNA_CICHLID: 916bebc0762SHawking Zhang adev->nbio.funcs->update_medium_grain_clock_gating(adev, 917a9d4fe2fSNirmoy Das state == AMD_CG_STATE_GATE); 918bebc0762SHawking Zhang adev->nbio.funcs->update_medium_grain_light_sleep(adev, 919a9d4fe2fSNirmoy Das state == AMD_CG_STATE_GATE); 920c6b6a421SHawking Zhang nv_update_hdp_mem_power_gating(adev, 921a9d4fe2fSNirmoy Das state == AMD_CG_STATE_GATE); 922c6b6a421SHawking Zhang nv_update_hdp_clock_gating(adev, 923a9d4fe2fSNirmoy Das state == AMD_CG_STATE_GATE); 924c6b6a421SHawking Zhang break; 925c6b6a421SHawking Zhang default: 926c6b6a421SHawking Zhang break; 927c6b6a421SHawking Zhang } 928c6b6a421SHawking Zhang return 0; 929c6b6a421SHawking Zhang } 930c6b6a421SHawking Zhang 931c6b6a421SHawking Zhang static int nv_common_set_powergating_state(void *handle, 932c6b6a421SHawking Zhang enum amd_powergating_state state) 933c6b6a421SHawking Zhang { 934c6b6a421SHawking Zhang /* TODO */ 935c6b6a421SHawking Zhang return 0; 936c6b6a421SHawking Zhang } 937c6b6a421SHawking Zhang 938c6b6a421SHawking Zhang static void nv_common_get_clockgating_state(void *handle, u32 *flags) 939c6b6a421SHawking Zhang { 940c6b6a421SHawking Zhang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 941c6b6a421SHawking Zhang uint32_t tmp; 942c6b6a421SHawking Zhang 943c6b6a421SHawking Zhang if (amdgpu_sriov_vf(adev)) 944c6b6a421SHawking Zhang *flags = 0; 945c6b6a421SHawking Zhang 946bebc0762SHawking Zhang adev->nbio.funcs->get_clockgating_state(adev, flags); 947c6b6a421SHawking Zhang 948c6b6a421SHawking Zhang /* AMD_CG_SUPPORT_HDP_MGCG */ 949c6b6a421SHawking Zhang tmp = RREG32_SOC15(HDP, 0, mmHDP_CLK_CNTL); 950c6b6a421SHawking Zhang if (!(tmp & (HDP_CLK_CNTL__IPH_MEM_CLK_SOFT_OVERRIDE_MASK | 951c6b6a421SHawking Zhang HDP_CLK_CNTL__RC_MEM_CLK_SOFT_OVERRIDE_MASK | 952c6b6a421SHawking Zhang HDP_CLK_CNTL__DBUS_CLK_SOFT_OVERRIDE_MASK | 953c6b6a421SHawking Zhang HDP_CLK_CNTL__DYN_CLK_SOFT_OVERRIDE_MASK | 954c6b6a421SHawking Zhang HDP_CLK_CNTL__XDP_REG_CLK_SOFT_OVERRIDE_MASK | 955c6b6a421SHawking Zhang HDP_CLK_CNTL__HDP_REG_CLK_SOFT_OVERRIDE_MASK))) 956c6b6a421SHawking Zhang *flags |= AMD_CG_SUPPORT_HDP_MGCG; 957c6b6a421SHawking Zhang 958c6b6a421SHawking Zhang /* AMD_CG_SUPPORT_HDP_LS/DS/SD */ 959c6b6a421SHawking Zhang tmp = RREG32_SOC15(HDP, 0, mmHDP_MEM_POWER_CTRL); 960c6b6a421SHawking Zhang if (tmp & HDP_MEM_POWER_CTRL__IPH_MEM_POWER_LS_EN_MASK) 961c6b6a421SHawking Zhang *flags |= AMD_CG_SUPPORT_HDP_LS; 962c6b6a421SHawking Zhang else if (tmp & HDP_MEM_POWER_CTRL__IPH_MEM_POWER_DS_EN_MASK) 963c6b6a421SHawking Zhang *flags |= AMD_CG_SUPPORT_HDP_DS; 964c6b6a421SHawking Zhang else if (tmp & HDP_MEM_POWER_CTRL__IPH_MEM_POWER_SD_EN_MASK) 965c6b6a421SHawking Zhang *flags |= AMD_CG_SUPPORT_HDP_SD; 966c6b6a421SHawking Zhang 967c6b6a421SHawking Zhang return; 968c6b6a421SHawking Zhang } 969c6b6a421SHawking Zhang 970c6b6a421SHawking Zhang static const struct amd_ip_funcs nv_common_ip_funcs = { 971c6b6a421SHawking Zhang .name = "nv_common", 972c6b6a421SHawking Zhang .early_init = nv_common_early_init, 973c6b6a421SHawking Zhang .late_init = nv_common_late_init, 974c6b6a421SHawking Zhang .sw_init = nv_common_sw_init, 975c6b6a421SHawking Zhang .sw_fini = nv_common_sw_fini, 976c6b6a421SHawking Zhang .hw_init = nv_common_hw_init, 977c6b6a421SHawking Zhang .hw_fini = nv_common_hw_fini, 978c6b6a421SHawking Zhang .suspend = nv_common_suspend, 979c6b6a421SHawking Zhang .resume = nv_common_resume, 980c6b6a421SHawking Zhang .is_idle = nv_common_is_idle, 981c6b6a421SHawking Zhang .wait_for_idle = nv_common_wait_for_idle, 982c6b6a421SHawking Zhang .soft_reset = nv_common_soft_reset, 983c6b6a421SHawking Zhang .set_clockgating_state = nv_common_set_clockgating_state, 984c6b6a421SHawking Zhang .set_powergating_state = nv_common_set_powergating_state, 985c6b6a421SHawking Zhang .get_clockgating_state = nv_common_get_clockgating_state, 986c6b6a421SHawking Zhang }; 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