1c6b6a421SHawking Zhang /* 2c6b6a421SHawking Zhang * Copyright 2019 Advanced Micro Devices, Inc. 3c6b6a421SHawking Zhang * 4c6b6a421SHawking Zhang * Permission is hereby granted, free of charge, to any person obtaining a 5c6b6a421SHawking Zhang * copy of this software and associated documentation files (the "Software"), 6c6b6a421SHawking Zhang * to deal in the Software without restriction, including without limitation 7c6b6a421SHawking Zhang * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8c6b6a421SHawking Zhang * and/or sell copies of the Software, and to permit persons to whom the 9c6b6a421SHawking Zhang * Software is furnished to do so, subject to the following conditions: 10c6b6a421SHawking Zhang * 11c6b6a421SHawking Zhang * The above copyright notice and this permission notice shall be included in 12c6b6a421SHawking Zhang * all copies or substantial portions of the Software. 13c6b6a421SHawking Zhang * 14c6b6a421SHawking Zhang * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15c6b6a421SHawking Zhang * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16c6b6a421SHawking Zhang * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17c6b6a421SHawking Zhang * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18c6b6a421SHawking Zhang * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19c6b6a421SHawking Zhang * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20c6b6a421SHawking Zhang * OTHER DEALINGS IN THE SOFTWARE. 21c6b6a421SHawking Zhang * 22c6b6a421SHawking Zhang */ 23c6b6a421SHawking Zhang #include <linux/firmware.h> 24c6b6a421SHawking Zhang #include <linux/slab.h> 25c6b6a421SHawking Zhang #include <linux/module.h> 26e9eea902SAlex Deucher #include <linux/pci.h> 27e9eea902SAlex Deucher 28c6b6a421SHawking Zhang #include "amdgpu.h" 29c6b6a421SHawking Zhang #include "amdgpu_atombios.h" 30c6b6a421SHawking Zhang #include "amdgpu_ih.h" 31c6b6a421SHawking Zhang #include "amdgpu_uvd.h" 32c6b6a421SHawking Zhang #include "amdgpu_vce.h" 33c6b6a421SHawking Zhang #include "amdgpu_ucode.h" 34c6b6a421SHawking Zhang #include "amdgpu_psp.h" 35767acabdSKevin Wang #include "amdgpu_smu.h" 36c6b6a421SHawking Zhang #include "atom.h" 37c6b6a421SHawking Zhang #include "amd_pcie.h" 38c6b6a421SHawking Zhang 39c6b6a421SHawking Zhang #include "gc/gc_10_1_0_offset.h" 40c6b6a421SHawking Zhang #include "gc/gc_10_1_0_sh_mask.h" 41c6b6a421SHawking Zhang #include "hdp/hdp_5_0_0_offset.h" 42c6b6a421SHawking Zhang #include "hdp/hdp_5_0_0_sh_mask.h" 4329bc37b4SAlex Deucher #include "smuio/smuio_11_0_0_offset.h" 443967ae6dSAlex Deucher #include "mp/mp_11_0_offset.h" 45c6b6a421SHawking Zhang 46c6b6a421SHawking Zhang #include "soc15.h" 47c6b6a421SHawking Zhang #include "soc15_common.h" 48c6b6a421SHawking Zhang #include "gmc_v10_0.h" 49c6b6a421SHawking Zhang #include "gfxhub_v2_0.h" 50c6b6a421SHawking Zhang #include "mmhub_v2_0.h" 51bebc0762SHawking Zhang #include "nbio_v2_3.h" 52c6b6a421SHawking Zhang #include "nv.h" 53c6b6a421SHawking Zhang #include "navi10_ih.h" 54c6b6a421SHawking Zhang #include "gfx_v10_0.h" 55c6b6a421SHawking Zhang #include "sdma_v5_0.h" 56157e72e8SLikun Gao #include "sdma_v5_2.h" 57c6b6a421SHawking Zhang #include "vcn_v2_0.h" 585be45a26SLeo Liu #include "jpeg_v2_0.h" 59c6b6a421SHawking Zhang #include "dce_virtual.h" 60c6b6a421SHawking Zhang #include "mes_v10_1.h" 61b05b6903SJiange Zhao #include "mxgpu_nv.h" 62c6b6a421SHawking Zhang 63c6b6a421SHawking Zhang static const struct amd_ip_funcs nv_common_ip_funcs; 64c6b6a421SHawking Zhang 65c6b6a421SHawking Zhang /* 66c6b6a421SHawking Zhang * Indirect registers accessor 67c6b6a421SHawking Zhang */ 68c6b6a421SHawking Zhang static u32 nv_pcie_rreg(struct amdgpu_device *adev, u32 reg) 69c6b6a421SHawking Zhang { 70c6b6a421SHawking Zhang unsigned long flags, address, data; 71c6b6a421SHawking Zhang u32 r; 72bebc0762SHawking Zhang address = adev->nbio.funcs->get_pcie_index_offset(adev); 73bebc0762SHawking Zhang data = adev->nbio.funcs->get_pcie_data_offset(adev); 74c6b6a421SHawking Zhang 75c6b6a421SHawking Zhang spin_lock_irqsave(&adev->pcie_idx_lock, flags); 76c6b6a421SHawking Zhang WREG32(address, reg); 77c6b6a421SHawking Zhang (void)RREG32(address); 78c6b6a421SHawking Zhang r = RREG32(data); 79c6b6a421SHawking Zhang spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); 80c6b6a421SHawking Zhang return r; 81c6b6a421SHawking Zhang } 82c6b6a421SHawking Zhang 83c6b6a421SHawking Zhang static void nv_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v) 84c6b6a421SHawking Zhang { 85c6b6a421SHawking Zhang unsigned long flags, address, data; 86c6b6a421SHawking Zhang 87bebc0762SHawking Zhang address = adev->nbio.funcs->get_pcie_index_offset(adev); 88bebc0762SHawking Zhang data = adev->nbio.funcs->get_pcie_data_offset(adev); 89c6b6a421SHawking Zhang 90c6b6a421SHawking Zhang spin_lock_irqsave(&adev->pcie_idx_lock, flags); 91c6b6a421SHawking Zhang WREG32(address, reg); 92c6b6a421SHawking Zhang (void)RREG32(address); 93c6b6a421SHawking Zhang WREG32(data, v); 94c6b6a421SHawking Zhang (void)RREG32(data); 95c6b6a421SHawking Zhang spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); 96c6b6a421SHawking Zhang } 97c6b6a421SHawking Zhang 98c6b6a421SHawking Zhang static u32 nv_didt_rreg(struct amdgpu_device *adev, u32 reg) 99c6b6a421SHawking Zhang { 100c6b6a421SHawking Zhang unsigned long flags, address, data; 101c6b6a421SHawking Zhang u32 r; 102c6b6a421SHawking Zhang 103c6b6a421SHawking Zhang address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX); 104c6b6a421SHawking Zhang data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA); 105c6b6a421SHawking Zhang 106c6b6a421SHawking Zhang spin_lock_irqsave(&adev->didt_idx_lock, flags); 107c6b6a421SHawking Zhang WREG32(address, (reg)); 108c6b6a421SHawking Zhang r = RREG32(data); 109c6b6a421SHawking Zhang spin_unlock_irqrestore(&adev->didt_idx_lock, flags); 110c6b6a421SHawking Zhang return r; 111c6b6a421SHawking Zhang } 112c6b6a421SHawking Zhang 113c6b6a421SHawking Zhang static void nv_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v) 114c6b6a421SHawking Zhang { 115c6b6a421SHawking Zhang unsigned long flags, address, data; 116c6b6a421SHawking Zhang 117c6b6a421SHawking Zhang address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX); 118c6b6a421SHawking Zhang data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA); 119c6b6a421SHawking Zhang 120c6b6a421SHawking Zhang spin_lock_irqsave(&adev->didt_idx_lock, flags); 121c6b6a421SHawking Zhang WREG32(address, (reg)); 122c6b6a421SHawking Zhang WREG32(data, (v)); 123c6b6a421SHawking Zhang spin_unlock_irqrestore(&adev->didt_idx_lock, flags); 124c6b6a421SHawking Zhang } 125c6b6a421SHawking Zhang 126c6b6a421SHawking Zhang static u32 nv_get_config_memsize(struct amdgpu_device *adev) 127c6b6a421SHawking Zhang { 128bebc0762SHawking Zhang return adev->nbio.funcs->get_memsize(adev); 129c6b6a421SHawking Zhang } 130c6b6a421SHawking Zhang 131c6b6a421SHawking Zhang static u32 nv_get_xclk(struct amdgpu_device *adev) 132c6b6a421SHawking Zhang { 133462a70d8STao Zhou return adev->clock.spll.reference_freq; 134c6b6a421SHawking Zhang } 135c6b6a421SHawking Zhang 136c6b6a421SHawking Zhang 137c6b6a421SHawking Zhang void nv_grbm_select(struct amdgpu_device *adev, 138c6b6a421SHawking Zhang u32 me, u32 pipe, u32 queue, u32 vmid) 139c6b6a421SHawking Zhang { 140c6b6a421SHawking Zhang u32 grbm_gfx_cntl = 0; 141c6b6a421SHawking Zhang grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, PIPEID, pipe); 142c6b6a421SHawking Zhang grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, MEID, me); 143c6b6a421SHawking Zhang grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, VMID, vmid); 144c6b6a421SHawking Zhang grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, QUEUEID, queue); 145c6b6a421SHawking Zhang 146c6b6a421SHawking Zhang WREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_CNTL), grbm_gfx_cntl); 147c6b6a421SHawking Zhang } 148c6b6a421SHawking Zhang 149c6b6a421SHawking Zhang static void nv_vga_set_state(struct amdgpu_device *adev, bool state) 150c6b6a421SHawking Zhang { 151c6b6a421SHawking Zhang /* todo */ 152c6b6a421SHawking Zhang } 153c6b6a421SHawking Zhang 154c6b6a421SHawking Zhang static bool nv_read_disabled_bios(struct amdgpu_device *adev) 155c6b6a421SHawking Zhang { 156c6b6a421SHawking Zhang /* todo */ 157c6b6a421SHawking Zhang return false; 158c6b6a421SHawking Zhang } 159c6b6a421SHawking Zhang 160c6b6a421SHawking Zhang static bool nv_read_bios_from_rom(struct amdgpu_device *adev, 161c6b6a421SHawking Zhang u8 *bios, u32 length_bytes) 162c6b6a421SHawking Zhang { 16329bc37b4SAlex Deucher u32 *dw_ptr; 16429bc37b4SAlex Deucher u32 i, length_dw; 16529bc37b4SAlex Deucher 16629bc37b4SAlex Deucher if (bios == NULL) 167c6b6a421SHawking Zhang return false; 16829bc37b4SAlex Deucher if (length_bytes == 0) 16929bc37b4SAlex Deucher return false; 17029bc37b4SAlex Deucher /* APU vbios image is part of sbios image */ 17129bc37b4SAlex Deucher if (adev->flags & AMD_IS_APU) 17229bc37b4SAlex Deucher return false; 17329bc37b4SAlex Deucher 17429bc37b4SAlex Deucher dw_ptr = (u32 *)bios; 17529bc37b4SAlex Deucher length_dw = ALIGN(length_bytes, 4) / 4; 17629bc37b4SAlex Deucher 17729bc37b4SAlex Deucher /* set rom index to 0 */ 17829bc37b4SAlex Deucher WREG32(SOC15_REG_OFFSET(SMUIO, 0, mmROM_INDEX), 0); 17929bc37b4SAlex Deucher /* read out the rom data */ 18029bc37b4SAlex Deucher for (i = 0; i < length_dw; i++) 18129bc37b4SAlex Deucher dw_ptr[i] = RREG32(SOC15_REG_OFFSET(SMUIO, 0, mmROM_DATA)); 18229bc37b4SAlex Deucher 18329bc37b4SAlex Deucher return true; 184c6b6a421SHawking Zhang } 185c6b6a421SHawking Zhang 186c6b6a421SHawking Zhang static struct soc15_allowed_register_entry nv_allowed_read_registers[] = { 187c6b6a421SHawking Zhang { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS)}, 188c6b6a421SHawking Zhang { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS2)}, 189c6b6a421SHawking Zhang { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE0)}, 190c6b6a421SHawking Zhang { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE1)}, 191c6b6a421SHawking Zhang { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE2)}, 192c6b6a421SHawking Zhang { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE3)}, 193c6b6a421SHawking Zhang { SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_STATUS_REG)}, 194c6b6a421SHawking Zhang { SOC15_REG_ENTRY(SDMA1, 0, mmSDMA1_STATUS_REG)}, 195c6b6a421SHawking Zhang { SOC15_REG_ENTRY(GC, 0, mmCP_STAT)}, 196c6b6a421SHawking Zhang { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT1)}, 197c6b6a421SHawking Zhang { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT2)}, 198c6b6a421SHawking Zhang { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT3)}, 199c6b6a421SHawking Zhang { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_BUSY_STAT)}, 200c6b6a421SHawking Zhang { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STALLED_STAT1)}, 201c6b6a421SHawking Zhang { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STATUS)}, 202664fe85aSMarek Olšák { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_BUSY_STAT)}, 203c6b6a421SHawking Zhang { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STALLED_STAT1)}, 204c6b6a421SHawking Zhang { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STATUS)}, 205c6b6a421SHawking Zhang { SOC15_REG_ENTRY(GC, 0, mmGB_ADDR_CONFIG)}, 206c6b6a421SHawking Zhang }; 207c6b6a421SHawking Zhang 208c6b6a421SHawking Zhang static uint32_t nv_read_indexed_register(struct amdgpu_device *adev, u32 se_num, 209c6b6a421SHawking Zhang u32 sh_num, u32 reg_offset) 210c6b6a421SHawking Zhang { 211c6b6a421SHawking Zhang uint32_t val; 212c6b6a421SHawking Zhang 213c6b6a421SHawking Zhang mutex_lock(&adev->grbm_idx_mutex); 214c6b6a421SHawking Zhang if (se_num != 0xffffffff || sh_num != 0xffffffff) 215c6b6a421SHawking Zhang amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff); 216c6b6a421SHawking Zhang 217c6b6a421SHawking Zhang val = RREG32(reg_offset); 218c6b6a421SHawking Zhang 219c6b6a421SHawking Zhang if (se_num != 0xffffffff || sh_num != 0xffffffff) 220c6b6a421SHawking Zhang amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 221c6b6a421SHawking Zhang mutex_unlock(&adev->grbm_idx_mutex); 222c6b6a421SHawking Zhang return val; 223c6b6a421SHawking Zhang } 224c6b6a421SHawking Zhang 225c6b6a421SHawking Zhang static uint32_t nv_get_register_value(struct amdgpu_device *adev, 226c6b6a421SHawking Zhang bool indexed, u32 se_num, 227c6b6a421SHawking Zhang u32 sh_num, u32 reg_offset) 228c6b6a421SHawking Zhang { 229c6b6a421SHawking Zhang if (indexed) { 230c6b6a421SHawking Zhang return nv_read_indexed_register(adev, se_num, sh_num, reg_offset); 231c6b6a421SHawking Zhang } else { 232c6b6a421SHawking Zhang if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG)) 233c6b6a421SHawking Zhang return adev->gfx.config.gb_addr_config; 234c6b6a421SHawking Zhang return RREG32(reg_offset); 235c6b6a421SHawking Zhang } 236c6b6a421SHawking Zhang } 237c6b6a421SHawking Zhang 238c6b6a421SHawking Zhang static int nv_read_register(struct amdgpu_device *adev, u32 se_num, 239c6b6a421SHawking Zhang u32 sh_num, u32 reg_offset, u32 *value) 240c6b6a421SHawking Zhang { 241c6b6a421SHawking Zhang uint32_t i; 242c6b6a421SHawking Zhang struct soc15_allowed_register_entry *en; 243c6b6a421SHawking Zhang 244c6b6a421SHawking Zhang *value = 0; 245c6b6a421SHawking Zhang for (i = 0; i < ARRAY_SIZE(nv_allowed_read_registers); i++) { 246c6b6a421SHawking Zhang en = &nv_allowed_read_registers[i]; 247c6b6a421SHawking Zhang if (reg_offset != 248c6b6a421SHawking Zhang (adev->reg_offset[en->hwip][en->inst][en->seg] + en->reg_offset)) 249c6b6a421SHawking Zhang continue; 250c6b6a421SHawking Zhang 251c6b6a421SHawking Zhang *value = nv_get_register_value(adev, 252c6b6a421SHawking Zhang nv_allowed_read_registers[i].grbm_indexed, 253c6b6a421SHawking Zhang se_num, sh_num, reg_offset); 254c6b6a421SHawking Zhang return 0; 255c6b6a421SHawking Zhang } 256c6b6a421SHawking Zhang return -EINVAL; 257c6b6a421SHawking Zhang } 258c6b6a421SHawking Zhang 2593e2bb60aSKevin Wang static int nv_asic_mode1_reset(struct amdgpu_device *adev) 2603e2bb60aSKevin Wang { 2613e2bb60aSKevin Wang u32 i; 2623e2bb60aSKevin Wang int ret = 0; 2633e2bb60aSKevin Wang 2643e2bb60aSKevin Wang amdgpu_atombios_scratch_regs_engine_hung(adev, true); 2653e2bb60aSKevin Wang 2663e2bb60aSKevin Wang dev_info(adev->dev, "GPU mode1 reset\n"); 2673e2bb60aSKevin Wang 2683e2bb60aSKevin Wang /* disable BM */ 2693e2bb60aSKevin Wang pci_clear_master(adev->pdev); 2703e2bb60aSKevin Wang 2713e2bb60aSKevin Wang pci_save_state(adev->pdev); 2723e2bb60aSKevin Wang 2733e2bb60aSKevin Wang ret = psp_gpu_reset(adev); 2743e2bb60aSKevin Wang if (ret) 2753e2bb60aSKevin Wang dev_err(adev->dev, "GPU mode1 reset failed\n"); 2763e2bb60aSKevin Wang 2773e2bb60aSKevin Wang pci_restore_state(adev->pdev); 2783e2bb60aSKevin Wang 2793e2bb60aSKevin Wang /* wait for asic to come out of reset */ 2803e2bb60aSKevin Wang for (i = 0; i < adev->usec_timeout; i++) { 281bebc0762SHawking Zhang u32 memsize = adev->nbio.funcs->get_memsize(adev); 2823e2bb60aSKevin Wang 2833e2bb60aSKevin Wang if (memsize != 0xffffffff) 2843e2bb60aSKevin Wang break; 2853e2bb60aSKevin Wang udelay(1); 2863e2bb60aSKevin Wang } 2873e2bb60aSKevin Wang 2883e2bb60aSKevin Wang amdgpu_atombios_scratch_regs_engine_hung(adev, false); 2893e2bb60aSKevin Wang 2903e2bb60aSKevin Wang return ret; 2913e2bb60aSKevin Wang } 2922ddc6c3eSAlex Deucher 293ac742616SAlex Deucher static bool nv_asic_supports_baco(struct amdgpu_device *adev) 294ac742616SAlex Deucher { 295ac742616SAlex Deucher struct smu_context *smu = &adev->smu; 296ac742616SAlex Deucher 297ac742616SAlex Deucher if (smu_baco_is_support(smu)) 298ac742616SAlex Deucher return true; 299ac742616SAlex Deucher else 300ac742616SAlex Deucher return false; 301ac742616SAlex Deucher } 302ac742616SAlex Deucher 3032ddc6c3eSAlex Deucher static enum amd_reset_method 3042ddc6c3eSAlex Deucher nv_asic_reset_method(struct amdgpu_device *adev) 3052ddc6c3eSAlex Deucher { 3062ddc6c3eSAlex Deucher struct smu_context *smu = &adev->smu; 3072ddc6c3eSAlex Deucher 308b4def374SJiange Zhao if (!amdgpu_sriov_vf(adev) && smu_baco_is_support(smu)) 3092ddc6c3eSAlex Deucher return AMD_RESET_METHOD_BACO; 3102ddc6c3eSAlex Deucher else 3112ddc6c3eSAlex Deucher return AMD_RESET_METHOD_MODE1; 3122ddc6c3eSAlex Deucher } 3132ddc6c3eSAlex Deucher 314c6b6a421SHawking Zhang static int nv_asic_reset(struct amdgpu_device *adev) 315c6b6a421SHawking Zhang { 316767acabdSKevin Wang int ret = 0; 317767acabdSKevin Wang struct smu_context *smu = &adev->smu; 318c6b6a421SHawking Zhang 319e3526257SMonk Liu if (nv_asic_reset_method(adev) == AMD_RESET_METHOD_BACO) { 32011520f27SAlex Deucher ret = smu_baco_enter(smu); 32111520f27SAlex Deucher if (ret) 32211520f27SAlex Deucher return ret; 32311520f27SAlex Deucher ret = smu_baco_exit(smu); 32411520f27SAlex Deucher if (ret) 32511520f27SAlex Deucher return ret; 326e3526257SMonk Liu } else { 3273e2bb60aSKevin Wang ret = nv_asic_mode1_reset(adev); 328e3526257SMonk Liu } 329767acabdSKevin Wang 330767acabdSKevin Wang return ret; 331c6b6a421SHawking Zhang } 332c6b6a421SHawking Zhang 333c6b6a421SHawking Zhang static int nv_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk) 334c6b6a421SHawking Zhang { 335c6b6a421SHawking Zhang /* todo */ 336c6b6a421SHawking Zhang return 0; 337c6b6a421SHawking Zhang } 338c6b6a421SHawking Zhang 339c6b6a421SHawking Zhang static int nv_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk) 340c6b6a421SHawking Zhang { 341c6b6a421SHawking Zhang /* todo */ 342c6b6a421SHawking Zhang return 0; 343c6b6a421SHawking Zhang } 344c6b6a421SHawking Zhang 345c6b6a421SHawking Zhang static void nv_pcie_gen3_enable(struct amdgpu_device *adev) 346c6b6a421SHawking Zhang { 347c6b6a421SHawking Zhang if (pci_is_root_bus(adev->pdev->bus)) 348c6b6a421SHawking Zhang return; 349c6b6a421SHawking Zhang 350c6b6a421SHawking Zhang if (amdgpu_pcie_gen2 == 0) 351c6b6a421SHawking Zhang return; 352c6b6a421SHawking Zhang 353c6b6a421SHawking Zhang if (!(adev->pm.pcie_gen_mask & (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 | 354c6b6a421SHawking Zhang CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3))) 355c6b6a421SHawking Zhang return; 356c6b6a421SHawking Zhang 357c6b6a421SHawking Zhang /* todo */ 358c6b6a421SHawking Zhang } 359c6b6a421SHawking Zhang 360c6b6a421SHawking Zhang static void nv_program_aspm(struct amdgpu_device *adev) 361c6b6a421SHawking Zhang { 362c6b6a421SHawking Zhang 363c6b6a421SHawking Zhang if (amdgpu_aspm == 0) 364c6b6a421SHawking Zhang return; 365c6b6a421SHawking Zhang 366c6b6a421SHawking Zhang /* todo */ 367c6b6a421SHawking Zhang } 368c6b6a421SHawking Zhang 369c6b6a421SHawking Zhang static void nv_enable_doorbell_aperture(struct amdgpu_device *adev, 370c6b6a421SHawking Zhang bool enable) 371c6b6a421SHawking Zhang { 372bebc0762SHawking Zhang adev->nbio.funcs->enable_doorbell_aperture(adev, enable); 373bebc0762SHawking Zhang adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, enable); 374c6b6a421SHawking Zhang } 375c6b6a421SHawking Zhang 376c6b6a421SHawking Zhang static const struct amdgpu_ip_block_version nv_common_ip_block = 377c6b6a421SHawking Zhang { 378c6b6a421SHawking Zhang .type = AMD_IP_BLOCK_TYPE_COMMON, 379c6b6a421SHawking Zhang .major = 1, 380c6b6a421SHawking Zhang .minor = 0, 381c6b6a421SHawking Zhang .rev = 0, 382c6b6a421SHawking Zhang .funcs = &nv_common_ip_funcs, 383c6b6a421SHawking Zhang }; 384c6b6a421SHawking Zhang 385b5c73856SXiaojie Yuan static int nv_reg_base_init(struct amdgpu_device *adev) 386c6b6a421SHawking Zhang { 387b5c73856SXiaojie Yuan int r; 388b5c73856SXiaojie Yuan 389b5c73856SXiaojie Yuan if (amdgpu_discovery) { 390b5c73856SXiaojie Yuan r = amdgpu_discovery_reg_base_init(adev); 391b5c73856SXiaojie Yuan if (r) { 392b5c73856SXiaojie Yuan DRM_WARN("failed to init reg base from ip discovery table, " 393b5c73856SXiaojie Yuan "fallback to legacy init method\n"); 394b5c73856SXiaojie Yuan goto legacy_init; 395b5c73856SXiaojie Yuan } 396b5c73856SXiaojie Yuan 397b5c73856SXiaojie Yuan return 0; 398b5c73856SXiaojie Yuan } 399b5c73856SXiaojie Yuan 400b5c73856SXiaojie Yuan legacy_init: 401c6b6a421SHawking Zhang switch (adev->asic_type) { 402c6b6a421SHawking Zhang case CHIP_NAVI10: 403c6b6a421SHawking Zhang navi10_reg_base_init(adev); 404c6b6a421SHawking Zhang break; 405a0f6d926SXiaojie Yuan case CHIP_NAVI14: 406a0f6d926SXiaojie Yuan navi14_reg_base_init(adev); 407a0f6d926SXiaojie Yuan break; 40803d0a073SXiaojie Yuan case CHIP_NAVI12: 40903d0a073SXiaojie Yuan navi12_reg_base_init(adev); 41003d0a073SXiaojie Yuan break; 411dccdbf3fSLikun Gao case CHIP_SIENNA_CICHLID: 412dccdbf3fSLikun Gao sienna_cichlid_reg_base_init(adev); 413dccdbf3fSLikun Gao break; 414c6b6a421SHawking Zhang default: 415c6b6a421SHawking Zhang return -EINVAL; 416c6b6a421SHawking Zhang } 417c6b6a421SHawking Zhang 418b5c73856SXiaojie Yuan return 0; 419b5c73856SXiaojie Yuan } 420b5c73856SXiaojie Yuan 421b5c73856SXiaojie Yuan int nv_set_ip_blocks(struct amdgpu_device *adev) 422b5c73856SXiaojie Yuan { 423b5c73856SXiaojie Yuan int r; 424b5c73856SXiaojie Yuan 425122078deSMonk Liu adev->nbio.funcs = &nbio_v2_3_funcs; 426122078deSMonk Liu adev->nbio.hdp_flush_reg = &nbio_v2_3_hdp_flush_reg; 427122078deSMonk Liu 428122078deSMonk Liu if (amdgpu_sriov_vf(adev)) { 429122078deSMonk Liu adev->virt.ops = &xgpu_nv_virt_ops; 430122078deSMonk Liu /* try send GPU_INIT_DATA request to host */ 431122078deSMonk Liu amdgpu_virt_request_init_data(adev); 432122078deSMonk Liu } 433122078deSMonk Liu 434b5c73856SXiaojie Yuan /* Set IP register base before any HW register access */ 435b5c73856SXiaojie Yuan r = nv_reg_base_init(adev); 436b5c73856SXiaojie Yuan if (r) 437b5c73856SXiaojie Yuan return r; 438b5c73856SXiaojie Yuan 439c6b6a421SHawking Zhang switch (adev->asic_type) { 440c6b6a421SHawking Zhang case CHIP_NAVI10: 441d1daf850SAlex Deucher case CHIP_NAVI14: 442c6b6a421SHawking Zhang amdgpu_device_ip_block_add(adev, &nv_common_ip_block); 443c6b6a421SHawking Zhang amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block); 444c6b6a421SHawking Zhang amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block); 445c6b6a421SHawking Zhang amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block); 446c6b6a421SHawking Zhang if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP && 4479530273eSEvan Quan !amdgpu_sriov_vf(adev)) 448c6b6a421SHawking Zhang amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 449c6b6a421SHawking Zhang if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) 450c6b6a421SHawking Zhang amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block); 451f8a7976bSAlex Deucher #if defined(CONFIG_DRM_AMD_DC) 452b4f199c7SHarry Wentland else if (amdgpu_device_has_dc_support(adev)) 453b4f199c7SHarry Wentland amdgpu_device_ip_block_add(adev, &dm_ip_block); 454f8a7976bSAlex Deucher #endif 455c6b6a421SHawking Zhang amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block); 456c6b6a421SHawking Zhang amdgpu_device_ip_block_add(adev, &sdma_v5_0_ip_block); 457c6b6a421SHawking Zhang if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT && 4589530273eSEvan Quan !amdgpu_sriov_vf(adev)) 459c6b6a421SHawking Zhang amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 460c6b6a421SHawking Zhang amdgpu_device_ip_block_add(adev, &vcn_v2_0_ip_block); 4615be45a26SLeo Liu amdgpu_device_ip_block_add(adev, &jpeg_v2_0_ip_block); 462c6b6a421SHawking Zhang if (adev->enable_mes) 463c6b6a421SHawking Zhang amdgpu_device_ip_block_add(adev, &mes_v10_1_ip_block); 464c6b6a421SHawking Zhang break; 46544e9e7c9SXiaojie Yuan case CHIP_NAVI12: 46644e9e7c9SXiaojie Yuan amdgpu_device_ip_block_add(adev, &nv_common_ip_block); 46744e9e7c9SXiaojie Yuan amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block); 46844e9e7c9SXiaojie Yuan amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block); 4696b66ae2eSXiaojie Yuan amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block); 47079bebabbSMonk Liu if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) 4717f47efebSXiaojie Yuan amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 47279902029SXiaojie Yuan if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) 47379902029SXiaojie Yuan amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block); 47420c14ee1SPetr Cvek #if defined(CONFIG_DRM_AMD_DC) 475078655d9SLeo Li else if (amdgpu_device_has_dc_support(adev)) 476078655d9SLeo Li amdgpu_device_ip_block_add(adev, &dm_ip_block); 47720c14ee1SPetr Cvek #endif 47844e9e7c9SXiaojie Yuan amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block); 47944e9e7c9SXiaojie Yuan amdgpu_device_ip_block_add(adev, &sdma_v5_0_ip_block); 4807f47efebSXiaojie Yuan if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT && 4819530273eSEvan Quan !amdgpu_sriov_vf(adev)) 4827f47efebSXiaojie Yuan amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 4831fbed280SBoyuan Zhang amdgpu_device_ip_block_add(adev, &vcn_v2_0_ip_block); 484fe442491SMonk Liu if (!amdgpu_sriov_vf(adev)) 4855be45a26SLeo Liu amdgpu_device_ip_block_add(adev, &jpeg_v2_0_ip_block); 48644e9e7c9SXiaojie Yuan break; 4872e1ba10eSLikun Gao case CHIP_SIENNA_CICHLID: 4882e1ba10eSLikun Gao amdgpu_device_ip_block_add(adev, &nv_common_ip_block); 4890b3df16bSLikun Gao amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block); 490757b3af8SLikun Gao amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block); 49156304e72SLikun Gao if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) 4925aa02350SLikun Gao amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block); 493b07e5c60SLikun Gao if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP && 494b07e5c60SLikun Gao is_support_sw_smu(adev)) 495b07e5c60SLikun Gao amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 4969a986760SLikun Gao if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) 4979a986760SLikun Gao amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block); 498933c8a93SLikun Gao amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block); 499157e72e8SLikun Gao amdgpu_device_ip_block_add(adev, &sdma_v5_2_ip_block); 5002e1ba10eSLikun Gao break; 501c6b6a421SHawking Zhang default: 502c6b6a421SHawking Zhang return -EINVAL; 503c6b6a421SHawking Zhang } 504c6b6a421SHawking Zhang 505c6b6a421SHawking Zhang return 0; 506c6b6a421SHawking Zhang } 507c6b6a421SHawking Zhang 508c6b6a421SHawking Zhang static uint32_t nv_get_rev_id(struct amdgpu_device *adev) 509c6b6a421SHawking Zhang { 510bebc0762SHawking Zhang return adev->nbio.funcs->get_rev_id(adev); 511c6b6a421SHawking Zhang } 512c6b6a421SHawking Zhang 513c6b6a421SHawking Zhang static void nv_flush_hdp(struct amdgpu_device *adev, struct amdgpu_ring *ring) 514c6b6a421SHawking Zhang { 515bebc0762SHawking Zhang adev->nbio.funcs->hdp_flush(adev, ring); 516c6b6a421SHawking Zhang } 517c6b6a421SHawking Zhang 518c6b6a421SHawking Zhang static void nv_invalidate_hdp(struct amdgpu_device *adev, 519c6b6a421SHawking Zhang struct amdgpu_ring *ring) 520c6b6a421SHawking Zhang { 521c6b6a421SHawking Zhang if (!ring || !ring->funcs->emit_wreg) { 522c6b6a421SHawking Zhang WREG32_SOC15_NO_KIQ(NBIO, 0, mmHDP_READ_CACHE_INVALIDATE, 1); 523c6b6a421SHawking Zhang } else { 524c6b6a421SHawking Zhang amdgpu_ring_emit_wreg(ring, SOC15_REG_OFFSET( 525c6b6a421SHawking Zhang HDP, 0, mmHDP_READ_CACHE_INVALIDATE), 1); 526c6b6a421SHawking Zhang } 527c6b6a421SHawking Zhang } 528c6b6a421SHawking Zhang 529c6b6a421SHawking Zhang static bool nv_need_full_reset(struct amdgpu_device *adev) 530c6b6a421SHawking Zhang { 531c6b6a421SHawking Zhang return true; 532c6b6a421SHawking Zhang } 533c6b6a421SHawking Zhang 534c6b6a421SHawking Zhang static bool nv_need_reset_on_init(struct amdgpu_device *adev) 535c6b6a421SHawking Zhang { 536c6b6a421SHawking Zhang u32 sol_reg; 537c6b6a421SHawking Zhang 538c6b6a421SHawking Zhang if (adev->flags & AMD_IS_APU) 539c6b6a421SHawking Zhang return false; 540c6b6a421SHawking Zhang 541c6b6a421SHawking Zhang /* Check sOS sign of life register to confirm sys driver and sOS 542c6b6a421SHawking Zhang * are already been loaded. 543c6b6a421SHawking Zhang */ 544c6b6a421SHawking Zhang sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81); 545c6b6a421SHawking Zhang if (sol_reg) 546c6b6a421SHawking Zhang return true; 5473967ae6dSAlex Deucher 548c6b6a421SHawking Zhang return false; 549c6b6a421SHawking Zhang } 550c6b6a421SHawking Zhang 5512af81531SKevin Wang static uint64_t nv_get_pcie_replay_count(struct amdgpu_device *adev) 5522af81531SKevin Wang { 5532af81531SKevin Wang 5542af81531SKevin Wang /* TODO 5552af81531SKevin Wang * dummy implement for pcie_replay_count sysfs interface 5562af81531SKevin Wang * */ 5572af81531SKevin Wang 5582af81531SKevin Wang return 0; 5592af81531SKevin Wang } 5602af81531SKevin Wang 561c6b6a421SHawking Zhang static void nv_init_doorbell_index(struct amdgpu_device *adev) 562c6b6a421SHawking Zhang { 563c6b6a421SHawking Zhang adev->doorbell_index.kiq = AMDGPU_NAVI10_DOORBELL_KIQ; 564c6b6a421SHawking Zhang adev->doorbell_index.mec_ring0 = AMDGPU_NAVI10_DOORBELL_MEC_RING0; 565c6b6a421SHawking Zhang adev->doorbell_index.mec_ring1 = AMDGPU_NAVI10_DOORBELL_MEC_RING1; 566c6b6a421SHawking Zhang adev->doorbell_index.mec_ring2 = AMDGPU_NAVI10_DOORBELL_MEC_RING2; 567c6b6a421SHawking Zhang adev->doorbell_index.mec_ring3 = AMDGPU_NAVI10_DOORBELL_MEC_RING3; 568c6b6a421SHawking Zhang adev->doorbell_index.mec_ring4 = AMDGPU_NAVI10_DOORBELL_MEC_RING4; 569c6b6a421SHawking Zhang adev->doorbell_index.mec_ring5 = AMDGPU_NAVI10_DOORBELL_MEC_RING5; 570c6b6a421SHawking Zhang adev->doorbell_index.mec_ring6 = AMDGPU_NAVI10_DOORBELL_MEC_RING6; 571c6b6a421SHawking Zhang adev->doorbell_index.mec_ring7 = AMDGPU_NAVI10_DOORBELL_MEC_RING7; 572c6b6a421SHawking Zhang adev->doorbell_index.userqueue_start = AMDGPU_NAVI10_DOORBELL_USERQUEUE_START; 573c6b6a421SHawking Zhang adev->doorbell_index.userqueue_end = AMDGPU_NAVI10_DOORBELL_USERQUEUE_END; 574c6b6a421SHawking Zhang adev->doorbell_index.gfx_ring0 = AMDGPU_NAVI10_DOORBELL_GFX_RING0; 575c6b6a421SHawking Zhang adev->doorbell_index.gfx_ring1 = AMDGPU_NAVI10_DOORBELL_GFX_RING1; 57620519232SJack Xiao adev->doorbell_index.mes_ring = AMDGPU_NAVI10_DOORBELL_MES_RING; 577c6b6a421SHawking Zhang adev->doorbell_index.sdma_engine[0] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE0; 578c6b6a421SHawking Zhang adev->doorbell_index.sdma_engine[1] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE1; 579157e72e8SLikun Gao adev->doorbell_index.sdma_engine[2] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE2; 580157e72e8SLikun Gao adev->doorbell_index.sdma_engine[3] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE3; 581c6b6a421SHawking Zhang adev->doorbell_index.ih = AMDGPU_NAVI10_DOORBELL_IH; 582c6b6a421SHawking Zhang adev->doorbell_index.vcn.vcn_ring0_1 = AMDGPU_NAVI10_DOORBELL64_VCN0_1; 583c6b6a421SHawking Zhang adev->doorbell_index.vcn.vcn_ring2_3 = AMDGPU_NAVI10_DOORBELL64_VCN2_3; 584c6b6a421SHawking Zhang adev->doorbell_index.vcn.vcn_ring4_5 = AMDGPU_NAVI10_DOORBELL64_VCN4_5; 585c6b6a421SHawking Zhang adev->doorbell_index.vcn.vcn_ring6_7 = AMDGPU_NAVI10_DOORBELL64_VCN6_7; 586c6b6a421SHawking Zhang adev->doorbell_index.first_non_cp = AMDGPU_NAVI10_DOORBELL64_FIRST_NON_CP; 587c6b6a421SHawking Zhang adev->doorbell_index.last_non_cp = AMDGPU_NAVI10_DOORBELL64_LAST_NON_CP; 588c6b6a421SHawking Zhang 589c6b6a421SHawking Zhang adev->doorbell_index.max_assignment = AMDGPU_NAVI10_DOORBELL_MAX_ASSIGNMENT << 1; 590c6b6a421SHawking Zhang adev->doorbell_index.sdma_doorbell_range = 20; 591c6b6a421SHawking Zhang } 592c6b6a421SHawking Zhang 593c6b6a421SHawking Zhang static const struct amdgpu_asic_funcs nv_asic_funcs = 594c6b6a421SHawking Zhang { 595c6b6a421SHawking Zhang .read_disabled_bios = &nv_read_disabled_bios, 596c6b6a421SHawking Zhang .read_bios_from_rom = &nv_read_bios_from_rom, 597c6b6a421SHawking Zhang .read_register = &nv_read_register, 598c6b6a421SHawking Zhang .reset = &nv_asic_reset, 5992ddc6c3eSAlex Deucher .reset_method = &nv_asic_reset_method, 600c6b6a421SHawking Zhang .set_vga_state = &nv_vga_set_state, 601c6b6a421SHawking Zhang .get_xclk = &nv_get_xclk, 602c6b6a421SHawking Zhang .set_uvd_clocks = &nv_set_uvd_clocks, 603c6b6a421SHawking Zhang .set_vce_clocks = &nv_set_vce_clocks, 604c6b6a421SHawking Zhang .get_config_memsize = &nv_get_config_memsize, 605c6b6a421SHawking Zhang .flush_hdp = &nv_flush_hdp, 606c6b6a421SHawking Zhang .invalidate_hdp = &nv_invalidate_hdp, 607c6b6a421SHawking Zhang .init_doorbell_index = &nv_init_doorbell_index, 608c6b6a421SHawking Zhang .need_full_reset = &nv_need_full_reset, 609c6b6a421SHawking Zhang .need_reset_on_init = &nv_need_reset_on_init, 6102af81531SKevin Wang .get_pcie_replay_count = &nv_get_pcie_replay_count, 611ac742616SAlex Deucher .supports_baco = &nv_asic_supports_baco, 612c6b6a421SHawking Zhang }; 613c6b6a421SHawking Zhang 614c6b6a421SHawking Zhang static int nv_common_early_init(void *handle) 615c6b6a421SHawking Zhang { 616923c087aSYong Zhao #define MMIO_REG_HOLE_OFFSET (0x80000 - PAGE_SIZE) 617c6b6a421SHawking Zhang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 618c6b6a421SHawking Zhang 619923c087aSYong Zhao adev->rmmio_remap.reg_offset = MMIO_REG_HOLE_OFFSET; 620923c087aSYong Zhao adev->rmmio_remap.bus_addr = adev->rmmio_base + MMIO_REG_HOLE_OFFSET; 621c6b6a421SHawking Zhang adev->smc_rreg = NULL; 622c6b6a421SHawking Zhang adev->smc_wreg = NULL; 623c6b6a421SHawking Zhang adev->pcie_rreg = &nv_pcie_rreg; 624c6b6a421SHawking Zhang adev->pcie_wreg = &nv_pcie_wreg; 625c6b6a421SHawking Zhang 626c6b6a421SHawking Zhang /* TODO: will add them during VCN v2 implementation */ 627c6b6a421SHawking Zhang adev->uvd_ctx_rreg = NULL; 628c6b6a421SHawking Zhang adev->uvd_ctx_wreg = NULL; 629c6b6a421SHawking Zhang 630c6b6a421SHawking Zhang adev->didt_rreg = &nv_didt_rreg; 631c6b6a421SHawking Zhang adev->didt_wreg = &nv_didt_wreg; 632c6b6a421SHawking Zhang 633c6b6a421SHawking Zhang adev->asic_funcs = &nv_asic_funcs; 634c6b6a421SHawking Zhang 635c6b6a421SHawking Zhang adev->rev_id = nv_get_rev_id(adev); 636c6b6a421SHawking Zhang adev->external_rev_id = 0xff; 637c6b6a421SHawking Zhang switch (adev->asic_type) { 638c6b6a421SHawking Zhang case CHIP_NAVI10: 639c6b6a421SHawking Zhang adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 640c6b6a421SHawking Zhang AMD_CG_SUPPORT_GFX_CGCG | 641c6b6a421SHawking Zhang AMD_CG_SUPPORT_IH_CG | 642c6b6a421SHawking Zhang AMD_CG_SUPPORT_HDP_MGCG | 643c6b6a421SHawking Zhang AMD_CG_SUPPORT_HDP_LS | 644c6b6a421SHawking Zhang AMD_CG_SUPPORT_SDMA_MGCG | 645c6b6a421SHawking Zhang AMD_CG_SUPPORT_SDMA_LS | 646c6b6a421SHawking Zhang AMD_CG_SUPPORT_MC_MGCG | 647c6b6a421SHawking Zhang AMD_CG_SUPPORT_MC_LS | 648c6b6a421SHawking Zhang AMD_CG_SUPPORT_ATHUB_MGCG | 649c6b6a421SHawking Zhang AMD_CG_SUPPORT_ATHUB_LS | 650c6b6a421SHawking Zhang AMD_CG_SUPPORT_VCN_MGCG | 651099d66e4SLeo Liu AMD_CG_SUPPORT_JPEG_MGCG | 652c6b6a421SHawking Zhang AMD_CG_SUPPORT_BIF_MGCG | 653c6b6a421SHawking Zhang AMD_CG_SUPPORT_BIF_LS; 654157710eaSLeo Liu adev->pg_flags = AMD_PG_SUPPORT_VCN | 655c12d410fSHuang Rui AMD_PG_SUPPORT_VCN_DPG | 656099d66e4SLeo Liu AMD_PG_SUPPORT_JPEG | 657a201b6acSHuang Rui AMD_PG_SUPPORT_ATHUB; 658c6b6a421SHawking Zhang adev->external_rev_id = adev->rev_id + 0x1; 659c6b6a421SHawking Zhang break; 6605e71e011SXiaojie Yuan case CHIP_NAVI14: 661d0c39f8cSXiaojie Yuan adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 662d0c39f8cSXiaojie Yuan AMD_CG_SUPPORT_GFX_CGCG | 663d0c39f8cSXiaojie Yuan AMD_CG_SUPPORT_IH_CG | 664d0c39f8cSXiaojie Yuan AMD_CG_SUPPORT_HDP_MGCG | 665d0c39f8cSXiaojie Yuan AMD_CG_SUPPORT_HDP_LS | 666d0c39f8cSXiaojie Yuan AMD_CG_SUPPORT_SDMA_MGCG | 667d0c39f8cSXiaojie Yuan AMD_CG_SUPPORT_SDMA_LS | 668d0c39f8cSXiaojie Yuan AMD_CG_SUPPORT_MC_MGCG | 669d0c39f8cSXiaojie Yuan AMD_CG_SUPPORT_MC_LS | 670d0c39f8cSXiaojie Yuan AMD_CG_SUPPORT_ATHUB_MGCG | 671d0c39f8cSXiaojie Yuan AMD_CG_SUPPORT_ATHUB_LS | 672d0c39f8cSXiaojie Yuan AMD_CG_SUPPORT_VCN_MGCG | 673099d66e4SLeo Liu AMD_CG_SUPPORT_JPEG_MGCG | 674d0c39f8cSXiaojie Yuan AMD_CG_SUPPORT_BIF_MGCG | 675d0c39f8cSXiaojie Yuan AMD_CG_SUPPORT_BIF_LS; 6760377b088SXiaojie Yuan adev->pg_flags = AMD_PG_SUPPORT_VCN | 677099d66e4SLeo Liu AMD_PG_SUPPORT_JPEG | 6780377b088SXiaojie Yuan AMD_PG_SUPPORT_VCN_DPG; 67935ef88faStiancyin adev->external_rev_id = adev->rev_id + 20; 6805e71e011SXiaojie Yuan break; 68174b5e509SXiaojie Yuan case CHIP_NAVI12: 682dca009e7SXiaojie Yuan adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 683dca009e7SXiaojie Yuan AMD_CG_SUPPORT_GFX_MGLS | 684dca009e7SXiaojie Yuan AMD_CG_SUPPORT_GFX_CGCG | 685dca009e7SXiaojie Yuan AMD_CG_SUPPORT_GFX_CP_LS | 6865211c37aSXiaojie Yuan AMD_CG_SUPPORT_GFX_RLC_LS | 687fbe0bc57SXiaojie Yuan AMD_CG_SUPPORT_IH_CG | 6885211c37aSXiaojie Yuan AMD_CG_SUPPORT_HDP_MGCG | 689358ab97fSXiaojie Yuan AMD_CG_SUPPORT_HDP_LS | 690358ab97fSXiaojie Yuan AMD_CG_SUPPORT_SDMA_MGCG | 6918b797b3dSXiaojie Yuan AMD_CG_SUPPORT_SDMA_LS | 6928b797b3dSXiaojie Yuan AMD_CG_SUPPORT_MC_MGCG | 693ca51678dSXiaojie Yuan AMD_CG_SUPPORT_MC_LS | 694ca51678dSXiaojie Yuan AMD_CG_SUPPORT_ATHUB_MGCG | 69565872e59SXiaojie Yuan AMD_CG_SUPPORT_ATHUB_LS | 696099d66e4SLeo Liu AMD_CG_SUPPORT_VCN_MGCG | 697099d66e4SLeo Liu AMD_CG_SUPPORT_JPEG_MGCG; 698c1653ea0SXiaojie Yuan adev->pg_flags = AMD_PG_SUPPORT_VCN | 6995ef3b8acSXiaojie Yuan AMD_PG_SUPPORT_VCN_DPG | 700099d66e4SLeo Liu AMD_PG_SUPPORT_JPEG | 7015ef3b8acSXiaojie Yuan AMD_PG_SUPPORT_ATHUB; 702df5e984cSTiecheng Zhou /* guest vm gets 0xffffffff when reading RCC_DEV0_EPF0_STRAP0, 703df5e984cSTiecheng Zhou * as a consequence, the rev_id and external_rev_id are wrong. 704df5e984cSTiecheng Zhou * workaround it by hardcoding rev_id to 0 (default value). 705df5e984cSTiecheng Zhou */ 706df5e984cSTiecheng Zhou if (amdgpu_sriov_vf(adev)) 707df5e984cSTiecheng Zhou adev->rev_id = 0; 70874b5e509SXiaojie Yuan adev->external_rev_id = adev->rev_id + 0xa; 70974b5e509SXiaojie Yuan break; 710117910edSLikun Gao case CHIP_SIENNA_CICHLID: 711117910edSLikun Gao adev->cg_flags = 0; 712117910edSLikun Gao adev->pg_flags = 0; 713117910edSLikun Gao adev->external_rev_id = adev->rev_id + 0x28; 714117910edSLikun Gao break; 715c6b6a421SHawking Zhang default: 716c6b6a421SHawking Zhang /* FIXME: not supported yet */ 717c6b6a421SHawking Zhang return -EINVAL; 718c6b6a421SHawking Zhang } 719c6b6a421SHawking Zhang 720b05b6903SJiange Zhao if (amdgpu_sriov_vf(adev)) { 721b05b6903SJiange Zhao amdgpu_virt_init_setting(adev); 722b05b6903SJiange Zhao xgpu_nv_mailbox_set_irq_funcs(adev); 723b05b6903SJiange Zhao } 724b05b6903SJiange Zhao 725c6b6a421SHawking Zhang return 0; 726c6b6a421SHawking Zhang } 727c6b6a421SHawking Zhang 728c6b6a421SHawking Zhang static int nv_common_late_init(void *handle) 729c6b6a421SHawking Zhang { 730b05b6903SJiange Zhao struct amdgpu_device *adev = (struct amdgpu_device *)handle; 731b05b6903SJiange Zhao 732b05b6903SJiange Zhao if (amdgpu_sriov_vf(adev)) 733b05b6903SJiange Zhao xgpu_nv_mailbox_get_irq(adev); 734b05b6903SJiange Zhao 735c6b6a421SHawking Zhang return 0; 736c6b6a421SHawking Zhang } 737c6b6a421SHawking Zhang 738c6b6a421SHawking Zhang static int nv_common_sw_init(void *handle) 739c6b6a421SHawking Zhang { 740b05b6903SJiange Zhao struct amdgpu_device *adev = (struct amdgpu_device *)handle; 741b05b6903SJiange Zhao 742b05b6903SJiange Zhao if (amdgpu_sriov_vf(adev)) 743b05b6903SJiange Zhao xgpu_nv_mailbox_add_irq_id(adev); 744b05b6903SJiange Zhao 745c6b6a421SHawking Zhang return 0; 746c6b6a421SHawking Zhang } 747c6b6a421SHawking Zhang 748c6b6a421SHawking Zhang static int nv_common_sw_fini(void *handle) 749c6b6a421SHawking Zhang { 750c6b6a421SHawking Zhang return 0; 751c6b6a421SHawking Zhang } 752c6b6a421SHawking Zhang 753c6b6a421SHawking Zhang static int nv_common_hw_init(void *handle) 754c6b6a421SHawking Zhang { 755c6b6a421SHawking Zhang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 756c6b6a421SHawking Zhang 757c6b6a421SHawking Zhang /* enable pcie gen2/3 link */ 758c6b6a421SHawking Zhang nv_pcie_gen3_enable(adev); 759c6b6a421SHawking Zhang /* enable aspm */ 760c6b6a421SHawking Zhang nv_program_aspm(adev); 761c6b6a421SHawking Zhang /* setup nbio registers */ 762bebc0762SHawking Zhang adev->nbio.funcs->init_registers(adev); 763923c087aSYong Zhao /* remap HDP registers to a hole in mmio space, 764923c087aSYong Zhao * for the purpose of expose those registers 765923c087aSYong Zhao * to process space 766923c087aSYong Zhao */ 767923c087aSYong Zhao if (adev->nbio.funcs->remap_hdp_registers) 768923c087aSYong Zhao adev->nbio.funcs->remap_hdp_registers(adev); 769c6b6a421SHawking Zhang /* enable the doorbell aperture */ 770c6b6a421SHawking Zhang nv_enable_doorbell_aperture(adev, true); 771c6b6a421SHawking Zhang 772c6b6a421SHawking Zhang return 0; 773c6b6a421SHawking Zhang } 774c6b6a421SHawking Zhang 775c6b6a421SHawking Zhang static int nv_common_hw_fini(void *handle) 776c6b6a421SHawking Zhang { 777c6b6a421SHawking Zhang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 778c6b6a421SHawking Zhang 779c6b6a421SHawking Zhang /* disable the doorbell aperture */ 780c6b6a421SHawking Zhang nv_enable_doorbell_aperture(adev, false); 781c6b6a421SHawking Zhang 782c6b6a421SHawking Zhang return 0; 783c6b6a421SHawking Zhang } 784c6b6a421SHawking Zhang 785c6b6a421SHawking Zhang static int nv_common_suspend(void *handle) 786c6b6a421SHawking Zhang { 787c6b6a421SHawking Zhang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 788c6b6a421SHawking Zhang 789c6b6a421SHawking Zhang return nv_common_hw_fini(adev); 790c6b6a421SHawking Zhang } 791c6b6a421SHawking Zhang 792c6b6a421SHawking Zhang static int nv_common_resume(void *handle) 793c6b6a421SHawking Zhang { 794c6b6a421SHawking Zhang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 795c6b6a421SHawking Zhang 796c6b6a421SHawking Zhang return nv_common_hw_init(adev); 797c6b6a421SHawking Zhang } 798c6b6a421SHawking Zhang 799c6b6a421SHawking Zhang static bool nv_common_is_idle(void *handle) 800c6b6a421SHawking Zhang { 801c6b6a421SHawking Zhang return true; 802c6b6a421SHawking Zhang } 803c6b6a421SHawking Zhang 804c6b6a421SHawking Zhang static int nv_common_wait_for_idle(void *handle) 805c6b6a421SHawking Zhang { 806c6b6a421SHawking Zhang return 0; 807c6b6a421SHawking Zhang } 808c6b6a421SHawking Zhang 809c6b6a421SHawking Zhang static int nv_common_soft_reset(void *handle) 810c6b6a421SHawking Zhang { 811c6b6a421SHawking Zhang return 0; 812c6b6a421SHawking Zhang } 813c6b6a421SHawking Zhang 814c6b6a421SHawking Zhang static void nv_update_hdp_mem_power_gating(struct amdgpu_device *adev, 815c6b6a421SHawking Zhang bool enable) 816c6b6a421SHawking Zhang { 817c6b6a421SHawking Zhang uint32_t hdp_clk_cntl, hdp_clk_cntl1; 818c6b6a421SHawking Zhang uint32_t hdp_mem_pwr_cntl; 819c6b6a421SHawking Zhang 820c6b6a421SHawking Zhang if (!(adev->cg_flags & (AMD_CG_SUPPORT_HDP_LS | 821c6b6a421SHawking Zhang AMD_CG_SUPPORT_HDP_DS | 822c6b6a421SHawking Zhang AMD_CG_SUPPORT_HDP_SD))) 823c6b6a421SHawking Zhang return; 824c6b6a421SHawking Zhang 825c6b6a421SHawking Zhang hdp_clk_cntl = hdp_clk_cntl1 = RREG32_SOC15(HDP, 0, mmHDP_CLK_CNTL); 826c6b6a421SHawking Zhang hdp_mem_pwr_cntl = RREG32_SOC15(HDP, 0, mmHDP_MEM_POWER_CTRL); 827c6b6a421SHawking Zhang 828c6b6a421SHawking Zhang /* Before doing clock/power mode switch, 829c6b6a421SHawking Zhang * forced on IPH & RC clock */ 830c6b6a421SHawking Zhang hdp_clk_cntl = REG_SET_FIELD(hdp_clk_cntl, HDP_CLK_CNTL, 831c6b6a421SHawking Zhang IPH_MEM_CLK_SOFT_OVERRIDE, 1); 832c6b6a421SHawking Zhang hdp_clk_cntl = REG_SET_FIELD(hdp_clk_cntl, HDP_CLK_CNTL, 833c6b6a421SHawking Zhang RC_MEM_CLK_SOFT_OVERRIDE, 1); 834c6b6a421SHawking Zhang WREG32_SOC15(HDP, 0, mmHDP_CLK_CNTL, hdp_clk_cntl); 835c6b6a421SHawking Zhang 836c6b6a421SHawking Zhang /* HDP 5.0 doesn't support dynamic power mode switch, 837c6b6a421SHawking Zhang * disable clock and power gating before any changing */ 838c6b6a421SHawking Zhang hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, 839c6b6a421SHawking Zhang IPH_MEM_POWER_CTRL_EN, 0); 840c6b6a421SHawking Zhang hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, 841c6b6a421SHawking Zhang IPH_MEM_POWER_LS_EN, 0); 842c6b6a421SHawking Zhang hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, 843c6b6a421SHawking Zhang IPH_MEM_POWER_DS_EN, 0); 844c6b6a421SHawking Zhang hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, 845c6b6a421SHawking Zhang IPH_MEM_POWER_SD_EN, 0); 846c6b6a421SHawking Zhang hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, 847c6b6a421SHawking Zhang RC_MEM_POWER_CTRL_EN, 0); 848c6b6a421SHawking Zhang hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, 849c6b6a421SHawking Zhang RC_MEM_POWER_LS_EN, 0); 850c6b6a421SHawking Zhang hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, 851c6b6a421SHawking Zhang RC_MEM_POWER_DS_EN, 0); 852c6b6a421SHawking Zhang hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, 853c6b6a421SHawking Zhang RC_MEM_POWER_SD_EN, 0); 854c6b6a421SHawking Zhang WREG32_SOC15(HDP, 0, mmHDP_MEM_POWER_CTRL, hdp_mem_pwr_cntl); 855c6b6a421SHawking Zhang 856c6b6a421SHawking Zhang /* only one clock gating mode (LS/DS/SD) can be enabled */ 857c6b6a421SHawking Zhang if (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS) { 858c6b6a421SHawking Zhang hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, 859c6b6a421SHawking Zhang HDP_MEM_POWER_CTRL, 860c6b6a421SHawking Zhang IPH_MEM_POWER_LS_EN, enable); 861c6b6a421SHawking Zhang hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, 862c6b6a421SHawking Zhang HDP_MEM_POWER_CTRL, 863c6b6a421SHawking Zhang RC_MEM_POWER_LS_EN, enable); 864c6b6a421SHawking Zhang } else if (adev->cg_flags & AMD_CG_SUPPORT_HDP_DS) { 865c6b6a421SHawking Zhang hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, 866c6b6a421SHawking Zhang HDP_MEM_POWER_CTRL, 867c6b6a421SHawking Zhang IPH_MEM_POWER_DS_EN, enable); 868c6b6a421SHawking Zhang hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, 869c6b6a421SHawking Zhang HDP_MEM_POWER_CTRL, 870c6b6a421SHawking Zhang RC_MEM_POWER_DS_EN, enable); 871c6b6a421SHawking Zhang } else if (adev->cg_flags & AMD_CG_SUPPORT_HDP_SD) { 872c6b6a421SHawking Zhang hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, 873c6b6a421SHawking Zhang HDP_MEM_POWER_CTRL, 874c6b6a421SHawking Zhang IPH_MEM_POWER_SD_EN, enable); 875c6b6a421SHawking Zhang /* RC should not use shut down mode, fallback to ds */ 876c6b6a421SHawking Zhang hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, 877c6b6a421SHawking Zhang HDP_MEM_POWER_CTRL, 878c6b6a421SHawking Zhang RC_MEM_POWER_DS_EN, enable); 879c6b6a421SHawking Zhang } 880c6b6a421SHawking Zhang 881c6b6a421SHawking Zhang WREG32_SOC15(HDP, 0, mmHDP_MEM_POWER_CTRL, hdp_mem_pwr_cntl); 882c6b6a421SHawking Zhang 883c6b6a421SHawking Zhang /* restore IPH & RC clock override after clock/power mode changing */ 884c6b6a421SHawking Zhang WREG32_SOC15(HDP, 0, mmHDP_CLK_CNTL, hdp_clk_cntl1); 885c6b6a421SHawking Zhang } 886c6b6a421SHawking Zhang 887c6b6a421SHawking Zhang static void nv_update_hdp_clock_gating(struct amdgpu_device *adev, 888c6b6a421SHawking Zhang bool enable) 889c6b6a421SHawking Zhang { 890c6b6a421SHawking Zhang uint32_t hdp_clk_cntl; 891c6b6a421SHawking Zhang 892c6b6a421SHawking Zhang if (!(adev->cg_flags & AMD_CG_SUPPORT_HDP_MGCG)) 893c6b6a421SHawking Zhang return; 894c6b6a421SHawking Zhang 895c6b6a421SHawking Zhang hdp_clk_cntl = RREG32_SOC15(HDP, 0, mmHDP_CLK_CNTL); 896c6b6a421SHawking Zhang 897c6b6a421SHawking Zhang if (enable) { 898c6b6a421SHawking Zhang hdp_clk_cntl &= 899c6b6a421SHawking Zhang ~(uint32_t) 900c6b6a421SHawking Zhang (HDP_CLK_CNTL__IPH_MEM_CLK_SOFT_OVERRIDE_MASK | 901c6b6a421SHawking Zhang HDP_CLK_CNTL__RC_MEM_CLK_SOFT_OVERRIDE_MASK | 902c6b6a421SHawking Zhang HDP_CLK_CNTL__DBUS_CLK_SOFT_OVERRIDE_MASK | 903c6b6a421SHawking Zhang HDP_CLK_CNTL__DYN_CLK_SOFT_OVERRIDE_MASK | 904c6b6a421SHawking Zhang HDP_CLK_CNTL__XDP_REG_CLK_SOFT_OVERRIDE_MASK | 905c6b6a421SHawking Zhang HDP_CLK_CNTL__HDP_REG_CLK_SOFT_OVERRIDE_MASK); 906c6b6a421SHawking Zhang } else { 907c6b6a421SHawking Zhang hdp_clk_cntl |= HDP_CLK_CNTL__IPH_MEM_CLK_SOFT_OVERRIDE_MASK | 908c6b6a421SHawking Zhang HDP_CLK_CNTL__RC_MEM_CLK_SOFT_OVERRIDE_MASK | 909c6b6a421SHawking Zhang HDP_CLK_CNTL__DBUS_CLK_SOFT_OVERRIDE_MASK | 910c6b6a421SHawking Zhang HDP_CLK_CNTL__DYN_CLK_SOFT_OVERRIDE_MASK | 911c6b6a421SHawking Zhang HDP_CLK_CNTL__XDP_REG_CLK_SOFT_OVERRIDE_MASK | 912c6b6a421SHawking Zhang HDP_CLK_CNTL__HDP_REG_CLK_SOFT_OVERRIDE_MASK; 913c6b6a421SHawking Zhang } 914c6b6a421SHawking Zhang 915c6b6a421SHawking Zhang WREG32_SOC15(HDP, 0, mmHDP_CLK_CNTL, hdp_clk_cntl); 916c6b6a421SHawking Zhang } 917c6b6a421SHawking Zhang 918c6b6a421SHawking Zhang static int nv_common_set_clockgating_state(void *handle, 919c6b6a421SHawking Zhang enum amd_clockgating_state state) 920c6b6a421SHawking Zhang { 921c6b6a421SHawking Zhang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 922c6b6a421SHawking Zhang 923c6b6a421SHawking Zhang if (amdgpu_sriov_vf(adev)) 924c6b6a421SHawking Zhang return 0; 925c6b6a421SHawking Zhang 926c6b6a421SHawking Zhang switch (adev->asic_type) { 927c6b6a421SHawking Zhang case CHIP_NAVI10: 9285e71e011SXiaojie Yuan case CHIP_NAVI14: 9297e17e58bSXiaojie Yuan case CHIP_NAVI12: 930117910edSLikun Gao case CHIP_SIENNA_CICHLID: 931bebc0762SHawking Zhang adev->nbio.funcs->update_medium_grain_clock_gating(adev, 932a9d4fe2fSNirmoy Das state == AMD_CG_STATE_GATE); 933bebc0762SHawking Zhang adev->nbio.funcs->update_medium_grain_light_sleep(adev, 934a9d4fe2fSNirmoy Das state == AMD_CG_STATE_GATE); 935c6b6a421SHawking Zhang nv_update_hdp_mem_power_gating(adev, 936a9d4fe2fSNirmoy Das state == AMD_CG_STATE_GATE); 937c6b6a421SHawking Zhang nv_update_hdp_clock_gating(adev, 938a9d4fe2fSNirmoy Das state == AMD_CG_STATE_GATE); 939c6b6a421SHawking Zhang break; 940c6b6a421SHawking Zhang default: 941c6b6a421SHawking Zhang break; 942c6b6a421SHawking Zhang } 943c6b6a421SHawking Zhang return 0; 944c6b6a421SHawking Zhang } 945c6b6a421SHawking Zhang 946c6b6a421SHawking Zhang static int nv_common_set_powergating_state(void *handle, 947c6b6a421SHawking Zhang enum amd_powergating_state state) 948c6b6a421SHawking Zhang { 949c6b6a421SHawking Zhang /* TODO */ 950c6b6a421SHawking Zhang return 0; 951c6b6a421SHawking Zhang } 952c6b6a421SHawking Zhang 953c6b6a421SHawking Zhang static void nv_common_get_clockgating_state(void *handle, u32 *flags) 954c6b6a421SHawking Zhang { 955c6b6a421SHawking Zhang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 956c6b6a421SHawking Zhang uint32_t tmp; 957c6b6a421SHawking Zhang 958c6b6a421SHawking Zhang if (amdgpu_sriov_vf(adev)) 959c6b6a421SHawking Zhang *flags = 0; 960c6b6a421SHawking Zhang 961bebc0762SHawking Zhang adev->nbio.funcs->get_clockgating_state(adev, flags); 962c6b6a421SHawking Zhang 963c6b6a421SHawking Zhang /* AMD_CG_SUPPORT_HDP_MGCG */ 964c6b6a421SHawking Zhang tmp = RREG32_SOC15(HDP, 0, mmHDP_CLK_CNTL); 965c6b6a421SHawking Zhang if (!(tmp & (HDP_CLK_CNTL__IPH_MEM_CLK_SOFT_OVERRIDE_MASK | 966c6b6a421SHawking Zhang HDP_CLK_CNTL__RC_MEM_CLK_SOFT_OVERRIDE_MASK | 967c6b6a421SHawking Zhang HDP_CLK_CNTL__DBUS_CLK_SOFT_OVERRIDE_MASK | 968c6b6a421SHawking Zhang HDP_CLK_CNTL__DYN_CLK_SOFT_OVERRIDE_MASK | 969c6b6a421SHawking Zhang HDP_CLK_CNTL__XDP_REG_CLK_SOFT_OVERRIDE_MASK | 970c6b6a421SHawking Zhang HDP_CLK_CNTL__HDP_REG_CLK_SOFT_OVERRIDE_MASK))) 971c6b6a421SHawking Zhang *flags |= AMD_CG_SUPPORT_HDP_MGCG; 972c6b6a421SHawking Zhang 973c6b6a421SHawking Zhang /* AMD_CG_SUPPORT_HDP_LS/DS/SD */ 974c6b6a421SHawking Zhang tmp = RREG32_SOC15(HDP, 0, mmHDP_MEM_POWER_CTRL); 975c6b6a421SHawking Zhang if (tmp & HDP_MEM_POWER_CTRL__IPH_MEM_POWER_LS_EN_MASK) 976c6b6a421SHawking Zhang *flags |= AMD_CG_SUPPORT_HDP_LS; 977c6b6a421SHawking Zhang else if (tmp & HDP_MEM_POWER_CTRL__IPH_MEM_POWER_DS_EN_MASK) 978c6b6a421SHawking Zhang *flags |= AMD_CG_SUPPORT_HDP_DS; 979c6b6a421SHawking Zhang else if (tmp & HDP_MEM_POWER_CTRL__IPH_MEM_POWER_SD_EN_MASK) 980c6b6a421SHawking Zhang *flags |= AMD_CG_SUPPORT_HDP_SD; 981c6b6a421SHawking Zhang 982c6b6a421SHawking Zhang return; 983c6b6a421SHawking Zhang } 984c6b6a421SHawking Zhang 985c6b6a421SHawking Zhang static const struct amd_ip_funcs nv_common_ip_funcs = { 986c6b6a421SHawking Zhang .name = "nv_common", 987c6b6a421SHawking Zhang .early_init = nv_common_early_init, 988c6b6a421SHawking Zhang .late_init = nv_common_late_init, 989c6b6a421SHawking Zhang .sw_init = nv_common_sw_init, 990c6b6a421SHawking Zhang .sw_fini = nv_common_sw_fini, 991c6b6a421SHawking Zhang .hw_init = nv_common_hw_init, 992c6b6a421SHawking Zhang .hw_fini = nv_common_hw_fini, 993c6b6a421SHawking Zhang .suspend = nv_common_suspend, 994c6b6a421SHawking Zhang .resume = nv_common_resume, 995c6b6a421SHawking Zhang .is_idle = nv_common_is_idle, 996c6b6a421SHawking Zhang .wait_for_idle = nv_common_wait_for_idle, 997c6b6a421SHawking Zhang .soft_reset = nv_common_soft_reset, 998c6b6a421SHawking Zhang .set_clockgating_state = nv_common_set_clockgating_state, 999c6b6a421SHawking Zhang .set_powergating_state = nv_common_set_powergating_state, 1000c6b6a421SHawking Zhang .get_clockgating_state = nv_common_get_clockgating_state, 1001c6b6a421SHawking Zhang }; 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