1c6b6a421SHawking Zhang /* 2c6b6a421SHawking Zhang * Copyright 2019 Advanced Micro Devices, Inc. 3c6b6a421SHawking Zhang * 4c6b6a421SHawking Zhang * Permission is hereby granted, free of charge, to any person obtaining a 5c6b6a421SHawking Zhang * copy of this software and associated documentation files (the "Software"), 6c6b6a421SHawking Zhang * to deal in the Software without restriction, including without limitation 7c6b6a421SHawking Zhang * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8c6b6a421SHawking Zhang * and/or sell copies of the Software, and to permit persons to whom the 9c6b6a421SHawking Zhang * Software is furnished to do so, subject to the following conditions: 10c6b6a421SHawking Zhang * 11c6b6a421SHawking Zhang * The above copyright notice and this permission notice shall be included in 12c6b6a421SHawking Zhang * all copies or substantial portions of the Software. 13c6b6a421SHawking Zhang * 14c6b6a421SHawking Zhang * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15c6b6a421SHawking Zhang * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16c6b6a421SHawking Zhang * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17c6b6a421SHawking Zhang * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18c6b6a421SHawking Zhang * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19c6b6a421SHawking Zhang * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20c6b6a421SHawking Zhang * OTHER DEALINGS IN THE SOFTWARE. 21c6b6a421SHawking Zhang * 22c6b6a421SHawking Zhang */ 23c6b6a421SHawking Zhang #include <linux/firmware.h> 24c6b6a421SHawking Zhang #include <linux/slab.h> 25c6b6a421SHawking Zhang #include <linux/module.h> 26e9eea902SAlex Deucher #include <linux/pci.h> 27e9eea902SAlex Deucher 286f786950SAlex Deucher #include <drm/amdgpu_drm.h> 296f786950SAlex Deucher 30c6b6a421SHawking Zhang #include "amdgpu.h" 31c6b6a421SHawking Zhang #include "amdgpu_atombios.h" 32c6b6a421SHawking Zhang #include "amdgpu_ih.h" 33c6b6a421SHawking Zhang #include "amdgpu_uvd.h" 34c6b6a421SHawking Zhang #include "amdgpu_vce.h" 35c6b6a421SHawking Zhang #include "amdgpu_ucode.h" 36c6b6a421SHawking Zhang #include "amdgpu_psp.h" 37c6b6a421SHawking Zhang #include "atom.h" 38c6b6a421SHawking Zhang #include "amd_pcie.h" 39c6b6a421SHawking Zhang 40c6b6a421SHawking Zhang #include "gc/gc_10_1_0_offset.h" 41c6b6a421SHawking Zhang #include "gc/gc_10_1_0_sh_mask.h" 423967ae6dSAlex Deucher #include "mp/mp_11_0_offset.h" 43c6b6a421SHawking Zhang 44c6b6a421SHawking Zhang #include "soc15.h" 45c6b6a421SHawking Zhang #include "soc15_common.h" 46c6b6a421SHawking Zhang #include "gmc_v10_0.h" 47c6b6a421SHawking Zhang #include "gfxhub_v2_0.h" 48c6b6a421SHawking Zhang #include "mmhub_v2_0.h" 49bebc0762SHawking Zhang #include "nbio_v2_3.h" 50a7e91bd7SHuang Rui #include "nbio_v7_2.h" 51bf087285SLikun Gao #include "hdp_v5_0.h" 52c6b6a421SHawking Zhang #include "nv.h" 53c6b6a421SHawking Zhang #include "navi10_ih.h" 54c6b6a421SHawking Zhang #include "gfx_v10_0.h" 55c6b6a421SHawking Zhang #include "sdma_v5_0.h" 56157e72e8SLikun Gao #include "sdma_v5_2.h" 57c6b6a421SHawking Zhang #include "vcn_v2_0.h" 585be45a26SLeo Liu #include "jpeg_v2_0.h" 59b8f10585SLeo Liu #include "vcn_v3_0.h" 604d72dd12SLeo Liu #include "jpeg_v3_0.h" 61c6b6a421SHawking Zhang #include "dce_virtual.h" 62c6b6a421SHawking Zhang #include "mes_v10_1.h" 63b05b6903SJiange Zhao #include "mxgpu_nv.h" 640bf7f2dcSLikun Gao #include "smuio_v11_0.h" 650bf7f2dcSLikun Gao #include "smuio_v11_0_6.h" 66c6b6a421SHawking Zhang 67c6b6a421SHawking Zhang static const struct amd_ip_funcs nv_common_ip_funcs; 68c6b6a421SHawking Zhang 693b246e8bSAlex Deucher /* Navi */ 703b246e8bSAlex Deucher static const struct amdgpu_video_codec_info nv_video_codecs_encode_array[] = 713b246e8bSAlex Deucher { 723b246e8bSAlex Deucher { 736f786950SAlex Deucher .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 743b246e8bSAlex Deucher .max_width = 4096, 753b246e8bSAlex Deucher .max_height = 2304, 763b246e8bSAlex Deucher .max_pixels_per_frame = 4096 * 2304, 773b246e8bSAlex Deucher .max_level = 0, 783b246e8bSAlex Deucher }, 793b246e8bSAlex Deucher { 806f786950SAlex Deucher .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 813b246e8bSAlex Deucher .max_width = 4096, 823b246e8bSAlex Deucher .max_height = 2304, 833b246e8bSAlex Deucher .max_pixels_per_frame = 4096 * 2304, 843b246e8bSAlex Deucher .max_level = 0, 853b246e8bSAlex Deucher }, 863b246e8bSAlex Deucher }; 873b246e8bSAlex Deucher 883b246e8bSAlex Deucher static const struct amdgpu_video_codecs nv_video_codecs_encode = 893b246e8bSAlex Deucher { 903b246e8bSAlex Deucher .codec_count = ARRAY_SIZE(nv_video_codecs_encode_array), 913b246e8bSAlex Deucher .codec_array = nv_video_codecs_encode_array, 923b246e8bSAlex Deucher }; 933b246e8bSAlex Deucher 943b246e8bSAlex Deucher /* Navi1x */ 953b246e8bSAlex Deucher static const struct amdgpu_video_codec_info nv_video_codecs_decode_array[] = 963b246e8bSAlex Deucher { 973b246e8bSAlex Deucher { 986f786950SAlex Deucher .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 993b246e8bSAlex Deucher .max_width = 4096, 1003b246e8bSAlex Deucher .max_height = 4096, 1013b246e8bSAlex Deucher .max_pixels_per_frame = 4096 * 4096, 1023b246e8bSAlex Deucher .max_level = 3, 1033b246e8bSAlex Deucher }, 1043b246e8bSAlex Deucher { 1056f786950SAlex Deucher .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 1063b246e8bSAlex Deucher .max_width = 4096, 1073b246e8bSAlex Deucher .max_height = 4096, 1083b246e8bSAlex Deucher .max_pixels_per_frame = 4096 * 4096, 1093b246e8bSAlex Deucher .max_level = 5, 1103b246e8bSAlex Deucher }, 1113b246e8bSAlex Deucher { 1126f786950SAlex Deucher .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 1133b246e8bSAlex Deucher .max_width = 4096, 1143b246e8bSAlex Deucher .max_height = 4096, 1153b246e8bSAlex Deucher .max_pixels_per_frame = 4096 * 4096, 1163b246e8bSAlex Deucher .max_level = 52, 1173b246e8bSAlex Deucher }, 1183b246e8bSAlex Deucher { 1196f786950SAlex Deucher .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 1203b246e8bSAlex Deucher .max_width = 4096, 1213b246e8bSAlex Deucher .max_height = 4096, 1223b246e8bSAlex Deucher .max_pixels_per_frame = 4096 * 4096, 1233b246e8bSAlex Deucher .max_level = 4, 1243b246e8bSAlex Deucher }, 1253b246e8bSAlex Deucher { 1266f786950SAlex Deucher .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 1273b246e8bSAlex Deucher .max_width = 8192, 1283b246e8bSAlex Deucher .max_height = 4352, 1293b246e8bSAlex Deucher .max_pixels_per_frame = 8192 * 4352, 1303b246e8bSAlex Deucher .max_level = 186, 1313b246e8bSAlex Deucher }, 1323b246e8bSAlex Deucher { 1336f786950SAlex Deucher .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 1343b246e8bSAlex Deucher .max_width = 4096, 1353b246e8bSAlex Deucher .max_height = 4096, 1363b246e8bSAlex Deucher .max_pixels_per_frame = 4096 * 4096, 1373b246e8bSAlex Deucher .max_level = 0, 1383b246e8bSAlex Deucher }, 1393b246e8bSAlex Deucher { 1406f786950SAlex Deucher .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 1413b246e8bSAlex Deucher .max_width = 8192, 1423b246e8bSAlex Deucher .max_height = 4352, 1433b246e8bSAlex Deucher .max_pixels_per_frame = 8192 * 4352, 1443b246e8bSAlex Deucher .max_level = 0, 1453b246e8bSAlex Deucher }, 1463b246e8bSAlex Deucher }; 1473b246e8bSAlex Deucher 1483b246e8bSAlex Deucher static const struct amdgpu_video_codecs nv_video_codecs_decode = 1493b246e8bSAlex Deucher { 1503b246e8bSAlex Deucher .codec_count = ARRAY_SIZE(nv_video_codecs_decode_array), 1513b246e8bSAlex Deucher .codec_array = nv_video_codecs_decode_array, 1523b246e8bSAlex Deucher }; 1533b246e8bSAlex Deucher 1543b246e8bSAlex Deucher /* Sienna Cichlid */ 1553b246e8bSAlex Deucher static const struct amdgpu_video_codec_info sc_video_codecs_decode_array[] = 1563b246e8bSAlex Deucher { 1573b246e8bSAlex Deucher { 1586f786950SAlex Deucher .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 1593b246e8bSAlex Deucher .max_width = 4096, 1603b246e8bSAlex Deucher .max_height = 4096, 1613b246e8bSAlex Deucher .max_pixels_per_frame = 4096 * 4096, 1623b246e8bSAlex Deucher .max_level = 3, 1633b246e8bSAlex Deucher }, 1643b246e8bSAlex Deucher { 1656f786950SAlex Deucher .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 1663b246e8bSAlex Deucher .max_width = 4096, 1673b246e8bSAlex Deucher .max_height = 4096, 1683b246e8bSAlex Deucher .max_pixels_per_frame = 4096 * 4096, 1693b246e8bSAlex Deucher .max_level = 5, 1703b246e8bSAlex Deucher }, 1713b246e8bSAlex Deucher { 1726f786950SAlex Deucher .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 1733b246e8bSAlex Deucher .max_width = 4096, 1743b246e8bSAlex Deucher .max_height = 4096, 1753b246e8bSAlex Deucher .max_pixels_per_frame = 4096 * 4096, 1763b246e8bSAlex Deucher .max_level = 52, 1773b246e8bSAlex Deucher }, 1783b246e8bSAlex Deucher { 1796f786950SAlex Deucher .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 1803b246e8bSAlex Deucher .max_width = 4096, 1813b246e8bSAlex Deucher .max_height = 4096, 1823b246e8bSAlex Deucher .max_pixels_per_frame = 4096 * 4096, 1833b246e8bSAlex Deucher .max_level = 4, 1843b246e8bSAlex Deucher }, 1853b246e8bSAlex Deucher { 1866f786950SAlex Deucher .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 1873b246e8bSAlex Deucher .max_width = 8192, 1883b246e8bSAlex Deucher .max_height = 4352, 1893b246e8bSAlex Deucher .max_pixels_per_frame = 8192 * 4352, 1903b246e8bSAlex Deucher .max_level = 186, 1913b246e8bSAlex Deucher }, 1923b246e8bSAlex Deucher { 1936f786950SAlex Deucher .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 1943b246e8bSAlex Deucher .max_width = 4096, 1953b246e8bSAlex Deucher .max_height = 4096, 1963b246e8bSAlex Deucher .max_pixels_per_frame = 4096 * 4096, 1973b246e8bSAlex Deucher .max_level = 0, 1983b246e8bSAlex Deucher }, 1993b246e8bSAlex Deucher { 2006f786950SAlex Deucher .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 2013b246e8bSAlex Deucher .max_width = 8192, 2023b246e8bSAlex Deucher .max_height = 4352, 2033b246e8bSAlex Deucher .max_pixels_per_frame = 8192 * 4352, 2043b246e8bSAlex Deucher .max_level = 0, 2053b246e8bSAlex Deucher }, 2063b246e8bSAlex Deucher { 2076f786950SAlex Deucher .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, 2083b246e8bSAlex Deucher .max_width = 8192, 2093b246e8bSAlex Deucher .max_height = 4352, 2103b246e8bSAlex Deucher .max_pixels_per_frame = 8192 * 4352, 2113b246e8bSAlex Deucher .max_level = 0, 2123b246e8bSAlex Deucher }, 2133b246e8bSAlex Deucher }; 2143b246e8bSAlex Deucher 2153b246e8bSAlex Deucher static const struct amdgpu_video_codecs sc_video_codecs_decode = 2163b246e8bSAlex Deucher { 2173b246e8bSAlex Deucher .codec_count = ARRAY_SIZE(sc_video_codecs_decode_array), 2183b246e8bSAlex Deucher .codec_array = sc_video_codecs_decode_array, 2193b246e8bSAlex Deucher }; 2203b246e8bSAlex Deucher 2213b246e8bSAlex Deucher static int nv_query_video_codecs(struct amdgpu_device *adev, bool encode, 2223b246e8bSAlex Deucher const struct amdgpu_video_codecs **codecs) 2233b246e8bSAlex Deucher { 2243b246e8bSAlex Deucher switch (adev->asic_type) { 2253b246e8bSAlex Deucher case CHIP_SIENNA_CICHLID: 2263b246e8bSAlex Deucher case CHIP_NAVY_FLOUNDER: 2273b246e8bSAlex Deucher case CHIP_DIMGREY_CAVEFISH: 2283b246e8bSAlex Deucher case CHIP_VANGOGH: 2293b246e8bSAlex Deucher if (encode) 2303b246e8bSAlex Deucher *codecs = &nv_video_codecs_encode; 2313b246e8bSAlex Deucher else 2323b246e8bSAlex Deucher *codecs = &sc_video_codecs_decode; 2333b246e8bSAlex Deucher return 0; 2343b246e8bSAlex Deucher case CHIP_NAVI10: 2353b246e8bSAlex Deucher case CHIP_NAVI14: 2363b246e8bSAlex Deucher case CHIP_NAVI12: 2373b246e8bSAlex Deucher if (encode) 2383b246e8bSAlex Deucher *codecs = &nv_video_codecs_encode; 2393b246e8bSAlex Deucher else 2403b246e8bSAlex Deucher *codecs = &nv_video_codecs_decode; 2413b246e8bSAlex Deucher return 0; 2423b246e8bSAlex Deucher default: 2433b246e8bSAlex Deucher return -EINVAL; 2443b246e8bSAlex Deucher } 2453b246e8bSAlex Deucher } 2463b246e8bSAlex Deucher 247c6b6a421SHawking Zhang /* 248c6b6a421SHawking Zhang * Indirect registers accessor 249c6b6a421SHawking Zhang */ 250c6b6a421SHawking Zhang static u32 nv_pcie_rreg(struct amdgpu_device *adev, u32 reg) 251c6b6a421SHawking Zhang { 252705a2b5bSHawking Zhang unsigned long address, data; 253bebc0762SHawking Zhang address = adev->nbio.funcs->get_pcie_index_offset(adev); 254bebc0762SHawking Zhang data = adev->nbio.funcs->get_pcie_data_offset(adev); 255c6b6a421SHawking Zhang 256705a2b5bSHawking Zhang return amdgpu_device_indirect_rreg(adev, address, data, reg); 257c6b6a421SHawking Zhang } 258c6b6a421SHawking Zhang 259c6b6a421SHawking Zhang static void nv_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v) 260c6b6a421SHawking Zhang { 261705a2b5bSHawking Zhang unsigned long address, data; 262c6b6a421SHawking Zhang 263bebc0762SHawking Zhang address = adev->nbio.funcs->get_pcie_index_offset(adev); 264bebc0762SHawking Zhang data = adev->nbio.funcs->get_pcie_data_offset(adev); 265c6b6a421SHawking Zhang 266705a2b5bSHawking Zhang amdgpu_device_indirect_wreg(adev, address, data, reg, v); 267c6b6a421SHawking Zhang } 268c6b6a421SHawking Zhang 2694922f1bcSJohn Clements static u64 nv_pcie_rreg64(struct amdgpu_device *adev, u32 reg) 2704922f1bcSJohn Clements { 271705a2b5bSHawking Zhang unsigned long address, data; 2724922f1bcSJohn Clements address = adev->nbio.funcs->get_pcie_index_offset(adev); 2734922f1bcSJohn Clements data = adev->nbio.funcs->get_pcie_data_offset(adev); 2744922f1bcSJohn Clements 275705a2b5bSHawking Zhang return amdgpu_device_indirect_rreg64(adev, address, data, reg); 2764922f1bcSJohn Clements } 2774922f1bcSJohn Clements 2785de54343SHuang Rui static u32 nv_pcie_port_rreg(struct amdgpu_device *adev, u32 reg) 2795de54343SHuang Rui { 2805de54343SHuang Rui unsigned long flags, address, data; 2815de54343SHuang Rui u32 r; 2825de54343SHuang Rui address = adev->nbio.funcs->get_pcie_port_index_offset(adev); 2835de54343SHuang Rui data = adev->nbio.funcs->get_pcie_port_data_offset(adev); 2845de54343SHuang Rui 2855de54343SHuang Rui spin_lock_irqsave(&adev->pcie_idx_lock, flags); 2865de54343SHuang Rui WREG32(address, reg * 4); 2875de54343SHuang Rui (void)RREG32(address); 2885de54343SHuang Rui r = RREG32(data); 2895de54343SHuang Rui spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); 2905de54343SHuang Rui return r; 2915de54343SHuang Rui } 2925de54343SHuang Rui 2934922f1bcSJohn Clements static void nv_pcie_wreg64(struct amdgpu_device *adev, u32 reg, u64 v) 2944922f1bcSJohn Clements { 295705a2b5bSHawking Zhang unsigned long address, data; 2964922f1bcSJohn Clements 2974922f1bcSJohn Clements address = adev->nbio.funcs->get_pcie_index_offset(adev); 2984922f1bcSJohn Clements data = adev->nbio.funcs->get_pcie_data_offset(adev); 2994922f1bcSJohn Clements 300705a2b5bSHawking Zhang amdgpu_device_indirect_wreg64(adev, address, data, reg, v); 3014922f1bcSJohn Clements } 3024922f1bcSJohn Clements 3035de54343SHuang Rui static void nv_pcie_port_wreg(struct amdgpu_device *adev, u32 reg, u32 v) 3045de54343SHuang Rui { 3055de54343SHuang Rui unsigned long flags, address, data; 3065de54343SHuang Rui 3075de54343SHuang Rui address = adev->nbio.funcs->get_pcie_port_index_offset(adev); 3085de54343SHuang Rui data = adev->nbio.funcs->get_pcie_port_data_offset(adev); 3095de54343SHuang Rui 3105de54343SHuang Rui spin_lock_irqsave(&adev->pcie_idx_lock, flags); 3115de54343SHuang Rui WREG32(address, reg * 4); 3125de54343SHuang Rui (void)RREG32(address); 3135de54343SHuang Rui WREG32(data, v); 3145de54343SHuang Rui (void)RREG32(data); 3155de54343SHuang Rui spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); 3165de54343SHuang Rui } 3175de54343SHuang Rui 318c6b6a421SHawking Zhang static u32 nv_didt_rreg(struct amdgpu_device *adev, u32 reg) 319c6b6a421SHawking Zhang { 320c6b6a421SHawking Zhang unsigned long flags, address, data; 321c6b6a421SHawking Zhang u32 r; 322c6b6a421SHawking Zhang 323c6b6a421SHawking Zhang address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX); 324c6b6a421SHawking Zhang data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA); 325c6b6a421SHawking Zhang 326c6b6a421SHawking Zhang spin_lock_irqsave(&adev->didt_idx_lock, flags); 327c6b6a421SHawking Zhang WREG32(address, (reg)); 328c6b6a421SHawking Zhang r = RREG32(data); 329c6b6a421SHawking Zhang spin_unlock_irqrestore(&adev->didt_idx_lock, flags); 330c6b6a421SHawking Zhang return r; 331c6b6a421SHawking Zhang } 332c6b6a421SHawking Zhang 333c6b6a421SHawking Zhang static void nv_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v) 334c6b6a421SHawking Zhang { 335c6b6a421SHawking Zhang unsigned long flags, address, data; 336c6b6a421SHawking Zhang 337c6b6a421SHawking Zhang address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX); 338c6b6a421SHawking Zhang data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA); 339c6b6a421SHawking Zhang 340c6b6a421SHawking Zhang spin_lock_irqsave(&adev->didt_idx_lock, flags); 341c6b6a421SHawking Zhang WREG32(address, (reg)); 342c6b6a421SHawking Zhang WREG32(data, (v)); 343c6b6a421SHawking Zhang spin_unlock_irqrestore(&adev->didt_idx_lock, flags); 344c6b6a421SHawking Zhang } 345c6b6a421SHawking Zhang 346c6b6a421SHawking Zhang static u32 nv_get_config_memsize(struct amdgpu_device *adev) 347c6b6a421SHawking Zhang { 348bebc0762SHawking Zhang return adev->nbio.funcs->get_memsize(adev); 349c6b6a421SHawking Zhang } 350c6b6a421SHawking Zhang 351c6b6a421SHawking Zhang static u32 nv_get_xclk(struct amdgpu_device *adev) 352c6b6a421SHawking Zhang { 353462a70d8STao Zhou return adev->clock.spll.reference_freq; 354c6b6a421SHawking Zhang } 355c6b6a421SHawking Zhang 356c6b6a421SHawking Zhang 357c6b6a421SHawking Zhang void nv_grbm_select(struct amdgpu_device *adev, 358c6b6a421SHawking Zhang u32 me, u32 pipe, u32 queue, u32 vmid) 359c6b6a421SHawking Zhang { 360c6b6a421SHawking Zhang u32 grbm_gfx_cntl = 0; 361c6b6a421SHawking Zhang grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, PIPEID, pipe); 362c6b6a421SHawking Zhang grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, MEID, me); 363c6b6a421SHawking Zhang grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, VMID, vmid); 364c6b6a421SHawking Zhang grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, QUEUEID, queue); 365c6b6a421SHawking Zhang 366c6b6a421SHawking Zhang WREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_CNTL), grbm_gfx_cntl); 367c6b6a421SHawking Zhang } 368c6b6a421SHawking Zhang 369c6b6a421SHawking Zhang static void nv_vga_set_state(struct amdgpu_device *adev, bool state) 370c6b6a421SHawking Zhang { 371c6b6a421SHawking Zhang /* todo */ 372c6b6a421SHawking Zhang } 373c6b6a421SHawking Zhang 374c6b6a421SHawking Zhang static bool nv_read_disabled_bios(struct amdgpu_device *adev) 375c6b6a421SHawking Zhang { 376c6b6a421SHawking Zhang /* todo */ 377c6b6a421SHawking Zhang return false; 378c6b6a421SHawking Zhang } 379c6b6a421SHawking Zhang 380c6b6a421SHawking Zhang static bool nv_read_bios_from_rom(struct amdgpu_device *adev, 381c6b6a421SHawking Zhang u8 *bios, u32 length_bytes) 382c6b6a421SHawking Zhang { 38329bc37b4SAlex Deucher u32 *dw_ptr; 38429bc37b4SAlex Deucher u32 i, length_dw; 3850bf7f2dcSLikun Gao u32 rom_index_offset, rom_data_offset; 38629bc37b4SAlex Deucher 38729bc37b4SAlex Deucher if (bios == NULL) 388c6b6a421SHawking Zhang return false; 38929bc37b4SAlex Deucher if (length_bytes == 0) 39029bc37b4SAlex Deucher return false; 39129bc37b4SAlex Deucher /* APU vbios image is part of sbios image */ 39229bc37b4SAlex Deucher if (adev->flags & AMD_IS_APU) 39329bc37b4SAlex Deucher return false; 39429bc37b4SAlex Deucher 39529bc37b4SAlex Deucher dw_ptr = (u32 *)bios; 39629bc37b4SAlex Deucher length_dw = ALIGN(length_bytes, 4) / 4; 39729bc37b4SAlex Deucher 3980bf7f2dcSLikun Gao rom_index_offset = 3990bf7f2dcSLikun Gao adev->smuio.funcs->get_rom_index_offset(adev); 4000bf7f2dcSLikun Gao rom_data_offset = 4010bf7f2dcSLikun Gao adev->smuio.funcs->get_rom_data_offset(adev); 4020bf7f2dcSLikun Gao 40329bc37b4SAlex Deucher /* set rom index to 0 */ 4040bf7f2dcSLikun Gao WREG32(rom_index_offset, 0); 40529bc37b4SAlex Deucher /* read out the rom data */ 40629bc37b4SAlex Deucher for (i = 0; i < length_dw; i++) 4070bf7f2dcSLikun Gao dw_ptr[i] = RREG32(rom_data_offset); 40829bc37b4SAlex Deucher 40929bc37b4SAlex Deucher return true; 410c6b6a421SHawking Zhang } 411c6b6a421SHawking Zhang 412c6b6a421SHawking Zhang static struct soc15_allowed_register_entry nv_allowed_read_registers[] = { 413c6b6a421SHawking Zhang { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS)}, 414c6b6a421SHawking Zhang { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS2)}, 415c6b6a421SHawking Zhang { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE0)}, 416c6b6a421SHawking Zhang { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE1)}, 417c6b6a421SHawking Zhang { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE2)}, 418c6b6a421SHawking Zhang { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE3)}, 419c6b6a421SHawking Zhang { SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_STATUS_REG)}, 420c6b6a421SHawking Zhang { SOC15_REG_ENTRY(SDMA1, 0, mmSDMA1_STATUS_REG)}, 421c6b6a421SHawking Zhang { SOC15_REG_ENTRY(GC, 0, mmCP_STAT)}, 422c6b6a421SHawking Zhang { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT1)}, 423c6b6a421SHawking Zhang { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT2)}, 424c6b6a421SHawking Zhang { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT3)}, 425c6b6a421SHawking Zhang { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_BUSY_STAT)}, 426c6b6a421SHawking Zhang { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STALLED_STAT1)}, 427c6b6a421SHawking Zhang { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STATUS)}, 428664fe85aSMarek Olšák { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_BUSY_STAT)}, 429c6b6a421SHawking Zhang { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STALLED_STAT1)}, 430c6b6a421SHawking Zhang { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STATUS)}, 431c6b6a421SHawking Zhang { SOC15_REG_ENTRY(GC, 0, mmGB_ADDR_CONFIG)}, 432c6b6a421SHawking Zhang }; 433c6b6a421SHawking Zhang 434c6b6a421SHawking Zhang static uint32_t nv_read_indexed_register(struct amdgpu_device *adev, u32 se_num, 435c6b6a421SHawking Zhang u32 sh_num, u32 reg_offset) 436c6b6a421SHawking Zhang { 437c6b6a421SHawking Zhang uint32_t val; 438c6b6a421SHawking Zhang 439c6b6a421SHawking Zhang mutex_lock(&adev->grbm_idx_mutex); 440c6b6a421SHawking Zhang if (se_num != 0xffffffff || sh_num != 0xffffffff) 441c6b6a421SHawking Zhang amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff); 442c6b6a421SHawking Zhang 443c6b6a421SHawking Zhang val = RREG32(reg_offset); 444c6b6a421SHawking Zhang 445c6b6a421SHawking Zhang if (se_num != 0xffffffff || sh_num != 0xffffffff) 446c6b6a421SHawking Zhang amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 447c6b6a421SHawking Zhang mutex_unlock(&adev->grbm_idx_mutex); 448c6b6a421SHawking Zhang return val; 449c6b6a421SHawking Zhang } 450c6b6a421SHawking Zhang 451c6b6a421SHawking Zhang static uint32_t nv_get_register_value(struct amdgpu_device *adev, 452c6b6a421SHawking Zhang bool indexed, u32 se_num, 453c6b6a421SHawking Zhang u32 sh_num, u32 reg_offset) 454c6b6a421SHawking Zhang { 455c6b6a421SHawking Zhang if (indexed) { 456c6b6a421SHawking Zhang return nv_read_indexed_register(adev, se_num, sh_num, reg_offset); 457c6b6a421SHawking Zhang } else { 458c6b6a421SHawking Zhang if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG)) 459c6b6a421SHawking Zhang return adev->gfx.config.gb_addr_config; 460c6b6a421SHawking Zhang return RREG32(reg_offset); 461c6b6a421SHawking Zhang } 462c6b6a421SHawking Zhang } 463c6b6a421SHawking Zhang 464c6b6a421SHawking Zhang static int nv_read_register(struct amdgpu_device *adev, u32 se_num, 465c6b6a421SHawking Zhang u32 sh_num, u32 reg_offset, u32 *value) 466c6b6a421SHawking Zhang { 467c6b6a421SHawking Zhang uint32_t i; 468c6b6a421SHawking Zhang struct soc15_allowed_register_entry *en; 469c6b6a421SHawking Zhang 470c6b6a421SHawking Zhang *value = 0; 471c6b6a421SHawking Zhang for (i = 0; i < ARRAY_SIZE(nv_allowed_read_registers); i++) { 472c6b6a421SHawking Zhang en = &nv_allowed_read_registers[i]; 473fced3c3aSHuang Rui if ((i == 7 && (adev->sdma.num_instances == 1)) || /* some asics don't have SDMA1 */ 474fced3c3aSHuang Rui reg_offset != 475c6b6a421SHawking Zhang (adev->reg_offset[en->hwip][en->inst][en->seg] + en->reg_offset)) 476c6b6a421SHawking Zhang continue; 477c6b6a421SHawking Zhang 478c6b6a421SHawking Zhang *value = nv_get_register_value(adev, 479c6b6a421SHawking Zhang nv_allowed_read_registers[i].grbm_indexed, 480c6b6a421SHawking Zhang se_num, sh_num, reg_offset); 481c6b6a421SHawking Zhang return 0; 482c6b6a421SHawking Zhang } 483c6b6a421SHawking Zhang return -EINVAL; 484c6b6a421SHawking Zhang } 485c6b6a421SHawking Zhang 486b913ec62SAlex Deucher static int nv_asic_mode2_reset(struct amdgpu_device *adev) 487b913ec62SAlex Deucher { 488b913ec62SAlex Deucher u32 i; 489b913ec62SAlex Deucher int ret = 0; 490b913ec62SAlex Deucher 491b913ec62SAlex Deucher amdgpu_atombios_scratch_regs_engine_hung(adev, true); 492b913ec62SAlex Deucher 493b913ec62SAlex Deucher /* disable BM */ 494b913ec62SAlex Deucher pci_clear_master(adev->pdev); 495b913ec62SAlex Deucher 496b913ec62SAlex Deucher amdgpu_device_cache_pci_state(adev->pdev); 497b913ec62SAlex Deucher 498b913ec62SAlex Deucher ret = amdgpu_dpm_mode2_reset(adev); 499b913ec62SAlex Deucher if (ret) 500b913ec62SAlex Deucher dev_err(adev->dev, "GPU mode2 reset failed\n"); 501b913ec62SAlex Deucher 502b913ec62SAlex Deucher amdgpu_device_load_pci_state(adev->pdev); 503b913ec62SAlex Deucher 504b913ec62SAlex Deucher /* wait for asic to come out of reset */ 505b913ec62SAlex Deucher for (i = 0; i < adev->usec_timeout; i++) { 506b913ec62SAlex Deucher u32 memsize = adev->nbio.funcs->get_memsize(adev); 507b913ec62SAlex Deucher 508b913ec62SAlex Deucher if (memsize != 0xffffffff) 509b913ec62SAlex Deucher break; 510b913ec62SAlex Deucher udelay(1); 511b913ec62SAlex Deucher } 512b913ec62SAlex Deucher 513b913ec62SAlex Deucher amdgpu_atombios_scratch_regs_engine_hung(adev, false); 514b913ec62SAlex Deucher 515b913ec62SAlex Deucher return ret; 516b913ec62SAlex Deucher } 517b913ec62SAlex Deucher 5182ddc6c3eSAlex Deucher static enum amd_reset_method 5192ddc6c3eSAlex Deucher nv_asic_reset_method(struct amdgpu_device *adev) 5202ddc6c3eSAlex Deucher { 521273da6ffSWenhui Sheng if (amdgpu_reset_method == AMD_RESET_METHOD_MODE1 || 52216086355SAlex Deucher amdgpu_reset_method == AMD_RESET_METHOD_MODE2 || 523f172865aSAlex Deucher amdgpu_reset_method == AMD_RESET_METHOD_BACO || 524f172865aSAlex Deucher amdgpu_reset_method == AMD_RESET_METHOD_PCI) 525273da6ffSWenhui Sheng return amdgpu_reset_method; 526273da6ffSWenhui Sheng 527273da6ffSWenhui Sheng if (amdgpu_reset_method != -1) 528273da6ffSWenhui Sheng dev_warn(adev->dev, "Specified reset method:%d isn't supported, using AUTO instead.\n", 529273da6ffSWenhui Sheng amdgpu_reset_method); 530273da6ffSWenhui Sheng 531ca6fd7a6SLikun Gao switch (adev->asic_type) { 53216086355SAlex Deucher case CHIP_VANGOGH: 53316086355SAlex Deucher return AMD_RESET_METHOD_MODE2; 534ca6fd7a6SLikun Gao case CHIP_SIENNA_CICHLID: 53522dd44f4SJiansong Chen case CHIP_NAVY_FLOUNDER: 53615ed44c0STao Zhou case CHIP_DIMGREY_CAVEFISH: 537ca6fd7a6SLikun Gao return AMD_RESET_METHOD_MODE1; 538ca6fd7a6SLikun Gao default: 539181e772fSEvan Quan if (amdgpu_dpm_is_baco_supported(adev)) 5402ddc6c3eSAlex Deucher return AMD_RESET_METHOD_BACO; 5412ddc6c3eSAlex Deucher else 5422ddc6c3eSAlex Deucher return AMD_RESET_METHOD_MODE1; 5432ddc6c3eSAlex Deucher } 544ca6fd7a6SLikun Gao } 5452ddc6c3eSAlex Deucher 546c6b6a421SHawking Zhang static int nv_asic_reset(struct amdgpu_device *adev) 547c6b6a421SHawking Zhang { 548767acabdSKevin Wang int ret = 0; 549c6b6a421SHawking Zhang 55016086355SAlex Deucher switch (nv_asic_reset_method(adev)) { 551f172865aSAlex Deucher case AMD_RESET_METHOD_PCI: 552f172865aSAlex Deucher dev_info(adev->dev, "PCI reset\n"); 553f172865aSAlex Deucher ret = amdgpu_device_pci_reset(adev); 554f172865aSAlex Deucher break; 55516086355SAlex Deucher case AMD_RESET_METHOD_BACO: 55611043b7aSAlex Deucher dev_info(adev->dev, "BACO reset\n"); 557181e772fSEvan Quan ret = amdgpu_dpm_baco_reset(adev); 55816086355SAlex Deucher break; 55916086355SAlex Deucher case AMD_RESET_METHOD_MODE2: 56016086355SAlex Deucher dev_info(adev->dev, "MODE2 reset\n"); 561b913ec62SAlex Deucher ret = nv_asic_mode2_reset(adev); 56216086355SAlex Deucher break; 56316086355SAlex Deucher default: 56411043b7aSAlex Deucher dev_info(adev->dev, "MODE1 reset\n"); 5655c03e584SFeifei Xu ret = amdgpu_device_mode1_reset(adev); 56616086355SAlex Deucher break; 56711043b7aSAlex Deucher } 568767acabdSKevin Wang 569767acabdSKevin Wang return ret; 570c6b6a421SHawking Zhang } 571c6b6a421SHawking Zhang 572c6b6a421SHawking Zhang static int nv_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk) 573c6b6a421SHawking Zhang { 574c6b6a421SHawking Zhang /* todo */ 575c6b6a421SHawking Zhang return 0; 576c6b6a421SHawking Zhang } 577c6b6a421SHawking Zhang 578c6b6a421SHawking Zhang static int nv_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk) 579c6b6a421SHawking Zhang { 580c6b6a421SHawking Zhang /* todo */ 581c6b6a421SHawking Zhang return 0; 582c6b6a421SHawking Zhang } 583c6b6a421SHawking Zhang 584c6b6a421SHawking Zhang static void nv_pcie_gen3_enable(struct amdgpu_device *adev) 585c6b6a421SHawking Zhang { 586c6b6a421SHawking Zhang if (pci_is_root_bus(adev->pdev->bus)) 587c6b6a421SHawking Zhang return; 588c6b6a421SHawking Zhang 589c6b6a421SHawking Zhang if (amdgpu_pcie_gen2 == 0) 590c6b6a421SHawking Zhang return; 591c6b6a421SHawking Zhang 592c6b6a421SHawking Zhang if (!(adev->pm.pcie_gen_mask & (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 | 593c6b6a421SHawking Zhang CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3))) 594c6b6a421SHawking Zhang return; 595c6b6a421SHawking Zhang 596c6b6a421SHawking Zhang /* todo */ 597c6b6a421SHawking Zhang } 598c6b6a421SHawking Zhang 599c6b6a421SHawking Zhang static void nv_program_aspm(struct amdgpu_device *adev) 600c6b6a421SHawking Zhang { 601e1edaeafSLikun Gao if (amdgpu_aspm != 1) 602c6b6a421SHawking Zhang return; 603c6b6a421SHawking Zhang 6043273f8b9SKenneth Feng if (!(adev->flags & AMD_IS_APU) && 605e1edaeafSLikun Gao (adev->nbio.funcs->program_aspm)) 606e1edaeafSLikun Gao adev->nbio.funcs->program_aspm(adev); 607e1edaeafSLikun Gao 608c6b6a421SHawking Zhang } 609c6b6a421SHawking Zhang 610c6b6a421SHawking Zhang static void nv_enable_doorbell_aperture(struct amdgpu_device *adev, 611c6b6a421SHawking Zhang bool enable) 612c6b6a421SHawking Zhang { 613bebc0762SHawking Zhang adev->nbio.funcs->enable_doorbell_aperture(adev, enable); 614bebc0762SHawking Zhang adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, enable); 615c6b6a421SHawking Zhang } 616c6b6a421SHawking Zhang 617c6b6a421SHawking Zhang static const struct amdgpu_ip_block_version nv_common_ip_block = 618c6b6a421SHawking Zhang { 619c6b6a421SHawking Zhang .type = AMD_IP_BLOCK_TYPE_COMMON, 620c6b6a421SHawking Zhang .major = 1, 621c6b6a421SHawking Zhang .minor = 0, 622c6b6a421SHawking Zhang .rev = 0, 623c6b6a421SHawking Zhang .funcs = &nv_common_ip_funcs, 624c6b6a421SHawking Zhang }; 625c6b6a421SHawking Zhang 626b5c73856SXiaojie Yuan static int nv_reg_base_init(struct amdgpu_device *adev) 627c6b6a421SHawking Zhang { 628b5c73856SXiaojie Yuan int r; 629b5c73856SXiaojie Yuan 630b5c73856SXiaojie Yuan if (amdgpu_discovery) { 631b5c73856SXiaojie Yuan r = amdgpu_discovery_reg_base_init(adev); 632b5c73856SXiaojie Yuan if (r) { 633b5c73856SXiaojie Yuan DRM_WARN("failed to init reg base from ip discovery table, " 634b5c73856SXiaojie Yuan "fallback to legacy init method\n"); 635b5c73856SXiaojie Yuan goto legacy_init; 636b5c73856SXiaojie Yuan } 637b5c73856SXiaojie Yuan 638b5c73856SXiaojie Yuan return 0; 639b5c73856SXiaojie Yuan } 640b5c73856SXiaojie Yuan 641b5c73856SXiaojie Yuan legacy_init: 642c6b6a421SHawking Zhang switch (adev->asic_type) { 643c6b6a421SHawking Zhang case CHIP_NAVI10: 644c6b6a421SHawking Zhang navi10_reg_base_init(adev); 645c6b6a421SHawking Zhang break; 646a0f6d926SXiaojie Yuan case CHIP_NAVI14: 647a0f6d926SXiaojie Yuan navi14_reg_base_init(adev); 648a0f6d926SXiaojie Yuan break; 64903d0a073SXiaojie Yuan case CHIP_NAVI12: 65003d0a073SXiaojie Yuan navi12_reg_base_init(adev); 65103d0a073SXiaojie Yuan break; 652dccdbf3fSLikun Gao case CHIP_SIENNA_CICHLID: 653c8c959f6SJiansong Chen case CHIP_NAVY_FLOUNDER: 654dccdbf3fSLikun Gao sienna_cichlid_reg_base_init(adev); 655dccdbf3fSLikun Gao break; 656026570e6SHuang Rui case CHIP_VANGOGH: 657026570e6SHuang Rui vangogh_reg_base_init(adev); 658026570e6SHuang Rui break; 659038d757bSTao Zhou case CHIP_DIMGREY_CAVEFISH: 660038d757bSTao Zhou dimgrey_cavefish_reg_base_init(adev); 661038d757bSTao Zhou break; 662c6b6a421SHawking Zhang default: 663c6b6a421SHawking Zhang return -EINVAL; 664c6b6a421SHawking Zhang } 665c6b6a421SHawking Zhang 666b5c73856SXiaojie Yuan return 0; 667b5c73856SXiaojie Yuan } 668b5c73856SXiaojie Yuan 669c1299461SWenhui Sheng void nv_set_virt_ops(struct amdgpu_device *adev) 670c1299461SWenhui Sheng { 671c1299461SWenhui Sheng adev->virt.ops = &xgpu_nv_virt_ops; 672c1299461SWenhui Sheng } 673c1299461SWenhui Sheng 6749c94b5efSFlora Cui static bool nv_is_headless_sku(struct pci_dev *pdev) 675aa5375c5STianci.Yin { 676dd657888SFlora Cui if ((pdev->device == 0x731E && 677dd657888SFlora Cui (pdev->revision == 0xC6 || pdev->revision == 0xC7)) || 678650bc7aeSAsher.Song (pdev->device == 0x7340 && pdev->revision == 0xC9) || 679650bc7aeSAsher.Song (pdev->device == 0x7360 && pdev->revision == 0xC7)) 680aa5375c5STianci.Yin return true; 681aa5375c5STianci.Yin return false; 682aa5375c5STianci.Yin } 683aa5375c5STianci.Yin 684b5c73856SXiaojie Yuan int nv_set_ip_blocks(struct amdgpu_device *adev) 685b5c73856SXiaojie Yuan { 686b5c73856SXiaojie Yuan int r; 687b5c73856SXiaojie Yuan 688a7e91bd7SHuang Rui if (adev->flags & AMD_IS_APU) { 689a7e91bd7SHuang Rui adev->nbio.funcs = &nbio_v7_2_funcs; 690a7e91bd7SHuang Rui adev->nbio.hdp_flush_reg = &nbio_v7_2_hdp_flush_reg; 691a7e91bd7SHuang Rui } else { 692122078deSMonk Liu adev->nbio.funcs = &nbio_v2_3_funcs; 693122078deSMonk Liu adev->nbio.hdp_flush_reg = &nbio_v2_3_hdp_flush_reg; 694a7e91bd7SHuang Rui } 695bf087285SLikun Gao adev->hdp.funcs = &hdp_v5_0_funcs; 696122078deSMonk Liu 6970bf7f2dcSLikun Gao if (adev->asic_type >= CHIP_SIENNA_CICHLID) 6980bf7f2dcSLikun Gao adev->smuio.funcs = &smuio_v11_0_6_funcs; 6990bf7f2dcSLikun Gao else 7000bf7f2dcSLikun Gao adev->smuio.funcs = &smuio_v11_0_funcs; 7010bf7f2dcSLikun Gao 702c652923aSJohn Clements if (adev->asic_type == CHIP_SIENNA_CICHLID) 703c652923aSJohn Clements adev->gmc.xgmi.supported = true; 704c652923aSJohn Clements 705b5c73856SXiaojie Yuan /* Set IP register base before any HW register access */ 706b5c73856SXiaojie Yuan r = nv_reg_base_init(adev); 707b5c73856SXiaojie Yuan if (r) 708b5c73856SXiaojie Yuan return r; 709b5c73856SXiaojie Yuan 710c6b6a421SHawking Zhang switch (adev->asic_type) { 711c6b6a421SHawking Zhang case CHIP_NAVI10: 712d1daf850SAlex Deucher case CHIP_NAVI14: 713c6b6a421SHawking Zhang amdgpu_device_ip_block_add(adev, &nv_common_ip_block); 714c6b6a421SHawking Zhang amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block); 715c6b6a421SHawking Zhang amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block); 716c6b6a421SHawking Zhang amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block); 717c6b6a421SHawking Zhang if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP && 7189530273eSEvan Quan !amdgpu_sriov_vf(adev)) 719c6b6a421SHawking Zhang amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 720c6b6a421SHawking Zhang if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) 721c6b6a421SHawking Zhang amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block); 722f8a7976bSAlex Deucher #if defined(CONFIG_DRM_AMD_DC) 7238301f6b9STianci.Yin else if (amdgpu_device_has_dc_support(adev)) 724b4f199c7SHarry Wentland amdgpu_device_ip_block_add(adev, &dm_ip_block); 725f8a7976bSAlex Deucher #endif 726c6b6a421SHawking Zhang amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block); 727c6b6a421SHawking Zhang amdgpu_device_ip_block_add(adev, &sdma_v5_0_ip_block); 728c6b6a421SHawking Zhang if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT && 7299530273eSEvan Quan !amdgpu_sriov_vf(adev)) 730c6b6a421SHawking Zhang amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 7319c94b5efSFlora Cui if (!nv_is_headless_sku(adev->pdev)) 732c6b6a421SHawking Zhang amdgpu_device_ip_block_add(adev, &vcn_v2_0_ip_block); 7335be45a26SLeo Liu amdgpu_device_ip_block_add(adev, &jpeg_v2_0_ip_block); 734c6b6a421SHawking Zhang if (adev->enable_mes) 735c6b6a421SHawking Zhang amdgpu_device_ip_block_add(adev, &mes_v10_1_ip_block); 736c6b6a421SHawking Zhang break; 73744e9e7c9SXiaojie Yuan case CHIP_NAVI12: 73844e9e7c9SXiaojie Yuan amdgpu_device_ip_block_add(adev, &nv_common_ip_block); 73944e9e7c9SXiaojie Yuan amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block); 74044e9e7c9SXiaojie Yuan amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block); 7416b66ae2eSXiaojie Yuan amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block); 74279bebabbSMonk Liu if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) 7437f47efebSXiaojie Yuan amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 74479902029SXiaojie Yuan if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) 74579902029SXiaojie Yuan amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block); 74620c14ee1SPetr Cvek #if defined(CONFIG_DRM_AMD_DC) 747078655d9SLeo Li else if (amdgpu_device_has_dc_support(adev)) 748078655d9SLeo Li amdgpu_device_ip_block_add(adev, &dm_ip_block); 74920c14ee1SPetr Cvek #endif 75044e9e7c9SXiaojie Yuan amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block); 75144e9e7c9SXiaojie Yuan amdgpu_device_ip_block_add(adev, &sdma_v5_0_ip_block); 7527f47efebSXiaojie Yuan if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT && 7539530273eSEvan Quan !amdgpu_sriov_vf(adev)) 7547f47efebSXiaojie Yuan amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 755650bc7aeSAsher.Song if (!nv_is_headless_sku(adev->pdev)) 7561fbed280SBoyuan Zhang amdgpu_device_ip_block_add(adev, &vcn_v2_0_ip_block); 757fe442491SMonk Liu if (!amdgpu_sriov_vf(adev)) 7585be45a26SLeo Liu amdgpu_device_ip_block_add(adev, &jpeg_v2_0_ip_block); 75944e9e7c9SXiaojie Yuan break; 7602e1ba10eSLikun Gao case CHIP_SIENNA_CICHLID: 7612e1ba10eSLikun Gao amdgpu_device_ip_block_add(adev, &nv_common_ip_block); 7620b3df16bSLikun Gao amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block); 763757b3af8SLikun Gao amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block); 76456304e72SLikun Gao if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) 7655aa02350SLikun Gao amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block); 766b07e5c60SLikun Gao if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP && 767acf2740fSJane Jian is_support_sw_smu(adev)) 768b07e5c60SLikun Gao amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 7699a986760SLikun Gao if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) 7709a986760SLikun Gao amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block); 771464ab91aSBhawanpreet Lakha #if defined(CONFIG_DRM_AMD_DC) 772464ab91aSBhawanpreet Lakha else if (amdgpu_device_has_dc_support(adev)) 773464ab91aSBhawanpreet Lakha amdgpu_device_ip_block_add(adev, &dm_ip_block); 774464ab91aSBhawanpreet Lakha #endif 775933c8a93SLikun Gao amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block); 776157e72e8SLikun Gao amdgpu_device_ip_block_add(adev, &sdma_v5_2_ip_block); 777b8f10585SLeo Liu amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block); 778c45fbe1bSJack Zhang if (!amdgpu_sriov_vf(adev)) 7794d72dd12SLeo Liu amdgpu_device_ip_block_add(adev, &jpeg_v3_0_ip_block); 780c45fbe1bSJack Zhang 781a346ef86SJack Xiao if (adev->enable_mes) 782a346ef86SJack Xiao amdgpu_device_ip_block_add(adev, &mes_v10_1_ip_block); 7832e1ba10eSLikun Gao break; 7848515e0a4SJiansong Chen case CHIP_NAVY_FLOUNDER: 7858515e0a4SJiansong Chen amdgpu_device_ip_block_add(adev, &nv_common_ip_block); 786fc8f07daSJiansong Chen amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block); 787026c396bSJiansong Chen amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block); 7887420eab2SJiansong Chen if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) 7897420eab2SJiansong Chen amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block); 7907420eab2SJiansong Chen if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP && 7917420eab2SJiansong Chen is_support_sw_smu(adev)) 7927420eab2SJiansong Chen amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 7935404f073SJiansong Chen if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) 7945404f073SJiansong Chen amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block); 795a6c5308fSBhawanpreet Lakha #if defined(CONFIG_DRM_AMD_DC) 796a6c5308fSBhawanpreet Lakha else if (amdgpu_device_has_dc_support(adev)) 797a6c5308fSBhawanpreet Lakha amdgpu_device_ip_block_add(adev, &dm_ip_block); 798a6c5308fSBhawanpreet Lakha #endif 799885eb3faSJiansong Chen amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block); 800df2d15dfSJiansong Chen amdgpu_device_ip_block_add(adev, &sdma_v5_2_ip_block); 801290b4ad5SBoyuan Zhang amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block); 802290b4ad5SBoyuan Zhang amdgpu_device_ip_block_add(adev, &jpeg_v3_0_ip_block); 803f4497d10SJiansong Chen if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT && 804f4497d10SJiansong Chen is_support_sw_smu(adev)) 805f4497d10SJiansong Chen amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 8068515e0a4SJiansong Chen break; 80788edbad6SHuang Rui case CHIP_VANGOGH: 80888edbad6SHuang Rui amdgpu_device_ip_block_add(adev, &nv_common_ip_block); 80988edbad6SHuang Rui amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block); 81088edbad6SHuang Rui amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block); 811ed3b7353SHuang Rui if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) 812ed3b7353SHuang Rui amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block); 813c821e0fbSHuang Rui amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 81488edbad6SHuang Rui if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) 81588edbad6SHuang Rui amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block); 81684b934bcSHuang Rui #if defined(CONFIG_DRM_AMD_DC) 81784b934bcSHuang Rui else if (amdgpu_device_has_dc_support(adev)) 81884b934bcSHuang Rui amdgpu_device_ip_block_add(adev, &dm_ip_block); 81984b934bcSHuang Rui #endif 82088edbad6SHuang Rui amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block); 82188edbad6SHuang Rui amdgpu_device_ip_block_add(adev, &sdma_v5_2_ip_block); 822b4e532d6SThong Thai amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block); 823b4e532d6SThong Thai amdgpu_device_ip_block_add(adev, &jpeg_v3_0_ip_block); 82488edbad6SHuang Rui break; 8252aa92b12STao Zhou case CHIP_DIMGREY_CAVEFISH: 8262aa92b12STao Zhou amdgpu_device_ip_block_add(adev, &nv_common_ip_block); 8273e02ad44STao Zhou amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block); 828771cc67eSTao Zhou amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block); 829aff39cdeSTao Zhou if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) 830aff39cdeSTao Zhou amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block); 831aff39cdeSTao Zhou if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP && 832aff39cdeSTao Zhou is_support_sw_smu(adev)) 833aff39cdeSTao Zhou amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 83476a2d9eaSTao Zhou if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) 83576a2d9eaSTao Zhou amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block); 8367cc656e2STao Zhou #if defined(CONFIG_DRM_AMD_DC) 8377cc656e2STao Zhou else if (amdgpu_device_has_dc_support(adev)) 8387cc656e2STao Zhou amdgpu_device_ip_block_add(adev, &dm_ip_block); 8397cc656e2STao Zhou #endif 840feb6329cSTao Zhou amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block); 84101069226STao Zhou amdgpu_device_ip_block_add(adev, &sdma_v5_2_ip_block); 8420afc770bSJames Zhu amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block); 843be6b1cd3SJames Zhu amdgpu_device_ip_block_add(adev, &jpeg_v3_0_ip_block); 8442aa92b12STao Zhou break; 845c6b6a421SHawking Zhang default: 846c6b6a421SHawking Zhang return -EINVAL; 847c6b6a421SHawking Zhang } 848c6b6a421SHawking Zhang 849c6b6a421SHawking Zhang return 0; 850c6b6a421SHawking Zhang } 851c6b6a421SHawking Zhang 852c6b6a421SHawking Zhang static uint32_t nv_get_rev_id(struct amdgpu_device *adev) 853c6b6a421SHawking Zhang { 854bebc0762SHawking Zhang return adev->nbio.funcs->get_rev_id(adev); 855c6b6a421SHawking Zhang } 856c6b6a421SHawking Zhang 857c6b6a421SHawking Zhang static bool nv_need_full_reset(struct amdgpu_device *adev) 858c6b6a421SHawking Zhang { 859c6b6a421SHawking Zhang return true; 860c6b6a421SHawking Zhang } 861c6b6a421SHawking Zhang 862c6b6a421SHawking Zhang static bool nv_need_reset_on_init(struct amdgpu_device *adev) 863c6b6a421SHawking Zhang { 864c6b6a421SHawking Zhang u32 sol_reg; 865c6b6a421SHawking Zhang 866c6b6a421SHawking Zhang if (adev->flags & AMD_IS_APU) 867c6b6a421SHawking Zhang return false; 868c6b6a421SHawking Zhang 869c6b6a421SHawking Zhang /* Check sOS sign of life register to confirm sys driver and sOS 870c6b6a421SHawking Zhang * are already been loaded. 871c6b6a421SHawking Zhang */ 872c6b6a421SHawking Zhang sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81); 873c6b6a421SHawking Zhang if (sol_reg) 874c6b6a421SHawking Zhang return true; 8753967ae6dSAlex Deucher 876c6b6a421SHawking Zhang return false; 877c6b6a421SHawking Zhang } 878c6b6a421SHawking Zhang 8792af81531SKevin Wang static uint64_t nv_get_pcie_replay_count(struct amdgpu_device *adev) 8802af81531SKevin Wang { 8812af81531SKevin Wang 8822af81531SKevin Wang /* TODO 8832af81531SKevin Wang * dummy implement for pcie_replay_count sysfs interface 8842af81531SKevin Wang * */ 8852af81531SKevin Wang 8862af81531SKevin Wang return 0; 8872af81531SKevin Wang } 8882af81531SKevin Wang 889c6b6a421SHawking Zhang static void nv_init_doorbell_index(struct amdgpu_device *adev) 890c6b6a421SHawking Zhang { 891c6b6a421SHawking Zhang adev->doorbell_index.kiq = AMDGPU_NAVI10_DOORBELL_KIQ; 892c6b6a421SHawking Zhang adev->doorbell_index.mec_ring0 = AMDGPU_NAVI10_DOORBELL_MEC_RING0; 893c6b6a421SHawking Zhang adev->doorbell_index.mec_ring1 = AMDGPU_NAVI10_DOORBELL_MEC_RING1; 894c6b6a421SHawking Zhang adev->doorbell_index.mec_ring2 = AMDGPU_NAVI10_DOORBELL_MEC_RING2; 895c6b6a421SHawking Zhang adev->doorbell_index.mec_ring3 = AMDGPU_NAVI10_DOORBELL_MEC_RING3; 896c6b6a421SHawking Zhang adev->doorbell_index.mec_ring4 = AMDGPU_NAVI10_DOORBELL_MEC_RING4; 897c6b6a421SHawking Zhang adev->doorbell_index.mec_ring5 = AMDGPU_NAVI10_DOORBELL_MEC_RING5; 898c6b6a421SHawking Zhang adev->doorbell_index.mec_ring6 = AMDGPU_NAVI10_DOORBELL_MEC_RING6; 899c6b6a421SHawking Zhang adev->doorbell_index.mec_ring7 = AMDGPU_NAVI10_DOORBELL_MEC_RING7; 900c6b6a421SHawking Zhang adev->doorbell_index.userqueue_start = AMDGPU_NAVI10_DOORBELL_USERQUEUE_START; 901c6b6a421SHawking Zhang adev->doorbell_index.userqueue_end = AMDGPU_NAVI10_DOORBELL_USERQUEUE_END; 902c6b6a421SHawking Zhang adev->doorbell_index.gfx_ring0 = AMDGPU_NAVI10_DOORBELL_GFX_RING0; 903c6b6a421SHawking Zhang adev->doorbell_index.gfx_ring1 = AMDGPU_NAVI10_DOORBELL_GFX_RING1; 90420519232SJack Xiao adev->doorbell_index.mes_ring = AMDGPU_NAVI10_DOORBELL_MES_RING; 905c6b6a421SHawking Zhang adev->doorbell_index.sdma_engine[0] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE0; 906c6b6a421SHawking Zhang adev->doorbell_index.sdma_engine[1] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE1; 907157e72e8SLikun Gao adev->doorbell_index.sdma_engine[2] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE2; 908157e72e8SLikun Gao adev->doorbell_index.sdma_engine[3] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE3; 909c6b6a421SHawking Zhang adev->doorbell_index.ih = AMDGPU_NAVI10_DOORBELL_IH; 910c6b6a421SHawking Zhang adev->doorbell_index.vcn.vcn_ring0_1 = AMDGPU_NAVI10_DOORBELL64_VCN0_1; 911c6b6a421SHawking Zhang adev->doorbell_index.vcn.vcn_ring2_3 = AMDGPU_NAVI10_DOORBELL64_VCN2_3; 912c6b6a421SHawking Zhang adev->doorbell_index.vcn.vcn_ring4_5 = AMDGPU_NAVI10_DOORBELL64_VCN4_5; 913c6b6a421SHawking Zhang adev->doorbell_index.vcn.vcn_ring6_7 = AMDGPU_NAVI10_DOORBELL64_VCN6_7; 914c6b6a421SHawking Zhang adev->doorbell_index.first_non_cp = AMDGPU_NAVI10_DOORBELL64_FIRST_NON_CP; 915c6b6a421SHawking Zhang adev->doorbell_index.last_non_cp = AMDGPU_NAVI10_DOORBELL64_LAST_NON_CP; 916c6b6a421SHawking Zhang 917c6b6a421SHawking Zhang adev->doorbell_index.max_assignment = AMDGPU_NAVI10_DOORBELL_MAX_ASSIGNMENT << 1; 918c6b6a421SHawking Zhang adev->doorbell_index.sdma_doorbell_range = 20; 919c6b6a421SHawking Zhang } 920c6b6a421SHawking Zhang 921a7173731SAlex Deucher static void nv_pre_asic_init(struct amdgpu_device *adev) 922a7173731SAlex Deucher { 923a7173731SAlex Deucher } 924a7173731SAlex Deucher 92527747293SEvan Quan static int nv_update_umd_stable_pstate(struct amdgpu_device *adev, 92627747293SEvan Quan bool enter) 92727747293SEvan Quan { 92827747293SEvan Quan if (enter) 92927747293SEvan Quan amdgpu_gfx_rlc_enter_safe_mode(adev); 93027747293SEvan Quan else 93127747293SEvan Quan amdgpu_gfx_rlc_exit_safe_mode(adev); 93227747293SEvan Quan 93327747293SEvan Quan if (adev->gfx.funcs->update_perfmon_mgcg) 93427747293SEvan Quan adev->gfx.funcs->update_perfmon_mgcg(adev, !enter); 93527747293SEvan Quan 9363273f8b9SKenneth Feng if (!(adev->flags & AMD_IS_APU) && 937e1edaeafSLikun Gao (adev->nbio.funcs->enable_aspm)) 93827747293SEvan Quan adev->nbio.funcs->enable_aspm(adev, !enter); 93927747293SEvan Quan 94027747293SEvan Quan return 0; 94127747293SEvan Quan } 94227747293SEvan Quan 943c6b6a421SHawking Zhang static const struct amdgpu_asic_funcs nv_asic_funcs = 944c6b6a421SHawking Zhang { 945c6b6a421SHawking Zhang .read_disabled_bios = &nv_read_disabled_bios, 946c6b6a421SHawking Zhang .read_bios_from_rom = &nv_read_bios_from_rom, 947c6b6a421SHawking Zhang .read_register = &nv_read_register, 948c6b6a421SHawking Zhang .reset = &nv_asic_reset, 9492ddc6c3eSAlex Deucher .reset_method = &nv_asic_reset_method, 950c6b6a421SHawking Zhang .set_vga_state = &nv_vga_set_state, 951c6b6a421SHawking Zhang .get_xclk = &nv_get_xclk, 952c6b6a421SHawking Zhang .set_uvd_clocks = &nv_set_uvd_clocks, 953c6b6a421SHawking Zhang .set_vce_clocks = &nv_set_vce_clocks, 954c6b6a421SHawking Zhang .get_config_memsize = &nv_get_config_memsize, 955c6b6a421SHawking Zhang .init_doorbell_index = &nv_init_doorbell_index, 956c6b6a421SHawking Zhang .need_full_reset = &nv_need_full_reset, 957c6b6a421SHawking Zhang .need_reset_on_init = &nv_need_reset_on_init, 9582af81531SKevin Wang .get_pcie_replay_count = &nv_get_pcie_replay_count, 959181e772fSEvan Quan .supports_baco = &amdgpu_dpm_is_baco_supported, 960a7173731SAlex Deucher .pre_asic_init = &nv_pre_asic_init, 96127747293SEvan Quan .update_umd_stable_pstate = &nv_update_umd_stable_pstate, 9623b246e8bSAlex Deucher .query_video_codecs = &nv_query_video_codecs, 963c6b6a421SHawking Zhang }; 964c6b6a421SHawking Zhang 965c6b6a421SHawking Zhang static int nv_common_early_init(void *handle) 966c6b6a421SHawking Zhang { 967923c087aSYong Zhao #define MMIO_REG_HOLE_OFFSET (0x80000 - PAGE_SIZE) 968c6b6a421SHawking Zhang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 969c6b6a421SHawking Zhang 970923c087aSYong Zhao adev->rmmio_remap.reg_offset = MMIO_REG_HOLE_OFFSET; 971923c087aSYong Zhao adev->rmmio_remap.bus_addr = adev->rmmio_base + MMIO_REG_HOLE_OFFSET; 972c6b6a421SHawking Zhang adev->smc_rreg = NULL; 973c6b6a421SHawking Zhang adev->smc_wreg = NULL; 974c6b6a421SHawking Zhang adev->pcie_rreg = &nv_pcie_rreg; 975c6b6a421SHawking Zhang adev->pcie_wreg = &nv_pcie_wreg; 9764922f1bcSJohn Clements adev->pcie_rreg64 = &nv_pcie_rreg64; 9774922f1bcSJohn Clements adev->pcie_wreg64 = &nv_pcie_wreg64; 9785de54343SHuang Rui adev->pciep_rreg = &nv_pcie_port_rreg; 9795de54343SHuang Rui adev->pciep_wreg = &nv_pcie_port_wreg; 980c6b6a421SHawking Zhang 981c6b6a421SHawking Zhang /* TODO: will add them during VCN v2 implementation */ 982c6b6a421SHawking Zhang adev->uvd_ctx_rreg = NULL; 983c6b6a421SHawking Zhang adev->uvd_ctx_wreg = NULL; 984c6b6a421SHawking Zhang 985c6b6a421SHawking Zhang adev->didt_rreg = &nv_didt_rreg; 986c6b6a421SHawking Zhang adev->didt_wreg = &nv_didt_wreg; 987c6b6a421SHawking Zhang 988c6b6a421SHawking Zhang adev->asic_funcs = &nv_asic_funcs; 989c6b6a421SHawking Zhang 990c6b6a421SHawking Zhang adev->rev_id = nv_get_rev_id(adev); 991c6b6a421SHawking Zhang adev->external_rev_id = 0xff; 992c6b6a421SHawking Zhang switch (adev->asic_type) { 993c6b6a421SHawking Zhang case CHIP_NAVI10: 994c6b6a421SHawking Zhang adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 995c6b6a421SHawking Zhang AMD_CG_SUPPORT_GFX_CGCG | 996c6b6a421SHawking Zhang AMD_CG_SUPPORT_IH_CG | 997c6b6a421SHawking Zhang AMD_CG_SUPPORT_HDP_MGCG | 998c6b6a421SHawking Zhang AMD_CG_SUPPORT_HDP_LS | 999c6b6a421SHawking Zhang AMD_CG_SUPPORT_SDMA_MGCG | 1000c6b6a421SHawking Zhang AMD_CG_SUPPORT_SDMA_LS | 1001c6b6a421SHawking Zhang AMD_CG_SUPPORT_MC_MGCG | 1002c6b6a421SHawking Zhang AMD_CG_SUPPORT_MC_LS | 1003c6b6a421SHawking Zhang AMD_CG_SUPPORT_ATHUB_MGCG | 1004c6b6a421SHawking Zhang AMD_CG_SUPPORT_ATHUB_LS | 1005c6b6a421SHawking Zhang AMD_CG_SUPPORT_VCN_MGCG | 1006099d66e4SLeo Liu AMD_CG_SUPPORT_JPEG_MGCG | 1007c6b6a421SHawking Zhang AMD_CG_SUPPORT_BIF_MGCG | 1008c6b6a421SHawking Zhang AMD_CG_SUPPORT_BIF_LS; 1009157710eaSLeo Liu adev->pg_flags = AMD_PG_SUPPORT_VCN | 1010c12d410fSHuang Rui AMD_PG_SUPPORT_VCN_DPG | 1011099d66e4SLeo Liu AMD_PG_SUPPORT_JPEG | 1012a201b6acSHuang Rui AMD_PG_SUPPORT_ATHUB; 1013c6b6a421SHawking Zhang adev->external_rev_id = adev->rev_id + 0x1; 1014c6b6a421SHawking Zhang break; 10155e71e011SXiaojie Yuan case CHIP_NAVI14: 1016d0c39f8cSXiaojie Yuan adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 1017d0c39f8cSXiaojie Yuan AMD_CG_SUPPORT_GFX_CGCG | 1018d0c39f8cSXiaojie Yuan AMD_CG_SUPPORT_IH_CG | 1019d0c39f8cSXiaojie Yuan AMD_CG_SUPPORT_HDP_MGCG | 1020d0c39f8cSXiaojie Yuan AMD_CG_SUPPORT_HDP_LS | 1021d0c39f8cSXiaojie Yuan AMD_CG_SUPPORT_SDMA_MGCG | 1022d0c39f8cSXiaojie Yuan AMD_CG_SUPPORT_SDMA_LS | 1023d0c39f8cSXiaojie Yuan AMD_CG_SUPPORT_MC_MGCG | 1024d0c39f8cSXiaojie Yuan AMD_CG_SUPPORT_MC_LS | 1025d0c39f8cSXiaojie Yuan AMD_CG_SUPPORT_ATHUB_MGCG | 1026d0c39f8cSXiaojie Yuan AMD_CG_SUPPORT_ATHUB_LS | 1027d0c39f8cSXiaojie Yuan AMD_CG_SUPPORT_VCN_MGCG | 1028099d66e4SLeo Liu AMD_CG_SUPPORT_JPEG_MGCG | 1029d0c39f8cSXiaojie Yuan AMD_CG_SUPPORT_BIF_MGCG | 1030d0c39f8cSXiaojie Yuan AMD_CG_SUPPORT_BIF_LS; 10310377b088SXiaojie Yuan adev->pg_flags = AMD_PG_SUPPORT_VCN | 1032099d66e4SLeo Liu AMD_PG_SUPPORT_JPEG | 10330377b088SXiaojie Yuan AMD_PG_SUPPORT_VCN_DPG; 103435ef88faStiancyin adev->external_rev_id = adev->rev_id + 20; 10355e71e011SXiaojie Yuan break; 103674b5e509SXiaojie Yuan case CHIP_NAVI12: 1037dca009e7SXiaojie Yuan adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 1038dca009e7SXiaojie Yuan AMD_CG_SUPPORT_GFX_MGLS | 1039dca009e7SXiaojie Yuan AMD_CG_SUPPORT_GFX_CGCG | 1040dca009e7SXiaojie Yuan AMD_CG_SUPPORT_GFX_CP_LS | 10415211c37aSXiaojie Yuan AMD_CG_SUPPORT_GFX_RLC_LS | 1042fbe0bc57SXiaojie Yuan AMD_CG_SUPPORT_IH_CG | 10435211c37aSXiaojie Yuan AMD_CG_SUPPORT_HDP_MGCG | 1044358ab97fSXiaojie Yuan AMD_CG_SUPPORT_HDP_LS | 1045358ab97fSXiaojie Yuan AMD_CG_SUPPORT_SDMA_MGCG | 10468b797b3dSXiaojie Yuan AMD_CG_SUPPORT_SDMA_LS | 10478b797b3dSXiaojie Yuan AMD_CG_SUPPORT_MC_MGCG | 1048ca51678dSXiaojie Yuan AMD_CG_SUPPORT_MC_LS | 1049ca51678dSXiaojie Yuan AMD_CG_SUPPORT_ATHUB_MGCG | 105065872e59SXiaojie Yuan AMD_CG_SUPPORT_ATHUB_LS | 1051099d66e4SLeo Liu AMD_CG_SUPPORT_VCN_MGCG | 1052099d66e4SLeo Liu AMD_CG_SUPPORT_JPEG_MGCG; 1053c1653ea0SXiaojie Yuan adev->pg_flags = AMD_PG_SUPPORT_VCN | 10545ef3b8acSXiaojie Yuan AMD_PG_SUPPORT_VCN_DPG | 1055099d66e4SLeo Liu AMD_PG_SUPPORT_JPEG | 10561b0443b1SLikun Gao AMD_PG_SUPPORT_ATHUB; 1057df5e984cSTiecheng Zhou /* guest vm gets 0xffffffff when reading RCC_DEV0_EPF0_STRAP0, 1058df5e984cSTiecheng Zhou * as a consequence, the rev_id and external_rev_id are wrong. 1059df5e984cSTiecheng Zhou * workaround it by hardcoding rev_id to 0 (default value). 1060df5e984cSTiecheng Zhou */ 1061df5e984cSTiecheng Zhou if (amdgpu_sriov_vf(adev)) 1062df5e984cSTiecheng Zhou adev->rev_id = 0; 106374b5e509SXiaojie Yuan adev->external_rev_id = adev->rev_id + 0xa; 106474b5e509SXiaojie Yuan break; 1065117910edSLikun Gao case CHIP_SIENNA_CICHLID: 106600194defSLikun Gao adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 106700194defSLikun Gao AMD_CG_SUPPORT_GFX_CGCG | 1068*1d712be9SKenneth Feng AMD_CG_SUPPORT_GFX_CGLS | 106900194defSLikun Gao AMD_CG_SUPPORT_GFX_3D_CGCG | 107098f8ea29SLikun Gao AMD_CG_SUPPORT_MC_MGCG | 107100194defSLikun Gao AMD_CG_SUPPORT_VCN_MGCG | 1072ca36461fSKenneth Feng AMD_CG_SUPPORT_JPEG_MGCG | 1073ca36461fSKenneth Feng AMD_CG_SUPPORT_HDP_MGCG | 10743a32c25aSKenneth Feng AMD_CG_SUPPORT_HDP_LS | 1075bcc8367fSKenneth Feng AMD_CG_SUPPORT_IH_CG | 1076bcc8367fSKenneth Feng AMD_CG_SUPPORT_MC_LS; 1077b467c4f5SLeo Liu adev->pg_flags = AMD_PG_SUPPORT_VCN | 1078d00b0fa9SBoyuan Zhang AMD_PG_SUPPORT_VCN_DPG | 1079b794616dSKenneth Feng AMD_PG_SUPPORT_JPEG | 10801b0443b1SLikun Gao AMD_PG_SUPPORT_ATHUB | 10811b0443b1SLikun Gao AMD_PG_SUPPORT_MMHUB; 1082c45fbe1bSJack Zhang if (amdgpu_sriov_vf(adev)) { 1083c45fbe1bSJack Zhang /* hypervisor control CG and PG enablement */ 1084c45fbe1bSJack Zhang adev->cg_flags = 0; 1085c45fbe1bSJack Zhang adev->pg_flags = 0; 1086c45fbe1bSJack Zhang } 1087117910edSLikun Gao adev->external_rev_id = adev->rev_id + 0x28; 1088117910edSLikun Gao break; 1089543aa259SJiansong Chen case CHIP_NAVY_FLOUNDER: 109040582e67SJiansong Chen adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 109140582e67SJiansong Chen AMD_CG_SUPPORT_GFX_CGCG | 1092*1d712be9SKenneth Feng AMD_CG_SUPPORT_GFX_CGLS | 109340582e67SJiansong Chen AMD_CG_SUPPORT_GFX_3D_CGCG | 109440582e67SJiansong Chen AMD_CG_SUPPORT_VCN_MGCG | 109592c73756SJiansong Chen AMD_CG_SUPPORT_JPEG_MGCG | 109692c73756SJiansong Chen AMD_CG_SUPPORT_MC_MGCG | 10974759f887SJiansong Chen AMD_CG_SUPPORT_MC_LS | 10984759f887SJiansong Chen AMD_CG_SUPPORT_HDP_MGCG | 109985e7151bSJiansong Chen AMD_CG_SUPPORT_HDP_LS | 110085e7151bSJiansong Chen AMD_CG_SUPPORT_IH_CG; 1101c6e9dd0eSBoyuan Zhang adev->pg_flags = AMD_PG_SUPPORT_VCN | 110200740df9SBoyuan Zhang AMD_PG_SUPPORT_VCN_DPG | 110347fc894aSJiansong Chen AMD_PG_SUPPORT_JPEG | 110447fc894aSJiansong Chen AMD_PG_SUPPORT_ATHUB | 110547fc894aSJiansong Chen AMD_PG_SUPPORT_MMHUB; 1106543aa259SJiansong Chen adev->external_rev_id = adev->rev_id + 0x32; 1107543aa259SJiansong Chen break; 1108543aa259SJiansong Chen 1109026570e6SHuang Rui case CHIP_VANGOGH: 1110c345c89bSHuang Rui adev->apu_flags |= AMD_APU_IS_VANGOGH; 111151a7e938SJinzhou.Su adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 111251a7e938SJinzhou.Su AMD_CG_SUPPORT_GFX_MGLS | 111351a7e938SJinzhou.Su AMD_CG_SUPPORT_GFX_CP_LS | 111451a7e938SJinzhou.Su AMD_CG_SUPPORT_GFX_RLC_LS | 111551a7e938SJinzhou.Su AMD_CG_SUPPORT_GFX_CGCG | 1116ac0dc4c5SHuang Rui AMD_CG_SUPPORT_GFX_CGLS | 1117ac0dc4c5SHuang Rui AMD_CG_SUPPORT_GFX_3D_CGCG | 111807f9c22fSBoyuan Zhang AMD_CG_SUPPORT_GFX_3D_CGLS | 11190ebce667SJinzhou.Su AMD_CG_SUPPORT_MC_MGCG | 11200ebce667SJinzhou.Su AMD_CG_SUPPORT_MC_LS | 1121a3964ec4SJinzhou.Su AMD_CG_SUPPORT_GFX_FGCG | 112207f9c22fSBoyuan Zhang AMD_CG_SUPPORT_VCN_MGCG | 1123ef9bcfdeSJinzhou Su AMD_CG_SUPPORT_SDMA_MGCG | 112407f9c22fSBoyuan Zhang AMD_CG_SUPPORT_JPEG_MGCG; 112507f9c22fSBoyuan Zhang adev->pg_flags = AMD_PG_SUPPORT_GFX_PG | 112607f9c22fSBoyuan Zhang AMD_PG_SUPPORT_VCN | 112707f9c22fSBoyuan Zhang AMD_PG_SUPPORT_VCN_DPG | 112807f9c22fSBoyuan Zhang AMD_PG_SUPPORT_JPEG; 1129c345c89bSHuang Rui if (adev->apu_flags & AMD_APU_IS_VANGOGH) 1130026570e6SHuang Rui adev->external_rev_id = adev->rev_id + 0x01; 1131026570e6SHuang Rui break; 1132550c58e0STao Zhou case CHIP_DIMGREY_CAVEFISH: 1133583e5a5eSTao Zhou adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 1134583e5a5eSTao Zhou AMD_CG_SUPPORT_GFX_CGCG | 1135*1d712be9SKenneth Feng AMD_CG_SUPPORT_GFX_CGLS | 1136583e5a5eSTao Zhou AMD_CG_SUPPORT_GFX_3D_CGCG | 1137583e5a5eSTao Zhou AMD_CG_SUPPORT_VCN_MGCG | 1138135333a0STao Zhou AMD_CG_SUPPORT_JPEG_MGCG | 1139135333a0STao Zhou AMD_CG_SUPPORT_MC_MGCG | 11402c70c332STao Zhou AMD_CG_SUPPORT_MC_LS | 11412c70c332STao Zhou AMD_CG_SUPPORT_HDP_MGCG | 11428e3bfb99STao Zhou AMD_CG_SUPPORT_HDP_LS | 11438e3bfb99STao Zhou AMD_CG_SUPPORT_IH_CG; 1144d5bc1579SJames Zhu adev->pg_flags = AMD_PG_SUPPORT_VCN | 1145cc6161aaSJames Zhu AMD_PG_SUPPORT_VCN_DPG | 114673da8e86STao Zhou AMD_PG_SUPPORT_JPEG | 114773da8e86STao Zhou AMD_PG_SUPPORT_ATHUB | 114873da8e86STao Zhou AMD_PG_SUPPORT_MMHUB; 1149550c58e0STao Zhou adev->external_rev_id = adev->rev_id + 0x3c; 1150550c58e0STao Zhou break; 1151c6b6a421SHawking Zhang default: 1152c6b6a421SHawking Zhang /* FIXME: not supported yet */ 1153c6b6a421SHawking Zhang return -EINVAL; 1154c6b6a421SHawking Zhang } 1155c6b6a421SHawking Zhang 1156b05b6903SJiange Zhao if (amdgpu_sriov_vf(adev)) { 1157b05b6903SJiange Zhao amdgpu_virt_init_setting(adev); 1158b05b6903SJiange Zhao xgpu_nv_mailbox_set_irq_funcs(adev); 1159b05b6903SJiange Zhao } 1160b05b6903SJiange Zhao 1161c6b6a421SHawking Zhang return 0; 1162c6b6a421SHawking Zhang } 1163c6b6a421SHawking Zhang 1164c6b6a421SHawking Zhang static int nv_common_late_init(void *handle) 1165c6b6a421SHawking Zhang { 1166b05b6903SJiange Zhao struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1167b05b6903SJiange Zhao 1168b05b6903SJiange Zhao if (amdgpu_sriov_vf(adev)) 1169b05b6903SJiange Zhao xgpu_nv_mailbox_get_irq(adev); 1170b05b6903SJiange Zhao 1171c6b6a421SHawking Zhang return 0; 1172c6b6a421SHawking Zhang } 1173c6b6a421SHawking Zhang 1174c6b6a421SHawking Zhang static int nv_common_sw_init(void *handle) 1175c6b6a421SHawking Zhang { 1176b05b6903SJiange Zhao struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1177b05b6903SJiange Zhao 1178b05b6903SJiange Zhao if (amdgpu_sriov_vf(adev)) 1179b05b6903SJiange Zhao xgpu_nv_mailbox_add_irq_id(adev); 1180b05b6903SJiange Zhao 1181c6b6a421SHawking Zhang return 0; 1182c6b6a421SHawking Zhang } 1183c6b6a421SHawking Zhang 1184c6b6a421SHawking Zhang static int nv_common_sw_fini(void *handle) 1185c6b6a421SHawking Zhang { 1186c6b6a421SHawking Zhang return 0; 1187c6b6a421SHawking Zhang } 1188c6b6a421SHawking Zhang 1189c6b6a421SHawking Zhang static int nv_common_hw_init(void *handle) 1190c6b6a421SHawking Zhang { 1191c6b6a421SHawking Zhang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1192c6b6a421SHawking Zhang 1193c6b6a421SHawking Zhang /* enable pcie gen2/3 link */ 1194c6b6a421SHawking Zhang nv_pcie_gen3_enable(adev); 1195c6b6a421SHawking Zhang /* enable aspm */ 1196c6b6a421SHawking Zhang nv_program_aspm(adev); 1197c6b6a421SHawking Zhang /* setup nbio registers */ 1198bebc0762SHawking Zhang adev->nbio.funcs->init_registers(adev); 1199923c087aSYong Zhao /* remap HDP registers to a hole in mmio space, 1200923c087aSYong Zhao * for the purpose of expose those registers 1201923c087aSYong Zhao * to process space 1202923c087aSYong Zhao */ 1203923c087aSYong Zhao if (adev->nbio.funcs->remap_hdp_registers) 1204923c087aSYong Zhao adev->nbio.funcs->remap_hdp_registers(adev); 1205c6b6a421SHawking Zhang /* enable the doorbell aperture */ 1206c6b6a421SHawking Zhang nv_enable_doorbell_aperture(adev, true); 1207c6b6a421SHawking Zhang 1208c6b6a421SHawking Zhang return 0; 1209c6b6a421SHawking Zhang } 1210c6b6a421SHawking Zhang 1211c6b6a421SHawking Zhang static int nv_common_hw_fini(void *handle) 1212c6b6a421SHawking Zhang { 1213c6b6a421SHawking Zhang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1214c6b6a421SHawking Zhang 1215c6b6a421SHawking Zhang /* disable the doorbell aperture */ 1216c6b6a421SHawking Zhang nv_enable_doorbell_aperture(adev, false); 1217c6b6a421SHawking Zhang 1218c6b6a421SHawking Zhang return 0; 1219c6b6a421SHawking Zhang } 1220c6b6a421SHawking Zhang 1221c6b6a421SHawking Zhang static int nv_common_suspend(void *handle) 1222c6b6a421SHawking Zhang { 1223c6b6a421SHawking Zhang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1224c6b6a421SHawking Zhang 1225c6b6a421SHawking Zhang return nv_common_hw_fini(adev); 1226c6b6a421SHawking Zhang } 1227c6b6a421SHawking Zhang 1228c6b6a421SHawking Zhang static int nv_common_resume(void *handle) 1229c6b6a421SHawking Zhang { 1230c6b6a421SHawking Zhang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1231c6b6a421SHawking Zhang 1232c6b6a421SHawking Zhang return nv_common_hw_init(adev); 1233c6b6a421SHawking Zhang } 1234c6b6a421SHawking Zhang 1235c6b6a421SHawking Zhang static bool nv_common_is_idle(void *handle) 1236c6b6a421SHawking Zhang { 1237c6b6a421SHawking Zhang return true; 1238c6b6a421SHawking Zhang } 1239c6b6a421SHawking Zhang 1240c6b6a421SHawking Zhang static int nv_common_wait_for_idle(void *handle) 1241c6b6a421SHawking Zhang { 1242c6b6a421SHawking Zhang return 0; 1243c6b6a421SHawking Zhang } 1244c6b6a421SHawking Zhang 1245c6b6a421SHawking Zhang static int nv_common_soft_reset(void *handle) 1246c6b6a421SHawking Zhang { 1247c6b6a421SHawking Zhang return 0; 1248c6b6a421SHawking Zhang } 1249c6b6a421SHawking Zhang 1250c6b6a421SHawking Zhang static int nv_common_set_clockgating_state(void *handle, 1251c6b6a421SHawking Zhang enum amd_clockgating_state state) 1252c6b6a421SHawking Zhang { 1253c6b6a421SHawking Zhang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1254c6b6a421SHawking Zhang 1255c6b6a421SHawking Zhang if (amdgpu_sriov_vf(adev)) 1256c6b6a421SHawking Zhang return 0; 1257c6b6a421SHawking Zhang 1258c6b6a421SHawking Zhang switch (adev->asic_type) { 1259c6b6a421SHawking Zhang case CHIP_NAVI10: 12605e71e011SXiaojie Yuan case CHIP_NAVI14: 12617e17e58bSXiaojie Yuan case CHIP_NAVI12: 1262117910edSLikun Gao case CHIP_SIENNA_CICHLID: 1263543aa259SJiansong Chen case CHIP_NAVY_FLOUNDER: 1264550c58e0STao Zhou case CHIP_DIMGREY_CAVEFISH: 1265bebc0762SHawking Zhang adev->nbio.funcs->update_medium_grain_clock_gating(adev, 1266a9d4fe2fSNirmoy Das state == AMD_CG_STATE_GATE); 1267bebc0762SHawking Zhang adev->nbio.funcs->update_medium_grain_light_sleep(adev, 1268a9d4fe2fSNirmoy Das state == AMD_CG_STATE_GATE); 1269bf087285SLikun Gao adev->hdp.funcs->update_clock_gating(adev, 1270a9d4fe2fSNirmoy Das state == AMD_CG_STATE_GATE); 12711001f2a1SLikun Gao adev->smuio.funcs->update_rom_clock_gating(adev, 12721001f2a1SLikun Gao state == AMD_CG_STATE_GATE); 1273c6b6a421SHawking Zhang break; 1274c6b6a421SHawking Zhang default: 1275c6b6a421SHawking Zhang break; 1276c6b6a421SHawking Zhang } 1277c6b6a421SHawking Zhang return 0; 1278c6b6a421SHawking Zhang } 1279c6b6a421SHawking Zhang 1280c6b6a421SHawking Zhang static int nv_common_set_powergating_state(void *handle, 1281c6b6a421SHawking Zhang enum amd_powergating_state state) 1282c6b6a421SHawking Zhang { 1283c6b6a421SHawking Zhang /* TODO */ 1284c6b6a421SHawking Zhang return 0; 1285c6b6a421SHawking Zhang } 1286c6b6a421SHawking Zhang 1287c6b6a421SHawking Zhang static void nv_common_get_clockgating_state(void *handle, u32 *flags) 1288c6b6a421SHawking Zhang { 1289c6b6a421SHawking Zhang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1290c6b6a421SHawking Zhang 1291c6b6a421SHawking Zhang if (amdgpu_sriov_vf(adev)) 1292c6b6a421SHawking Zhang *flags = 0; 1293c6b6a421SHawking Zhang 1294bebc0762SHawking Zhang adev->nbio.funcs->get_clockgating_state(adev, flags); 1295c6b6a421SHawking Zhang 1296bf087285SLikun Gao adev->hdp.funcs->get_clock_gating_state(adev, flags); 1297c6b6a421SHawking Zhang 12981001f2a1SLikun Gao adev->smuio.funcs->get_clock_gating_state(adev, flags); 12991001f2a1SLikun Gao 1300c6b6a421SHawking Zhang return; 1301c6b6a421SHawking Zhang } 1302c6b6a421SHawking Zhang 1303c6b6a421SHawking Zhang static const struct amd_ip_funcs nv_common_ip_funcs = { 1304c6b6a421SHawking Zhang .name = "nv_common", 1305c6b6a421SHawking Zhang .early_init = nv_common_early_init, 1306c6b6a421SHawking Zhang .late_init = nv_common_late_init, 1307c6b6a421SHawking Zhang .sw_init = nv_common_sw_init, 1308c6b6a421SHawking Zhang .sw_fini = nv_common_sw_fini, 1309c6b6a421SHawking Zhang .hw_init = nv_common_hw_init, 1310c6b6a421SHawking Zhang .hw_fini = nv_common_hw_fini, 1311c6b6a421SHawking Zhang .suspend = nv_common_suspend, 1312c6b6a421SHawking Zhang .resume = nv_common_resume, 1313c6b6a421SHawking Zhang .is_idle = nv_common_is_idle, 1314c6b6a421SHawking Zhang .wait_for_idle = nv_common_wait_for_idle, 1315c6b6a421SHawking Zhang .soft_reset = nv_common_soft_reset, 1316c6b6a421SHawking Zhang .set_clockgating_state = nv_common_set_clockgating_state, 1317c6b6a421SHawking Zhang .set_powergating_state = nv_common_set_powergating_state, 1318c6b6a421SHawking Zhang .get_clockgating_state = nv_common_get_clockgating_state, 1319c6b6a421SHawking Zhang }; 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