1c6b6a421SHawking Zhang /* 2c6b6a421SHawking Zhang * Copyright 2019 Advanced Micro Devices, Inc. 3c6b6a421SHawking Zhang * 4c6b6a421SHawking Zhang * Permission is hereby granted, free of charge, to any person obtaining a 5c6b6a421SHawking Zhang * copy of this software and associated documentation files (the "Software"), 6c6b6a421SHawking Zhang * to deal in the Software without restriction, including without limitation 7c6b6a421SHawking Zhang * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8c6b6a421SHawking Zhang * and/or sell copies of the Software, and to permit persons to whom the 9c6b6a421SHawking Zhang * Software is furnished to do so, subject to the following conditions: 10c6b6a421SHawking Zhang * 11c6b6a421SHawking Zhang * The above copyright notice and this permission notice shall be included in 12c6b6a421SHawking Zhang * all copies or substantial portions of the Software. 13c6b6a421SHawking Zhang * 14c6b6a421SHawking Zhang * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15c6b6a421SHawking Zhang * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16c6b6a421SHawking Zhang * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17c6b6a421SHawking Zhang * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18c6b6a421SHawking Zhang * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19c6b6a421SHawking Zhang * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20c6b6a421SHawking Zhang * OTHER DEALINGS IN THE SOFTWARE. 21c6b6a421SHawking Zhang * 22c6b6a421SHawking Zhang */ 23c6b6a421SHawking Zhang #include <linux/firmware.h> 24c6b6a421SHawking Zhang #include <linux/slab.h> 25c6b6a421SHawking Zhang #include <linux/module.h> 26e9eea902SAlex Deucher #include <linux/pci.h> 27e9eea902SAlex Deucher 28c6b6a421SHawking Zhang #include "amdgpu.h" 29c6b6a421SHawking Zhang #include "amdgpu_atombios.h" 30c6b6a421SHawking Zhang #include "amdgpu_ih.h" 31c6b6a421SHawking Zhang #include "amdgpu_uvd.h" 32c6b6a421SHawking Zhang #include "amdgpu_vce.h" 33c6b6a421SHawking Zhang #include "amdgpu_ucode.h" 34c6b6a421SHawking Zhang #include "amdgpu_psp.h" 35767acabdSKevin Wang #include "amdgpu_smu.h" 36c6b6a421SHawking Zhang #include "atom.h" 37c6b6a421SHawking Zhang #include "amd_pcie.h" 38c6b6a421SHawking Zhang 39c6b6a421SHawking Zhang #include "gc/gc_10_1_0_offset.h" 40c6b6a421SHawking Zhang #include "gc/gc_10_1_0_sh_mask.h" 413967ae6dSAlex Deucher #include "mp/mp_11_0_offset.h" 42c6b6a421SHawking Zhang 43c6b6a421SHawking Zhang #include "soc15.h" 44c6b6a421SHawking Zhang #include "soc15_common.h" 45c6b6a421SHawking Zhang #include "gmc_v10_0.h" 46c6b6a421SHawking Zhang #include "gfxhub_v2_0.h" 47c6b6a421SHawking Zhang #include "mmhub_v2_0.h" 48bebc0762SHawking Zhang #include "nbio_v2_3.h" 49a7e91bd7SHuang Rui #include "nbio_v7_2.h" 50bf087285SLikun Gao #include "hdp_v5_0.h" 51c6b6a421SHawking Zhang #include "nv.h" 52c6b6a421SHawking Zhang #include "navi10_ih.h" 53c6b6a421SHawking Zhang #include "gfx_v10_0.h" 54c6b6a421SHawking Zhang #include "sdma_v5_0.h" 55157e72e8SLikun Gao #include "sdma_v5_2.h" 56c6b6a421SHawking Zhang #include "vcn_v2_0.h" 575be45a26SLeo Liu #include "jpeg_v2_0.h" 58b8f10585SLeo Liu #include "vcn_v3_0.h" 594d72dd12SLeo Liu #include "jpeg_v3_0.h" 60c6b6a421SHawking Zhang #include "dce_virtual.h" 61c6b6a421SHawking Zhang #include "mes_v10_1.h" 62b05b6903SJiange Zhao #include "mxgpu_nv.h" 63*0bf7f2dcSLikun Gao #include "smuio_v11_0.h" 64*0bf7f2dcSLikun Gao #include "smuio_v11_0_6.h" 65c6b6a421SHawking Zhang 66c6b6a421SHawking Zhang static const struct amd_ip_funcs nv_common_ip_funcs; 67c6b6a421SHawking Zhang 68c6b6a421SHawking Zhang /* 69c6b6a421SHawking Zhang * Indirect registers accessor 70c6b6a421SHawking Zhang */ 71c6b6a421SHawking Zhang static u32 nv_pcie_rreg(struct amdgpu_device *adev, u32 reg) 72c6b6a421SHawking Zhang { 73705a2b5bSHawking Zhang unsigned long address, data; 74bebc0762SHawking Zhang address = adev->nbio.funcs->get_pcie_index_offset(adev); 75bebc0762SHawking Zhang data = adev->nbio.funcs->get_pcie_data_offset(adev); 76c6b6a421SHawking Zhang 77705a2b5bSHawking Zhang return amdgpu_device_indirect_rreg(adev, address, data, reg); 78c6b6a421SHawking Zhang } 79c6b6a421SHawking Zhang 80c6b6a421SHawking Zhang static void nv_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v) 81c6b6a421SHawking Zhang { 82705a2b5bSHawking Zhang unsigned long address, data; 83c6b6a421SHawking Zhang 84bebc0762SHawking Zhang address = adev->nbio.funcs->get_pcie_index_offset(adev); 85bebc0762SHawking Zhang data = adev->nbio.funcs->get_pcie_data_offset(adev); 86c6b6a421SHawking Zhang 87705a2b5bSHawking Zhang amdgpu_device_indirect_wreg(adev, address, data, reg, v); 88c6b6a421SHawking Zhang } 89c6b6a421SHawking Zhang 904922f1bcSJohn Clements static u64 nv_pcie_rreg64(struct amdgpu_device *adev, u32 reg) 914922f1bcSJohn Clements { 92705a2b5bSHawking Zhang unsigned long address, data; 934922f1bcSJohn Clements address = adev->nbio.funcs->get_pcie_index_offset(adev); 944922f1bcSJohn Clements data = adev->nbio.funcs->get_pcie_data_offset(adev); 954922f1bcSJohn Clements 96705a2b5bSHawking Zhang return amdgpu_device_indirect_rreg64(adev, address, data, reg); 974922f1bcSJohn Clements } 984922f1bcSJohn Clements 995de54343SHuang Rui static u32 nv_pcie_port_rreg(struct amdgpu_device *adev, u32 reg) 1005de54343SHuang Rui { 1015de54343SHuang Rui unsigned long flags, address, data; 1025de54343SHuang Rui u32 r; 1035de54343SHuang Rui address = adev->nbio.funcs->get_pcie_port_index_offset(adev); 1045de54343SHuang Rui data = adev->nbio.funcs->get_pcie_port_data_offset(adev); 1055de54343SHuang Rui 1065de54343SHuang Rui spin_lock_irqsave(&adev->pcie_idx_lock, flags); 1075de54343SHuang Rui WREG32(address, reg * 4); 1085de54343SHuang Rui (void)RREG32(address); 1095de54343SHuang Rui r = RREG32(data); 1105de54343SHuang Rui spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); 1115de54343SHuang Rui return r; 1125de54343SHuang Rui } 1135de54343SHuang Rui 1144922f1bcSJohn Clements static void nv_pcie_wreg64(struct amdgpu_device *adev, u32 reg, u64 v) 1154922f1bcSJohn Clements { 116705a2b5bSHawking Zhang unsigned long address, data; 1174922f1bcSJohn Clements 1184922f1bcSJohn Clements address = adev->nbio.funcs->get_pcie_index_offset(adev); 1194922f1bcSJohn Clements data = adev->nbio.funcs->get_pcie_data_offset(adev); 1204922f1bcSJohn Clements 121705a2b5bSHawking Zhang amdgpu_device_indirect_wreg64(adev, address, data, reg, v); 1224922f1bcSJohn Clements } 1234922f1bcSJohn Clements 1245de54343SHuang Rui static void nv_pcie_port_wreg(struct amdgpu_device *adev, u32 reg, u32 v) 1255de54343SHuang Rui { 1265de54343SHuang Rui unsigned long flags, address, data; 1275de54343SHuang Rui 1285de54343SHuang Rui address = adev->nbio.funcs->get_pcie_port_index_offset(adev); 1295de54343SHuang Rui data = adev->nbio.funcs->get_pcie_port_data_offset(adev); 1305de54343SHuang Rui 1315de54343SHuang Rui spin_lock_irqsave(&adev->pcie_idx_lock, flags); 1325de54343SHuang Rui WREG32(address, reg * 4); 1335de54343SHuang Rui (void)RREG32(address); 1345de54343SHuang Rui WREG32(data, v); 1355de54343SHuang Rui (void)RREG32(data); 1365de54343SHuang Rui spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); 1375de54343SHuang Rui } 1385de54343SHuang Rui 139c6b6a421SHawking Zhang static u32 nv_didt_rreg(struct amdgpu_device *adev, u32 reg) 140c6b6a421SHawking Zhang { 141c6b6a421SHawking Zhang unsigned long flags, address, data; 142c6b6a421SHawking Zhang u32 r; 143c6b6a421SHawking Zhang 144c6b6a421SHawking Zhang address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX); 145c6b6a421SHawking Zhang data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA); 146c6b6a421SHawking Zhang 147c6b6a421SHawking Zhang spin_lock_irqsave(&adev->didt_idx_lock, flags); 148c6b6a421SHawking Zhang WREG32(address, (reg)); 149c6b6a421SHawking Zhang r = RREG32(data); 150c6b6a421SHawking Zhang spin_unlock_irqrestore(&adev->didt_idx_lock, flags); 151c6b6a421SHawking Zhang return r; 152c6b6a421SHawking Zhang } 153c6b6a421SHawking Zhang 154c6b6a421SHawking Zhang static void nv_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v) 155c6b6a421SHawking Zhang { 156c6b6a421SHawking Zhang unsigned long flags, address, data; 157c6b6a421SHawking Zhang 158c6b6a421SHawking Zhang address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX); 159c6b6a421SHawking Zhang data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA); 160c6b6a421SHawking Zhang 161c6b6a421SHawking Zhang spin_lock_irqsave(&adev->didt_idx_lock, flags); 162c6b6a421SHawking Zhang WREG32(address, (reg)); 163c6b6a421SHawking Zhang WREG32(data, (v)); 164c6b6a421SHawking Zhang spin_unlock_irqrestore(&adev->didt_idx_lock, flags); 165c6b6a421SHawking Zhang } 166c6b6a421SHawking Zhang 167c6b6a421SHawking Zhang static u32 nv_get_config_memsize(struct amdgpu_device *adev) 168c6b6a421SHawking Zhang { 169bebc0762SHawking Zhang return adev->nbio.funcs->get_memsize(adev); 170c6b6a421SHawking Zhang } 171c6b6a421SHawking Zhang 172c6b6a421SHawking Zhang static u32 nv_get_xclk(struct amdgpu_device *adev) 173c6b6a421SHawking Zhang { 174462a70d8STao Zhou return adev->clock.spll.reference_freq; 175c6b6a421SHawking Zhang } 176c6b6a421SHawking Zhang 177c6b6a421SHawking Zhang 178c6b6a421SHawking Zhang void nv_grbm_select(struct amdgpu_device *adev, 179c6b6a421SHawking Zhang u32 me, u32 pipe, u32 queue, u32 vmid) 180c6b6a421SHawking Zhang { 181c6b6a421SHawking Zhang u32 grbm_gfx_cntl = 0; 182c6b6a421SHawking Zhang grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, PIPEID, pipe); 183c6b6a421SHawking Zhang grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, MEID, me); 184c6b6a421SHawking Zhang grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, VMID, vmid); 185c6b6a421SHawking Zhang grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, QUEUEID, queue); 186c6b6a421SHawking Zhang 187c6b6a421SHawking Zhang WREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_CNTL), grbm_gfx_cntl); 188c6b6a421SHawking Zhang } 189c6b6a421SHawking Zhang 190c6b6a421SHawking Zhang static void nv_vga_set_state(struct amdgpu_device *adev, bool state) 191c6b6a421SHawking Zhang { 192c6b6a421SHawking Zhang /* todo */ 193c6b6a421SHawking Zhang } 194c6b6a421SHawking Zhang 195c6b6a421SHawking Zhang static bool nv_read_disabled_bios(struct amdgpu_device *adev) 196c6b6a421SHawking Zhang { 197c6b6a421SHawking Zhang /* todo */ 198c6b6a421SHawking Zhang return false; 199c6b6a421SHawking Zhang } 200c6b6a421SHawking Zhang 201c6b6a421SHawking Zhang static bool nv_read_bios_from_rom(struct amdgpu_device *adev, 202c6b6a421SHawking Zhang u8 *bios, u32 length_bytes) 203c6b6a421SHawking Zhang { 20429bc37b4SAlex Deucher u32 *dw_ptr; 20529bc37b4SAlex Deucher u32 i, length_dw; 206*0bf7f2dcSLikun Gao u32 rom_index_offset, rom_data_offset; 20729bc37b4SAlex Deucher 20829bc37b4SAlex Deucher if (bios == NULL) 209c6b6a421SHawking Zhang return false; 21029bc37b4SAlex Deucher if (length_bytes == 0) 21129bc37b4SAlex Deucher return false; 21229bc37b4SAlex Deucher /* APU vbios image is part of sbios image */ 21329bc37b4SAlex Deucher if (adev->flags & AMD_IS_APU) 21429bc37b4SAlex Deucher return false; 21529bc37b4SAlex Deucher 21629bc37b4SAlex Deucher dw_ptr = (u32 *)bios; 21729bc37b4SAlex Deucher length_dw = ALIGN(length_bytes, 4) / 4; 21829bc37b4SAlex Deucher 219*0bf7f2dcSLikun Gao rom_index_offset = 220*0bf7f2dcSLikun Gao adev->smuio.funcs->get_rom_index_offset(adev); 221*0bf7f2dcSLikun Gao rom_data_offset = 222*0bf7f2dcSLikun Gao adev->smuio.funcs->get_rom_data_offset(adev); 223*0bf7f2dcSLikun Gao 22429bc37b4SAlex Deucher /* set rom index to 0 */ 225*0bf7f2dcSLikun Gao WREG32(rom_index_offset, 0); 22629bc37b4SAlex Deucher /* read out the rom data */ 22729bc37b4SAlex Deucher for (i = 0; i < length_dw; i++) 228*0bf7f2dcSLikun Gao dw_ptr[i] = RREG32(rom_data_offset); 22929bc37b4SAlex Deucher 23029bc37b4SAlex Deucher return true; 231c6b6a421SHawking Zhang } 232c6b6a421SHawking Zhang 233c6b6a421SHawking Zhang static struct soc15_allowed_register_entry nv_allowed_read_registers[] = { 234c6b6a421SHawking Zhang { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS)}, 235c6b6a421SHawking Zhang { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS2)}, 236c6b6a421SHawking Zhang { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE0)}, 237c6b6a421SHawking Zhang { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE1)}, 238c6b6a421SHawking Zhang { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE2)}, 239c6b6a421SHawking Zhang { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE3)}, 240c6b6a421SHawking Zhang { SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_STATUS_REG)}, 241c6b6a421SHawking Zhang { SOC15_REG_ENTRY(SDMA1, 0, mmSDMA1_STATUS_REG)}, 242c6b6a421SHawking Zhang { SOC15_REG_ENTRY(GC, 0, mmCP_STAT)}, 243c6b6a421SHawking Zhang { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT1)}, 244c6b6a421SHawking Zhang { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT2)}, 245c6b6a421SHawking Zhang { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT3)}, 246c6b6a421SHawking Zhang { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_BUSY_STAT)}, 247c6b6a421SHawking Zhang { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STALLED_STAT1)}, 248c6b6a421SHawking Zhang { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STATUS)}, 249664fe85aSMarek Olšák { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_BUSY_STAT)}, 250c6b6a421SHawking Zhang { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STALLED_STAT1)}, 251c6b6a421SHawking Zhang { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STATUS)}, 252c6b6a421SHawking Zhang { SOC15_REG_ENTRY(GC, 0, mmGB_ADDR_CONFIG)}, 253c6b6a421SHawking Zhang }; 254c6b6a421SHawking Zhang 255c6b6a421SHawking Zhang static uint32_t nv_read_indexed_register(struct amdgpu_device *adev, u32 se_num, 256c6b6a421SHawking Zhang u32 sh_num, u32 reg_offset) 257c6b6a421SHawking Zhang { 258c6b6a421SHawking Zhang uint32_t val; 259c6b6a421SHawking Zhang 260c6b6a421SHawking Zhang mutex_lock(&adev->grbm_idx_mutex); 261c6b6a421SHawking Zhang if (se_num != 0xffffffff || sh_num != 0xffffffff) 262c6b6a421SHawking Zhang amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff); 263c6b6a421SHawking Zhang 264c6b6a421SHawking Zhang val = RREG32(reg_offset); 265c6b6a421SHawking Zhang 266c6b6a421SHawking Zhang if (se_num != 0xffffffff || sh_num != 0xffffffff) 267c6b6a421SHawking Zhang amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 268c6b6a421SHawking Zhang mutex_unlock(&adev->grbm_idx_mutex); 269c6b6a421SHawking Zhang return val; 270c6b6a421SHawking Zhang } 271c6b6a421SHawking Zhang 272c6b6a421SHawking Zhang static uint32_t nv_get_register_value(struct amdgpu_device *adev, 273c6b6a421SHawking Zhang bool indexed, u32 se_num, 274c6b6a421SHawking Zhang u32 sh_num, u32 reg_offset) 275c6b6a421SHawking Zhang { 276c6b6a421SHawking Zhang if (indexed) { 277c6b6a421SHawking Zhang return nv_read_indexed_register(adev, se_num, sh_num, reg_offset); 278c6b6a421SHawking Zhang } else { 279c6b6a421SHawking Zhang if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG)) 280c6b6a421SHawking Zhang return adev->gfx.config.gb_addr_config; 281c6b6a421SHawking Zhang return RREG32(reg_offset); 282c6b6a421SHawking Zhang } 283c6b6a421SHawking Zhang } 284c6b6a421SHawking Zhang 285c6b6a421SHawking Zhang static int nv_read_register(struct amdgpu_device *adev, u32 se_num, 286c6b6a421SHawking Zhang u32 sh_num, u32 reg_offset, u32 *value) 287c6b6a421SHawking Zhang { 288c6b6a421SHawking Zhang uint32_t i; 289c6b6a421SHawking Zhang struct soc15_allowed_register_entry *en; 290c6b6a421SHawking Zhang 291c6b6a421SHawking Zhang *value = 0; 292c6b6a421SHawking Zhang for (i = 0; i < ARRAY_SIZE(nv_allowed_read_registers); i++) { 293c6b6a421SHawking Zhang en = &nv_allowed_read_registers[i]; 294fced3c3aSHuang Rui if ((i == 7 && (adev->sdma.num_instances == 1)) || /* some asics don't have SDMA1 */ 295fced3c3aSHuang Rui reg_offset != 296c6b6a421SHawking Zhang (adev->reg_offset[en->hwip][en->inst][en->seg] + en->reg_offset)) 297c6b6a421SHawking Zhang continue; 298c6b6a421SHawking Zhang 299c6b6a421SHawking Zhang *value = nv_get_register_value(adev, 300c6b6a421SHawking Zhang nv_allowed_read_registers[i].grbm_indexed, 301c6b6a421SHawking Zhang se_num, sh_num, reg_offset); 302c6b6a421SHawking Zhang return 0; 303c6b6a421SHawking Zhang } 304c6b6a421SHawking Zhang return -EINVAL; 305c6b6a421SHawking Zhang } 306c6b6a421SHawking Zhang 3073e2bb60aSKevin Wang static int nv_asic_mode1_reset(struct amdgpu_device *adev) 3083e2bb60aSKevin Wang { 3093e2bb60aSKevin Wang u32 i; 3103e2bb60aSKevin Wang int ret = 0; 3113e2bb60aSKevin Wang 3123e2bb60aSKevin Wang amdgpu_atombios_scratch_regs_engine_hung(adev, true); 3133e2bb60aSKevin Wang 3143e2bb60aSKevin Wang /* disable BM */ 3153e2bb60aSKevin Wang pci_clear_master(adev->pdev); 3163e2bb60aSKevin Wang 317c1dd4aa6SAndrey Grodzovsky amdgpu_device_cache_pci_state(adev->pdev); 3183e2bb60aSKevin Wang 319311531f0SWenhui Sheng if (amdgpu_dpm_is_mode1_reset_supported(adev)) { 320311531f0SWenhui Sheng dev_info(adev->dev, "GPU smu mode1 reset\n"); 321311531f0SWenhui Sheng ret = amdgpu_dpm_mode1_reset(adev); 322311531f0SWenhui Sheng } else { 323311531f0SWenhui Sheng dev_info(adev->dev, "GPU psp mode1 reset\n"); 3243e2bb60aSKevin Wang ret = psp_gpu_reset(adev); 325311531f0SWenhui Sheng } 326311531f0SWenhui Sheng 3273e2bb60aSKevin Wang if (ret) 3283e2bb60aSKevin Wang dev_err(adev->dev, "GPU mode1 reset failed\n"); 329c1dd4aa6SAndrey Grodzovsky amdgpu_device_load_pci_state(adev->pdev); 3303e2bb60aSKevin Wang 3313e2bb60aSKevin Wang /* wait for asic to come out of reset */ 3323e2bb60aSKevin Wang for (i = 0; i < adev->usec_timeout; i++) { 333bebc0762SHawking Zhang u32 memsize = adev->nbio.funcs->get_memsize(adev); 3343e2bb60aSKevin Wang 3353e2bb60aSKevin Wang if (memsize != 0xffffffff) 3363e2bb60aSKevin Wang break; 3373e2bb60aSKevin Wang udelay(1); 3383e2bb60aSKevin Wang } 3393e2bb60aSKevin Wang 3403e2bb60aSKevin Wang amdgpu_atombios_scratch_regs_engine_hung(adev, false); 3413e2bb60aSKevin Wang 3423e2bb60aSKevin Wang return ret; 3433e2bb60aSKevin Wang } 3442ddc6c3eSAlex Deucher 345b913ec62SAlex Deucher static int nv_asic_mode2_reset(struct amdgpu_device *adev) 346b913ec62SAlex Deucher { 347b913ec62SAlex Deucher u32 i; 348b913ec62SAlex Deucher int ret = 0; 349b913ec62SAlex Deucher 350b913ec62SAlex Deucher amdgpu_atombios_scratch_regs_engine_hung(adev, true); 351b913ec62SAlex Deucher 352b913ec62SAlex Deucher /* disable BM */ 353b913ec62SAlex Deucher pci_clear_master(adev->pdev); 354b913ec62SAlex Deucher 355b913ec62SAlex Deucher amdgpu_device_cache_pci_state(adev->pdev); 356b913ec62SAlex Deucher 357b913ec62SAlex Deucher ret = amdgpu_dpm_mode2_reset(adev); 358b913ec62SAlex Deucher if (ret) 359b913ec62SAlex Deucher dev_err(adev->dev, "GPU mode2 reset failed\n"); 360b913ec62SAlex Deucher 361b913ec62SAlex Deucher amdgpu_device_load_pci_state(adev->pdev); 362b913ec62SAlex Deucher 363b913ec62SAlex Deucher /* wait for asic to come out of reset */ 364b913ec62SAlex Deucher for (i = 0; i < adev->usec_timeout; i++) { 365b913ec62SAlex Deucher u32 memsize = adev->nbio.funcs->get_memsize(adev); 366b913ec62SAlex Deucher 367b913ec62SAlex Deucher if (memsize != 0xffffffff) 368b913ec62SAlex Deucher break; 369b913ec62SAlex Deucher udelay(1); 370b913ec62SAlex Deucher } 371b913ec62SAlex Deucher 372b913ec62SAlex Deucher amdgpu_atombios_scratch_regs_engine_hung(adev, false); 373b913ec62SAlex Deucher 374b913ec62SAlex Deucher return ret; 375b913ec62SAlex Deucher } 376b913ec62SAlex Deucher 377ac742616SAlex Deucher static bool nv_asic_supports_baco(struct amdgpu_device *adev) 378ac742616SAlex Deucher { 379ac742616SAlex Deucher struct smu_context *smu = &adev->smu; 380ac742616SAlex Deucher 381ac742616SAlex Deucher if (smu_baco_is_support(smu)) 382ac742616SAlex Deucher return true; 383ac742616SAlex Deucher else 384ac742616SAlex Deucher return false; 385ac742616SAlex Deucher } 386ac742616SAlex Deucher 3872ddc6c3eSAlex Deucher static enum amd_reset_method 3882ddc6c3eSAlex Deucher nv_asic_reset_method(struct amdgpu_device *adev) 3892ddc6c3eSAlex Deucher { 3902ddc6c3eSAlex Deucher struct smu_context *smu = &adev->smu; 3912ddc6c3eSAlex Deucher 392273da6ffSWenhui Sheng if (amdgpu_reset_method == AMD_RESET_METHOD_MODE1 || 39316086355SAlex Deucher amdgpu_reset_method == AMD_RESET_METHOD_MODE2 || 394273da6ffSWenhui Sheng amdgpu_reset_method == AMD_RESET_METHOD_BACO) 395273da6ffSWenhui Sheng return amdgpu_reset_method; 396273da6ffSWenhui Sheng 397273da6ffSWenhui Sheng if (amdgpu_reset_method != -1) 398273da6ffSWenhui Sheng dev_warn(adev->dev, "Specified reset method:%d isn't supported, using AUTO instead.\n", 399273da6ffSWenhui Sheng amdgpu_reset_method); 400273da6ffSWenhui Sheng 401ca6fd7a6SLikun Gao switch (adev->asic_type) { 40216086355SAlex Deucher case CHIP_VANGOGH: 40316086355SAlex Deucher return AMD_RESET_METHOD_MODE2; 404ca6fd7a6SLikun Gao case CHIP_SIENNA_CICHLID: 40522dd44f4SJiansong Chen case CHIP_NAVY_FLOUNDER: 40615ed44c0STao Zhou case CHIP_DIMGREY_CAVEFISH: 407ca6fd7a6SLikun Gao return AMD_RESET_METHOD_MODE1; 408ca6fd7a6SLikun Gao default: 409311531f0SWenhui Sheng if (smu_baco_is_support(smu)) 4102ddc6c3eSAlex Deucher return AMD_RESET_METHOD_BACO; 4112ddc6c3eSAlex Deucher else 4122ddc6c3eSAlex Deucher return AMD_RESET_METHOD_MODE1; 4132ddc6c3eSAlex Deucher } 414ca6fd7a6SLikun Gao } 4152ddc6c3eSAlex Deucher 416c6b6a421SHawking Zhang static int nv_asic_reset(struct amdgpu_device *adev) 417c6b6a421SHawking Zhang { 418767acabdSKevin Wang int ret = 0; 419767acabdSKevin Wang struct smu_context *smu = &adev->smu; 420c6b6a421SHawking Zhang 42133cf440dSAlex Deucher /* skip reset on vangogh for now */ 42233cf440dSAlex Deucher if (adev->asic_type == CHIP_VANGOGH) 42333cf440dSAlex Deucher return 0; 42433cf440dSAlex Deucher 42516086355SAlex Deucher switch (nv_asic_reset_method(adev)) { 42616086355SAlex Deucher case AMD_RESET_METHOD_BACO: 42711043b7aSAlex Deucher dev_info(adev->dev, "BACO reset\n"); 428311531f0SWenhui Sheng 42911520f27SAlex Deucher ret = smu_baco_enter(smu); 43011520f27SAlex Deucher if (ret) 43111520f27SAlex Deucher return ret; 43211520f27SAlex Deucher ret = smu_baco_exit(smu); 43311520f27SAlex Deucher if (ret) 43411520f27SAlex Deucher return ret; 43516086355SAlex Deucher break; 43616086355SAlex Deucher case AMD_RESET_METHOD_MODE2: 43716086355SAlex Deucher dev_info(adev->dev, "MODE2 reset\n"); 438b913ec62SAlex Deucher ret = nv_asic_mode2_reset(adev); 43916086355SAlex Deucher break; 44016086355SAlex Deucher default: 44111043b7aSAlex Deucher dev_info(adev->dev, "MODE1 reset\n"); 4423e2bb60aSKevin Wang ret = nv_asic_mode1_reset(adev); 44316086355SAlex Deucher break; 44411043b7aSAlex Deucher } 445767acabdSKevin Wang 446767acabdSKevin Wang return ret; 447c6b6a421SHawking Zhang } 448c6b6a421SHawking Zhang 449c6b6a421SHawking Zhang static int nv_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk) 450c6b6a421SHawking Zhang { 451c6b6a421SHawking Zhang /* todo */ 452c6b6a421SHawking Zhang return 0; 453c6b6a421SHawking Zhang } 454c6b6a421SHawking Zhang 455c6b6a421SHawking Zhang static int nv_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk) 456c6b6a421SHawking Zhang { 457c6b6a421SHawking Zhang /* todo */ 458c6b6a421SHawking Zhang return 0; 459c6b6a421SHawking Zhang } 460c6b6a421SHawking Zhang 461c6b6a421SHawking Zhang static void nv_pcie_gen3_enable(struct amdgpu_device *adev) 462c6b6a421SHawking Zhang { 463c6b6a421SHawking Zhang if (pci_is_root_bus(adev->pdev->bus)) 464c6b6a421SHawking Zhang return; 465c6b6a421SHawking Zhang 466c6b6a421SHawking Zhang if (amdgpu_pcie_gen2 == 0) 467c6b6a421SHawking Zhang return; 468c6b6a421SHawking Zhang 469c6b6a421SHawking Zhang if (!(adev->pm.pcie_gen_mask & (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 | 470c6b6a421SHawking Zhang CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3))) 471c6b6a421SHawking Zhang return; 472c6b6a421SHawking Zhang 473c6b6a421SHawking Zhang /* todo */ 474c6b6a421SHawking Zhang } 475c6b6a421SHawking Zhang 476c6b6a421SHawking Zhang static void nv_program_aspm(struct amdgpu_device *adev) 477c6b6a421SHawking Zhang { 478e1edaeafSLikun Gao if (amdgpu_aspm != 1) 479c6b6a421SHawking Zhang return; 480c6b6a421SHawking Zhang 481e1edaeafSLikun Gao if ((adev->asic_type >= CHIP_SIENNA_CICHLID) && 482e1edaeafSLikun Gao !(adev->flags & AMD_IS_APU) && 483e1edaeafSLikun Gao (adev->nbio.funcs->program_aspm)) 484e1edaeafSLikun Gao adev->nbio.funcs->program_aspm(adev); 485e1edaeafSLikun Gao 486c6b6a421SHawking Zhang } 487c6b6a421SHawking Zhang 488c6b6a421SHawking Zhang static void nv_enable_doorbell_aperture(struct amdgpu_device *adev, 489c6b6a421SHawking Zhang bool enable) 490c6b6a421SHawking Zhang { 491bebc0762SHawking Zhang adev->nbio.funcs->enable_doorbell_aperture(adev, enable); 492bebc0762SHawking Zhang adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, enable); 493c6b6a421SHawking Zhang } 494c6b6a421SHawking Zhang 495c6b6a421SHawking Zhang static const struct amdgpu_ip_block_version nv_common_ip_block = 496c6b6a421SHawking Zhang { 497c6b6a421SHawking Zhang .type = AMD_IP_BLOCK_TYPE_COMMON, 498c6b6a421SHawking Zhang .major = 1, 499c6b6a421SHawking Zhang .minor = 0, 500c6b6a421SHawking Zhang .rev = 0, 501c6b6a421SHawking Zhang .funcs = &nv_common_ip_funcs, 502c6b6a421SHawking Zhang }; 503c6b6a421SHawking Zhang 504b5c73856SXiaojie Yuan static int nv_reg_base_init(struct amdgpu_device *adev) 505c6b6a421SHawking Zhang { 506b5c73856SXiaojie Yuan int r; 507b5c73856SXiaojie Yuan 508b5c73856SXiaojie Yuan if (amdgpu_discovery) { 509b5c73856SXiaojie Yuan r = amdgpu_discovery_reg_base_init(adev); 510b5c73856SXiaojie Yuan if (r) { 511b5c73856SXiaojie Yuan DRM_WARN("failed to init reg base from ip discovery table, " 512b5c73856SXiaojie Yuan "fallback to legacy init method\n"); 513b5c73856SXiaojie Yuan goto legacy_init; 514b5c73856SXiaojie Yuan } 515b5c73856SXiaojie Yuan 516b5c73856SXiaojie Yuan return 0; 517b5c73856SXiaojie Yuan } 518b5c73856SXiaojie Yuan 519b5c73856SXiaojie Yuan legacy_init: 520c6b6a421SHawking Zhang switch (adev->asic_type) { 521c6b6a421SHawking Zhang case CHIP_NAVI10: 522c6b6a421SHawking Zhang navi10_reg_base_init(adev); 523c6b6a421SHawking Zhang break; 524a0f6d926SXiaojie Yuan case CHIP_NAVI14: 525a0f6d926SXiaojie Yuan navi14_reg_base_init(adev); 526a0f6d926SXiaojie Yuan break; 52703d0a073SXiaojie Yuan case CHIP_NAVI12: 52803d0a073SXiaojie Yuan navi12_reg_base_init(adev); 52903d0a073SXiaojie Yuan break; 530dccdbf3fSLikun Gao case CHIP_SIENNA_CICHLID: 531c8c959f6SJiansong Chen case CHIP_NAVY_FLOUNDER: 532dccdbf3fSLikun Gao sienna_cichlid_reg_base_init(adev); 533dccdbf3fSLikun Gao break; 534026570e6SHuang Rui case CHIP_VANGOGH: 535026570e6SHuang Rui vangogh_reg_base_init(adev); 536026570e6SHuang Rui break; 537038d757bSTao Zhou case CHIP_DIMGREY_CAVEFISH: 538038d757bSTao Zhou dimgrey_cavefish_reg_base_init(adev); 539038d757bSTao Zhou break; 540c6b6a421SHawking Zhang default: 541c6b6a421SHawking Zhang return -EINVAL; 542c6b6a421SHawking Zhang } 543c6b6a421SHawking Zhang 544b5c73856SXiaojie Yuan return 0; 545b5c73856SXiaojie Yuan } 546b5c73856SXiaojie Yuan 547c1299461SWenhui Sheng void nv_set_virt_ops(struct amdgpu_device *adev) 548c1299461SWenhui Sheng { 549c1299461SWenhui Sheng adev->virt.ops = &xgpu_nv_virt_ops; 550c1299461SWenhui Sheng } 551c1299461SWenhui Sheng 5529c94b5efSFlora Cui static bool nv_is_headless_sku(struct pci_dev *pdev) 553aa5375c5STianci.Yin { 554dd657888SFlora Cui if ((pdev->device == 0x731E && 555dd657888SFlora Cui (pdev->revision == 0xC6 || pdev->revision == 0xC7)) || 556dd657888SFlora Cui (pdev->device == 0x7340 && pdev->revision == 0xC9)) 557aa5375c5STianci.Yin return true; 558aa5375c5STianci.Yin return false; 559aa5375c5STianci.Yin } 560aa5375c5STianci.Yin 561b5c73856SXiaojie Yuan int nv_set_ip_blocks(struct amdgpu_device *adev) 562b5c73856SXiaojie Yuan { 563b5c73856SXiaojie Yuan int r; 564b5c73856SXiaojie Yuan 565a7e91bd7SHuang Rui if (adev->flags & AMD_IS_APU) { 566a7e91bd7SHuang Rui adev->nbio.funcs = &nbio_v7_2_funcs; 567a7e91bd7SHuang Rui adev->nbio.hdp_flush_reg = &nbio_v7_2_hdp_flush_reg; 568a7e91bd7SHuang Rui } else { 569122078deSMonk Liu adev->nbio.funcs = &nbio_v2_3_funcs; 570122078deSMonk Liu adev->nbio.hdp_flush_reg = &nbio_v2_3_hdp_flush_reg; 571a7e91bd7SHuang Rui } 572bf087285SLikun Gao adev->hdp.funcs = &hdp_v5_0_funcs; 573122078deSMonk Liu 574*0bf7f2dcSLikun Gao if (adev->asic_type >= CHIP_SIENNA_CICHLID) 575*0bf7f2dcSLikun Gao adev->smuio.funcs = &smuio_v11_0_6_funcs; 576*0bf7f2dcSLikun Gao else 577*0bf7f2dcSLikun Gao adev->smuio.funcs = &smuio_v11_0_funcs; 578*0bf7f2dcSLikun Gao 579c652923aSJohn Clements if (adev->asic_type == CHIP_SIENNA_CICHLID) 580c652923aSJohn Clements adev->gmc.xgmi.supported = true; 581c652923aSJohn Clements 582b5c73856SXiaojie Yuan /* Set IP register base before any HW register access */ 583b5c73856SXiaojie Yuan r = nv_reg_base_init(adev); 584b5c73856SXiaojie Yuan if (r) 585b5c73856SXiaojie Yuan return r; 586b5c73856SXiaojie Yuan 587c6b6a421SHawking Zhang switch (adev->asic_type) { 588c6b6a421SHawking Zhang case CHIP_NAVI10: 589d1daf850SAlex Deucher case CHIP_NAVI14: 590c6b6a421SHawking Zhang amdgpu_device_ip_block_add(adev, &nv_common_ip_block); 591c6b6a421SHawking Zhang amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block); 592c6b6a421SHawking Zhang amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block); 593c6b6a421SHawking Zhang amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block); 594c6b6a421SHawking Zhang if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP && 5959530273eSEvan Quan !amdgpu_sriov_vf(adev)) 596c6b6a421SHawking Zhang amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 597c6b6a421SHawking Zhang if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) 598c6b6a421SHawking Zhang amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block); 599f8a7976bSAlex Deucher #if defined(CONFIG_DRM_AMD_DC) 6008301f6b9STianci.Yin else if (amdgpu_device_has_dc_support(adev)) 601b4f199c7SHarry Wentland amdgpu_device_ip_block_add(adev, &dm_ip_block); 602f8a7976bSAlex Deucher #endif 603c6b6a421SHawking Zhang amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block); 604c6b6a421SHawking Zhang amdgpu_device_ip_block_add(adev, &sdma_v5_0_ip_block); 605c6b6a421SHawking Zhang if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT && 6069530273eSEvan Quan !amdgpu_sriov_vf(adev)) 607c6b6a421SHawking Zhang amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 6089c94b5efSFlora Cui if (!nv_is_headless_sku(adev->pdev)) 609c6b6a421SHawking Zhang amdgpu_device_ip_block_add(adev, &vcn_v2_0_ip_block); 6105be45a26SLeo Liu amdgpu_device_ip_block_add(adev, &jpeg_v2_0_ip_block); 611c6b6a421SHawking Zhang if (adev->enable_mes) 612c6b6a421SHawking Zhang amdgpu_device_ip_block_add(adev, &mes_v10_1_ip_block); 613c6b6a421SHawking Zhang break; 61444e9e7c9SXiaojie Yuan case CHIP_NAVI12: 61544e9e7c9SXiaojie Yuan amdgpu_device_ip_block_add(adev, &nv_common_ip_block); 61644e9e7c9SXiaojie Yuan amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block); 61744e9e7c9SXiaojie Yuan amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block); 6186b66ae2eSXiaojie Yuan amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block); 61979bebabbSMonk Liu if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) 6207f47efebSXiaojie Yuan amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 62179902029SXiaojie Yuan if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) 62279902029SXiaojie Yuan amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block); 62320c14ee1SPetr Cvek #if defined(CONFIG_DRM_AMD_DC) 624078655d9SLeo Li else if (amdgpu_device_has_dc_support(adev)) 625078655d9SLeo Li amdgpu_device_ip_block_add(adev, &dm_ip_block); 62620c14ee1SPetr Cvek #endif 62744e9e7c9SXiaojie Yuan amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block); 62844e9e7c9SXiaojie Yuan amdgpu_device_ip_block_add(adev, &sdma_v5_0_ip_block); 6297f47efebSXiaojie Yuan if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT && 6309530273eSEvan Quan !amdgpu_sriov_vf(adev)) 6317f47efebSXiaojie Yuan amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 6321fbed280SBoyuan Zhang amdgpu_device_ip_block_add(adev, &vcn_v2_0_ip_block); 633fe442491SMonk Liu if (!amdgpu_sriov_vf(adev)) 6345be45a26SLeo Liu amdgpu_device_ip_block_add(adev, &jpeg_v2_0_ip_block); 63544e9e7c9SXiaojie Yuan break; 6362e1ba10eSLikun Gao case CHIP_SIENNA_CICHLID: 6372e1ba10eSLikun Gao amdgpu_device_ip_block_add(adev, &nv_common_ip_block); 6380b3df16bSLikun Gao amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block); 639757b3af8SLikun Gao amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block); 64056304e72SLikun Gao if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) 6415aa02350SLikun Gao amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block); 642b07e5c60SLikun Gao if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP && 643acf2740fSJane Jian is_support_sw_smu(adev)) 644b07e5c60SLikun Gao amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 6459a986760SLikun Gao if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) 6469a986760SLikun Gao amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block); 647464ab91aSBhawanpreet Lakha #if defined(CONFIG_DRM_AMD_DC) 648464ab91aSBhawanpreet Lakha else if (amdgpu_device_has_dc_support(adev)) 649464ab91aSBhawanpreet Lakha amdgpu_device_ip_block_add(adev, &dm_ip_block); 650464ab91aSBhawanpreet Lakha #endif 651933c8a93SLikun Gao amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block); 652157e72e8SLikun Gao amdgpu_device_ip_block_add(adev, &sdma_v5_2_ip_block); 653b8f10585SLeo Liu amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block); 654c45fbe1bSJack Zhang if (!amdgpu_sriov_vf(adev)) 6554d72dd12SLeo Liu amdgpu_device_ip_block_add(adev, &jpeg_v3_0_ip_block); 656c45fbe1bSJack Zhang 657a346ef86SJack Xiao if (adev->enable_mes) 658a346ef86SJack Xiao amdgpu_device_ip_block_add(adev, &mes_v10_1_ip_block); 6592e1ba10eSLikun Gao break; 6608515e0a4SJiansong Chen case CHIP_NAVY_FLOUNDER: 6618515e0a4SJiansong Chen amdgpu_device_ip_block_add(adev, &nv_common_ip_block); 662fc8f07daSJiansong Chen amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block); 663026c396bSJiansong Chen amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block); 6647420eab2SJiansong Chen if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) 6657420eab2SJiansong Chen amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block); 6667420eab2SJiansong Chen if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP && 6677420eab2SJiansong Chen is_support_sw_smu(adev)) 6687420eab2SJiansong Chen amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 6695404f073SJiansong Chen if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) 6705404f073SJiansong Chen amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block); 671a6c5308fSBhawanpreet Lakha #if defined(CONFIG_DRM_AMD_DC) 672a6c5308fSBhawanpreet Lakha else if (amdgpu_device_has_dc_support(adev)) 673a6c5308fSBhawanpreet Lakha amdgpu_device_ip_block_add(adev, &dm_ip_block); 674a6c5308fSBhawanpreet Lakha #endif 675885eb3faSJiansong Chen amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block); 676df2d15dfSJiansong Chen amdgpu_device_ip_block_add(adev, &sdma_v5_2_ip_block); 677290b4ad5SBoyuan Zhang amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block); 678290b4ad5SBoyuan Zhang amdgpu_device_ip_block_add(adev, &jpeg_v3_0_ip_block); 679f4497d10SJiansong Chen if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT && 680f4497d10SJiansong Chen is_support_sw_smu(adev)) 681f4497d10SJiansong Chen amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 6828515e0a4SJiansong Chen break; 68388edbad6SHuang Rui case CHIP_VANGOGH: 68488edbad6SHuang Rui amdgpu_device_ip_block_add(adev, &nv_common_ip_block); 68588edbad6SHuang Rui amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block); 68688edbad6SHuang Rui amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block); 687ed3b7353SHuang Rui if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) 688ed3b7353SHuang Rui amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block); 689c821e0fbSHuang Rui amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 69088edbad6SHuang Rui if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) 69188edbad6SHuang Rui amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block); 69284b934bcSHuang Rui #if defined(CONFIG_DRM_AMD_DC) 69384b934bcSHuang Rui else if (amdgpu_device_has_dc_support(adev)) 69484b934bcSHuang Rui amdgpu_device_ip_block_add(adev, &dm_ip_block); 69584b934bcSHuang Rui #endif 69688edbad6SHuang Rui amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block); 69788edbad6SHuang Rui amdgpu_device_ip_block_add(adev, &sdma_v5_2_ip_block); 698b4e532d6SThong Thai amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block); 699b4e532d6SThong Thai amdgpu_device_ip_block_add(adev, &jpeg_v3_0_ip_block); 70088edbad6SHuang Rui break; 7012aa92b12STao Zhou case CHIP_DIMGREY_CAVEFISH: 7022aa92b12STao Zhou amdgpu_device_ip_block_add(adev, &nv_common_ip_block); 7033e02ad44STao Zhou amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block); 704771cc67eSTao Zhou amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block); 705aff39cdeSTao Zhou if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) 706aff39cdeSTao Zhou amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block); 707aff39cdeSTao Zhou if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP && 708aff39cdeSTao Zhou is_support_sw_smu(adev)) 709aff39cdeSTao Zhou amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 71076a2d9eaSTao Zhou if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) 71176a2d9eaSTao Zhou amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block); 7127cc656e2STao Zhou #if defined(CONFIG_DRM_AMD_DC) 7137cc656e2STao Zhou else if (amdgpu_device_has_dc_support(adev)) 7147cc656e2STao Zhou amdgpu_device_ip_block_add(adev, &dm_ip_block); 7157cc656e2STao Zhou #endif 716feb6329cSTao Zhou amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block); 71701069226STao Zhou amdgpu_device_ip_block_add(adev, &sdma_v5_2_ip_block); 7180afc770bSJames Zhu amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block); 719be6b1cd3SJames Zhu amdgpu_device_ip_block_add(adev, &jpeg_v3_0_ip_block); 7202aa92b12STao Zhou break; 721c6b6a421SHawking Zhang default: 722c6b6a421SHawking Zhang return -EINVAL; 723c6b6a421SHawking Zhang } 724c6b6a421SHawking Zhang 725c6b6a421SHawking Zhang return 0; 726c6b6a421SHawking Zhang } 727c6b6a421SHawking Zhang 728c6b6a421SHawking Zhang static uint32_t nv_get_rev_id(struct amdgpu_device *adev) 729c6b6a421SHawking Zhang { 730bebc0762SHawking Zhang return adev->nbio.funcs->get_rev_id(adev); 731c6b6a421SHawking Zhang } 732c6b6a421SHawking Zhang 733c6b6a421SHawking Zhang static bool nv_need_full_reset(struct amdgpu_device *adev) 734c6b6a421SHawking Zhang { 735c6b6a421SHawking Zhang return true; 736c6b6a421SHawking Zhang } 737c6b6a421SHawking Zhang 738c6b6a421SHawking Zhang static bool nv_need_reset_on_init(struct amdgpu_device *adev) 739c6b6a421SHawking Zhang { 740c6b6a421SHawking Zhang u32 sol_reg; 741c6b6a421SHawking Zhang 742c6b6a421SHawking Zhang if (adev->flags & AMD_IS_APU) 743c6b6a421SHawking Zhang return false; 744c6b6a421SHawking Zhang 745c6b6a421SHawking Zhang /* Check sOS sign of life register to confirm sys driver and sOS 746c6b6a421SHawking Zhang * are already been loaded. 747c6b6a421SHawking Zhang */ 748c6b6a421SHawking Zhang sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81); 749c6b6a421SHawking Zhang if (sol_reg) 750c6b6a421SHawking Zhang return true; 7513967ae6dSAlex Deucher 752c6b6a421SHawking Zhang return false; 753c6b6a421SHawking Zhang } 754c6b6a421SHawking Zhang 7552af81531SKevin Wang static uint64_t nv_get_pcie_replay_count(struct amdgpu_device *adev) 7562af81531SKevin Wang { 7572af81531SKevin Wang 7582af81531SKevin Wang /* TODO 7592af81531SKevin Wang * dummy implement for pcie_replay_count sysfs interface 7602af81531SKevin Wang * */ 7612af81531SKevin Wang 7622af81531SKevin Wang return 0; 7632af81531SKevin Wang } 7642af81531SKevin Wang 765c6b6a421SHawking Zhang static void nv_init_doorbell_index(struct amdgpu_device *adev) 766c6b6a421SHawking Zhang { 767c6b6a421SHawking Zhang adev->doorbell_index.kiq = AMDGPU_NAVI10_DOORBELL_KIQ; 768c6b6a421SHawking Zhang adev->doorbell_index.mec_ring0 = AMDGPU_NAVI10_DOORBELL_MEC_RING0; 769c6b6a421SHawking Zhang adev->doorbell_index.mec_ring1 = AMDGPU_NAVI10_DOORBELL_MEC_RING1; 770c6b6a421SHawking Zhang adev->doorbell_index.mec_ring2 = AMDGPU_NAVI10_DOORBELL_MEC_RING2; 771c6b6a421SHawking Zhang adev->doorbell_index.mec_ring3 = AMDGPU_NAVI10_DOORBELL_MEC_RING3; 772c6b6a421SHawking Zhang adev->doorbell_index.mec_ring4 = AMDGPU_NAVI10_DOORBELL_MEC_RING4; 773c6b6a421SHawking Zhang adev->doorbell_index.mec_ring5 = AMDGPU_NAVI10_DOORBELL_MEC_RING5; 774c6b6a421SHawking Zhang adev->doorbell_index.mec_ring6 = AMDGPU_NAVI10_DOORBELL_MEC_RING6; 775c6b6a421SHawking Zhang adev->doorbell_index.mec_ring7 = AMDGPU_NAVI10_DOORBELL_MEC_RING7; 776c6b6a421SHawking Zhang adev->doorbell_index.userqueue_start = AMDGPU_NAVI10_DOORBELL_USERQUEUE_START; 777c6b6a421SHawking Zhang adev->doorbell_index.userqueue_end = AMDGPU_NAVI10_DOORBELL_USERQUEUE_END; 778c6b6a421SHawking Zhang adev->doorbell_index.gfx_ring0 = AMDGPU_NAVI10_DOORBELL_GFX_RING0; 779c6b6a421SHawking Zhang adev->doorbell_index.gfx_ring1 = AMDGPU_NAVI10_DOORBELL_GFX_RING1; 78020519232SJack Xiao adev->doorbell_index.mes_ring = AMDGPU_NAVI10_DOORBELL_MES_RING; 781c6b6a421SHawking Zhang adev->doorbell_index.sdma_engine[0] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE0; 782c6b6a421SHawking Zhang adev->doorbell_index.sdma_engine[1] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE1; 783157e72e8SLikun Gao adev->doorbell_index.sdma_engine[2] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE2; 784157e72e8SLikun Gao adev->doorbell_index.sdma_engine[3] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE3; 785c6b6a421SHawking Zhang adev->doorbell_index.ih = AMDGPU_NAVI10_DOORBELL_IH; 786c6b6a421SHawking Zhang adev->doorbell_index.vcn.vcn_ring0_1 = AMDGPU_NAVI10_DOORBELL64_VCN0_1; 787c6b6a421SHawking Zhang adev->doorbell_index.vcn.vcn_ring2_3 = AMDGPU_NAVI10_DOORBELL64_VCN2_3; 788c6b6a421SHawking Zhang adev->doorbell_index.vcn.vcn_ring4_5 = AMDGPU_NAVI10_DOORBELL64_VCN4_5; 789c6b6a421SHawking Zhang adev->doorbell_index.vcn.vcn_ring6_7 = AMDGPU_NAVI10_DOORBELL64_VCN6_7; 790c6b6a421SHawking Zhang adev->doorbell_index.first_non_cp = AMDGPU_NAVI10_DOORBELL64_FIRST_NON_CP; 791c6b6a421SHawking Zhang adev->doorbell_index.last_non_cp = AMDGPU_NAVI10_DOORBELL64_LAST_NON_CP; 792c6b6a421SHawking Zhang 793c6b6a421SHawking Zhang adev->doorbell_index.max_assignment = AMDGPU_NAVI10_DOORBELL_MAX_ASSIGNMENT << 1; 794c6b6a421SHawking Zhang adev->doorbell_index.sdma_doorbell_range = 20; 795c6b6a421SHawking Zhang } 796c6b6a421SHawking Zhang 797a7173731SAlex Deucher static void nv_pre_asic_init(struct amdgpu_device *adev) 798a7173731SAlex Deucher { 799a7173731SAlex Deucher } 800a7173731SAlex Deucher 80127747293SEvan Quan static int nv_update_umd_stable_pstate(struct amdgpu_device *adev, 80227747293SEvan Quan bool enter) 80327747293SEvan Quan { 80427747293SEvan Quan if (enter) 80527747293SEvan Quan amdgpu_gfx_rlc_enter_safe_mode(adev); 80627747293SEvan Quan else 80727747293SEvan Quan amdgpu_gfx_rlc_exit_safe_mode(adev); 80827747293SEvan Quan 80927747293SEvan Quan if (adev->gfx.funcs->update_perfmon_mgcg) 81027747293SEvan Quan adev->gfx.funcs->update_perfmon_mgcg(adev, !enter); 81127747293SEvan Quan 81227747293SEvan Quan /* 81327747293SEvan Quan * The ASPM function is not fully enabled and verified on 81427747293SEvan Quan * Navi yet. Temporarily skip this until ASPM enabled. 81527747293SEvan Quan */ 816e1edaeafSLikun Gao if ((adev->asic_type >= CHIP_SIENNA_CICHLID) && 817e1edaeafSLikun Gao !(adev->flags & AMD_IS_APU) && 818e1edaeafSLikun Gao (adev->nbio.funcs->enable_aspm)) 81927747293SEvan Quan adev->nbio.funcs->enable_aspm(adev, !enter); 82027747293SEvan Quan 82127747293SEvan Quan return 0; 82227747293SEvan Quan } 82327747293SEvan Quan 824c6b6a421SHawking Zhang static const struct amdgpu_asic_funcs nv_asic_funcs = 825c6b6a421SHawking Zhang { 826c6b6a421SHawking Zhang .read_disabled_bios = &nv_read_disabled_bios, 827c6b6a421SHawking Zhang .read_bios_from_rom = &nv_read_bios_from_rom, 828c6b6a421SHawking Zhang .read_register = &nv_read_register, 829c6b6a421SHawking Zhang .reset = &nv_asic_reset, 8302ddc6c3eSAlex Deucher .reset_method = &nv_asic_reset_method, 831c6b6a421SHawking Zhang .set_vga_state = &nv_vga_set_state, 832c6b6a421SHawking Zhang .get_xclk = &nv_get_xclk, 833c6b6a421SHawking Zhang .set_uvd_clocks = &nv_set_uvd_clocks, 834c6b6a421SHawking Zhang .set_vce_clocks = &nv_set_vce_clocks, 835c6b6a421SHawking Zhang .get_config_memsize = &nv_get_config_memsize, 836c6b6a421SHawking Zhang .init_doorbell_index = &nv_init_doorbell_index, 837c6b6a421SHawking Zhang .need_full_reset = &nv_need_full_reset, 838c6b6a421SHawking Zhang .need_reset_on_init = &nv_need_reset_on_init, 8392af81531SKevin Wang .get_pcie_replay_count = &nv_get_pcie_replay_count, 840ac742616SAlex Deucher .supports_baco = &nv_asic_supports_baco, 841a7173731SAlex Deucher .pre_asic_init = &nv_pre_asic_init, 84227747293SEvan Quan .update_umd_stable_pstate = &nv_update_umd_stable_pstate, 843c6b6a421SHawking Zhang }; 844c6b6a421SHawking Zhang 845c6b6a421SHawking Zhang static int nv_common_early_init(void *handle) 846c6b6a421SHawking Zhang { 847923c087aSYong Zhao #define MMIO_REG_HOLE_OFFSET (0x80000 - PAGE_SIZE) 848c6b6a421SHawking Zhang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 849c6b6a421SHawking Zhang 850923c087aSYong Zhao adev->rmmio_remap.reg_offset = MMIO_REG_HOLE_OFFSET; 851923c087aSYong Zhao adev->rmmio_remap.bus_addr = adev->rmmio_base + MMIO_REG_HOLE_OFFSET; 852c6b6a421SHawking Zhang adev->smc_rreg = NULL; 853c6b6a421SHawking Zhang adev->smc_wreg = NULL; 854c6b6a421SHawking Zhang adev->pcie_rreg = &nv_pcie_rreg; 855c6b6a421SHawking Zhang adev->pcie_wreg = &nv_pcie_wreg; 8564922f1bcSJohn Clements adev->pcie_rreg64 = &nv_pcie_rreg64; 8574922f1bcSJohn Clements adev->pcie_wreg64 = &nv_pcie_wreg64; 8585de54343SHuang Rui adev->pciep_rreg = &nv_pcie_port_rreg; 8595de54343SHuang Rui adev->pciep_wreg = &nv_pcie_port_wreg; 860c6b6a421SHawking Zhang 861c6b6a421SHawking Zhang /* TODO: will add them during VCN v2 implementation */ 862c6b6a421SHawking Zhang adev->uvd_ctx_rreg = NULL; 863c6b6a421SHawking Zhang adev->uvd_ctx_wreg = NULL; 864c6b6a421SHawking Zhang 865c6b6a421SHawking Zhang adev->didt_rreg = &nv_didt_rreg; 866c6b6a421SHawking Zhang adev->didt_wreg = &nv_didt_wreg; 867c6b6a421SHawking Zhang 868c6b6a421SHawking Zhang adev->asic_funcs = &nv_asic_funcs; 869c6b6a421SHawking Zhang 870c6b6a421SHawking Zhang adev->rev_id = nv_get_rev_id(adev); 871c6b6a421SHawking Zhang adev->external_rev_id = 0xff; 872c6b6a421SHawking Zhang switch (adev->asic_type) { 873c6b6a421SHawking Zhang case CHIP_NAVI10: 874c6b6a421SHawking Zhang adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 875c6b6a421SHawking Zhang AMD_CG_SUPPORT_GFX_CGCG | 876c6b6a421SHawking Zhang AMD_CG_SUPPORT_IH_CG | 877c6b6a421SHawking Zhang AMD_CG_SUPPORT_HDP_MGCG | 878c6b6a421SHawking Zhang AMD_CG_SUPPORT_HDP_LS | 879c6b6a421SHawking Zhang AMD_CG_SUPPORT_SDMA_MGCG | 880c6b6a421SHawking Zhang AMD_CG_SUPPORT_SDMA_LS | 881c6b6a421SHawking Zhang AMD_CG_SUPPORT_MC_MGCG | 882c6b6a421SHawking Zhang AMD_CG_SUPPORT_MC_LS | 883c6b6a421SHawking Zhang AMD_CG_SUPPORT_ATHUB_MGCG | 884c6b6a421SHawking Zhang AMD_CG_SUPPORT_ATHUB_LS | 885c6b6a421SHawking Zhang AMD_CG_SUPPORT_VCN_MGCG | 886099d66e4SLeo Liu AMD_CG_SUPPORT_JPEG_MGCG | 887c6b6a421SHawking Zhang AMD_CG_SUPPORT_BIF_MGCG | 888c6b6a421SHawking Zhang AMD_CG_SUPPORT_BIF_LS; 889157710eaSLeo Liu adev->pg_flags = AMD_PG_SUPPORT_VCN | 890c12d410fSHuang Rui AMD_PG_SUPPORT_VCN_DPG | 891099d66e4SLeo Liu AMD_PG_SUPPORT_JPEG | 892a201b6acSHuang Rui AMD_PG_SUPPORT_ATHUB; 893c6b6a421SHawking Zhang adev->external_rev_id = adev->rev_id + 0x1; 894c6b6a421SHawking Zhang break; 8955e71e011SXiaojie Yuan case CHIP_NAVI14: 896d0c39f8cSXiaojie Yuan adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 897d0c39f8cSXiaojie Yuan AMD_CG_SUPPORT_GFX_CGCG | 898d0c39f8cSXiaojie Yuan AMD_CG_SUPPORT_IH_CG | 899d0c39f8cSXiaojie Yuan AMD_CG_SUPPORT_HDP_MGCG | 900d0c39f8cSXiaojie Yuan AMD_CG_SUPPORT_HDP_LS | 901d0c39f8cSXiaojie Yuan AMD_CG_SUPPORT_SDMA_MGCG | 902d0c39f8cSXiaojie Yuan AMD_CG_SUPPORT_SDMA_LS | 903d0c39f8cSXiaojie Yuan AMD_CG_SUPPORT_MC_MGCG | 904d0c39f8cSXiaojie Yuan AMD_CG_SUPPORT_MC_LS | 905d0c39f8cSXiaojie Yuan AMD_CG_SUPPORT_ATHUB_MGCG | 906d0c39f8cSXiaojie Yuan AMD_CG_SUPPORT_ATHUB_LS | 907d0c39f8cSXiaojie Yuan AMD_CG_SUPPORT_VCN_MGCG | 908099d66e4SLeo Liu AMD_CG_SUPPORT_JPEG_MGCG | 909d0c39f8cSXiaojie Yuan AMD_CG_SUPPORT_BIF_MGCG | 910d0c39f8cSXiaojie Yuan AMD_CG_SUPPORT_BIF_LS; 9110377b088SXiaojie Yuan adev->pg_flags = AMD_PG_SUPPORT_VCN | 912099d66e4SLeo Liu AMD_PG_SUPPORT_JPEG | 9130377b088SXiaojie Yuan AMD_PG_SUPPORT_VCN_DPG; 91435ef88faStiancyin adev->external_rev_id = adev->rev_id + 20; 9155e71e011SXiaojie Yuan break; 91674b5e509SXiaojie Yuan case CHIP_NAVI12: 917dca009e7SXiaojie Yuan adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 918dca009e7SXiaojie Yuan AMD_CG_SUPPORT_GFX_MGLS | 919dca009e7SXiaojie Yuan AMD_CG_SUPPORT_GFX_CGCG | 920dca009e7SXiaojie Yuan AMD_CG_SUPPORT_GFX_CP_LS | 9215211c37aSXiaojie Yuan AMD_CG_SUPPORT_GFX_RLC_LS | 922fbe0bc57SXiaojie Yuan AMD_CG_SUPPORT_IH_CG | 9235211c37aSXiaojie Yuan AMD_CG_SUPPORT_HDP_MGCG | 924358ab97fSXiaojie Yuan AMD_CG_SUPPORT_HDP_LS | 925358ab97fSXiaojie Yuan AMD_CG_SUPPORT_SDMA_MGCG | 9268b797b3dSXiaojie Yuan AMD_CG_SUPPORT_SDMA_LS | 9278b797b3dSXiaojie Yuan AMD_CG_SUPPORT_MC_MGCG | 928ca51678dSXiaojie Yuan AMD_CG_SUPPORT_MC_LS | 929ca51678dSXiaojie Yuan AMD_CG_SUPPORT_ATHUB_MGCG | 93065872e59SXiaojie Yuan AMD_CG_SUPPORT_ATHUB_LS | 931099d66e4SLeo Liu AMD_CG_SUPPORT_VCN_MGCG | 932099d66e4SLeo Liu AMD_CG_SUPPORT_JPEG_MGCG; 933c1653ea0SXiaojie Yuan adev->pg_flags = AMD_PG_SUPPORT_VCN | 9345ef3b8acSXiaojie Yuan AMD_PG_SUPPORT_VCN_DPG | 935099d66e4SLeo Liu AMD_PG_SUPPORT_JPEG | 9361b0443b1SLikun Gao AMD_PG_SUPPORT_ATHUB; 937df5e984cSTiecheng Zhou /* guest vm gets 0xffffffff when reading RCC_DEV0_EPF0_STRAP0, 938df5e984cSTiecheng Zhou * as a consequence, the rev_id and external_rev_id are wrong. 939df5e984cSTiecheng Zhou * workaround it by hardcoding rev_id to 0 (default value). 940df5e984cSTiecheng Zhou */ 941df5e984cSTiecheng Zhou if (amdgpu_sriov_vf(adev)) 942df5e984cSTiecheng Zhou adev->rev_id = 0; 94374b5e509SXiaojie Yuan adev->external_rev_id = adev->rev_id + 0xa; 94474b5e509SXiaojie Yuan break; 945117910edSLikun Gao case CHIP_SIENNA_CICHLID: 94600194defSLikun Gao adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 94700194defSLikun Gao AMD_CG_SUPPORT_GFX_CGCG | 94800194defSLikun Gao AMD_CG_SUPPORT_GFX_3D_CGCG | 94998f8ea29SLikun Gao AMD_CG_SUPPORT_MC_MGCG | 95000194defSLikun Gao AMD_CG_SUPPORT_VCN_MGCG | 951ca36461fSKenneth Feng AMD_CG_SUPPORT_JPEG_MGCG | 952ca36461fSKenneth Feng AMD_CG_SUPPORT_HDP_MGCG | 9533a32c25aSKenneth Feng AMD_CG_SUPPORT_HDP_LS | 954bcc8367fSKenneth Feng AMD_CG_SUPPORT_IH_CG | 955bcc8367fSKenneth Feng AMD_CG_SUPPORT_MC_LS; 956b467c4f5SLeo Liu adev->pg_flags = AMD_PG_SUPPORT_VCN | 957d00b0fa9SBoyuan Zhang AMD_PG_SUPPORT_VCN_DPG | 958b794616dSKenneth Feng AMD_PG_SUPPORT_JPEG | 9591b0443b1SLikun Gao AMD_PG_SUPPORT_ATHUB | 9601b0443b1SLikun Gao AMD_PG_SUPPORT_MMHUB; 961c45fbe1bSJack Zhang if (amdgpu_sriov_vf(adev)) { 962c45fbe1bSJack Zhang /* hypervisor control CG and PG enablement */ 963c45fbe1bSJack Zhang adev->cg_flags = 0; 964c45fbe1bSJack Zhang adev->pg_flags = 0; 965c45fbe1bSJack Zhang } 966117910edSLikun Gao adev->external_rev_id = adev->rev_id + 0x28; 967117910edSLikun Gao break; 968543aa259SJiansong Chen case CHIP_NAVY_FLOUNDER: 96940582e67SJiansong Chen adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 97040582e67SJiansong Chen AMD_CG_SUPPORT_GFX_CGCG | 97140582e67SJiansong Chen AMD_CG_SUPPORT_GFX_3D_CGCG | 97240582e67SJiansong Chen AMD_CG_SUPPORT_VCN_MGCG | 97392c73756SJiansong Chen AMD_CG_SUPPORT_JPEG_MGCG | 97492c73756SJiansong Chen AMD_CG_SUPPORT_MC_MGCG | 9754759f887SJiansong Chen AMD_CG_SUPPORT_MC_LS | 9764759f887SJiansong Chen AMD_CG_SUPPORT_HDP_MGCG | 97785e7151bSJiansong Chen AMD_CG_SUPPORT_HDP_LS | 97885e7151bSJiansong Chen AMD_CG_SUPPORT_IH_CG; 979c6e9dd0eSBoyuan Zhang adev->pg_flags = AMD_PG_SUPPORT_VCN | 98000740df9SBoyuan Zhang AMD_PG_SUPPORT_VCN_DPG | 98147fc894aSJiansong Chen AMD_PG_SUPPORT_JPEG | 98247fc894aSJiansong Chen AMD_PG_SUPPORT_ATHUB | 98347fc894aSJiansong Chen AMD_PG_SUPPORT_MMHUB; 984543aa259SJiansong Chen adev->external_rev_id = adev->rev_id + 0x32; 985543aa259SJiansong Chen break; 986543aa259SJiansong Chen 987026570e6SHuang Rui case CHIP_VANGOGH: 988c345c89bSHuang Rui adev->apu_flags |= AMD_APU_IS_VANGOGH; 98951a7e938SJinzhou.Su adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 99051a7e938SJinzhou.Su AMD_CG_SUPPORT_GFX_MGLS | 99151a7e938SJinzhou.Su AMD_CG_SUPPORT_GFX_CP_LS | 99251a7e938SJinzhou.Su AMD_CG_SUPPORT_GFX_RLC_LS | 99351a7e938SJinzhou.Su AMD_CG_SUPPORT_GFX_CGCG | 994ac0dc4c5SHuang Rui AMD_CG_SUPPORT_GFX_CGLS | 995ac0dc4c5SHuang Rui AMD_CG_SUPPORT_GFX_3D_CGCG | 99607f9c22fSBoyuan Zhang AMD_CG_SUPPORT_GFX_3D_CGLS | 9970ebce667SJinzhou.Su AMD_CG_SUPPORT_MC_MGCG | 9980ebce667SJinzhou.Su AMD_CG_SUPPORT_MC_LS | 999a3964ec4SJinzhou.Su AMD_CG_SUPPORT_GFX_FGCG | 100007f9c22fSBoyuan Zhang AMD_CG_SUPPORT_VCN_MGCG | 100107f9c22fSBoyuan Zhang AMD_CG_SUPPORT_JPEG_MGCG; 100207f9c22fSBoyuan Zhang adev->pg_flags = AMD_PG_SUPPORT_GFX_PG | 100307f9c22fSBoyuan Zhang AMD_PG_SUPPORT_VCN | 100407f9c22fSBoyuan Zhang AMD_PG_SUPPORT_VCN_DPG | 100507f9c22fSBoyuan Zhang AMD_PG_SUPPORT_JPEG; 1006c345c89bSHuang Rui if (adev->apu_flags & AMD_APU_IS_VANGOGH) 1007026570e6SHuang Rui adev->external_rev_id = adev->rev_id + 0x01; 1008026570e6SHuang Rui break; 1009550c58e0STao Zhou case CHIP_DIMGREY_CAVEFISH: 1010583e5a5eSTao Zhou adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 1011583e5a5eSTao Zhou AMD_CG_SUPPORT_GFX_CGCG | 1012583e5a5eSTao Zhou AMD_CG_SUPPORT_GFX_3D_CGCG | 1013583e5a5eSTao Zhou AMD_CG_SUPPORT_VCN_MGCG | 1014135333a0STao Zhou AMD_CG_SUPPORT_JPEG_MGCG | 1015135333a0STao Zhou AMD_CG_SUPPORT_MC_MGCG | 10162c70c332STao Zhou AMD_CG_SUPPORT_MC_LS | 10172c70c332STao Zhou AMD_CG_SUPPORT_HDP_MGCG | 10188e3bfb99STao Zhou AMD_CG_SUPPORT_HDP_LS | 10198e3bfb99STao Zhou AMD_CG_SUPPORT_IH_CG; 1020d5bc1579SJames Zhu adev->pg_flags = AMD_PG_SUPPORT_VCN | 1021cc6161aaSJames Zhu AMD_PG_SUPPORT_VCN_DPG | 102273da8e86STao Zhou AMD_PG_SUPPORT_JPEG | 102373da8e86STao Zhou AMD_PG_SUPPORT_ATHUB | 102473da8e86STao Zhou AMD_PG_SUPPORT_MMHUB; 1025550c58e0STao Zhou adev->external_rev_id = adev->rev_id + 0x3c; 1026550c58e0STao Zhou break; 1027c6b6a421SHawking Zhang default: 1028c6b6a421SHawking Zhang /* FIXME: not supported yet */ 1029c6b6a421SHawking Zhang return -EINVAL; 1030c6b6a421SHawking Zhang } 1031c6b6a421SHawking Zhang 1032b05b6903SJiange Zhao if (amdgpu_sriov_vf(adev)) { 1033b05b6903SJiange Zhao amdgpu_virt_init_setting(adev); 1034b05b6903SJiange Zhao xgpu_nv_mailbox_set_irq_funcs(adev); 1035b05b6903SJiange Zhao } 1036b05b6903SJiange Zhao 1037c6b6a421SHawking Zhang return 0; 1038c6b6a421SHawking Zhang } 1039c6b6a421SHawking Zhang 1040c6b6a421SHawking Zhang static int nv_common_late_init(void *handle) 1041c6b6a421SHawking Zhang { 1042b05b6903SJiange Zhao struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1043b05b6903SJiange Zhao 1044b05b6903SJiange Zhao if (amdgpu_sriov_vf(adev)) 1045b05b6903SJiange Zhao xgpu_nv_mailbox_get_irq(adev); 1046b05b6903SJiange Zhao 1047c6b6a421SHawking Zhang return 0; 1048c6b6a421SHawking Zhang } 1049c6b6a421SHawking Zhang 1050c6b6a421SHawking Zhang static int nv_common_sw_init(void *handle) 1051c6b6a421SHawking Zhang { 1052b05b6903SJiange Zhao struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1053b05b6903SJiange Zhao 1054b05b6903SJiange Zhao if (amdgpu_sriov_vf(adev)) 1055b05b6903SJiange Zhao xgpu_nv_mailbox_add_irq_id(adev); 1056b05b6903SJiange Zhao 1057c6b6a421SHawking Zhang return 0; 1058c6b6a421SHawking Zhang } 1059c6b6a421SHawking Zhang 1060c6b6a421SHawking Zhang static int nv_common_sw_fini(void *handle) 1061c6b6a421SHawking Zhang { 1062c6b6a421SHawking Zhang return 0; 1063c6b6a421SHawking Zhang } 1064c6b6a421SHawking Zhang 1065c6b6a421SHawking Zhang static int nv_common_hw_init(void *handle) 1066c6b6a421SHawking Zhang { 1067c6b6a421SHawking Zhang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1068c6b6a421SHawking Zhang 1069c6b6a421SHawking Zhang /* enable pcie gen2/3 link */ 1070c6b6a421SHawking Zhang nv_pcie_gen3_enable(adev); 1071c6b6a421SHawking Zhang /* enable aspm */ 1072c6b6a421SHawking Zhang nv_program_aspm(adev); 1073c6b6a421SHawking Zhang /* setup nbio registers */ 1074bebc0762SHawking Zhang adev->nbio.funcs->init_registers(adev); 1075923c087aSYong Zhao /* remap HDP registers to a hole in mmio space, 1076923c087aSYong Zhao * for the purpose of expose those registers 1077923c087aSYong Zhao * to process space 1078923c087aSYong Zhao */ 1079923c087aSYong Zhao if (adev->nbio.funcs->remap_hdp_registers) 1080923c087aSYong Zhao adev->nbio.funcs->remap_hdp_registers(adev); 1081c6b6a421SHawking Zhang /* enable the doorbell aperture */ 1082c6b6a421SHawking Zhang nv_enable_doorbell_aperture(adev, true); 1083c6b6a421SHawking Zhang 1084c6b6a421SHawking Zhang return 0; 1085c6b6a421SHawking Zhang } 1086c6b6a421SHawking Zhang 1087c6b6a421SHawking Zhang static int nv_common_hw_fini(void *handle) 1088c6b6a421SHawking Zhang { 1089c6b6a421SHawking Zhang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1090c6b6a421SHawking Zhang 1091c6b6a421SHawking Zhang /* disable the doorbell aperture */ 1092c6b6a421SHawking Zhang nv_enable_doorbell_aperture(adev, false); 1093c6b6a421SHawking Zhang 1094c6b6a421SHawking Zhang return 0; 1095c6b6a421SHawking Zhang } 1096c6b6a421SHawking Zhang 1097c6b6a421SHawking Zhang static int nv_common_suspend(void *handle) 1098c6b6a421SHawking Zhang { 1099c6b6a421SHawking Zhang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1100c6b6a421SHawking Zhang 1101c6b6a421SHawking Zhang return nv_common_hw_fini(adev); 1102c6b6a421SHawking Zhang } 1103c6b6a421SHawking Zhang 1104c6b6a421SHawking Zhang static int nv_common_resume(void *handle) 1105c6b6a421SHawking Zhang { 1106c6b6a421SHawking Zhang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1107c6b6a421SHawking Zhang 1108c6b6a421SHawking Zhang return nv_common_hw_init(adev); 1109c6b6a421SHawking Zhang } 1110c6b6a421SHawking Zhang 1111c6b6a421SHawking Zhang static bool nv_common_is_idle(void *handle) 1112c6b6a421SHawking Zhang { 1113c6b6a421SHawking Zhang return true; 1114c6b6a421SHawking Zhang } 1115c6b6a421SHawking Zhang 1116c6b6a421SHawking Zhang static int nv_common_wait_for_idle(void *handle) 1117c6b6a421SHawking Zhang { 1118c6b6a421SHawking Zhang return 0; 1119c6b6a421SHawking Zhang } 1120c6b6a421SHawking Zhang 1121c6b6a421SHawking Zhang static int nv_common_soft_reset(void *handle) 1122c6b6a421SHawking Zhang { 1123c6b6a421SHawking Zhang return 0; 1124c6b6a421SHawking Zhang } 1125c6b6a421SHawking Zhang 1126c6b6a421SHawking Zhang static int nv_common_set_clockgating_state(void *handle, 1127c6b6a421SHawking Zhang enum amd_clockgating_state state) 1128c6b6a421SHawking Zhang { 1129c6b6a421SHawking Zhang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1130c6b6a421SHawking Zhang 1131c6b6a421SHawking Zhang if (amdgpu_sriov_vf(adev)) 1132c6b6a421SHawking Zhang return 0; 1133c6b6a421SHawking Zhang 1134c6b6a421SHawking Zhang switch (adev->asic_type) { 1135c6b6a421SHawking Zhang case CHIP_NAVI10: 11365e71e011SXiaojie Yuan case CHIP_NAVI14: 11377e17e58bSXiaojie Yuan case CHIP_NAVI12: 1138117910edSLikun Gao case CHIP_SIENNA_CICHLID: 1139543aa259SJiansong Chen case CHIP_NAVY_FLOUNDER: 1140550c58e0STao Zhou case CHIP_DIMGREY_CAVEFISH: 1141bebc0762SHawking Zhang adev->nbio.funcs->update_medium_grain_clock_gating(adev, 1142a9d4fe2fSNirmoy Das state == AMD_CG_STATE_GATE); 1143bebc0762SHawking Zhang adev->nbio.funcs->update_medium_grain_light_sleep(adev, 1144a9d4fe2fSNirmoy Das state == AMD_CG_STATE_GATE); 1145bf087285SLikun Gao adev->hdp.funcs->update_clock_gating(adev, 1146a9d4fe2fSNirmoy Das state == AMD_CG_STATE_GATE); 1147c6b6a421SHawking Zhang break; 1148c6b6a421SHawking Zhang default: 1149c6b6a421SHawking Zhang break; 1150c6b6a421SHawking Zhang } 1151c6b6a421SHawking Zhang return 0; 1152c6b6a421SHawking Zhang } 1153c6b6a421SHawking Zhang 1154c6b6a421SHawking Zhang static int nv_common_set_powergating_state(void *handle, 1155c6b6a421SHawking Zhang enum amd_powergating_state state) 1156c6b6a421SHawking Zhang { 1157c6b6a421SHawking Zhang /* TODO */ 1158c6b6a421SHawking Zhang return 0; 1159c6b6a421SHawking Zhang } 1160c6b6a421SHawking Zhang 1161c6b6a421SHawking Zhang static void nv_common_get_clockgating_state(void *handle, u32 *flags) 1162c6b6a421SHawking Zhang { 1163c6b6a421SHawking Zhang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1164c6b6a421SHawking Zhang 1165c6b6a421SHawking Zhang if (amdgpu_sriov_vf(adev)) 1166c6b6a421SHawking Zhang *flags = 0; 1167c6b6a421SHawking Zhang 1168bebc0762SHawking Zhang adev->nbio.funcs->get_clockgating_state(adev, flags); 1169c6b6a421SHawking Zhang 1170bf087285SLikun Gao adev->hdp.funcs->get_clock_gating_state(adev, flags); 1171c6b6a421SHawking Zhang 1172c6b6a421SHawking Zhang return; 1173c6b6a421SHawking Zhang } 1174c6b6a421SHawking Zhang 1175c6b6a421SHawking Zhang static const struct amd_ip_funcs nv_common_ip_funcs = { 1176c6b6a421SHawking Zhang .name = "nv_common", 1177c6b6a421SHawking Zhang .early_init = nv_common_early_init, 1178c6b6a421SHawking Zhang .late_init = nv_common_late_init, 1179c6b6a421SHawking Zhang .sw_init = nv_common_sw_init, 1180c6b6a421SHawking Zhang .sw_fini = nv_common_sw_fini, 1181c6b6a421SHawking Zhang .hw_init = nv_common_hw_init, 1182c6b6a421SHawking Zhang .hw_fini = nv_common_hw_fini, 1183c6b6a421SHawking Zhang .suspend = nv_common_suspend, 1184c6b6a421SHawking Zhang .resume = nv_common_resume, 1185c6b6a421SHawking Zhang .is_idle = nv_common_is_idle, 1186c6b6a421SHawking Zhang .wait_for_idle = nv_common_wait_for_idle, 1187c6b6a421SHawking Zhang .soft_reset = nv_common_soft_reset, 1188c6b6a421SHawking Zhang .set_clockgating_state = nv_common_set_clockgating_state, 1189c6b6a421SHawking Zhang .set_powergating_state = nv_common_set_powergating_state, 1190c6b6a421SHawking Zhang .get_clockgating_state = nv_common_get_clockgating_state, 1191c6b6a421SHawking Zhang }; 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