1c6b6a421SHawking Zhang /* 2c6b6a421SHawking Zhang * Copyright 2019 Advanced Micro Devices, Inc. 3c6b6a421SHawking Zhang * 4c6b6a421SHawking Zhang * Permission is hereby granted, free of charge, to any person obtaining a 5c6b6a421SHawking Zhang * copy of this software and associated documentation files (the "Software"), 6c6b6a421SHawking Zhang * to deal in the Software without restriction, including without limitation 7c6b6a421SHawking Zhang * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8c6b6a421SHawking Zhang * and/or sell copies of the Software, and to permit persons to whom the 9c6b6a421SHawking Zhang * Software is furnished to do so, subject to the following conditions: 10c6b6a421SHawking Zhang * 11c6b6a421SHawking Zhang * The above copyright notice and this permission notice shall be included in 12c6b6a421SHawking Zhang * all copies or substantial portions of the Software. 13c6b6a421SHawking Zhang * 14c6b6a421SHawking Zhang * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15c6b6a421SHawking Zhang * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16c6b6a421SHawking Zhang * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17c6b6a421SHawking Zhang * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18c6b6a421SHawking Zhang * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19c6b6a421SHawking Zhang * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20c6b6a421SHawking Zhang * OTHER DEALINGS IN THE SOFTWARE. 21c6b6a421SHawking Zhang * 22c6b6a421SHawking Zhang */ 23c6b6a421SHawking Zhang #include <linux/firmware.h> 24c6b6a421SHawking Zhang #include <linux/slab.h> 25c6b6a421SHawking Zhang #include <linux/module.h> 26e9eea902SAlex Deucher #include <linux/pci.h> 27e9eea902SAlex Deucher 286f786950SAlex Deucher #include <drm/amdgpu_drm.h> 296f786950SAlex Deucher 30c6b6a421SHawking Zhang #include "amdgpu.h" 31c6b6a421SHawking Zhang #include "amdgpu_atombios.h" 32c6b6a421SHawking Zhang #include "amdgpu_ih.h" 33c6b6a421SHawking Zhang #include "amdgpu_uvd.h" 34c6b6a421SHawking Zhang #include "amdgpu_vce.h" 35c6b6a421SHawking Zhang #include "amdgpu_ucode.h" 36c6b6a421SHawking Zhang #include "amdgpu_psp.h" 37c6b6a421SHawking Zhang #include "atom.h" 38c6b6a421SHawking Zhang #include "amd_pcie.h" 39c6b6a421SHawking Zhang 40c6b6a421SHawking Zhang #include "gc/gc_10_1_0_offset.h" 41c6b6a421SHawking Zhang #include "gc/gc_10_1_0_sh_mask.h" 423967ae6dSAlex Deucher #include "mp/mp_11_0_offset.h" 43c6b6a421SHawking Zhang 44c6b6a421SHawking Zhang #include "soc15.h" 45c6b6a421SHawking Zhang #include "soc15_common.h" 46c6b6a421SHawking Zhang #include "gmc_v10_0.h" 47c6b6a421SHawking Zhang #include "gfxhub_v2_0.h" 48c6b6a421SHawking Zhang #include "mmhub_v2_0.h" 49bebc0762SHawking Zhang #include "nbio_v2_3.h" 50a7e91bd7SHuang Rui #include "nbio_v7_2.h" 51bf087285SLikun Gao #include "hdp_v5_0.h" 52c6b6a421SHawking Zhang #include "nv.h" 53c6b6a421SHawking Zhang #include "navi10_ih.h" 54c6b6a421SHawking Zhang #include "gfx_v10_0.h" 55c6b6a421SHawking Zhang #include "sdma_v5_0.h" 56157e72e8SLikun Gao #include "sdma_v5_2.h" 57c6b6a421SHawking Zhang #include "vcn_v2_0.h" 585be45a26SLeo Liu #include "jpeg_v2_0.h" 59b8f10585SLeo Liu #include "vcn_v3_0.h" 604d72dd12SLeo Liu #include "jpeg_v3_0.h" 61733ee71aSRyan Taylor #include "amdgpu_vkms.h" 62c6b6a421SHawking Zhang #include "mes_v10_1.h" 63b05b6903SJiange Zhao #include "mxgpu_nv.h" 640bf7f2dcSLikun Gao #include "smuio_v11_0.h" 650bf7f2dcSLikun Gao #include "smuio_v11_0_6.h" 66c6b6a421SHawking Zhang 67c6b6a421SHawking Zhang static const struct amd_ip_funcs nv_common_ip_funcs; 68c6b6a421SHawking Zhang 693b246e8bSAlex Deucher /* Navi */ 703b246e8bSAlex Deucher static const struct amdgpu_video_codec_info nv_video_codecs_encode_array[] = 713b246e8bSAlex Deucher { 729075096bSVeerabadhran Gopalakrishnan {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 2304, 0)}, 739075096bSVeerabadhran Gopalakrishnan {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 4096, 2304, 0)}, 743b246e8bSAlex Deucher }; 753b246e8bSAlex Deucher 763b246e8bSAlex Deucher static const struct amdgpu_video_codecs nv_video_codecs_encode = 773b246e8bSAlex Deucher { 783b246e8bSAlex Deucher .codec_count = ARRAY_SIZE(nv_video_codecs_encode_array), 793b246e8bSAlex Deucher .codec_array = nv_video_codecs_encode_array, 803b246e8bSAlex Deucher }; 813b246e8bSAlex Deucher 823b246e8bSAlex Deucher /* Navi1x */ 833b246e8bSAlex Deucher static const struct amdgpu_video_codec_info nv_video_codecs_decode_array[] = 843b246e8bSAlex Deucher { 859075096bSVeerabadhran Gopalakrishnan {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 4096, 4906, 3)}, 869075096bSVeerabadhran Gopalakrishnan {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 4096, 4906, 5)}, 879075096bSVeerabadhran Gopalakrishnan {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4906, 52)}, 889075096bSVeerabadhran Gopalakrishnan {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 4096, 4906, 4)}, 899075096bSVeerabadhran Gopalakrishnan {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)}, 909075096bSVeerabadhran Gopalakrishnan {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)}, 919075096bSVeerabadhran Gopalakrishnan {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)}, 923b246e8bSAlex Deucher }; 933b246e8bSAlex Deucher 943b246e8bSAlex Deucher static const struct amdgpu_video_codecs nv_video_codecs_decode = 953b246e8bSAlex Deucher { 963b246e8bSAlex Deucher .codec_count = ARRAY_SIZE(nv_video_codecs_decode_array), 973b246e8bSAlex Deucher .codec_array = nv_video_codecs_decode_array, 983b246e8bSAlex Deucher }; 993b246e8bSAlex Deucher 1003b246e8bSAlex Deucher /* Sienna Cichlid */ 1013b246e8bSAlex Deucher static const struct amdgpu_video_codec_info sc_video_codecs_decode_array[] = 1023b246e8bSAlex Deucher { 1039075096bSVeerabadhran Gopalakrishnan {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 4096, 4906, 3)}, 1049075096bSVeerabadhran Gopalakrishnan {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 4096, 4906, 5)}, 1059075096bSVeerabadhran Gopalakrishnan {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4906, 52)}, 1069075096bSVeerabadhran Gopalakrishnan {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 4096, 4906, 4)}, 1079075096bSVeerabadhran Gopalakrishnan {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)}, 1089075096bSVeerabadhran Gopalakrishnan {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)}, 1099075096bSVeerabadhran Gopalakrishnan {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)}, 1109075096bSVeerabadhran Gopalakrishnan {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, 8192, 4352, 0)}, 1113b246e8bSAlex Deucher }; 1123b246e8bSAlex Deucher 1133b246e8bSAlex Deucher static const struct amdgpu_video_codecs sc_video_codecs_decode = 1143b246e8bSAlex Deucher { 1153b246e8bSAlex Deucher .codec_count = ARRAY_SIZE(sc_video_codecs_decode_array), 1163b246e8bSAlex Deucher .codec_array = sc_video_codecs_decode_array, 1173b246e8bSAlex Deucher }; 1183b246e8bSAlex Deucher 119ed9d2053SBokun Zhang /* SRIOV Sienna Cichlid, not const since data is controlled by host */ 120ed9d2053SBokun Zhang static struct amdgpu_video_codec_info sriov_sc_video_codecs_encode_array[] = 121ed9d2053SBokun Zhang { 1229075096bSVeerabadhran Gopalakrishnan {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 2304, 0)}, 1239075096bSVeerabadhran Gopalakrishnan {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 4096, 2304, 0)}, 124ed9d2053SBokun Zhang }; 125ed9d2053SBokun Zhang 126ed9d2053SBokun Zhang static struct amdgpu_video_codec_info sriov_sc_video_codecs_decode_array[] = 127ed9d2053SBokun Zhang { 1289075096bSVeerabadhran Gopalakrishnan {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 4096, 4906, 3)}, 1299075096bSVeerabadhran Gopalakrishnan {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 4096, 4906, 5)}, 1309075096bSVeerabadhran Gopalakrishnan {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4906, 52)}, 1319075096bSVeerabadhran Gopalakrishnan {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 4096, 4906, 4)}, 1329075096bSVeerabadhran Gopalakrishnan {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)}, 1339075096bSVeerabadhran Gopalakrishnan {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)}, 1349075096bSVeerabadhran Gopalakrishnan {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)}, 1359075096bSVeerabadhran Gopalakrishnan {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, 8192, 4352, 0)}, 136ed9d2053SBokun Zhang }; 137ed9d2053SBokun Zhang 138ed9d2053SBokun Zhang static struct amdgpu_video_codecs sriov_sc_video_codecs_encode = 139ed9d2053SBokun Zhang { 140ed9d2053SBokun Zhang .codec_count = ARRAY_SIZE(sriov_sc_video_codecs_encode_array), 141ed9d2053SBokun Zhang .codec_array = sriov_sc_video_codecs_encode_array, 142ed9d2053SBokun Zhang }; 143ed9d2053SBokun Zhang 144ed9d2053SBokun Zhang static struct amdgpu_video_codecs sriov_sc_video_codecs_decode = 145ed9d2053SBokun Zhang { 146ed9d2053SBokun Zhang .codec_count = ARRAY_SIZE(sriov_sc_video_codecs_decode_array), 147ed9d2053SBokun Zhang .codec_array = sriov_sc_video_codecs_decode_array, 148ed9d2053SBokun Zhang }; 149ed9d2053SBokun Zhang 150b3a24461SVeerabadhran Gopalakrishnan /* Beige Goby*/ 151b3a24461SVeerabadhran Gopalakrishnan static const struct amdgpu_video_codec_info bg_video_codecs_decode_array[] = { 152b3a24461SVeerabadhran Gopalakrishnan {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4906, 52)}, 153b3a24461SVeerabadhran Gopalakrishnan {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)}, 154b3a24461SVeerabadhran Gopalakrishnan {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)}, 155b3a24461SVeerabadhran Gopalakrishnan }; 156b3a24461SVeerabadhran Gopalakrishnan 157b3a24461SVeerabadhran Gopalakrishnan static const struct amdgpu_video_codecs bg_video_codecs_decode = { 158b3a24461SVeerabadhran Gopalakrishnan .codec_count = ARRAY_SIZE(bg_video_codecs_decode_array), 159b3a24461SVeerabadhran Gopalakrishnan .codec_array = bg_video_codecs_decode_array, 160b3a24461SVeerabadhran Gopalakrishnan }; 161b3a24461SVeerabadhran Gopalakrishnan 162b3a24461SVeerabadhran Gopalakrishnan static const struct amdgpu_video_codecs bg_video_codecs_encode = { 163b3a24461SVeerabadhran Gopalakrishnan .codec_count = 0, 164b3a24461SVeerabadhran Gopalakrishnan .codec_array = NULL, 165b3a24461SVeerabadhran Gopalakrishnan }; 166b3a24461SVeerabadhran Gopalakrishnan 16755439817SVeerabadhran Gopalakrishnan /* Yellow Carp*/ 16855439817SVeerabadhran Gopalakrishnan static const struct amdgpu_video_codec_info yc_video_codecs_decode_array[] = { 16955439817SVeerabadhran Gopalakrishnan {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4906, 52)}, 17055439817SVeerabadhran Gopalakrishnan {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)}, 17155439817SVeerabadhran Gopalakrishnan {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)}, 17255439817SVeerabadhran Gopalakrishnan {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)}, 17355439817SVeerabadhran Gopalakrishnan }; 17455439817SVeerabadhran Gopalakrishnan 17555439817SVeerabadhran Gopalakrishnan static const struct amdgpu_video_codecs yc_video_codecs_decode = { 176f72ac409SVeerabadhran Gopalakrishnan .codec_count = ARRAY_SIZE(yc_video_codecs_decode_array), 177f72ac409SVeerabadhran Gopalakrishnan .codec_array = yc_video_codecs_decode_array, 17855439817SVeerabadhran Gopalakrishnan }; 17955439817SVeerabadhran Gopalakrishnan 1803b246e8bSAlex Deucher static int nv_query_video_codecs(struct amdgpu_device *adev, bool encode, 1813b246e8bSAlex Deucher const struct amdgpu_video_codecs **codecs) 1823b246e8bSAlex Deucher { 1831d789535SAlex Deucher switch (adev->ip_versions[UVD_HWIP][0]) { 1843e67f4f2SAlex Deucher case IP_VERSION(3, 0, 0): 1854d395f93SGuchun Chen case IP_VERSION(3, 0, 64): 186da3b36a2SJane Jian case IP_VERSION(3, 0, 192): 187ed9d2053SBokun Zhang if (amdgpu_sriov_vf(adev)) { 188ed9d2053SBokun Zhang if (encode) 189ed9d2053SBokun Zhang *codecs = &sriov_sc_video_codecs_encode; 190ed9d2053SBokun Zhang else 191ed9d2053SBokun Zhang *codecs = &sriov_sc_video_codecs_decode; 192ed9d2053SBokun Zhang } else { 193ed9d2053SBokun Zhang if (encode) 194ed9d2053SBokun Zhang *codecs = &nv_video_codecs_encode; 195ed9d2053SBokun Zhang else 196ed9d2053SBokun Zhang *codecs = &sc_video_codecs_decode; 197ed9d2053SBokun Zhang } 198ed9d2053SBokun Zhang return 0; 1993e67f4f2SAlex Deucher case IP_VERSION(3, 0, 16): 2003e67f4f2SAlex Deucher case IP_VERSION(3, 0, 2): 2013b246e8bSAlex Deucher if (encode) 2023b246e8bSAlex Deucher *codecs = &nv_video_codecs_encode; 2033b246e8bSAlex Deucher else 2043b246e8bSAlex Deucher *codecs = &sc_video_codecs_decode; 2053b246e8bSAlex Deucher return 0; 2063e67f4f2SAlex Deucher case IP_VERSION(3, 1, 1): 20755439817SVeerabadhran Gopalakrishnan if (encode) 20855439817SVeerabadhran Gopalakrishnan *codecs = &nv_video_codecs_encode; 20955439817SVeerabadhran Gopalakrishnan else 21055439817SVeerabadhran Gopalakrishnan *codecs = &yc_video_codecs_decode; 21155439817SVeerabadhran Gopalakrishnan return 0; 2123e67f4f2SAlex Deucher case IP_VERSION(3, 0, 33): 213b3a24461SVeerabadhran Gopalakrishnan if (encode) 214b3a24461SVeerabadhran Gopalakrishnan *codecs = &bg_video_codecs_encode; 215b3a24461SVeerabadhran Gopalakrishnan else 216b3a24461SVeerabadhran Gopalakrishnan *codecs = &bg_video_codecs_decode; 217b3a24461SVeerabadhran Gopalakrishnan return 0; 2183e67f4f2SAlex Deucher case IP_VERSION(2, 0, 0): 2193e67f4f2SAlex Deucher case IP_VERSION(2, 0, 2): 2203b246e8bSAlex Deucher if (encode) 2213b246e8bSAlex Deucher *codecs = &nv_video_codecs_encode; 2223b246e8bSAlex Deucher else 2233b246e8bSAlex Deucher *codecs = &nv_video_codecs_decode; 2243b246e8bSAlex Deucher return 0; 2253b246e8bSAlex Deucher default: 2263b246e8bSAlex Deucher return -EINVAL; 2273b246e8bSAlex Deucher } 2283b246e8bSAlex Deucher } 2293b246e8bSAlex Deucher 230c6b6a421SHawking Zhang /* 231c6b6a421SHawking Zhang * Indirect registers accessor 232c6b6a421SHawking Zhang */ 233c6b6a421SHawking Zhang static u32 nv_pcie_rreg(struct amdgpu_device *adev, u32 reg) 234c6b6a421SHawking Zhang { 235705a2b5bSHawking Zhang unsigned long address, data; 236bebc0762SHawking Zhang address = adev->nbio.funcs->get_pcie_index_offset(adev); 237bebc0762SHawking Zhang data = adev->nbio.funcs->get_pcie_data_offset(adev); 238c6b6a421SHawking Zhang 239705a2b5bSHawking Zhang return amdgpu_device_indirect_rreg(adev, address, data, reg); 240c6b6a421SHawking Zhang } 241c6b6a421SHawking Zhang 242c6b6a421SHawking Zhang static void nv_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v) 243c6b6a421SHawking Zhang { 244705a2b5bSHawking Zhang unsigned long address, data; 245c6b6a421SHawking Zhang 246bebc0762SHawking Zhang address = adev->nbio.funcs->get_pcie_index_offset(adev); 247bebc0762SHawking Zhang data = adev->nbio.funcs->get_pcie_data_offset(adev); 248c6b6a421SHawking Zhang 249705a2b5bSHawking Zhang amdgpu_device_indirect_wreg(adev, address, data, reg, v); 250c6b6a421SHawking Zhang } 251c6b6a421SHawking Zhang 2524922f1bcSJohn Clements static u64 nv_pcie_rreg64(struct amdgpu_device *adev, u32 reg) 2534922f1bcSJohn Clements { 254705a2b5bSHawking Zhang unsigned long address, data; 2554922f1bcSJohn Clements address = adev->nbio.funcs->get_pcie_index_offset(adev); 2564922f1bcSJohn Clements data = adev->nbio.funcs->get_pcie_data_offset(adev); 2574922f1bcSJohn Clements 258705a2b5bSHawking Zhang return amdgpu_device_indirect_rreg64(adev, address, data, reg); 2594922f1bcSJohn Clements } 2604922f1bcSJohn Clements 2614922f1bcSJohn Clements static void nv_pcie_wreg64(struct amdgpu_device *adev, u32 reg, u64 v) 2624922f1bcSJohn Clements { 263705a2b5bSHawking Zhang unsigned long address, data; 2644922f1bcSJohn Clements 2654922f1bcSJohn Clements address = adev->nbio.funcs->get_pcie_index_offset(adev); 2664922f1bcSJohn Clements data = adev->nbio.funcs->get_pcie_data_offset(adev); 2674922f1bcSJohn Clements 268705a2b5bSHawking Zhang amdgpu_device_indirect_wreg64(adev, address, data, reg, v); 2694922f1bcSJohn Clements } 2704922f1bcSJohn Clements 271c6b6a421SHawking Zhang static u32 nv_didt_rreg(struct amdgpu_device *adev, u32 reg) 272c6b6a421SHawking Zhang { 273c6b6a421SHawking Zhang unsigned long flags, address, data; 274c6b6a421SHawking Zhang u32 r; 275c6b6a421SHawking Zhang 276c6b6a421SHawking Zhang address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX); 277c6b6a421SHawking Zhang data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA); 278c6b6a421SHawking Zhang 279c6b6a421SHawking Zhang spin_lock_irqsave(&adev->didt_idx_lock, flags); 280c6b6a421SHawking Zhang WREG32(address, (reg)); 281c6b6a421SHawking Zhang r = RREG32(data); 282c6b6a421SHawking Zhang spin_unlock_irqrestore(&adev->didt_idx_lock, flags); 283c6b6a421SHawking Zhang return r; 284c6b6a421SHawking Zhang } 285c6b6a421SHawking Zhang 286c6b6a421SHawking Zhang static void nv_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v) 287c6b6a421SHawking Zhang { 288c6b6a421SHawking Zhang unsigned long flags, address, data; 289c6b6a421SHawking Zhang 290c6b6a421SHawking Zhang address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX); 291c6b6a421SHawking Zhang data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA); 292c6b6a421SHawking Zhang 293c6b6a421SHawking Zhang spin_lock_irqsave(&adev->didt_idx_lock, flags); 294c6b6a421SHawking Zhang WREG32(address, (reg)); 295c6b6a421SHawking Zhang WREG32(data, (v)); 296c6b6a421SHawking Zhang spin_unlock_irqrestore(&adev->didt_idx_lock, flags); 297c6b6a421SHawking Zhang } 298c6b6a421SHawking Zhang 299c6b6a421SHawking Zhang static u32 nv_get_config_memsize(struct amdgpu_device *adev) 300c6b6a421SHawking Zhang { 301bebc0762SHawking Zhang return adev->nbio.funcs->get_memsize(adev); 302c6b6a421SHawking Zhang } 303c6b6a421SHawking Zhang 304c6b6a421SHawking Zhang static u32 nv_get_xclk(struct amdgpu_device *adev) 305c6b6a421SHawking Zhang { 306462a70d8STao Zhou return adev->clock.spll.reference_freq; 307c6b6a421SHawking Zhang } 308c6b6a421SHawking Zhang 309c6b6a421SHawking Zhang 310c6b6a421SHawking Zhang void nv_grbm_select(struct amdgpu_device *adev, 311c6b6a421SHawking Zhang u32 me, u32 pipe, u32 queue, u32 vmid) 312c6b6a421SHawking Zhang { 313c6b6a421SHawking Zhang u32 grbm_gfx_cntl = 0; 314c6b6a421SHawking Zhang grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, PIPEID, pipe); 315c6b6a421SHawking Zhang grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, MEID, me); 316c6b6a421SHawking Zhang grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, VMID, vmid); 317c6b6a421SHawking Zhang grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, QUEUEID, queue); 318c6b6a421SHawking Zhang 319f2958a8bSPeng Ju Zhou WREG32_SOC15(GC, 0, mmGRBM_GFX_CNTL, grbm_gfx_cntl); 320c6b6a421SHawking Zhang } 321c6b6a421SHawking Zhang 322c6b6a421SHawking Zhang static void nv_vga_set_state(struct amdgpu_device *adev, bool state) 323c6b6a421SHawking Zhang { 324c6b6a421SHawking Zhang /* todo */ 325c6b6a421SHawking Zhang } 326c6b6a421SHawking Zhang 327c6b6a421SHawking Zhang static bool nv_read_disabled_bios(struct amdgpu_device *adev) 328c6b6a421SHawking Zhang { 329c6b6a421SHawking Zhang /* todo */ 330c6b6a421SHawking Zhang return false; 331c6b6a421SHawking Zhang } 332c6b6a421SHawking Zhang 333c6b6a421SHawking Zhang static struct soc15_allowed_register_entry nv_allowed_read_registers[] = { 334c6b6a421SHawking Zhang { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS)}, 335c6b6a421SHawking Zhang { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS2)}, 336c6b6a421SHawking Zhang { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE0)}, 337c6b6a421SHawking Zhang { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE1)}, 338c6b6a421SHawking Zhang { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE2)}, 339c6b6a421SHawking Zhang { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE3)}, 340c6b6a421SHawking Zhang { SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_STATUS_REG)}, 341c6b6a421SHawking Zhang { SOC15_REG_ENTRY(SDMA1, 0, mmSDMA1_STATUS_REG)}, 342c6b6a421SHawking Zhang { SOC15_REG_ENTRY(GC, 0, mmCP_STAT)}, 343c6b6a421SHawking Zhang { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT1)}, 344c6b6a421SHawking Zhang { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT2)}, 345c6b6a421SHawking Zhang { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT3)}, 346c6b6a421SHawking Zhang { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_BUSY_STAT)}, 347c6b6a421SHawking Zhang { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STALLED_STAT1)}, 348c6b6a421SHawking Zhang { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STATUS)}, 349664fe85aSMarek Olšák { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_BUSY_STAT)}, 350c6b6a421SHawking Zhang { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STALLED_STAT1)}, 351c6b6a421SHawking Zhang { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STATUS)}, 352c6b6a421SHawking Zhang { SOC15_REG_ENTRY(GC, 0, mmGB_ADDR_CONFIG)}, 353c6b6a421SHawking Zhang }; 354c6b6a421SHawking Zhang 355c6b6a421SHawking Zhang static uint32_t nv_read_indexed_register(struct amdgpu_device *adev, u32 se_num, 356c6b6a421SHawking Zhang u32 sh_num, u32 reg_offset) 357c6b6a421SHawking Zhang { 358c6b6a421SHawking Zhang uint32_t val; 359c6b6a421SHawking Zhang 360c6b6a421SHawking Zhang mutex_lock(&adev->grbm_idx_mutex); 361c6b6a421SHawking Zhang if (se_num != 0xffffffff || sh_num != 0xffffffff) 362c6b6a421SHawking Zhang amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff); 363c6b6a421SHawking Zhang 364c6b6a421SHawking Zhang val = RREG32(reg_offset); 365c6b6a421SHawking Zhang 366c6b6a421SHawking Zhang if (se_num != 0xffffffff || sh_num != 0xffffffff) 367c6b6a421SHawking Zhang amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 368c6b6a421SHawking Zhang mutex_unlock(&adev->grbm_idx_mutex); 369c6b6a421SHawking Zhang return val; 370c6b6a421SHawking Zhang } 371c6b6a421SHawking Zhang 372c6b6a421SHawking Zhang static uint32_t nv_get_register_value(struct amdgpu_device *adev, 373c6b6a421SHawking Zhang bool indexed, u32 se_num, 374c6b6a421SHawking Zhang u32 sh_num, u32 reg_offset) 375c6b6a421SHawking Zhang { 376c6b6a421SHawking Zhang if (indexed) { 377c6b6a421SHawking Zhang return nv_read_indexed_register(adev, se_num, sh_num, reg_offset); 378c6b6a421SHawking Zhang } else { 379c6b6a421SHawking Zhang if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG)) 380c6b6a421SHawking Zhang return adev->gfx.config.gb_addr_config; 381c6b6a421SHawking Zhang return RREG32(reg_offset); 382c6b6a421SHawking Zhang } 383c6b6a421SHawking Zhang } 384c6b6a421SHawking Zhang 385c6b6a421SHawking Zhang static int nv_read_register(struct amdgpu_device *adev, u32 se_num, 386c6b6a421SHawking Zhang u32 sh_num, u32 reg_offset, u32 *value) 387c6b6a421SHawking Zhang { 388c6b6a421SHawking Zhang uint32_t i; 389c6b6a421SHawking Zhang struct soc15_allowed_register_entry *en; 390c6b6a421SHawking Zhang 391c6b6a421SHawking Zhang *value = 0; 392c6b6a421SHawking Zhang for (i = 0; i < ARRAY_SIZE(nv_allowed_read_registers); i++) { 393c6b6a421SHawking Zhang en = &nv_allowed_read_registers[i]; 394fced3c3aSHuang Rui if ((i == 7 && (adev->sdma.num_instances == 1)) || /* some asics don't have SDMA1 */ 395fced3c3aSHuang Rui reg_offset != 396c6b6a421SHawking Zhang (adev->reg_offset[en->hwip][en->inst][en->seg] + en->reg_offset)) 397c6b6a421SHawking Zhang continue; 398c6b6a421SHawking Zhang 399c6b6a421SHawking Zhang *value = nv_get_register_value(adev, 400c6b6a421SHawking Zhang nv_allowed_read_registers[i].grbm_indexed, 401c6b6a421SHawking Zhang se_num, sh_num, reg_offset); 402c6b6a421SHawking Zhang return 0; 403c6b6a421SHawking Zhang } 404c6b6a421SHawking Zhang return -EINVAL; 405c6b6a421SHawking Zhang } 406c6b6a421SHawking Zhang 407b913ec62SAlex Deucher static int nv_asic_mode2_reset(struct amdgpu_device *adev) 408b913ec62SAlex Deucher { 409b913ec62SAlex Deucher u32 i; 410b913ec62SAlex Deucher int ret = 0; 411b913ec62SAlex Deucher 412b913ec62SAlex Deucher amdgpu_atombios_scratch_regs_engine_hung(adev, true); 413b913ec62SAlex Deucher 414b913ec62SAlex Deucher /* disable BM */ 415b913ec62SAlex Deucher pci_clear_master(adev->pdev); 416b913ec62SAlex Deucher 417b913ec62SAlex Deucher amdgpu_device_cache_pci_state(adev->pdev); 418b913ec62SAlex Deucher 419b913ec62SAlex Deucher ret = amdgpu_dpm_mode2_reset(adev); 420b913ec62SAlex Deucher if (ret) 421b913ec62SAlex Deucher dev_err(adev->dev, "GPU mode2 reset failed\n"); 422b913ec62SAlex Deucher 423b913ec62SAlex Deucher amdgpu_device_load_pci_state(adev->pdev); 424b913ec62SAlex Deucher 425b913ec62SAlex Deucher /* wait for asic to come out of reset */ 426b913ec62SAlex Deucher for (i = 0; i < adev->usec_timeout; i++) { 427b913ec62SAlex Deucher u32 memsize = adev->nbio.funcs->get_memsize(adev); 428b913ec62SAlex Deucher 429b913ec62SAlex Deucher if (memsize != 0xffffffff) 430b913ec62SAlex Deucher break; 431b913ec62SAlex Deucher udelay(1); 432b913ec62SAlex Deucher } 433b913ec62SAlex Deucher 434b913ec62SAlex Deucher amdgpu_atombios_scratch_regs_engine_hung(adev, false); 435b913ec62SAlex Deucher 436b913ec62SAlex Deucher return ret; 437b913ec62SAlex Deucher } 438b913ec62SAlex Deucher 4392ddc6c3eSAlex Deucher static enum amd_reset_method 4402ddc6c3eSAlex Deucher nv_asic_reset_method(struct amdgpu_device *adev) 4412ddc6c3eSAlex Deucher { 442273da6ffSWenhui Sheng if (amdgpu_reset_method == AMD_RESET_METHOD_MODE1 || 44316086355SAlex Deucher amdgpu_reset_method == AMD_RESET_METHOD_MODE2 || 444f172865aSAlex Deucher amdgpu_reset_method == AMD_RESET_METHOD_BACO || 445f172865aSAlex Deucher amdgpu_reset_method == AMD_RESET_METHOD_PCI) 446273da6ffSWenhui Sheng return amdgpu_reset_method; 447273da6ffSWenhui Sheng 448273da6ffSWenhui Sheng if (amdgpu_reset_method != -1) 449273da6ffSWenhui Sheng dev_warn(adev->dev, "Specified reset method:%d isn't supported, using AUTO instead.\n", 450273da6ffSWenhui Sheng amdgpu_reset_method); 451273da6ffSWenhui Sheng 4521d789535SAlex Deucher switch (adev->ip_versions[MP1_HWIP][0]) { 4533e67f4f2SAlex Deucher case IP_VERSION(11, 5, 0): 4543e67f4f2SAlex Deucher case IP_VERSION(13, 0, 1): 4553e67f4f2SAlex Deucher case IP_VERSION(13, 0, 3): 45616086355SAlex Deucher return AMD_RESET_METHOD_MODE2; 4573e67f4f2SAlex Deucher case IP_VERSION(11, 0, 7): 4583e67f4f2SAlex Deucher case IP_VERSION(11, 0, 11): 4593e67f4f2SAlex Deucher case IP_VERSION(11, 0, 12): 4603e67f4f2SAlex Deucher case IP_VERSION(11, 0, 13): 461ca6fd7a6SLikun Gao return AMD_RESET_METHOD_MODE1; 462ca6fd7a6SLikun Gao default: 463181e772fSEvan Quan if (amdgpu_dpm_is_baco_supported(adev)) 4642ddc6c3eSAlex Deucher return AMD_RESET_METHOD_BACO; 4652ddc6c3eSAlex Deucher else 4662ddc6c3eSAlex Deucher return AMD_RESET_METHOD_MODE1; 4672ddc6c3eSAlex Deucher } 468ca6fd7a6SLikun Gao } 4692ddc6c3eSAlex Deucher 470c6b6a421SHawking Zhang static int nv_asic_reset(struct amdgpu_device *adev) 471c6b6a421SHawking Zhang { 472767acabdSKevin Wang int ret = 0; 473c6b6a421SHawking Zhang 47416086355SAlex Deucher switch (nv_asic_reset_method(adev)) { 475f172865aSAlex Deucher case AMD_RESET_METHOD_PCI: 476f172865aSAlex Deucher dev_info(adev->dev, "PCI reset\n"); 477f172865aSAlex Deucher ret = amdgpu_device_pci_reset(adev); 478f172865aSAlex Deucher break; 47916086355SAlex Deucher case AMD_RESET_METHOD_BACO: 48011043b7aSAlex Deucher dev_info(adev->dev, "BACO reset\n"); 481181e772fSEvan Quan ret = amdgpu_dpm_baco_reset(adev); 48216086355SAlex Deucher break; 48316086355SAlex Deucher case AMD_RESET_METHOD_MODE2: 48416086355SAlex Deucher dev_info(adev->dev, "MODE2 reset\n"); 485b913ec62SAlex Deucher ret = nv_asic_mode2_reset(adev); 48616086355SAlex Deucher break; 48716086355SAlex Deucher default: 48811043b7aSAlex Deucher dev_info(adev->dev, "MODE1 reset\n"); 4895c03e584SFeifei Xu ret = amdgpu_device_mode1_reset(adev); 49016086355SAlex Deucher break; 49111043b7aSAlex Deucher } 492767acabdSKevin Wang 493767acabdSKevin Wang return ret; 494c6b6a421SHawking Zhang } 495c6b6a421SHawking Zhang 496c6b6a421SHawking Zhang static int nv_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk) 497c6b6a421SHawking Zhang { 498c6b6a421SHawking Zhang /* todo */ 499c6b6a421SHawking Zhang return 0; 500c6b6a421SHawking Zhang } 501c6b6a421SHawking Zhang 502c6b6a421SHawking Zhang static int nv_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk) 503c6b6a421SHawking Zhang { 504c6b6a421SHawking Zhang /* todo */ 505c6b6a421SHawking Zhang return 0; 506c6b6a421SHawking Zhang } 507c6b6a421SHawking Zhang 508c6b6a421SHawking Zhang static void nv_pcie_gen3_enable(struct amdgpu_device *adev) 509c6b6a421SHawking Zhang { 510c6b6a421SHawking Zhang if (pci_is_root_bus(adev->pdev->bus)) 511c6b6a421SHawking Zhang return; 512c6b6a421SHawking Zhang 513c6b6a421SHawking Zhang if (amdgpu_pcie_gen2 == 0) 514c6b6a421SHawking Zhang return; 515c6b6a421SHawking Zhang 516c6b6a421SHawking Zhang if (!(adev->pm.pcie_gen_mask & (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 | 517c6b6a421SHawking Zhang CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3))) 518c6b6a421SHawking Zhang return; 519c6b6a421SHawking Zhang 520c6b6a421SHawking Zhang /* todo */ 521c6b6a421SHawking Zhang } 522c6b6a421SHawking Zhang 523c6b6a421SHawking Zhang static void nv_program_aspm(struct amdgpu_device *adev) 524c6b6a421SHawking Zhang { 525*0ab5d711SMario Limonciello if (!amdgpu_device_should_use_aspm(adev)) 526c6b6a421SHawking Zhang return; 527c6b6a421SHawking Zhang 5283273f8b9SKenneth Feng if (!(adev->flags & AMD_IS_APU) && 529e1edaeafSLikun Gao (adev->nbio.funcs->program_aspm)) 530e1edaeafSLikun Gao adev->nbio.funcs->program_aspm(adev); 531e1edaeafSLikun Gao 532c6b6a421SHawking Zhang } 533c6b6a421SHawking Zhang 534c6b6a421SHawking Zhang static void nv_enable_doorbell_aperture(struct amdgpu_device *adev, 535c6b6a421SHawking Zhang bool enable) 536c6b6a421SHawking Zhang { 537bebc0762SHawking Zhang adev->nbio.funcs->enable_doorbell_aperture(adev, enable); 538bebc0762SHawking Zhang adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, enable); 539c6b6a421SHawking Zhang } 540c6b6a421SHawking Zhang 541a1f62df7SAlex Deucher const struct amdgpu_ip_block_version nv_common_ip_block = 542c6b6a421SHawking Zhang { 543c6b6a421SHawking Zhang .type = AMD_IP_BLOCK_TYPE_COMMON, 544c6b6a421SHawking Zhang .major = 1, 545c6b6a421SHawking Zhang .minor = 0, 546c6b6a421SHawking Zhang .rev = 0, 547c6b6a421SHawking Zhang .funcs = &nv_common_ip_funcs, 548c6b6a421SHawking Zhang }; 549c6b6a421SHawking Zhang 550c1299461SWenhui Sheng void nv_set_virt_ops(struct amdgpu_device *adev) 551c1299461SWenhui Sheng { 552c1299461SWenhui Sheng adev->virt.ops = &xgpu_nv_virt_ops; 553c1299461SWenhui Sheng } 554c1299461SWenhui Sheng 555c6b6a421SHawking Zhang static uint32_t nv_get_rev_id(struct amdgpu_device *adev) 556c6b6a421SHawking Zhang { 557bebc0762SHawking Zhang return adev->nbio.funcs->get_rev_id(adev); 558c6b6a421SHawking Zhang } 559c6b6a421SHawking Zhang 560c6b6a421SHawking Zhang static bool nv_need_full_reset(struct amdgpu_device *adev) 561c6b6a421SHawking Zhang { 562c6b6a421SHawking Zhang return true; 563c6b6a421SHawking Zhang } 564c6b6a421SHawking Zhang 565c6b6a421SHawking Zhang static bool nv_need_reset_on_init(struct amdgpu_device *adev) 566c6b6a421SHawking Zhang { 567c6b6a421SHawking Zhang u32 sol_reg; 568c6b6a421SHawking Zhang 569c6b6a421SHawking Zhang if (adev->flags & AMD_IS_APU) 570c6b6a421SHawking Zhang return false; 571c6b6a421SHawking Zhang 572c6b6a421SHawking Zhang /* Check sOS sign of life register to confirm sys driver and sOS 573c6b6a421SHawking Zhang * are already been loaded. 574c6b6a421SHawking Zhang */ 575c6b6a421SHawking Zhang sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81); 576c6b6a421SHawking Zhang if (sol_reg) 577c6b6a421SHawking Zhang return true; 5783967ae6dSAlex Deucher 579c6b6a421SHawking Zhang return false; 580c6b6a421SHawking Zhang } 581c6b6a421SHawking Zhang 5822af81531SKevin Wang static uint64_t nv_get_pcie_replay_count(struct amdgpu_device *adev) 5832af81531SKevin Wang { 5842af81531SKevin Wang 5852af81531SKevin Wang /* TODO 5862af81531SKevin Wang * dummy implement for pcie_replay_count sysfs interface 5872af81531SKevin Wang * */ 5882af81531SKevin Wang 5892af81531SKevin Wang return 0; 5902af81531SKevin Wang } 5912af81531SKevin Wang 592c6b6a421SHawking Zhang static void nv_init_doorbell_index(struct amdgpu_device *adev) 593c6b6a421SHawking Zhang { 594c6b6a421SHawking Zhang adev->doorbell_index.kiq = AMDGPU_NAVI10_DOORBELL_KIQ; 595c6b6a421SHawking Zhang adev->doorbell_index.mec_ring0 = AMDGPU_NAVI10_DOORBELL_MEC_RING0; 596c6b6a421SHawking Zhang adev->doorbell_index.mec_ring1 = AMDGPU_NAVI10_DOORBELL_MEC_RING1; 597c6b6a421SHawking Zhang adev->doorbell_index.mec_ring2 = AMDGPU_NAVI10_DOORBELL_MEC_RING2; 598c6b6a421SHawking Zhang adev->doorbell_index.mec_ring3 = AMDGPU_NAVI10_DOORBELL_MEC_RING3; 599c6b6a421SHawking Zhang adev->doorbell_index.mec_ring4 = AMDGPU_NAVI10_DOORBELL_MEC_RING4; 600c6b6a421SHawking Zhang adev->doorbell_index.mec_ring5 = AMDGPU_NAVI10_DOORBELL_MEC_RING5; 601c6b6a421SHawking Zhang adev->doorbell_index.mec_ring6 = AMDGPU_NAVI10_DOORBELL_MEC_RING6; 602c6b6a421SHawking Zhang adev->doorbell_index.mec_ring7 = AMDGPU_NAVI10_DOORBELL_MEC_RING7; 603c6b6a421SHawking Zhang adev->doorbell_index.userqueue_start = AMDGPU_NAVI10_DOORBELL_USERQUEUE_START; 604c6b6a421SHawking Zhang adev->doorbell_index.userqueue_end = AMDGPU_NAVI10_DOORBELL_USERQUEUE_END; 605c6b6a421SHawking Zhang adev->doorbell_index.gfx_ring0 = AMDGPU_NAVI10_DOORBELL_GFX_RING0; 606c6b6a421SHawking Zhang adev->doorbell_index.gfx_ring1 = AMDGPU_NAVI10_DOORBELL_GFX_RING1; 60720519232SJack Xiao adev->doorbell_index.mes_ring = AMDGPU_NAVI10_DOORBELL_MES_RING; 608c6b6a421SHawking Zhang adev->doorbell_index.sdma_engine[0] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE0; 609c6b6a421SHawking Zhang adev->doorbell_index.sdma_engine[1] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE1; 610157e72e8SLikun Gao adev->doorbell_index.sdma_engine[2] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE2; 611157e72e8SLikun Gao adev->doorbell_index.sdma_engine[3] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE3; 612c6b6a421SHawking Zhang adev->doorbell_index.ih = AMDGPU_NAVI10_DOORBELL_IH; 613c6b6a421SHawking Zhang adev->doorbell_index.vcn.vcn_ring0_1 = AMDGPU_NAVI10_DOORBELL64_VCN0_1; 614c6b6a421SHawking Zhang adev->doorbell_index.vcn.vcn_ring2_3 = AMDGPU_NAVI10_DOORBELL64_VCN2_3; 615c6b6a421SHawking Zhang adev->doorbell_index.vcn.vcn_ring4_5 = AMDGPU_NAVI10_DOORBELL64_VCN4_5; 616c6b6a421SHawking Zhang adev->doorbell_index.vcn.vcn_ring6_7 = AMDGPU_NAVI10_DOORBELL64_VCN6_7; 617c6b6a421SHawking Zhang adev->doorbell_index.first_non_cp = AMDGPU_NAVI10_DOORBELL64_FIRST_NON_CP; 618c6b6a421SHawking Zhang adev->doorbell_index.last_non_cp = AMDGPU_NAVI10_DOORBELL64_LAST_NON_CP; 619c6b6a421SHawking Zhang 620c6b6a421SHawking Zhang adev->doorbell_index.max_assignment = AMDGPU_NAVI10_DOORBELL_MAX_ASSIGNMENT << 1; 621c6b6a421SHawking Zhang adev->doorbell_index.sdma_doorbell_range = 20; 622c6b6a421SHawking Zhang } 623c6b6a421SHawking Zhang 624a7173731SAlex Deucher static void nv_pre_asic_init(struct amdgpu_device *adev) 625a7173731SAlex Deucher { 626a7173731SAlex Deucher } 627a7173731SAlex Deucher 62827747293SEvan Quan static int nv_update_umd_stable_pstate(struct amdgpu_device *adev, 62927747293SEvan Quan bool enter) 63027747293SEvan Quan { 63127747293SEvan Quan if (enter) 63227747293SEvan Quan amdgpu_gfx_rlc_enter_safe_mode(adev); 63327747293SEvan Quan else 63427747293SEvan Quan amdgpu_gfx_rlc_exit_safe_mode(adev); 63527747293SEvan Quan 63627747293SEvan Quan if (adev->gfx.funcs->update_perfmon_mgcg) 63727747293SEvan Quan adev->gfx.funcs->update_perfmon_mgcg(adev, !enter); 63827747293SEvan Quan 6393273f8b9SKenneth Feng if (!(adev->flags & AMD_IS_APU) && 640e1edaeafSLikun Gao (adev->nbio.funcs->enable_aspm)) 64127747293SEvan Quan adev->nbio.funcs->enable_aspm(adev, !enter); 64227747293SEvan Quan 64327747293SEvan Quan return 0; 64427747293SEvan Quan } 64527747293SEvan Quan 646c6b6a421SHawking Zhang static const struct amdgpu_asic_funcs nv_asic_funcs = 647c6b6a421SHawking Zhang { 648c6b6a421SHawking Zhang .read_disabled_bios = &nv_read_disabled_bios, 64904022982SHawking Zhang .read_bios_from_rom = &amdgpu_soc15_read_bios_from_rom, 650c6b6a421SHawking Zhang .read_register = &nv_read_register, 651c6b6a421SHawking Zhang .reset = &nv_asic_reset, 6522ddc6c3eSAlex Deucher .reset_method = &nv_asic_reset_method, 653c6b6a421SHawking Zhang .set_vga_state = &nv_vga_set_state, 654c6b6a421SHawking Zhang .get_xclk = &nv_get_xclk, 655c6b6a421SHawking Zhang .set_uvd_clocks = &nv_set_uvd_clocks, 656c6b6a421SHawking Zhang .set_vce_clocks = &nv_set_vce_clocks, 657c6b6a421SHawking Zhang .get_config_memsize = &nv_get_config_memsize, 658c6b6a421SHawking Zhang .init_doorbell_index = &nv_init_doorbell_index, 659c6b6a421SHawking Zhang .need_full_reset = &nv_need_full_reset, 660c6b6a421SHawking Zhang .need_reset_on_init = &nv_need_reset_on_init, 6612af81531SKevin Wang .get_pcie_replay_count = &nv_get_pcie_replay_count, 662181e772fSEvan Quan .supports_baco = &amdgpu_dpm_is_baco_supported, 663a7173731SAlex Deucher .pre_asic_init = &nv_pre_asic_init, 66427747293SEvan Quan .update_umd_stable_pstate = &nv_update_umd_stable_pstate, 6653b246e8bSAlex Deucher .query_video_codecs = &nv_query_video_codecs, 666c6b6a421SHawking Zhang }; 667c6b6a421SHawking Zhang 668c6b6a421SHawking Zhang static int nv_common_early_init(void *handle) 669c6b6a421SHawking Zhang { 670923c087aSYong Zhao #define MMIO_REG_HOLE_OFFSET (0x80000 - PAGE_SIZE) 671c6b6a421SHawking Zhang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 672c6b6a421SHawking Zhang 673d3a21f7eSFelix Kuehling if (!amdgpu_sriov_vf(adev)) { 674923c087aSYong Zhao adev->rmmio_remap.reg_offset = MMIO_REG_HOLE_OFFSET; 675923c087aSYong Zhao adev->rmmio_remap.bus_addr = adev->rmmio_base + MMIO_REG_HOLE_OFFSET; 676d3a21f7eSFelix Kuehling } 677c6b6a421SHawking Zhang adev->smc_rreg = NULL; 678c6b6a421SHawking Zhang adev->smc_wreg = NULL; 679c6b6a421SHawking Zhang adev->pcie_rreg = &nv_pcie_rreg; 680c6b6a421SHawking Zhang adev->pcie_wreg = &nv_pcie_wreg; 6814922f1bcSJohn Clements adev->pcie_rreg64 = &nv_pcie_rreg64; 6824922f1bcSJohn Clements adev->pcie_wreg64 = &nv_pcie_wreg64; 68386700a40SXiaojian Du adev->pciep_rreg = amdgpu_device_pcie_port_rreg; 68486700a40SXiaojian Du adev->pciep_wreg = amdgpu_device_pcie_port_wreg; 685c6b6a421SHawking Zhang 686c6b6a421SHawking Zhang /* TODO: will add them during VCN v2 implementation */ 687c6b6a421SHawking Zhang adev->uvd_ctx_rreg = NULL; 688c6b6a421SHawking Zhang adev->uvd_ctx_wreg = NULL; 689c6b6a421SHawking Zhang 690c6b6a421SHawking Zhang adev->didt_rreg = &nv_didt_rreg; 691c6b6a421SHawking Zhang adev->didt_wreg = &nv_didt_wreg; 692c6b6a421SHawking Zhang 693c6b6a421SHawking Zhang adev->asic_funcs = &nv_asic_funcs; 694c6b6a421SHawking Zhang 695c6b6a421SHawking Zhang adev->rev_id = nv_get_rev_id(adev); 696c6b6a421SHawking Zhang adev->external_rev_id = 0xff; 6973e67f4f2SAlex Deucher /* TODO: split the GC and PG flags based on the relevant IP version for which 6983e67f4f2SAlex Deucher * they are relevant. 6993e67f4f2SAlex Deucher */ 7001d789535SAlex Deucher switch (adev->ip_versions[GC_HWIP][0]) { 7013e67f4f2SAlex Deucher case IP_VERSION(10, 1, 10): 702c6b6a421SHawking Zhang adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 703c6b6a421SHawking Zhang AMD_CG_SUPPORT_GFX_CGCG | 704c6b6a421SHawking Zhang AMD_CG_SUPPORT_IH_CG | 705c6b6a421SHawking Zhang AMD_CG_SUPPORT_HDP_MGCG | 706c6b6a421SHawking Zhang AMD_CG_SUPPORT_HDP_LS | 707c6b6a421SHawking Zhang AMD_CG_SUPPORT_SDMA_MGCG | 708c6b6a421SHawking Zhang AMD_CG_SUPPORT_SDMA_LS | 709c6b6a421SHawking Zhang AMD_CG_SUPPORT_MC_MGCG | 710c6b6a421SHawking Zhang AMD_CG_SUPPORT_MC_LS | 711c6b6a421SHawking Zhang AMD_CG_SUPPORT_ATHUB_MGCG | 712c6b6a421SHawking Zhang AMD_CG_SUPPORT_ATHUB_LS | 713c6b6a421SHawking Zhang AMD_CG_SUPPORT_VCN_MGCG | 714099d66e4SLeo Liu AMD_CG_SUPPORT_JPEG_MGCG | 715c6b6a421SHawking Zhang AMD_CG_SUPPORT_BIF_MGCG | 716c6b6a421SHawking Zhang AMD_CG_SUPPORT_BIF_LS; 717157710eaSLeo Liu adev->pg_flags = AMD_PG_SUPPORT_VCN | 718c12d410fSHuang Rui AMD_PG_SUPPORT_VCN_DPG | 719099d66e4SLeo Liu AMD_PG_SUPPORT_JPEG | 720a201b6acSHuang Rui AMD_PG_SUPPORT_ATHUB; 721c6b6a421SHawking Zhang adev->external_rev_id = adev->rev_id + 0x1; 722c6b6a421SHawking Zhang break; 7233e67f4f2SAlex Deucher case IP_VERSION(10, 1, 1): 724d0c39f8cSXiaojie Yuan adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 725d0c39f8cSXiaojie Yuan AMD_CG_SUPPORT_GFX_CGCG | 726d0c39f8cSXiaojie Yuan AMD_CG_SUPPORT_IH_CG | 727d0c39f8cSXiaojie Yuan AMD_CG_SUPPORT_HDP_MGCG | 728d0c39f8cSXiaojie Yuan AMD_CG_SUPPORT_HDP_LS | 729d0c39f8cSXiaojie Yuan AMD_CG_SUPPORT_SDMA_MGCG | 730d0c39f8cSXiaojie Yuan AMD_CG_SUPPORT_SDMA_LS | 731d0c39f8cSXiaojie Yuan AMD_CG_SUPPORT_MC_MGCG | 732d0c39f8cSXiaojie Yuan AMD_CG_SUPPORT_MC_LS | 733d0c39f8cSXiaojie Yuan AMD_CG_SUPPORT_ATHUB_MGCG | 734d0c39f8cSXiaojie Yuan AMD_CG_SUPPORT_ATHUB_LS | 735d0c39f8cSXiaojie Yuan AMD_CG_SUPPORT_VCN_MGCG | 736099d66e4SLeo Liu AMD_CG_SUPPORT_JPEG_MGCG | 737d0c39f8cSXiaojie Yuan AMD_CG_SUPPORT_BIF_MGCG | 738d0c39f8cSXiaojie Yuan AMD_CG_SUPPORT_BIF_LS; 7390377b088SXiaojie Yuan adev->pg_flags = AMD_PG_SUPPORT_VCN | 740099d66e4SLeo Liu AMD_PG_SUPPORT_JPEG | 7410377b088SXiaojie Yuan AMD_PG_SUPPORT_VCN_DPG; 74235ef88faStiancyin adev->external_rev_id = adev->rev_id + 20; 7435e71e011SXiaojie Yuan break; 7443e67f4f2SAlex Deucher case IP_VERSION(10, 1, 2): 745dca009e7SXiaojie Yuan adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 746dca009e7SXiaojie Yuan AMD_CG_SUPPORT_GFX_MGLS | 747dca009e7SXiaojie Yuan AMD_CG_SUPPORT_GFX_CGCG | 748dca009e7SXiaojie Yuan AMD_CG_SUPPORT_GFX_CP_LS | 7495211c37aSXiaojie Yuan AMD_CG_SUPPORT_GFX_RLC_LS | 750fbe0bc57SXiaojie Yuan AMD_CG_SUPPORT_IH_CG | 7515211c37aSXiaojie Yuan AMD_CG_SUPPORT_HDP_MGCG | 752358ab97fSXiaojie Yuan AMD_CG_SUPPORT_HDP_LS | 753358ab97fSXiaojie Yuan AMD_CG_SUPPORT_SDMA_MGCG | 7548b797b3dSXiaojie Yuan AMD_CG_SUPPORT_SDMA_LS | 7558b797b3dSXiaojie Yuan AMD_CG_SUPPORT_MC_MGCG | 756ca51678dSXiaojie Yuan AMD_CG_SUPPORT_MC_LS | 757ca51678dSXiaojie Yuan AMD_CG_SUPPORT_ATHUB_MGCG | 75865872e59SXiaojie Yuan AMD_CG_SUPPORT_ATHUB_LS | 759099d66e4SLeo Liu AMD_CG_SUPPORT_VCN_MGCG | 760099d66e4SLeo Liu AMD_CG_SUPPORT_JPEG_MGCG; 761c1653ea0SXiaojie Yuan adev->pg_flags = AMD_PG_SUPPORT_VCN | 7625ef3b8acSXiaojie Yuan AMD_PG_SUPPORT_VCN_DPG | 763099d66e4SLeo Liu AMD_PG_SUPPORT_JPEG | 7641b0443b1SLikun Gao AMD_PG_SUPPORT_ATHUB; 765df5e984cSTiecheng Zhou /* guest vm gets 0xffffffff when reading RCC_DEV0_EPF0_STRAP0, 766df5e984cSTiecheng Zhou * as a consequence, the rev_id and external_rev_id are wrong. 767df5e984cSTiecheng Zhou * workaround it by hardcoding rev_id to 0 (default value). 768df5e984cSTiecheng Zhou */ 769df5e984cSTiecheng Zhou if (amdgpu_sriov_vf(adev)) 770df5e984cSTiecheng Zhou adev->rev_id = 0; 77174b5e509SXiaojie Yuan adev->external_rev_id = adev->rev_id + 0xa; 77274b5e509SXiaojie Yuan break; 7733e67f4f2SAlex Deucher case IP_VERSION(10, 3, 0): 77400194defSLikun Gao adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 77500194defSLikun Gao AMD_CG_SUPPORT_GFX_CGCG | 7761d712be9SKenneth Feng AMD_CG_SUPPORT_GFX_CGLS | 77700194defSLikun Gao AMD_CG_SUPPORT_GFX_3D_CGCG | 77898f8ea29SLikun Gao AMD_CG_SUPPORT_MC_MGCG | 77900194defSLikun Gao AMD_CG_SUPPORT_VCN_MGCG | 780ca36461fSKenneth Feng AMD_CG_SUPPORT_JPEG_MGCG | 781ca36461fSKenneth Feng AMD_CG_SUPPORT_HDP_MGCG | 7823a32c25aSKenneth Feng AMD_CG_SUPPORT_HDP_LS | 783bcc8367fSKenneth Feng AMD_CG_SUPPORT_IH_CG | 784bcc8367fSKenneth Feng AMD_CG_SUPPORT_MC_LS; 785b467c4f5SLeo Liu adev->pg_flags = AMD_PG_SUPPORT_VCN | 786d00b0fa9SBoyuan Zhang AMD_PG_SUPPORT_VCN_DPG | 787b794616dSKenneth Feng AMD_PG_SUPPORT_JPEG | 7881b0443b1SLikun Gao AMD_PG_SUPPORT_ATHUB | 7891b0443b1SLikun Gao AMD_PG_SUPPORT_MMHUB; 790c45fbe1bSJack Zhang if (amdgpu_sriov_vf(adev)) { 791c45fbe1bSJack Zhang /* hypervisor control CG and PG enablement */ 792c45fbe1bSJack Zhang adev->cg_flags = 0; 793c45fbe1bSJack Zhang adev->pg_flags = 0; 794c45fbe1bSJack Zhang } 795117910edSLikun Gao adev->external_rev_id = adev->rev_id + 0x28; 796117910edSLikun Gao break; 7973e67f4f2SAlex Deucher case IP_VERSION(10, 3, 2): 79840582e67SJiansong Chen adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 79940582e67SJiansong Chen AMD_CG_SUPPORT_GFX_CGCG | 8001d712be9SKenneth Feng AMD_CG_SUPPORT_GFX_CGLS | 80140582e67SJiansong Chen AMD_CG_SUPPORT_GFX_3D_CGCG | 80240582e67SJiansong Chen AMD_CG_SUPPORT_VCN_MGCG | 80392c73756SJiansong Chen AMD_CG_SUPPORT_JPEG_MGCG | 80492c73756SJiansong Chen AMD_CG_SUPPORT_MC_MGCG | 8054759f887SJiansong Chen AMD_CG_SUPPORT_MC_LS | 8064759f887SJiansong Chen AMD_CG_SUPPORT_HDP_MGCG | 80785e7151bSJiansong Chen AMD_CG_SUPPORT_HDP_LS | 80885e7151bSJiansong Chen AMD_CG_SUPPORT_IH_CG; 809c6e9dd0eSBoyuan Zhang adev->pg_flags = AMD_PG_SUPPORT_VCN | 81000740df9SBoyuan Zhang AMD_PG_SUPPORT_VCN_DPG | 81147fc894aSJiansong Chen AMD_PG_SUPPORT_JPEG | 81247fc894aSJiansong Chen AMD_PG_SUPPORT_ATHUB | 81347fc894aSJiansong Chen AMD_PG_SUPPORT_MMHUB; 814543aa259SJiansong Chen adev->external_rev_id = adev->rev_id + 0x32; 815543aa259SJiansong Chen break; 8163e67f4f2SAlex Deucher case IP_VERSION(10, 3, 1): 81751a7e938SJinzhou.Su adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 81851a7e938SJinzhou.Su AMD_CG_SUPPORT_GFX_MGLS | 81951a7e938SJinzhou.Su AMD_CG_SUPPORT_GFX_CP_LS | 82051a7e938SJinzhou.Su AMD_CG_SUPPORT_GFX_RLC_LS | 82151a7e938SJinzhou.Su AMD_CG_SUPPORT_GFX_CGCG | 822ac0dc4c5SHuang Rui AMD_CG_SUPPORT_GFX_CGLS | 823ac0dc4c5SHuang Rui AMD_CG_SUPPORT_GFX_3D_CGCG | 82407f9c22fSBoyuan Zhang AMD_CG_SUPPORT_GFX_3D_CGLS | 8250ebce667SJinzhou.Su AMD_CG_SUPPORT_MC_MGCG | 8260ebce667SJinzhou.Su AMD_CG_SUPPORT_MC_LS | 827a3964ec4SJinzhou.Su AMD_CG_SUPPORT_GFX_FGCG | 82807f9c22fSBoyuan Zhang AMD_CG_SUPPORT_VCN_MGCG | 829ef9bcfdeSJinzhou Su AMD_CG_SUPPORT_SDMA_MGCG | 830ec0f72cbSJinzhou Su AMD_CG_SUPPORT_SDMA_LS | 83107f9c22fSBoyuan Zhang AMD_CG_SUPPORT_JPEG_MGCG; 83207f9c22fSBoyuan Zhang adev->pg_flags = AMD_PG_SUPPORT_GFX_PG | 83307f9c22fSBoyuan Zhang AMD_PG_SUPPORT_VCN | 83407f9c22fSBoyuan Zhang AMD_PG_SUPPORT_VCN_DPG | 83507f9c22fSBoyuan Zhang AMD_PG_SUPPORT_JPEG; 836c345c89bSHuang Rui if (adev->apu_flags & AMD_APU_IS_VANGOGH) 837026570e6SHuang Rui adev->external_rev_id = adev->rev_id + 0x01; 838026570e6SHuang Rui break; 8393e67f4f2SAlex Deucher case IP_VERSION(10, 3, 4): 840583e5a5eSTao Zhou adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 841583e5a5eSTao Zhou AMD_CG_SUPPORT_GFX_CGCG | 8421d712be9SKenneth Feng AMD_CG_SUPPORT_GFX_CGLS | 843583e5a5eSTao Zhou AMD_CG_SUPPORT_GFX_3D_CGCG | 844583e5a5eSTao Zhou AMD_CG_SUPPORT_VCN_MGCG | 845135333a0STao Zhou AMD_CG_SUPPORT_JPEG_MGCG | 846135333a0STao Zhou AMD_CG_SUPPORT_MC_MGCG | 8472c70c332STao Zhou AMD_CG_SUPPORT_MC_LS | 8482c70c332STao Zhou AMD_CG_SUPPORT_HDP_MGCG | 8498e3bfb99STao Zhou AMD_CG_SUPPORT_HDP_LS | 8508e3bfb99STao Zhou AMD_CG_SUPPORT_IH_CG; 851d5bc1579SJames Zhu adev->pg_flags = AMD_PG_SUPPORT_VCN | 852cc6161aaSJames Zhu AMD_PG_SUPPORT_VCN_DPG | 85373da8e86STao Zhou AMD_PG_SUPPORT_JPEG | 85473da8e86STao Zhou AMD_PG_SUPPORT_ATHUB | 85573da8e86STao Zhou AMD_PG_SUPPORT_MMHUB; 856550c58e0STao Zhou adev->external_rev_id = adev->rev_id + 0x3c; 857550c58e0STao Zhou break; 8583e67f4f2SAlex Deucher case IP_VERSION(10, 3, 5): 859bc6bd46bSTao Zhou adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 860bc6bd46bSTao Zhou AMD_CG_SUPPORT_GFX_CGCG | 861d69d278fSTao Zhou AMD_CG_SUPPORT_GFX_CGLS | 8625d36b865STao Zhou AMD_CG_SUPPORT_GFX_3D_CGCG | 8635d36b865STao Zhou AMD_CG_SUPPORT_MC_MGCG | 864170c193fSTao Zhou AMD_CG_SUPPORT_MC_LS | 865170c193fSTao Zhou AMD_CG_SUPPORT_HDP_MGCG | 866a764bef3STao Zhou AMD_CG_SUPPORT_HDP_LS | 867e47e4c0eSVeerabadhran Gopalakrishnan AMD_CG_SUPPORT_IH_CG | 868e47e4c0eSVeerabadhran Gopalakrishnan AMD_CG_SUPPORT_VCN_MGCG; 869f703d4b6SVeerabadhran Gopalakrishnan adev->pg_flags = AMD_PG_SUPPORT_VCN | 870147de218STao Zhou AMD_PG_SUPPORT_VCN_DPG | 871147de218STao Zhou AMD_PG_SUPPORT_ATHUB | 872147de218STao Zhou AMD_PG_SUPPORT_MMHUB; 8738573035aSChengming Gui adev->external_rev_id = adev->rev_id + 0x46; 8748573035aSChengming Gui break; 8753e67f4f2SAlex Deucher case IP_VERSION(10, 3, 3): 8769c6c48e6SAaron Liu adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 8779c6c48e6SAaron Liu AMD_CG_SUPPORT_GFX_MGLS | 8789c6c48e6SAaron Liu AMD_CG_SUPPORT_GFX_CGCG | 8799c6c48e6SAaron Liu AMD_CG_SUPPORT_GFX_CGLS | 8809c6c48e6SAaron Liu AMD_CG_SUPPORT_GFX_3D_CGCG | 8819c6c48e6SAaron Liu AMD_CG_SUPPORT_GFX_3D_CGLS | 8829c6c48e6SAaron Liu AMD_CG_SUPPORT_GFX_RLC_LS | 8839c6c48e6SAaron Liu AMD_CG_SUPPORT_GFX_CP_LS | 88483ae09b5SAaron Liu AMD_CG_SUPPORT_GFX_FGCG | 88583ae09b5SAaron Liu AMD_CG_SUPPORT_MC_MGCG | 886f1e9aa65SAaron Liu AMD_CG_SUPPORT_MC_LS | 8876bd95572SAaron Liu AMD_CG_SUPPORT_SDMA_LS | 8886bd95572SAaron Liu AMD_CG_SUPPORT_HDP_MGCG | 889b7dd14c7SAaron Liu AMD_CG_SUPPORT_HDP_LS | 890b7dd14c7SAaron Liu AMD_CG_SUPPORT_ATHUB_MGCG | 891db72c3faSAaron Liu AMD_CG_SUPPORT_ATHUB_LS | 892948b1216SAaron Liu AMD_CG_SUPPORT_IH_CG | 893948b1216SAaron Liu AMD_CG_SUPPORT_VCN_MGCG | 894948b1216SAaron Liu AMD_CG_SUPPORT_JPEG_MGCG; 89554f4f6f3SJames Zhu adev->pg_flags = AMD_PG_SUPPORT_GFX_PG | 896948b1216SAaron Liu AMD_PG_SUPPORT_VCN | 897948b1216SAaron Liu AMD_PG_SUPPORT_VCN_DPG | 898948b1216SAaron Liu AMD_PG_SUPPORT_JPEG; 899e97c8d86SAaron Liu if (adev->pdev->device == 0x1681) 9005efacdf0SAaron Liu adev->external_rev_id = 0x20; 901e97c8d86SAaron Liu else 902e7990721SAaron Liu adev->external_rev_id = adev->rev_id + 0x01; 903e7990721SAaron Liu break; 9043e67f4f2SAlex Deucher case IP_VERSION(10, 1, 3): 905f9ed188dSLang Yu case IP_VERSION(10, 1, 4): 906b515937bSTao Zhou adev->cg_flags = 0; 907b515937bSTao Zhou adev->pg_flags = 0; 908b515937bSTao Zhou adev->external_rev_id = adev->rev_id + 0x82; 909b515937bSTao Zhou break; 910b67f00e0SPrike Liang case IP_VERSION(10, 3, 7): 911b67f00e0SPrike Liang adev->cg_flags = 0; 91235c27d95SSathishkumar S adev->pg_flags = AMD_PG_SUPPORT_VCN | 91335c27d95SSathishkumar S AMD_PG_SUPPORT_VCN_DPG | 91435c27d95SSathishkumar S AMD_PG_SUPPORT_JPEG; 915b67f00e0SPrike Liang adev->external_rev_id = adev->rev_id + 0x01; 916b67f00e0SPrike Liang break; 917c6b6a421SHawking Zhang default: 918c6b6a421SHawking Zhang /* FIXME: not supported yet */ 919c6b6a421SHawking Zhang return -EINVAL; 920c6b6a421SHawking Zhang } 921c6b6a421SHawking Zhang 9227bd939d0SLikun GAO if (adev->harvest_ip_mask & AMD_HARVEST_IP_VCN_MASK) 9237bd939d0SLikun GAO adev->pg_flags &= ~(AMD_PG_SUPPORT_VCN | 9247bd939d0SLikun GAO AMD_PG_SUPPORT_VCN_DPG | 9257bd939d0SLikun GAO AMD_PG_SUPPORT_JPEG); 9267bd939d0SLikun GAO 927b05b6903SJiange Zhao if (amdgpu_sriov_vf(adev)) { 928b05b6903SJiange Zhao amdgpu_virt_init_setting(adev); 929b05b6903SJiange Zhao xgpu_nv_mailbox_set_irq_funcs(adev); 930b05b6903SJiange Zhao } 931b05b6903SJiange Zhao 932c6b6a421SHawking Zhang return 0; 933c6b6a421SHawking Zhang } 934c6b6a421SHawking Zhang 935c6b6a421SHawking Zhang static int nv_common_late_init(void *handle) 936c6b6a421SHawking Zhang { 937b05b6903SJiange Zhao struct amdgpu_device *adev = (struct amdgpu_device *)handle; 938b05b6903SJiange Zhao 939ed9d2053SBokun Zhang if (amdgpu_sriov_vf(adev)) { 940b05b6903SJiange Zhao xgpu_nv_mailbox_get_irq(adev); 941ed9d2053SBokun Zhang amdgpu_virt_update_sriov_video_codec(adev, 942ed9d2053SBokun Zhang sriov_sc_video_codecs_encode_array, ARRAY_SIZE(sriov_sc_video_codecs_encode_array), 943ed9d2053SBokun Zhang sriov_sc_video_codecs_decode_array, ARRAY_SIZE(sriov_sc_video_codecs_decode_array)); 944ed9d2053SBokun Zhang } 945b05b6903SJiange Zhao 946c6b6a421SHawking Zhang return 0; 947c6b6a421SHawking Zhang } 948c6b6a421SHawking Zhang 949c6b6a421SHawking Zhang static int nv_common_sw_init(void *handle) 950c6b6a421SHawking Zhang { 951b05b6903SJiange Zhao struct amdgpu_device *adev = (struct amdgpu_device *)handle; 952b05b6903SJiange Zhao 953b05b6903SJiange Zhao if (amdgpu_sriov_vf(adev)) 954b05b6903SJiange Zhao xgpu_nv_mailbox_add_irq_id(adev); 955b05b6903SJiange Zhao 956c6b6a421SHawking Zhang return 0; 957c6b6a421SHawking Zhang } 958c6b6a421SHawking Zhang 959c6b6a421SHawking Zhang static int nv_common_sw_fini(void *handle) 960c6b6a421SHawking Zhang { 961c6b6a421SHawking Zhang return 0; 962c6b6a421SHawking Zhang } 963c6b6a421SHawking Zhang 964c6b6a421SHawking Zhang static int nv_common_hw_init(void *handle) 965c6b6a421SHawking Zhang { 966c6b6a421SHawking Zhang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 967c6b6a421SHawking Zhang 9685a5da8aeSEvan Quan if (adev->nbio.funcs->apply_lc_spc_mode_wa) 9695a5da8aeSEvan Quan adev->nbio.funcs->apply_lc_spc_mode_wa(adev); 9705a5da8aeSEvan Quan 971adcf949eSEvan Quan if (adev->nbio.funcs->apply_l1_link_width_reconfig_wa) 972adcf949eSEvan Quan adev->nbio.funcs->apply_l1_link_width_reconfig_wa(adev); 973adcf949eSEvan Quan 974c6b6a421SHawking Zhang /* enable pcie gen2/3 link */ 975c6b6a421SHawking Zhang nv_pcie_gen3_enable(adev); 976c6b6a421SHawking Zhang /* enable aspm */ 977c6b6a421SHawking Zhang nv_program_aspm(adev); 978c6b6a421SHawking Zhang /* setup nbio registers */ 979bebc0762SHawking Zhang adev->nbio.funcs->init_registers(adev); 980923c087aSYong Zhao /* remap HDP registers to a hole in mmio space, 981923c087aSYong Zhao * for the purpose of expose those registers 982923c087aSYong Zhao * to process space 983923c087aSYong Zhao */ 984d3a21f7eSFelix Kuehling if (adev->nbio.funcs->remap_hdp_registers && !amdgpu_sriov_vf(adev)) 985923c087aSYong Zhao adev->nbio.funcs->remap_hdp_registers(adev); 986c6b6a421SHawking Zhang /* enable the doorbell aperture */ 987c6b6a421SHawking Zhang nv_enable_doorbell_aperture(adev, true); 988c6b6a421SHawking Zhang 989c6b6a421SHawking Zhang return 0; 990c6b6a421SHawking Zhang } 991c6b6a421SHawking Zhang 992c6b6a421SHawking Zhang static int nv_common_hw_fini(void *handle) 993c6b6a421SHawking Zhang { 994c6b6a421SHawking Zhang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 995c6b6a421SHawking Zhang 996c6b6a421SHawking Zhang /* disable the doorbell aperture */ 997c6b6a421SHawking Zhang nv_enable_doorbell_aperture(adev, false); 998c6b6a421SHawking Zhang 999c6b6a421SHawking Zhang return 0; 1000c6b6a421SHawking Zhang } 1001c6b6a421SHawking Zhang 1002c6b6a421SHawking Zhang static int nv_common_suspend(void *handle) 1003c6b6a421SHawking Zhang { 1004c6b6a421SHawking Zhang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1005c6b6a421SHawking Zhang 1006c6b6a421SHawking Zhang return nv_common_hw_fini(adev); 1007c6b6a421SHawking Zhang } 1008c6b6a421SHawking Zhang 1009c6b6a421SHawking Zhang static int nv_common_resume(void *handle) 1010c6b6a421SHawking Zhang { 1011c6b6a421SHawking Zhang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1012c6b6a421SHawking Zhang 1013c6b6a421SHawking Zhang return nv_common_hw_init(adev); 1014c6b6a421SHawking Zhang } 1015c6b6a421SHawking Zhang 1016c6b6a421SHawking Zhang static bool nv_common_is_idle(void *handle) 1017c6b6a421SHawking Zhang { 1018c6b6a421SHawking Zhang return true; 1019c6b6a421SHawking Zhang } 1020c6b6a421SHawking Zhang 1021c6b6a421SHawking Zhang static int nv_common_wait_for_idle(void *handle) 1022c6b6a421SHawking Zhang { 1023c6b6a421SHawking Zhang return 0; 1024c6b6a421SHawking Zhang } 1025c6b6a421SHawking Zhang 1026c6b6a421SHawking Zhang static int nv_common_soft_reset(void *handle) 1027c6b6a421SHawking Zhang { 1028c6b6a421SHawking Zhang return 0; 1029c6b6a421SHawking Zhang } 1030c6b6a421SHawking Zhang 1031c6b6a421SHawking Zhang static int nv_common_set_clockgating_state(void *handle, 1032c6b6a421SHawking Zhang enum amd_clockgating_state state) 1033c6b6a421SHawking Zhang { 1034c6b6a421SHawking Zhang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1035c6b6a421SHawking Zhang 1036c6b6a421SHawking Zhang if (amdgpu_sriov_vf(adev)) 1037c6b6a421SHawking Zhang return 0; 1038c6b6a421SHawking Zhang 10391d789535SAlex Deucher switch (adev->ip_versions[NBIO_HWIP][0]) { 10403e67f4f2SAlex Deucher case IP_VERSION(2, 3, 0): 10413e67f4f2SAlex Deucher case IP_VERSION(2, 3, 1): 10423e67f4f2SAlex Deucher case IP_VERSION(2, 3, 2): 10433e67f4f2SAlex Deucher case IP_VERSION(3, 3, 0): 10443e67f4f2SAlex Deucher case IP_VERSION(3, 3, 1): 10453e67f4f2SAlex Deucher case IP_VERSION(3, 3, 2): 10463e67f4f2SAlex Deucher case IP_VERSION(3, 3, 3): 1047bebc0762SHawking Zhang adev->nbio.funcs->update_medium_grain_clock_gating(adev, 1048a9d4fe2fSNirmoy Das state == AMD_CG_STATE_GATE); 1049bebc0762SHawking Zhang adev->nbio.funcs->update_medium_grain_light_sleep(adev, 1050a9d4fe2fSNirmoy Das state == AMD_CG_STATE_GATE); 1051bf087285SLikun Gao adev->hdp.funcs->update_clock_gating(adev, 1052a9d4fe2fSNirmoy Das state == AMD_CG_STATE_GATE); 10531001f2a1SLikun Gao adev->smuio.funcs->update_rom_clock_gating(adev, 10541001f2a1SLikun Gao state == AMD_CG_STATE_GATE); 1055c6b6a421SHawking Zhang break; 1056c6b6a421SHawking Zhang default: 1057c6b6a421SHawking Zhang break; 1058c6b6a421SHawking Zhang } 1059c6b6a421SHawking Zhang return 0; 1060c6b6a421SHawking Zhang } 1061c6b6a421SHawking Zhang 1062c6b6a421SHawking Zhang static int nv_common_set_powergating_state(void *handle, 1063c6b6a421SHawking Zhang enum amd_powergating_state state) 1064c6b6a421SHawking Zhang { 1065c6b6a421SHawking Zhang /* TODO */ 1066c6b6a421SHawking Zhang return 0; 1067c6b6a421SHawking Zhang } 1068c6b6a421SHawking Zhang 1069c6b6a421SHawking Zhang static void nv_common_get_clockgating_state(void *handle, u32 *flags) 1070c6b6a421SHawking Zhang { 1071c6b6a421SHawking Zhang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1072c6b6a421SHawking Zhang 1073c6b6a421SHawking Zhang if (amdgpu_sriov_vf(adev)) 1074c6b6a421SHawking Zhang *flags = 0; 1075c6b6a421SHawking Zhang 1076bebc0762SHawking Zhang adev->nbio.funcs->get_clockgating_state(adev, flags); 1077c6b6a421SHawking Zhang 1078bf087285SLikun Gao adev->hdp.funcs->get_clock_gating_state(adev, flags); 1079c6b6a421SHawking Zhang 10801001f2a1SLikun Gao adev->smuio.funcs->get_clock_gating_state(adev, flags); 10811001f2a1SLikun Gao 1082c6b6a421SHawking Zhang return; 1083c6b6a421SHawking Zhang } 1084c6b6a421SHawking Zhang 1085c6b6a421SHawking Zhang static const struct amd_ip_funcs nv_common_ip_funcs = { 1086c6b6a421SHawking Zhang .name = "nv_common", 1087c6b6a421SHawking Zhang .early_init = nv_common_early_init, 1088c6b6a421SHawking Zhang .late_init = nv_common_late_init, 1089c6b6a421SHawking Zhang .sw_init = nv_common_sw_init, 1090c6b6a421SHawking Zhang .sw_fini = nv_common_sw_fini, 1091c6b6a421SHawking Zhang .hw_init = nv_common_hw_init, 1092c6b6a421SHawking Zhang .hw_fini = nv_common_hw_fini, 1093c6b6a421SHawking Zhang .suspend = nv_common_suspend, 1094c6b6a421SHawking Zhang .resume = nv_common_resume, 1095c6b6a421SHawking Zhang .is_idle = nv_common_is_idle, 1096c6b6a421SHawking Zhang .wait_for_idle = nv_common_wait_for_idle, 1097c6b6a421SHawking Zhang .soft_reset = nv_common_soft_reset, 1098c6b6a421SHawking Zhang .set_clockgating_state = nv_common_set_clockgating_state, 1099c6b6a421SHawking Zhang .set_powergating_state = nv_common_set_powergating_state, 1100c6b6a421SHawking Zhang .get_clockgating_state = nv_common_get_clockgating_state, 1101c6b6a421SHawking Zhang }; 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