1 /* 2 * Copyright 2022 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include "amdgpu.h" 24 #include "amdgpu_atombios.h" 25 #include "nbio_v7_9.h" 26 #include "amdgpu_ras.h" 27 28 #include "nbio/nbio_7_9_0_offset.h" 29 #include "nbio/nbio_7_9_0_sh_mask.h" 30 #include "ivsrcid/nbio/irqsrcs_nbif_7_4.h" 31 #include <uapi/linux/kfd_ioctl.h> 32 33 static void nbio_v7_9_remap_hdp_registers(struct amdgpu_device *adev) 34 { 35 WREG32_SOC15(NBIO, 0, regBIF_BX0_REMAP_HDP_MEM_FLUSH_CNTL, 36 adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL); 37 WREG32_SOC15(NBIO, 0, regBIF_BX0_REMAP_HDP_REG_FLUSH_CNTL, 38 adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_REG_FLUSH_CNTL); 39 } 40 41 static u32 nbio_v7_9_get_rev_id(struct amdgpu_device *adev) 42 { 43 u32 tmp; 44 45 tmp = RREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_DEV0_EPF0_STRAP0); 46 tmp = REG_GET_FIELD(tmp, RCC_STRAP0_RCC_DEV0_EPF0_STRAP0, STRAP_ATI_REV_ID_DEV0_F0); 47 48 return tmp; 49 } 50 51 static void nbio_v7_9_mc_access_enable(struct amdgpu_device *adev, bool enable) 52 { 53 if (enable) 54 WREG32_SOC15(NBIO, 0, regBIF_BX0_BIF_FB_EN, 55 BIF_BX0_BIF_FB_EN__FB_READ_EN_MASK | BIF_BX0_BIF_FB_EN__FB_WRITE_EN_MASK); 56 else 57 WREG32_SOC15(NBIO, 0, regBIF_BX0_BIF_FB_EN, 0); 58 } 59 60 static u32 nbio_v7_9_get_memsize(struct amdgpu_device *adev) 61 { 62 return RREG32_SOC15(NBIO, 0, regRCC_DEV0_EPF0_RCC_CONFIG_MEMSIZE); 63 } 64 65 static void nbio_v7_9_sdma_doorbell_range(struct amdgpu_device *adev, int instance, 66 bool use_doorbell, int doorbell_index, int doorbell_size) 67 { 68 u32 doorbell_range = 0, doorbell_ctrl = 0; 69 70 doorbell_range = 71 REG_SET_FIELD(doorbell_range, DOORBELL0_CTRL_ENTRY_0, 72 BIF_DOORBELL0_RANGE_OFFSET_ENTRY, doorbell_index); 73 doorbell_range = 74 REG_SET_FIELD(doorbell_range, DOORBELL0_CTRL_ENTRY_0, 75 BIF_DOORBELL0_RANGE_SIZE_ENTRY, doorbell_size); 76 doorbell_ctrl = 77 REG_SET_FIELD(doorbell_ctrl, S2A_DOORBELL_ENTRY_1_CTRL, 78 S2A_DOORBELL_PORT1_ENABLE, 1); 79 doorbell_ctrl = 80 REG_SET_FIELD(doorbell_ctrl, S2A_DOORBELL_ENTRY_1_CTRL, 81 S2A_DOORBELL_PORT1_RANGE_SIZE, doorbell_size); 82 83 switch (instance) { 84 case 0: 85 WREG32_SOC15(NBIO, 0, regDOORBELL0_CTRL_ENTRY_1, doorbell_range); 86 87 doorbell_ctrl = REG_SET_FIELD(doorbell_ctrl, 88 S2A_DOORBELL_ENTRY_1_CTRL, 89 S2A_DOORBELL_PORT1_AWID, 0xe); 90 doorbell_ctrl = REG_SET_FIELD(doorbell_ctrl, 91 S2A_DOORBELL_ENTRY_1_CTRL, 92 S2A_DOORBELL_PORT1_RANGE_OFFSET, 0xe); 93 doorbell_ctrl = REG_SET_FIELD(doorbell_ctrl, 94 S2A_DOORBELL_ENTRY_1_CTRL, 95 S2A_DOORBELL_PORT1_AWADDR_31_28_VALUE, 96 0x1); 97 WREG32_SOC15(NBIO, 0, regS2A_DOORBELL_ENTRY_1_CTRL, doorbell_ctrl); 98 break; 99 case 1: 100 WREG32_SOC15(NBIO, 0, regDOORBELL0_CTRL_ENTRY_2, doorbell_range); 101 102 doorbell_ctrl = REG_SET_FIELD(doorbell_ctrl, 103 S2A_DOORBELL_ENTRY_1_CTRL, 104 S2A_DOORBELL_PORT1_AWID, 0x8); 105 doorbell_ctrl = REG_SET_FIELD(doorbell_ctrl, 106 S2A_DOORBELL_ENTRY_1_CTRL, 107 S2A_DOORBELL_PORT1_RANGE_OFFSET, 0x8); 108 doorbell_ctrl = REG_SET_FIELD(doorbell_ctrl, 109 S2A_DOORBELL_ENTRY_1_CTRL, 110 S2A_DOORBELL_PORT1_AWADDR_31_28_VALUE, 111 0x2); 112 WREG32_SOC15(NBIO, 0, regS2A_DOORBELL_ENTRY_2_CTRL, doorbell_ctrl); 113 break; 114 case 2: 115 WREG32_SOC15(NBIO, 0, regDOORBELL0_CTRL_ENTRY_3, doorbell_range); 116 117 doorbell_ctrl = REG_SET_FIELD(doorbell_ctrl, 118 S2A_DOORBELL_ENTRY_1_CTRL, 119 S2A_DOORBELL_PORT1_AWID, 0x9); 120 doorbell_ctrl = REG_SET_FIELD(doorbell_ctrl, 121 S2A_DOORBELL_ENTRY_1_CTRL, 122 S2A_DOORBELL_PORT1_RANGE_OFFSET, 0x9); 123 doorbell_ctrl = REG_SET_FIELD(doorbell_ctrl, 124 S2A_DOORBELL_ENTRY_1_CTRL, 125 S2A_DOORBELL_PORT1_AWADDR_31_28_VALUE, 126 0x8); 127 WREG32_SOC15(NBIO, 0, regS2A_DOORBELL_ENTRY_5_CTRL, doorbell_ctrl); 128 break; 129 case 3: 130 WREG32_SOC15(NBIO, 0, regDOORBELL0_CTRL_ENTRY_4, doorbell_range); 131 132 doorbell_ctrl = REG_SET_FIELD(doorbell_ctrl, 133 S2A_DOORBELL_ENTRY_1_CTRL, 134 S2A_DOORBELL_PORT1_AWID, 0xa); 135 doorbell_ctrl = REG_SET_FIELD(doorbell_ctrl, 136 S2A_DOORBELL_ENTRY_1_CTRL, 137 S2A_DOORBELL_PORT1_RANGE_OFFSET, 0xa); 138 doorbell_ctrl = REG_SET_FIELD(doorbell_ctrl, 139 S2A_DOORBELL_ENTRY_1_CTRL, 140 S2A_DOORBELL_PORT1_AWADDR_31_28_VALUE, 141 0x9); 142 WREG32_SOC15(NBIO, 0, regS2A_DOORBELL_ENTRY_6_CTRL, doorbell_ctrl); 143 break; 144 default: 145 break; 146 }; 147 148 return; 149 } 150 151 static void nbio_v7_9_vcn_doorbell_range(struct amdgpu_device *adev, bool use_doorbell, 152 int doorbell_index, int instance) 153 { 154 u32 doorbell_range = 0, doorbell_ctrl = 0; 155 156 if (use_doorbell) { 157 doorbell_range = REG_SET_FIELD(doorbell_range, 158 DOORBELL0_CTRL_ENTRY_0, 159 BIF_DOORBELL0_RANGE_OFFSET_ENTRY, 160 doorbell_index); 161 doorbell_range = REG_SET_FIELD(doorbell_range, 162 DOORBELL0_CTRL_ENTRY_0, 163 BIF_DOORBELL0_RANGE_SIZE_ENTRY, 164 0x8); 165 166 doorbell_ctrl = REG_SET_FIELD(doorbell_ctrl, 167 S2A_DOORBELL_ENTRY_1_CTRL, 168 S2A_DOORBELL_PORT1_ENABLE, 1); 169 doorbell_ctrl = REG_SET_FIELD(doorbell_ctrl, 170 S2A_DOORBELL_ENTRY_1_CTRL, 171 S2A_DOORBELL_PORT1_AWID, 0x4); 172 doorbell_ctrl = REG_SET_FIELD(doorbell_ctrl, 173 S2A_DOORBELL_ENTRY_1_CTRL, 174 S2A_DOORBELL_PORT1_RANGE_OFFSET, 0x4); 175 doorbell_ctrl = REG_SET_FIELD(doorbell_ctrl, 176 S2A_DOORBELL_ENTRY_1_CTRL, 177 S2A_DOORBELL_PORT1_RANGE_SIZE, 0x8); 178 doorbell_ctrl = REG_SET_FIELD(doorbell_ctrl, 179 S2A_DOORBELL_ENTRY_1_CTRL, 180 S2A_DOORBELL_PORT1_AWADDR_31_28_VALUE, 0x4); 181 } else { 182 doorbell_range = REG_SET_FIELD(doorbell_range, 183 DOORBELL0_CTRL_ENTRY_0, 184 BIF_DOORBELL0_RANGE_SIZE_ENTRY, 0); 185 doorbell_ctrl = REG_SET_FIELD(doorbell_ctrl, 186 S2A_DOORBELL_ENTRY_1_CTRL, 187 S2A_DOORBELL_PORT1_RANGE_SIZE, 0); 188 } 189 190 WREG32_SOC15(NBIO, 0, regDOORBELL0_CTRL_ENTRY_17, doorbell_range); 191 WREG32_SOC15(NBIO, 0, regS2A_DOORBELL_ENTRY_4_CTRL, doorbell_ctrl); 192 } 193 194 static void nbio_v7_9_enable_doorbell_aperture(struct amdgpu_device *adev, 195 bool enable) 196 { 197 /* Enable to allow doorbell pass thru on pre-silicon bare-metal */ 198 WREG32_SOC15(NBIO, 0, regBIFC_DOORBELL_ACCESS_EN_PF, 0xfffff); 199 WREG32_FIELD15_PREREG(NBIO, 0, RCC_DEV0_EPF0_RCC_DOORBELL_APER_EN, 200 BIF_DOORBELL_APER_EN, enable ? 1 : 0); 201 } 202 203 static void nbio_v7_9_enable_doorbell_selfring_aperture(struct amdgpu_device *adev, 204 bool enable) 205 { 206 u32 tmp = 0; 207 208 if (enable) { 209 tmp = REG_SET_FIELD(tmp, BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL, 210 DOORBELL_SELFRING_GPA_APER_EN, 1) | 211 REG_SET_FIELD(tmp, BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL, 212 DOORBELL_SELFRING_GPA_APER_MODE, 1) | 213 REG_SET_FIELD(tmp, BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL, 214 DOORBELL_SELFRING_GPA_APER_SIZE, 0); 215 216 WREG32_SOC15(NBIO, 0, regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW, 217 lower_32_bits(adev->doorbell.base)); 218 WREG32_SOC15(NBIO, 0, regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH, 219 upper_32_bits(adev->doorbell.base)); 220 } 221 222 WREG32_SOC15(NBIO, 0, regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL, tmp); 223 } 224 225 static void nbio_v7_9_ih_doorbell_range(struct amdgpu_device *adev, 226 bool use_doorbell, int doorbell_index) 227 { 228 u32 ih_doorbell_range = 0, ih_doorbell_ctrl = 0; 229 230 if (use_doorbell) { 231 ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, 232 DOORBELL0_CTRL_ENTRY_0, 233 BIF_DOORBELL0_RANGE_OFFSET_ENTRY, 234 doorbell_index); 235 ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, 236 DOORBELL0_CTRL_ENTRY_0, 237 BIF_DOORBELL0_RANGE_SIZE_ENTRY, 238 0x4); 239 240 ih_doorbell_ctrl = REG_SET_FIELD(ih_doorbell_ctrl, 241 S2A_DOORBELL_ENTRY_1_CTRL, 242 S2A_DOORBELL_PORT1_ENABLE, 1); 243 ih_doorbell_ctrl = REG_SET_FIELD(ih_doorbell_ctrl, 244 S2A_DOORBELL_ENTRY_1_CTRL, 245 S2A_DOORBELL_PORT1_AWID, 0); 246 ih_doorbell_ctrl = REG_SET_FIELD(ih_doorbell_ctrl, 247 S2A_DOORBELL_ENTRY_1_CTRL, 248 S2A_DOORBELL_PORT1_RANGE_OFFSET, 0); 249 ih_doorbell_ctrl = REG_SET_FIELD(ih_doorbell_ctrl, 250 S2A_DOORBELL_ENTRY_1_CTRL, 251 S2A_DOORBELL_PORT1_RANGE_SIZE, 0x4); 252 ih_doorbell_ctrl = REG_SET_FIELD(ih_doorbell_ctrl, 253 S2A_DOORBELL_ENTRY_1_CTRL, 254 S2A_DOORBELL_PORT1_AWADDR_31_28_VALUE, 0); 255 } else { 256 ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, 257 DOORBELL0_CTRL_ENTRY_0, 258 BIF_DOORBELL0_RANGE_SIZE_ENTRY, 0); 259 ih_doorbell_ctrl = REG_SET_FIELD(ih_doorbell_ctrl, 260 S2A_DOORBELL_ENTRY_1_CTRL, 261 S2A_DOORBELL_PORT1_RANGE_SIZE, 0); 262 } 263 264 WREG32_SOC15(NBIO, 0, regDOORBELL0_CTRL_ENTRY_0, ih_doorbell_range); 265 WREG32_SOC15(NBIO, 0, regS2A_DOORBELL_ENTRY_3_CTRL, ih_doorbell_ctrl); 266 } 267 268 269 static void nbio_v7_9_update_medium_grain_clock_gating(struct amdgpu_device *adev, 270 bool enable) 271 { 272 } 273 274 static void nbio_v7_9_update_medium_grain_light_sleep(struct amdgpu_device *adev, 275 bool enable) 276 { 277 } 278 279 static void nbio_v7_9_get_clockgating_state(struct amdgpu_device *adev, 280 u64 *flags) 281 { 282 } 283 284 static void nbio_v7_9_ih_control(struct amdgpu_device *adev) 285 { 286 u32 interrupt_cntl; 287 288 /* setup interrupt control */ 289 WREG32_SOC15(NBIO, 0, regBIF_BX0_INTERRUPT_CNTL2, adev->dummy_page_addr >> 8); 290 interrupt_cntl = RREG32_SOC15(NBIO, 0, regBIF_BX0_INTERRUPT_CNTL); 291 /* INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=0 - dummy read disabled with msi, enabled without msi 292 * INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=1 - dummy read controlled by IH_DUMMY_RD_EN 293 */ 294 interrupt_cntl = 295 REG_SET_FIELD(interrupt_cntl, BIF_BX0_INTERRUPT_CNTL, IH_DUMMY_RD_OVERRIDE, 0); 296 /* INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN_MASK=1 if ring is in non-cacheable memory, e.g., vram */ 297 interrupt_cntl = 298 REG_SET_FIELD(interrupt_cntl, BIF_BX0_INTERRUPT_CNTL, IH_REQ_NONSNOOP_EN, 0); 299 WREG32_SOC15(NBIO, 0, regBIF_BX0_INTERRUPT_CNTL, interrupt_cntl); 300 } 301 302 static u32 nbio_v7_9_get_hdp_flush_req_offset(struct amdgpu_device *adev) 303 { 304 return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX_PF0_GPU_HDP_FLUSH_REQ); 305 } 306 307 static u32 nbio_v7_9_get_hdp_flush_done_offset(struct amdgpu_device *adev) 308 { 309 return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX_PF0_GPU_HDP_FLUSH_DONE); 310 } 311 312 static u32 nbio_v7_9_get_pcie_index_offset(struct amdgpu_device *adev) 313 { 314 return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX0_PCIE_INDEX2); 315 } 316 317 static u32 nbio_v7_9_get_pcie_data_offset(struct amdgpu_device *adev) 318 { 319 return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX0_PCIE_DATA2); 320 } 321 322 const struct nbio_hdp_flush_reg nbio_v7_9_hdp_flush_reg = { 323 .ref_and_mask_cp0 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP0_MASK, 324 .ref_and_mask_cp1 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP1_MASK, 325 .ref_and_mask_cp2 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP2_MASK, 326 .ref_and_mask_cp3 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP3_MASK, 327 .ref_and_mask_cp4 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP4_MASK, 328 .ref_and_mask_cp5 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP5_MASK, 329 .ref_and_mask_cp6 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP6_MASK, 330 .ref_and_mask_cp7 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP7_MASK, 331 .ref_and_mask_cp8 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP8_MASK, 332 .ref_and_mask_cp9 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP9_MASK, 333 .ref_and_mask_sdma0 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__SDMA0_MASK, 334 .ref_and_mask_sdma1 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__SDMA1_MASK, 335 .ref_and_mask_sdma2 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG0_MASK, 336 .ref_and_mask_sdma3 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG1_MASK, 337 .ref_and_mask_sdma4 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG2_MASK, 338 .ref_and_mask_sdma5 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG3_MASK, 339 .ref_and_mask_sdma6 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG4_MASK, 340 .ref_and_mask_sdma7 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG5_MASK, 341 }; 342 343 static void nbio_v7_9_enable_doorbell_interrupt(struct amdgpu_device *adev, 344 bool enable) 345 { 346 WREG32_FIELD15_PREREG(NBIO, 0, BIF_BX0_BIF_DOORBELL_INT_CNTL, 347 DOORBELL_INTERRUPT_DISABLE, enable ? 0 : 1); 348 } 349 350 const struct amdgpu_nbio_funcs nbio_v7_9_funcs = { 351 .get_hdp_flush_req_offset = nbio_v7_9_get_hdp_flush_req_offset, 352 .get_hdp_flush_done_offset = nbio_v7_9_get_hdp_flush_done_offset, 353 .get_pcie_index_offset = nbio_v7_9_get_pcie_index_offset, 354 .get_pcie_data_offset = nbio_v7_9_get_pcie_data_offset, 355 .get_rev_id = nbio_v7_9_get_rev_id, 356 .mc_access_enable = nbio_v7_9_mc_access_enable, 357 .get_memsize = nbio_v7_9_get_memsize, 358 .sdma_doorbell_range = nbio_v7_9_sdma_doorbell_range, 359 .vcn_doorbell_range = nbio_v7_9_vcn_doorbell_range, 360 .enable_doorbell_aperture = nbio_v7_9_enable_doorbell_aperture, 361 .enable_doorbell_selfring_aperture = nbio_v7_9_enable_doorbell_selfring_aperture, 362 .ih_doorbell_range = nbio_v7_9_ih_doorbell_range, 363 .enable_doorbell_interrupt = nbio_v7_9_enable_doorbell_interrupt, 364 .update_medium_grain_clock_gating = nbio_v7_9_update_medium_grain_clock_gating, 365 .update_medium_grain_light_sleep = nbio_v7_9_update_medium_grain_light_sleep, 366 .get_clockgating_state = nbio_v7_9_get_clockgating_state, 367 .ih_control = nbio_v7_9_ih_control, 368 .remap_hdp_registers = nbio_v7_9_remap_hdp_registers, 369 }; 370