1 /* 2 * Copyright 2022 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include "amdgpu.h" 24 #include "amdgpu_atombios.h" 25 #include "nbio_v7_9.h" 26 #include "amdgpu_ras.h" 27 28 #include "nbio/nbio_7_9_0_offset.h" 29 #include "nbio/nbio_7_9_0_sh_mask.h" 30 #include "ivsrcid/nbio/irqsrcs_nbif_7_4.h" 31 #include <uapi/linux/kfd_ioctl.h> 32 33 #define NPS_MODE_MASK 0x000000FFL 34 35 static void nbio_v7_9_remap_hdp_registers(struct amdgpu_device *adev) 36 { 37 WREG32_SOC15(NBIO, 0, regBIF_BX0_REMAP_HDP_MEM_FLUSH_CNTL, 38 adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL); 39 WREG32_SOC15(NBIO, 0, regBIF_BX0_REMAP_HDP_REG_FLUSH_CNTL, 40 adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_REG_FLUSH_CNTL); 41 } 42 43 static u32 nbio_v7_9_get_rev_id(struct amdgpu_device *adev) 44 { 45 u32 tmp; 46 47 tmp = RREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_DEV0_EPF0_STRAP0); 48 tmp = REG_GET_FIELD(tmp, RCC_STRAP0_RCC_DEV0_EPF0_STRAP0, STRAP_ATI_REV_ID_DEV0_F0); 49 50 return tmp; 51 } 52 53 static void nbio_v7_9_mc_access_enable(struct amdgpu_device *adev, bool enable) 54 { 55 if (enable) 56 WREG32_SOC15(NBIO, 0, regBIF_BX0_BIF_FB_EN, 57 BIF_BX0_BIF_FB_EN__FB_READ_EN_MASK | BIF_BX0_BIF_FB_EN__FB_WRITE_EN_MASK); 58 else 59 WREG32_SOC15(NBIO, 0, regBIF_BX0_BIF_FB_EN, 0); 60 } 61 62 static u32 nbio_v7_9_get_memsize(struct amdgpu_device *adev) 63 { 64 return RREG32_SOC15(NBIO, 0, regRCC_DEV0_EPF0_RCC_CONFIG_MEMSIZE); 65 } 66 67 static void nbio_v7_9_sdma_doorbell_range(struct amdgpu_device *adev, int instance, 68 bool use_doorbell, int doorbell_index, int doorbell_size) 69 { 70 u32 doorbell_range = 0, doorbell_ctrl = 0; 71 int aid_id, dev_inst; 72 73 dev_inst = GET_INST(SDMA0, instance); 74 aid_id = adev->sdma.instance[instance].aid_id; 75 76 if (use_doorbell == false) 77 return; 78 79 doorbell_range = 80 REG_SET_FIELD(doorbell_range, DOORBELL0_CTRL_ENTRY_0, 81 BIF_DOORBELL0_RANGE_OFFSET_ENTRY, doorbell_index); 82 doorbell_range = 83 REG_SET_FIELD(doorbell_range, DOORBELL0_CTRL_ENTRY_0, 84 BIF_DOORBELL0_RANGE_SIZE_ENTRY, doorbell_size); 85 doorbell_ctrl = 86 REG_SET_FIELD(doorbell_ctrl, S2A_DOORBELL_ENTRY_1_CTRL, 87 S2A_DOORBELL_PORT1_ENABLE, 1); 88 doorbell_ctrl = 89 REG_SET_FIELD(doorbell_ctrl, S2A_DOORBELL_ENTRY_1_CTRL, 90 S2A_DOORBELL_PORT1_RANGE_SIZE, doorbell_size); 91 92 switch (dev_inst % adev->sdma.num_inst_per_aid) { 93 case 0: 94 WREG32_SOC15_OFFSET(NBIO, 0, regDOORBELL0_CTRL_ENTRY_1, 95 4 * aid_id, doorbell_range); 96 97 doorbell_ctrl = REG_SET_FIELD(doorbell_ctrl, 98 S2A_DOORBELL_ENTRY_1_CTRL, 99 S2A_DOORBELL_PORT1_AWID, 0xe); 100 doorbell_ctrl = REG_SET_FIELD(doorbell_ctrl, 101 S2A_DOORBELL_ENTRY_1_CTRL, 102 S2A_DOORBELL_PORT1_RANGE_OFFSET, 0xe); 103 doorbell_ctrl = REG_SET_FIELD(doorbell_ctrl, 104 S2A_DOORBELL_ENTRY_1_CTRL, 105 S2A_DOORBELL_PORT1_AWADDR_31_28_VALUE, 106 0x1); 107 WREG32_SOC15_EXT(NBIO, aid_id, regS2A_DOORBELL_ENTRY_1_CTRL, 108 aid_id, doorbell_ctrl); 109 break; 110 case 1: 111 WREG32_SOC15_OFFSET(NBIO, 0, regDOORBELL0_CTRL_ENTRY_2, 112 4 * aid_id, doorbell_range); 113 114 doorbell_ctrl = REG_SET_FIELD(doorbell_ctrl, 115 S2A_DOORBELL_ENTRY_1_CTRL, 116 S2A_DOORBELL_PORT1_AWID, 0x8); 117 doorbell_ctrl = REG_SET_FIELD(doorbell_ctrl, 118 S2A_DOORBELL_ENTRY_1_CTRL, 119 S2A_DOORBELL_PORT1_RANGE_OFFSET, 0x8); 120 doorbell_ctrl = REG_SET_FIELD(doorbell_ctrl, 121 S2A_DOORBELL_ENTRY_1_CTRL, 122 S2A_DOORBELL_PORT1_AWADDR_31_28_VALUE, 123 0x2); 124 WREG32_SOC15_EXT(NBIO, aid_id, regS2A_DOORBELL_ENTRY_2_CTRL, 125 aid_id, doorbell_ctrl); 126 break; 127 case 2: 128 WREG32_SOC15_OFFSET(NBIO, 0, regDOORBELL0_CTRL_ENTRY_3, 129 4 * aid_id, doorbell_range); 130 131 doorbell_ctrl = REG_SET_FIELD(doorbell_ctrl, 132 S2A_DOORBELL_ENTRY_1_CTRL, 133 S2A_DOORBELL_PORT1_AWID, 0x9); 134 doorbell_ctrl = REG_SET_FIELD(doorbell_ctrl, 135 S2A_DOORBELL_ENTRY_1_CTRL, 136 S2A_DOORBELL_PORT1_RANGE_OFFSET, 0x9); 137 doorbell_ctrl = REG_SET_FIELD(doorbell_ctrl, 138 S2A_DOORBELL_ENTRY_1_CTRL, 139 S2A_DOORBELL_PORT1_AWADDR_31_28_VALUE, 140 0x8); 141 WREG32_SOC15_EXT(NBIO, aid_id, regS2A_DOORBELL_ENTRY_5_CTRL, 142 aid_id, doorbell_ctrl); 143 break; 144 case 3: 145 WREG32_SOC15_OFFSET(NBIO, 0, regDOORBELL0_CTRL_ENTRY_4, 146 4 * aid_id, doorbell_range); 147 148 doorbell_ctrl = REG_SET_FIELD(doorbell_ctrl, 149 S2A_DOORBELL_ENTRY_1_CTRL, 150 S2A_DOORBELL_PORT1_AWID, 0xa); 151 doorbell_ctrl = REG_SET_FIELD(doorbell_ctrl, 152 S2A_DOORBELL_ENTRY_1_CTRL, 153 S2A_DOORBELL_PORT1_RANGE_OFFSET, 0xa); 154 doorbell_ctrl = REG_SET_FIELD(doorbell_ctrl, 155 S2A_DOORBELL_ENTRY_1_CTRL, 156 S2A_DOORBELL_PORT1_AWADDR_31_28_VALUE, 157 0x9); 158 WREG32_SOC15_EXT(NBIO, aid_id, regS2A_DOORBELL_ENTRY_6_CTRL, 159 aid_id, doorbell_ctrl); 160 break; 161 default: 162 break; 163 } 164 165 return; 166 } 167 168 static void nbio_v7_9_vcn_doorbell_range(struct amdgpu_device *adev, bool use_doorbell, 169 int doorbell_index, int instance) 170 { 171 u32 doorbell_range = 0, doorbell_ctrl = 0; 172 u32 aid_id = instance; 173 174 if (use_doorbell) { 175 doorbell_range = REG_SET_FIELD(doorbell_range, 176 DOORBELL0_CTRL_ENTRY_0, 177 BIF_DOORBELL0_RANGE_OFFSET_ENTRY, 178 doorbell_index); 179 doorbell_range = REG_SET_FIELD(doorbell_range, 180 DOORBELL0_CTRL_ENTRY_0, 181 BIF_DOORBELL0_RANGE_SIZE_ENTRY, 182 0x9); 183 if (aid_id) 184 doorbell_range = REG_SET_FIELD(doorbell_range, 185 DOORBELL0_CTRL_ENTRY_0, 186 DOORBELL0_FENCE_ENABLE_ENTRY, 187 0x4); 188 189 doorbell_ctrl = REG_SET_FIELD(doorbell_ctrl, 190 S2A_DOORBELL_ENTRY_1_CTRL, 191 S2A_DOORBELL_PORT1_ENABLE, 1); 192 doorbell_ctrl = REG_SET_FIELD(doorbell_ctrl, 193 S2A_DOORBELL_ENTRY_1_CTRL, 194 S2A_DOORBELL_PORT1_AWID, 0x4); 195 doorbell_ctrl = REG_SET_FIELD(doorbell_ctrl, 196 S2A_DOORBELL_ENTRY_1_CTRL, 197 S2A_DOORBELL_PORT1_RANGE_OFFSET, 0x4); 198 doorbell_ctrl = REG_SET_FIELD(doorbell_ctrl, 199 S2A_DOORBELL_ENTRY_1_CTRL, 200 S2A_DOORBELL_PORT1_RANGE_SIZE, 0x9); 201 doorbell_ctrl = REG_SET_FIELD(doorbell_ctrl, 202 S2A_DOORBELL_ENTRY_1_CTRL, 203 S2A_DOORBELL_PORT1_AWADDR_31_28_VALUE, 0x4); 204 205 WREG32_SOC15_OFFSET(NBIO, 0, regDOORBELL0_CTRL_ENTRY_17, 206 aid_id, doorbell_range); 207 WREG32_SOC15_EXT(NBIO, aid_id, regS2A_DOORBELL_ENTRY_4_CTRL, 208 aid_id, doorbell_ctrl); 209 } else { 210 doorbell_range = REG_SET_FIELD(doorbell_range, 211 DOORBELL0_CTRL_ENTRY_0, 212 BIF_DOORBELL0_RANGE_SIZE_ENTRY, 0); 213 doorbell_ctrl = REG_SET_FIELD(doorbell_ctrl, 214 S2A_DOORBELL_ENTRY_1_CTRL, 215 S2A_DOORBELL_PORT1_RANGE_SIZE, 0); 216 217 WREG32_SOC15_OFFSET(NBIO, 0, regDOORBELL0_CTRL_ENTRY_17, 218 aid_id, doorbell_range); 219 WREG32_SOC15_EXT(NBIO, aid_id, regS2A_DOORBELL_ENTRY_4_CTRL, 220 aid_id, doorbell_ctrl); 221 } 222 } 223 224 static void nbio_v7_9_enable_doorbell_aperture(struct amdgpu_device *adev, 225 bool enable) 226 { 227 /* Enable to allow doorbell pass thru on pre-silicon bare-metal */ 228 WREG32_SOC15(NBIO, 0, regBIFC_DOORBELL_ACCESS_EN_PF, 0xfffff); 229 WREG32_FIELD15_PREREG(NBIO, 0, RCC_DEV0_EPF0_RCC_DOORBELL_APER_EN, 230 BIF_DOORBELL_APER_EN, enable ? 1 : 0); 231 } 232 233 static void nbio_v7_9_enable_doorbell_selfring_aperture(struct amdgpu_device *adev, 234 bool enable) 235 { 236 u32 tmp = 0; 237 238 if (enable) { 239 tmp = REG_SET_FIELD(tmp, BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL, 240 DOORBELL_SELFRING_GPA_APER_EN, 1) | 241 REG_SET_FIELD(tmp, BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL, 242 DOORBELL_SELFRING_GPA_APER_MODE, 1) | 243 REG_SET_FIELD(tmp, BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL, 244 DOORBELL_SELFRING_GPA_APER_SIZE, 0); 245 246 WREG32_SOC15(NBIO, 0, regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW, 247 lower_32_bits(adev->doorbell.base)); 248 WREG32_SOC15(NBIO, 0, regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH, 249 upper_32_bits(adev->doorbell.base)); 250 } 251 252 WREG32_SOC15(NBIO, 0, regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL, tmp); 253 } 254 255 static void nbio_v7_9_ih_doorbell_range(struct amdgpu_device *adev, 256 bool use_doorbell, int doorbell_index) 257 { 258 u32 ih_doorbell_range = 0, ih_doorbell_ctrl = 0; 259 260 if (use_doorbell) { 261 ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, 262 DOORBELL0_CTRL_ENTRY_0, 263 BIF_DOORBELL0_RANGE_OFFSET_ENTRY, 264 doorbell_index); 265 ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, 266 DOORBELL0_CTRL_ENTRY_0, 267 BIF_DOORBELL0_RANGE_SIZE_ENTRY, 268 0x8); 269 270 ih_doorbell_ctrl = REG_SET_FIELD(ih_doorbell_ctrl, 271 S2A_DOORBELL_ENTRY_1_CTRL, 272 S2A_DOORBELL_PORT1_ENABLE, 1); 273 ih_doorbell_ctrl = REG_SET_FIELD(ih_doorbell_ctrl, 274 S2A_DOORBELL_ENTRY_1_CTRL, 275 S2A_DOORBELL_PORT1_AWID, 0); 276 ih_doorbell_ctrl = REG_SET_FIELD(ih_doorbell_ctrl, 277 S2A_DOORBELL_ENTRY_1_CTRL, 278 S2A_DOORBELL_PORT1_RANGE_OFFSET, 0); 279 ih_doorbell_ctrl = REG_SET_FIELD(ih_doorbell_ctrl, 280 S2A_DOORBELL_ENTRY_1_CTRL, 281 S2A_DOORBELL_PORT1_RANGE_SIZE, 0x8); 282 ih_doorbell_ctrl = REG_SET_FIELD(ih_doorbell_ctrl, 283 S2A_DOORBELL_ENTRY_1_CTRL, 284 S2A_DOORBELL_PORT1_AWADDR_31_28_VALUE, 0); 285 } else { 286 ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, 287 DOORBELL0_CTRL_ENTRY_0, 288 BIF_DOORBELL0_RANGE_SIZE_ENTRY, 0); 289 ih_doorbell_ctrl = REG_SET_FIELD(ih_doorbell_ctrl, 290 S2A_DOORBELL_ENTRY_1_CTRL, 291 S2A_DOORBELL_PORT1_RANGE_SIZE, 0); 292 } 293 294 WREG32_SOC15(NBIO, 0, regDOORBELL0_CTRL_ENTRY_0, ih_doorbell_range); 295 WREG32_SOC15(NBIO, 0, regS2A_DOORBELL_ENTRY_3_CTRL, ih_doorbell_ctrl); 296 } 297 298 299 static void nbio_v7_9_update_medium_grain_clock_gating(struct amdgpu_device *adev, 300 bool enable) 301 { 302 } 303 304 static void nbio_v7_9_update_medium_grain_light_sleep(struct amdgpu_device *adev, 305 bool enable) 306 { 307 } 308 309 static void nbio_v7_9_get_clockgating_state(struct amdgpu_device *adev, 310 u64 *flags) 311 { 312 } 313 314 static void nbio_v7_9_ih_control(struct amdgpu_device *adev) 315 { 316 u32 interrupt_cntl; 317 318 /* setup interrupt control */ 319 WREG32_SOC15(NBIO, 0, regBIF_BX0_INTERRUPT_CNTL2, adev->dummy_page_addr >> 8); 320 interrupt_cntl = RREG32_SOC15(NBIO, 0, regBIF_BX0_INTERRUPT_CNTL); 321 /* INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=0 - dummy read disabled with msi, enabled without msi 322 * INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=1 - dummy read controlled by IH_DUMMY_RD_EN 323 */ 324 interrupt_cntl = 325 REG_SET_FIELD(interrupt_cntl, BIF_BX0_INTERRUPT_CNTL, IH_DUMMY_RD_OVERRIDE, 0); 326 /* INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN_MASK=1 if ring is in non-cacheable memory, e.g., vram */ 327 interrupt_cntl = 328 REG_SET_FIELD(interrupt_cntl, BIF_BX0_INTERRUPT_CNTL, IH_REQ_NONSNOOP_EN, 0); 329 WREG32_SOC15(NBIO, 0, regBIF_BX0_INTERRUPT_CNTL, interrupt_cntl); 330 } 331 332 static u32 nbio_v7_9_get_hdp_flush_req_offset(struct amdgpu_device *adev) 333 { 334 return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX_PF0_GPU_HDP_FLUSH_REQ); 335 } 336 337 static u32 nbio_v7_9_get_hdp_flush_done_offset(struct amdgpu_device *adev) 338 { 339 return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX_PF0_GPU_HDP_FLUSH_DONE); 340 } 341 342 static u32 nbio_v7_9_get_pcie_index_offset(struct amdgpu_device *adev) 343 { 344 return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX0_PCIE_INDEX2); 345 } 346 347 static u32 nbio_v7_9_get_pcie_data_offset(struct amdgpu_device *adev) 348 { 349 return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX0_PCIE_DATA2); 350 } 351 352 static u32 nbio_v7_9_get_pcie_index_hi_offset(struct amdgpu_device *adev) 353 { 354 return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX0_PCIE_INDEX2_HI); 355 } 356 357 const struct nbio_hdp_flush_reg nbio_v7_9_hdp_flush_reg = { 358 .ref_and_mask_cp0 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP0_MASK, 359 .ref_and_mask_cp1 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP1_MASK, 360 .ref_and_mask_cp2 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP2_MASK, 361 .ref_and_mask_cp3 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP3_MASK, 362 .ref_and_mask_cp4 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP4_MASK, 363 .ref_and_mask_cp5 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP5_MASK, 364 .ref_and_mask_cp6 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP6_MASK, 365 .ref_and_mask_cp7 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP7_MASK, 366 .ref_and_mask_cp8 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP8_MASK, 367 .ref_and_mask_cp9 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP9_MASK, 368 .ref_and_mask_sdma0 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__SDMA0_MASK, 369 .ref_and_mask_sdma1 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__SDMA1_MASK, 370 .ref_and_mask_sdma2 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG0_MASK, 371 .ref_and_mask_sdma3 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG1_MASK, 372 .ref_and_mask_sdma4 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG2_MASK, 373 .ref_and_mask_sdma5 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG3_MASK, 374 .ref_and_mask_sdma6 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG4_MASK, 375 .ref_and_mask_sdma7 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG5_MASK, 376 }; 377 378 static void nbio_v7_9_enable_doorbell_interrupt(struct amdgpu_device *adev, 379 bool enable) 380 { 381 WREG32_FIELD15_PREREG(NBIO, 0, BIF_BX0_BIF_DOORBELL_INT_CNTL, 382 DOORBELL_INTERRUPT_DISABLE, enable ? 0 : 1); 383 } 384 385 static int nbio_v7_9_get_compute_partition_mode(struct amdgpu_device *adev) 386 { 387 u32 tmp, px; 388 389 tmp = RREG32_SOC15(NBIO, 0, regBIF_BX_PF0_PARTITION_COMPUTE_STATUS); 390 px = REG_GET_FIELD(tmp, BIF_BX_PF0_PARTITION_COMPUTE_STATUS, 391 PARTITION_MODE); 392 393 return px; 394 } 395 396 static u32 nbio_v7_9_get_memory_partition_mode(struct amdgpu_device *adev, 397 u32 *supp_modes) 398 { 399 u32 tmp; 400 401 tmp = RREG32_SOC15(NBIO, 0, regBIF_BX_PF0_PARTITION_MEM_STATUS); 402 tmp = REG_GET_FIELD(tmp, BIF_BX_PF0_PARTITION_MEM_STATUS, NPS_MODE); 403 404 if (supp_modes) { 405 *supp_modes = 406 RREG32_SOC15(NBIO, 0, regBIF_BX_PF0_PARTITION_MEM_CAP); 407 } 408 409 return ffs(tmp); 410 } 411 412 static void nbio_v7_9_init_registers(struct amdgpu_device *adev) 413 { 414 u32 inst_mask; 415 int i; 416 417 WREG32_SOC15(NBIO, 0, regXCC_DOORBELL_FENCE, 418 0xff & ~(adev->gfx.xcc_mask)); 419 420 WREG32_SOC15(NBIO, 0, regBIFC_GFX_INT_MONITOR_MASK, 0x7ff); 421 422 inst_mask = adev->aid_mask & ~1U; 423 for_each_inst(i, inst_mask) { 424 WREG32_SOC15_EXT(NBIO, i, regXCC_DOORBELL_FENCE, i, 425 XCC_DOORBELL_FENCE__SHUB_SLV_MODE_MASK); 426 427 } 428 } 429 430 const struct amdgpu_nbio_funcs nbio_v7_9_funcs = { 431 .get_hdp_flush_req_offset = nbio_v7_9_get_hdp_flush_req_offset, 432 .get_hdp_flush_done_offset = nbio_v7_9_get_hdp_flush_done_offset, 433 .get_pcie_index_offset = nbio_v7_9_get_pcie_index_offset, 434 .get_pcie_data_offset = nbio_v7_9_get_pcie_data_offset, 435 .get_pcie_index_hi_offset = nbio_v7_9_get_pcie_index_hi_offset, 436 .get_rev_id = nbio_v7_9_get_rev_id, 437 .mc_access_enable = nbio_v7_9_mc_access_enable, 438 .get_memsize = nbio_v7_9_get_memsize, 439 .sdma_doorbell_range = nbio_v7_9_sdma_doorbell_range, 440 .vcn_doorbell_range = nbio_v7_9_vcn_doorbell_range, 441 .enable_doorbell_aperture = nbio_v7_9_enable_doorbell_aperture, 442 .enable_doorbell_selfring_aperture = nbio_v7_9_enable_doorbell_selfring_aperture, 443 .ih_doorbell_range = nbio_v7_9_ih_doorbell_range, 444 .enable_doorbell_interrupt = nbio_v7_9_enable_doorbell_interrupt, 445 .update_medium_grain_clock_gating = nbio_v7_9_update_medium_grain_clock_gating, 446 .update_medium_grain_light_sleep = nbio_v7_9_update_medium_grain_light_sleep, 447 .get_clockgating_state = nbio_v7_9_get_clockgating_state, 448 .ih_control = nbio_v7_9_ih_control, 449 .remap_hdp_registers = nbio_v7_9_remap_hdp_registers, 450 .get_compute_partition_mode = nbio_v7_9_get_compute_partition_mode, 451 .get_memory_partition_mode = nbio_v7_9_get_memory_partition_mode, 452 .init_registers = nbio_v7_9_init_registers, 453 }; 454