1 /* 2 * Copyright 2021 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include "amdgpu.h" 24 #include "amdgpu_atombios.h" 25 #include "nbio_v7_7.h" 26 27 #include "nbio/nbio_7_7_0_offset.h" 28 #include "nbio/nbio_7_7_0_sh_mask.h" 29 #include <uapi/linux/kfd_ioctl.h> 30 31 static u32 nbio_v7_7_get_rev_id(struct amdgpu_device *adev) 32 { 33 u32 tmp; 34 35 tmp = RREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_DEV0_EPF0_STRAP0); 36 37 tmp &= RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0_MASK; 38 tmp >>= RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0__SHIFT; 39 40 return tmp; 41 } 42 43 static void nbio_v7_7_mc_access_enable(struct amdgpu_device *adev, bool enable) 44 { 45 if (enable) 46 WREG32_SOC15(NBIO, 0, regBIF_BX1_BIF_FB_EN, 47 BIF_BX1_BIF_FB_EN__FB_READ_EN_MASK | 48 BIF_BX1_BIF_FB_EN__FB_WRITE_EN_MASK); 49 else 50 WREG32_SOC15(NBIO, 0, regBIF_BX1_BIF_FB_EN, 0); 51 } 52 53 static u32 nbio_v7_7_get_memsize(struct amdgpu_device *adev) 54 { 55 return RREG32_SOC15(NBIO, 0, regRCC_DEV0_EPF0_0_RCC_CONFIG_MEMSIZE); 56 } 57 58 static void nbio_v7_7_sdma_doorbell_range(struct amdgpu_device *adev, int instance, 59 bool use_doorbell, int doorbell_index, 60 int doorbell_size) 61 { 62 u32 reg = SOC15_REG_OFFSET(NBIO, 0, regGDC0_BIF_SDMA0_DOORBELL_RANGE); 63 u32 doorbell_range = RREG32_PCIE_PORT(reg); 64 65 if (use_doorbell) { 66 doorbell_range = REG_SET_FIELD(doorbell_range, 67 GDC0_BIF_SDMA0_DOORBELL_RANGE, 68 OFFSET, doorbell_index); 69 doorbell_range = REG_SET_FIELD(doorbell_range, 70 GDC0_BIF_SDMA0_DOORBELL_RANGE, 71 SIZE, doorbell_size); 72 } else { 73 doorbell_range = REG_SET_FIELD(doorbell_range, 74 GDC0_BIF_SDMA0_DOORBELL_RANGE, 75 SIZE, 0); 76 } 77 78 WREG32_PCIE_PORT(reg, doorbell_range); 79 } 80 81 static void nbio_v7_7_enable_doorbell_aperture(struct amdgpu_device *adev, 82 bool enable) 83 { 84 u32 reg; 85 86 reg = RREG32_SOC15(NBIO, 0, regRCC_DEV0_EPF0_0_RCC_DOORBELL_APER_EN); 87 reg = REG_SET_FIELD(reg, RCC_DEV0_EPF0_0_RCC_DOORBELL_APER_EN, 88 BIF_DOORBELL_APER_EN, enable ? 1 : 0); 89 90 WREG32_SOC15(NBIO, 0, regRCC_DEV0_EPF0_0_RCC_DOORBELL_APER_EN, reg); 91 } 92 93 static void nbio_v7_7_enable_doorbell_selfring_aperture(struct amdgpu_device *adev, 94 bool enable) 95 { 96 u32 tmp = 0; 97 98 if (enable) { 99 tmp = REG_SET_FIELD(tmp, BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL, 100 DOORBELL_SELFRING_GPA_APER_EN, 1) | 101 REG_SET_FIELD(tmp, BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL, 102 DOORBELL_SELFRING_GPA_APER_MODE, 1) | 103 REG_SET_FIELD(tmp, BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL, 104 DOORBELL_SELFRING_GPA_APER_SIZE, 0); 105 106 WREG32_SOC15(NBIO, 0, 107 regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW, 108 lower_32_bits(adev->doorbell.base)); 109 WREG32_SOC15(NBIO, 0, 110 regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH, 111 upper_32_bits(adev->doorbell.base)); 112 } 113 114 WREG32_SOC15(NBIO, 0, regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL, 115 tmp); 116 } 117 118 119 static void nbio_v7_7_ih_doorbell_range(struct amdgpu_device *adev, 120 bool use_doorbell, int doorbell_index) 121 { 122 u32 ih_doorbell_range = RREG32_SOC15(NBIO, 0, 123 regGDC0_BIF_IH_DOORBELL_RANGE); 124 125 if (use_doorbell) { 126 ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, 127 GDC0_BIF_IH_DOORBELL_RANGE, OFFSET, 128 doorbell_index); 129 ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, 130 GDC0_BIF_IH_DOORBELL_RANGE, SIZE, 131 2); 132 } else { 133 ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, 134 GDC0_BIF_IH_DOORBELL_RANGE, SIZE, 135 0); 136 } 137 138 WREG32_SOC15(NBIO, 0, regGDC0_BIF_IH_DOORBELL_RANGE, 139 ih_doorbell_range); 140 } 141 142 static void nbio_v7_7_ih_control(struct amdgpu_device *adev) 143 { 144 u32 interrupt_cntl; 145 146 /* setup interrupt control */ 147 WREG32_SOC15(NBIO, 0, regBIF_BX1_INTERRUPT_CNTL2, 148 adev->dummy_page_addr >> 8); 149 150 interrupt_cntl = RREG32_SOC15(NBIO, 0, regBIF_BX1_INTERRUPT_CNTL); 151 /* 152 * INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=0 - dummy read disabled with msi, enabled without msi 153 * INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=1 - dummy read controlled by IH_DUMMY_RD_EN 154 */ 155 interrupt_cntl = REG_SET_FIELD(interrupt_cntl, BIF_BX1_INTERRUPT_CNTL, 156 IH_DUMMY_RD_OVERRIDE, 0); 157 158 /* INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN_MASK=1 if ring is in non-cacheable memory, e.g., vram */ 159 interrupt_cntl = REG_SET_FIELD(interrupt_cntl, BIF_BX1_INTERRUPT_CNTL, 160 IH_REQ_NONSNOOP_EN, 0); 161 162 WREG32_SOC15(NBIO, 0, regBIF_BX1_INTERRUPT_CNTL, interrupt_cntl); 163 } 164 165 static u32 nbio_v7_7_get_hdp_flush_req_offset(struct amdgpu_device *adev) 166 { 167 return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX_PF0_GPU_HDP_FLUSH_REQ); 168 } 169 170 static u32 nbio_v7_7_get_hdp_flush_done_offset(struct amdgpu_device *adev) 171 { 172 return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX_PF0_GPU_HDP_FLUSH_DONE); 173 } 174 175 static u32 nbio_v7_7_get_pcie_index_offset(struct amdgpu_device *adev) 176 { 177 return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX0_PCIE_INDEX2); 178 } 179 180 static u32 nbio_v7_7_get_pcie_data_offset(struct amdgpu_device *adev) 181 { 182 return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX0_PCIE_DATA2); 183 } 184 185 static u32 nbio_v7_7_get_pcie_port_index_offset(struct amdgpu_device *adev) 186 { 187 return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX_PF0_RSMU_INDEX); 188 } 189 190 static u32 nbio_v7_7_get_pcie_port_data_offset(struct amdgpu_device *adev) 191 { 192 return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX_PF0_RSMU_DATA); 193 } 194 195 const struct nbio_hdp_flush_reg nbio_v7_7_hdp_flush_reg = { 196 .ref_and_mask_cp0 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP0_MASK, 197 .ref_and_mask_cp1 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP1_MASK, 198 .ref_and_mask_cp2 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP2_MASK, 199 .ref_and_mask_cp3 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP3_MASK, 200 .ref_and_mask_cp4 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP4_MASK, 201 .ref_and_mask_cp5 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP5_MASK, 202 .ref_and_mask_cp6 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP6_MASK, 203 .ref_and_mask_cp7 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP7_MASK, 204 .ref_and_mask_cp8 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP8_MASK, 205 .ref_and_mask_cp9 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP9_MASK, 206 .ref_and_mask_sdma0 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__SDMA0_MASK, 207 .ref_and_mask_sdma1 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__SDMA1_MASK, 208 }; 209 210 static void nbio_v7_7_init_registers(struct amdgpu_device *adev) 211 { 212 uint32_t def, data; 213 214 def = data = RREG32_SOC15(NBIO, 0, regBIF0_PCIE_MST_CTRL_3); 215 data = REG_SET_FIELD(data, BIF0_PCIE_MST_CTRL_3, 216 CI_SWUS_MAX_READ_REQUEST_SIZE_MODE, 1); 217 data = REG_SET_FIELD(data, BIF0_PCIE_MST_CTRL_3, 218 CI_SWUS_MAX_READ_REQUEST_SIZE_PRIV, 1); 219 220 if (def != data) 221 WREG32_SOC15(NBIO, 0, regBIF0_PCIE_MST_CTRL_3, data); 222 223 } 224 225 const struct amdgpu_nbio_funcs nbio_v7_7_funcs = { 226 .get_hdp_flush_req_offset = nbio_v7_7_get_hdp_flush_req_offset, 227 .get_hdp_flush_done_offset = nbio_v7_7_get_hdp_flush_done_offset, 228 .get_pcie_index_offset = nbio_v7_7_get_pcie_index_offset, 229 .get_pcie_data_offset = nbio_v7_7_get_pcie_data_offset, 230 .get_pcie_port_index_offset = nbio_v7_7_get_pcie_port_index_offset, 231 .get_pcie_port_data_offset = nbio_v7_7_get_pcie_port_data_offset, 232 .get_rev_id = nbio_v7_7_get_rev_id, 233 .mc_access_enable = nbio_v7_7_mc_access_enable, 234 .get_memsize = nbio_v7_7_get_memsize, 235 .sdma_doorbell_range = nbio_v7_7_sdma_doorbell_range, 236 .enable_doorbell_aperture = nbio_v7_7_enable_doorbell_aperture, 237 .enable_doorbell_selfring_aperture = nbio_v7_7_enable_doorbell_selfring_aperture, 238 .ih_doorbell_range = nbio_v7_7_ih_doorbell_range, 239 .ih_control = nbio_v7_7_ih_control, 240 .init_registers = nbio_v7_7_init_registers, 241 }; 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