1 /* 2 * Copyright 2018 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include "amdgpu.h" 24 #include "amdgpu_atombios.h" 25 #include "nbio_v7_4.h" 26 #include "amdgpu_ras.h" 27 28 #include "nbio/nbio_7_4_offset.h" 29 #include "nbio/nbio_7_4_sh_mask.h" 30 #include "nbio/nbio_7_4_0_smn.h" 31 #include "ivsrcid/nbio/irqsrcs_nbif_7_4.h" 32 #include <uapi/linux/kfd_ioctl.h> 33 34 #define smnPCIE_LC_CNTL 0x11140280 35 #define smnPCIE_LC_CNTL3 0x111402d4 36 #define smnPCIE_LC_CNTL6 0x111402ec 37 #define smnPCIE_LC_CNTL7 0x111402f0 38 #define smnNBIF_MGCG_CTRL_LCLK 0x1013a21c 39 #define smnRCC_BIF_STRAP3 0x1012348c 40 #define RCC_BIF_STRAP3__STRAP_VLINK_ASPM_IDLE_TIMER_MASK 0x0000FFFFL 41 #define RCC_BIF_STRAP3__STRAP_VLINK_PM_L1_ENTRY_TIMER_MASK 0xFFFF0000L 42 #define smnRCC_BIF_STRAP5 0x10123494 43 #define RCC_BIF_STRAP5__STRAP_VLINK_LDN_ENTRY_TIMER_MASK 0x0000FFFFL 44 #define smnBIF_CFG_DEV0_EPF0_DEVICE_CNTL2 0x1014008c 45 #define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__LTR_EN_MASK 0x0400L 46 #define smnBIF_CFG_DEV0_EPF0_PCIE_LTR_CAP 0x10140324 47 #define smnPSWUSP0_PCIE_LC_CNTL2 0x111402c4 48 #define smnRCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL 0x10123538 49 #define smnRCC_BIF_STRAP2 0x10123488 50 #define RCC_BIF_STRAP2__STRAP_LTR_IN_ASPML1_DIS_MASK 0x00004000L 51 #define RCC_BIF_STRAP3__STRAP_VLINK_ASPM_IDLE_TIMER__SHIFT 0x0 52 #define RCC_BIF_STRAP3__STRAP_VLINK_PM_L1_ENTRY_TIMER__SHIFT 0x10 53 #define RCC_BIF_STRAP5__STRAP_VLINK_LDN_ENTRY_TIMER__SHIFT 0x0 54 55 /* 56 * These are nbio v7_4_1 registers mask. Temporarily define these here since 57 * nbio v7_4_1 header is incomplete. 58 */ 59 #define GPU_HDP_FLUSH_DONE__RSVD_ENG0_MASK 0x00001000L /* Don't use. Firmware uses this bit internally */ 60 #define GPU_HDP_FLUSH_DONE__RSVD_ENG1_MASK 0x00002000L 61 #define GPU_HDP_FLUSH_DONE__RSVD_ENG2_MASK 0x00004000L 62 #define GPU_HDP_FLUSH_DONE__RSVD_ENG3_MASK 0x00008000L 63 #define GPU_HDP_FLUSH_DONE__RSVD_ENG4_MASK 0x00010000L 64 #define GPU_HDP_FLUSH_DONE__RSVD_ENG5_MASK 0x00020000L 65 #define GPU_HDP_FLUSH_DONE__RSVD_ENG6_MASK 0x00040000L 66 #define GPU_HDP_FLUSH_DONE__RSVD_ENG7_MASK 0x00080000L 67 #define GPU_HDP_FLUSH_DONE__RSVD_ENG8_MASK 0x00100000L 68 69 #define mmBIF_MMSCH1_DOORBELL_RANGE 0x01dc 70 #define mmBIF_MMSCH1_DOORBELL_RANGE_BASE_IDX 2 71 //BIF_MMSCH1_DOORBELL_RANGE 72 #define BIF_MMSCH1_DOORBELL_RANGE__OFFSET__SHIFT 0x2 73 #define BIF_MMSCH1_DOORBELL_RANGE__SIZE__SHIFT 0x10 74 #define BIF_MMSCH1_DOORBELL_RANGE__OFFSET_MASK 0x00000FFCL 75 #define BIF_MMSCH1_DOORBELL_RANGE__SIZE_MASK 0x001F0000L 76 77 #define BIF_MMSCH1_DOORBELL_RANGE__OFFSET_MASK 0x00000FFCL 78 #define BIF_MMSCH1_DOORBELL_RANGE__SIZE_MASK 0x001F0000L 79 80 #define mmBIF_MMSCH1_DOORBELL_RANGE_ALDE 0x01d8 81 #define mmBIF_MMSCH1_DOORBELL_RANGE_ALDE_BASE_IDX 2 82 //BIF_MMSCH1_DOORBELL_ALDE_RANGE 83 #define BIF_MMSCH1_DOORBELL_RANGE_ALDE__OFFSET__SHIFT 0x2 84 #define BIF_MMSCH1_DOORBELL_RANGE_ALDE__SIZE__SHIFT 0x10 85 #define BIF_MMSCH1_DOORBELL_RANGE_ALDE__OFFSET_MASK 0x00000FFCL 86 #define BIF_MMSCH1_DOORBELL_RANGE_ALDE__SIZE_MASK 0x001F0000L 87 88 #define mmRCC_DEV0_EPF0_STRAP0_ALDE 0x0015 89 #define mmRCC_DEV0_EPF0_STRAP0_ALDE_BASE_IDX 2 90 91 #define mmBIF_DOORBELL_INT_CNTL_ALDE 0x00fe 92 #define mmBIF_DOORBELL_INT_CNTL_ALDE_BASE_IDX 2 93 #define BIF_DOORBELL_INT_CNTL_ALDE__DOORBELL_INTERRUPT_DISABLE__SHIFT 0x18 94 #define BIF_DOORBELL_INT_CNTL_ALDE__DOORBELL_INTERRUPT_DISABLE_MASK 0x01000000L 95 96 #define mmBIF_INTR_CNTL_ALDE 0x0101 97 #define mmBIF_INTR_CNTL_ALDE_BASE_IDX 2 98 99 static void nbio_v7_4_query_ras_error_count(struct amdgpu_device *adev, 100 void *ras_error_status); 101 102 static void nbio_v7_4_remap_hdp_registers(struct amdgpu_device *adev) 103 { 104 WREG32_SOC15(NBIO, 0, mmREMAP_HDP_MEM_FLUSH_CNTL, 105 adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL); 106 WREG32_SOC15(NBIO, 0, mmREMAP_HDP_REG_FLUSH_CNTL, 107 adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_REG_FLUSH_CNTL); 108 } 109 110 static u32 nbio_v7_4_get_rev_id(struct amdgpu_device *adev) 111 { 112 u32 tmp; 113 114 if (adev->asic_type == CHIP_ALDEBARAN) 115 tmp = RREG32_SOC15(NBIO, 0, mmRCC_DEV0_EPF0_STRAP0_ALDE); 116 else 117 tmp = RREG32_SOC15(NBIO, 0, mmRCC_DEV0_EPF0_STRAP0); 118 119 tmp &= RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0_MASK; 120 tmp >>= RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0__SHIFT; 121 122 return tmp; 123 } 124 125 static void nbio_v7_4_mc_access_enable(struct amdgpu_device *adev, bool enable) 126 { 127 if (enable) 128 WREG32_SOC15(NBIO, 0, mmBIF_FB_EN, 129 BIF_FB_EN__FB_READ_EN_MASK | BIF_FB_EN__FB_WRITE_EN_MASK); 130 else 131 WREG32_SOC15(NBIO, 0, mmBIF_FB_EN, 0); 132 } 133 134 static u32 nbio_v7_4_get_memsize(struct amdgpu_device *adev) 135 { 136 return RREG32_SOC15(NBIO, 0, mmRCC_CONFIG_MEMSIZE); 137 } 138 139 static void nbio_v7_4_sdma_doorbell_range(struct amdgpu_device *adev, int instance, 140 bool use_doorbell, int doorbell_index, int doorbell_size) 141 { 142 u32 reg, doorbell_range; 143 144 if (instance < 2) { 145 reg = instance + 146 SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA0_DOORBELL_RANGE); 147 } else { 148 /* 149 * These registers address of SDMA2~7 is not consecutive 150 * from SDMA0~1. Need plus 4 dwords offset. 151 * 152 * BIF_SDMA0_DOORBELL_RANGE: 0x3bc0 153 * BIF_SDMA1_DOORBELL_RANGE: 0x3bc4 154 * BIF_SDMA2_DOORBELL_RANGE: 0x3bd8 155 + * BIF_SDMA4_DOORBELL_RANGE: 156 + * ARCTURUS: 0x3be0 157 + * ALDEBARAN: 0x3be4 158 */ 159 if (adev->asic_type == CHIP_ALDEBARAN && instance == 4) 160 reg = instance + 0x4 + 0x1 + 161 SOC15_REG_OFFSET(NBIO, 0, 162 mmBIF_SDMA0_DOORBELL_RANGE); 163 else 164 reg = instance + 0x4 + 165 SOC15_REG_OFFSET(NBIO, 0, 166 mmBIF_SDMA0_DOORBELL_RANGE); 167 } 168 169 doorbell_range = RREG32(reg); 170 171 if (use_doorbell) { 172 doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, OFFSET, doorbell_index); 173 doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, SIZE, doorbell_size); 174 } else 175 doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, SIZE, 0); 176 177 WREG32(reg, doorbell_range); 178 } 179 180 static void nbio_v7_4_vcn_doorbell_range(struct amdgpu_device *adev, bool use_doorbell, 181 int doorbell_index, int instance) 182 { 183 u32 reg; 184 u32 doorbell_range; 185 186 if (instance) { 187 if (adev->asic_type == CHIP_ALDEBARAN) 188 reg = SOC15_REG_OFFSET(NBIO, 0, mmBIF_MMSCH1_DOORBELL_RANGE_ALDE); 189 else 190 reg = SOC15_REG_OFFSET(NBIO, 0, mmBIF_MMSCH1_DOORBELL_RANGE); 191 } else 192 reg = SOC15_REG_OFFSET(NBIO, 0, mmBIF_MMSCH0_DOORBELL_RANGE); 193 194 doorbell_range = RREG32(reg); 195 196 if (use_doorbell) { 197 doorbell_range = REG_SET_FIELD(doorbell_range, 198 BIF_MMSCH0_DOORBELL_RANGE, OFFSET, 199 doorbell_index); 200 doorbell_range = REG_SET_FIELD(doorbell_range, 201 BIF_MMSCH0_DOORBELL_RANGE, SIZE, 8); 202 } else 203 doorbell_range = REG_SET_FIELD(doorbell_range, 204 BIF_MMSCH0_DOORBELL_RANGE, SIZE, 0); 205 206 WREG32(reg, doorbell_range); 207 } 208 209 static void nbio_v7_4_enable_doorbell_aperture(struct amdgpu_device *adev, 210 bool enable) 211 { 212 WREG32_FIELD15(NBIO, 0, RCC_DOORBELL_APER_EN, BIF_DOORBELL_APER_EN, enable ? 1 : 0); 213 } 214 215 static void nbio_v7_4_enable_doorbell_selfring_aperture(struct amdgpu_device *adev, 216 bool enable) 217 { 218 u32 tmp = 0; 219 220 if (enable) { 221 tmp = REG_SET_FIELD(tmp, DOORBELL_SELFRING_GPA_APER_CNTL, DOORBELL_SELFRING_GPA_APER_EN, 1) | 222 REG_SET_FIELD(tmp, DOORBELL_SELFRING_GPA_APER_CNTL, DOORBELL_SELFRING_GPA_APER_MODE, 1) | 223 REG_SET_FIELD(tmp, DOORBELL_SELFRING_GPA_APER_CNTL, DOORBELL_SELFRING_GPA_APER_SIZE, 0); 224 225 WREG32_SOC15(NBIO, 0, mmDOORBELL_SELFRING_GPA_APER_BASE_LOW, 226 lower_32_bits(adev->doorbell.base)); 227 WREG32_SOC15(NBIO, 0, mmDOORBELL_SELFRING_GPA_APER_BASE_HIGH, 228 upper_32_bits(adev->doorbell.base)); 229 } 230 231 WREG32_SOC15(NBIO, 0, mmDOORBELL_SELFRING_GPA_APER_CNTL, tmp); 232 } 233 234 static void nbio_v7_4_ih_doorbell_range(struct amdgpu_device *adev, 235 bool use_doorbell, int doorbell_index) 236 { 237 u32 ih_doorbell_range = RREG32_SOC15(NBIO, 0 , mmBIF_IH_DOORBELL_RANGE); 238 239 if (use_doorbell) { 240 ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, BIF_IH_DOORBELL_RANGE, OFFSET, doorbell_index); 241 ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, BIF_IH_DOORBELL_RANGE, SIZE, 4); 242 } else 243 ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, BIF_IH_DOORBELL_RANGE, SIZE, 0); 244 245 WREG32_SOC15(NBIO, 0, mmBIF_IH_DOORBELL_RANGE, ih_doorbell_range); 246 } 247 248 249 static void nbio_v7_4_update_medium_grain_clock_gating(struct amdgpu_device *adev, 250 bool enable) 251 { 252 //TODO: Add support for v7.4 253 } 254 255 static void nbio_v7_4_update_medium_grain_light_sleep(struct amdgpu_device *adev, 256 bool enable) 257 { 258 uint32_t def, data; 259 260 def = data = RREG32_PCIE(smnPCIE_CNTL2); 261 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_LS)) { 262 data |= (PCIE_CNTL2__SLV_MEM_LS_EN_MASK | 263 PCIE_CNTL2__MST_MEM_LS_EN_MASK | 264 PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK); 265 } else { 266 data &= ~(PCIE_CNTL2__SLV_MEM_LS_EN_MASK | 267 PCIE_CNTL2__MST_MEM_LS_EN_MASK | 268 PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK); 269 } 270 271 if (def != data) 272 WREG32_PCIE(smnPCIE_CNTL2, data); 273 } 274 275 static void nbio_v7_4_get_clockgating_state(struct amdgpu_device *adev, 276 u32 *flags) 277 { 278 int data; 279 280 /* AMD_CG_SUPPORT_BIF_MGCG */ 281 data = RREG32_PCIE(smnCPM_CONTROL); 282 if (data & CPM_CONTROL__LCLK_DYN_GATE_ENABLE_MASK) 283 *flags |= AMD_CG_SUPPORT_BIF_MGCG; 284 285 /* AMD_CG_SUPPORT_BIF_LS */ 286 data = RREG32_PCIE(smnPCIE_CNTL2); 287 if (data & PCIE_CNTL2__SLV_MEM_LS_EN_MASK) 288 *flags |= AMD_CG_SUPPORT_BIF_LS; 289 } 290 291 static void nbio_v7_4_ih_control(struct amdgpu_device *adev) 292 { 293 u32 interrupt_cntl; 294 295 /* setup interrupt control */ 296 WREG32_SOC15(NBIO, 0, mmINTERRUPT_CNTL2, adev->dummy_page_addr >> 8); 297 interrupt_cntl = RREG32_SOC15(NBIO, 0, mmINTERRUPT_CNTL); 298 /* INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=0 - dummy read disabled with msi, enabled without msi 299 * INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=1 - dummy read controlled by IH_DUMMY_RD_EN 300 */ 301 interrupt_cntl = REG_SET_FIELD(interrupt_cntl, INTERRUPT_CNTL, IH_DUMMY_RD_OVERRIDE, 0); 302 /* INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN_MASK=1 if ring is in non-cacheable memory, e.g., vram */ 303 interrupt_cntl = REG_SET_FIELD(interrupt_cntl, INTERRUPT_CNTL, IH_REQ_NONSNOOP_EN, 0); 304 WREG32_SOC15(NBIO, 0, mmINTERRUPT_CNTL, interrupt_cntl); 305 } 306 307 static u32 nbio_v7_4_get_hdp_flush_req_offset(struct amdgpu_device *adev) 308 { 309 return SOC15_REG_OFFSET(NBIO, 0, mmGPU_HDP_FLUSH_REQ); 310 } 311 312 static u32 nbio_v7_4_get_hdp_flush_done_offset(struct amdgpu_device *adev) 313 { 314 return SOC15_REG_OFFSET(NBIO, 0, mmGPU_HDP_FLUSH_DONE); 315 } 316 317 static u32 nbio_v7_4_get_pcie_index_offset(struct amdgpu_device *adev) 318 { 319 return SOC15_REG_OFFSET(NBIO, 0, mmPCIE_INDEX2); 320 } 321 322 static u32 nbio_v7_4_get_pcie_data_offset(struct amdgpu_device *adev) 323 { 324 return SOC15_REG_OFFSET(NBIO, 0, mmPCIE_DATA2); 325 } 326 327 const struct nbio_hdp_flush_reg nbio_v7_4_hdp_flush_reg = { 328 .ref_and_mask_cp0 = GPU_HDP_FLUSH_DONE__CP0_MASK, 329 .ref_and_mask_cp1 = GPU_HDP_FLUSH_DONE__CP1_MASK, 330 .ref_and_mask_cp2 = GPU_HDP_FLUSH_DONE__CP2_MASK, 331 .ref_and_mask_cp3 = GPU_HDP_FLUSH_DONE__CP3_MASK, 332 .ref_and_mask_cp4 = GPU_HDP_FLUSH_DONE__CP4_MASK, 333 .ref_and_mask_cp5 = GPU_HDP_FLUSH_DONE__CP5_MASK, 334 .ref_and_mask_cp6 = GPU_HDP_FLUSH_DONE__CP6_MASK, 335 .ref_and_mask_cp7 = GPU_HDP_FLUSH_DONE__CP7_MASK, 336 .ref_and_mask_cp8 = GPU_HDP_FLUSH_DONE__CP8_MASK, 337 .ref_and_mask_cp9 = GPU_HDP_FLUSH_DONE__CP9_MASK, 338 .ref_and_mask_sdma0 = GPU_HDP_FLUSH_DONE__SDMA0_MASK, 339 .ref_and_mask_sdma1 = GPU_HDP_FLUSH_DONE__SDMA1_MASK, 340 }; 341 342 const struct nbio_hdp_flush_reg nbio_v7_4_hdp_flush_reg_ald = { 343 .ref_and_mask_cp0 = GPU_HDP_FLUSH_DONE__CP0_MASK, 344 .ref_and_mask_cp1 = GPU_HDP_FLUSH_DONE__CP1_MASK, 345 .ref_and_mask_cp2 = GPU_HDP_FLUSH_DONE__CP2_MASK, 346 .ref_and_mask_cp3 = GPU_HDP_FLUSH_DONE__CP3_MASK, 347 .ref_and_mask_cp4 = GPU_HDP_FLUSH_DONE__CP4_MASK, 348 .ref_and_mask_cp5 = GPU_HDP_FLUSH_DONE__CP5_MASK, 349 .ref_and_mask_cp6 = GPU_HDP_FLUSH_DONE__CP6_MASK, 350 .ref_and_mask_cp7 = GPU_HDP_FLUSH_DONE__CP7_MASK, 351 .ref_and_mask_cp8 = GPU_HDP_FLUSH_DONE__CP8_MASK, 352 .ref_and_mask_cp9 = GPU_HDP_FLUSH_DONE__CP9_MASK, 353 .ref_and_mask_sdma0 = GPU_HDP_FLUSH_DONE__RSVD_ENG1_MASK, 354 .ref_and_mask_sdma1 = GPU_HDP_FLUSH_DONE__RSVD_ENG2_MASK, 355 .ref_and_mask_sdma2 = GPU_HDP_FLUSH_DONE__RSVD_ENG3_MASK, 356 .ref_and_mask_sdma3 = GPU_HDP_FLUSH_DONE__RSVD_ENG4_MASK, 357 .ref_and_mask_sdma4 = GPU_HDP_FLUSH_DONE__RSVD_ENG5_MASK, 358 .ref_and_mask_sdma5 = GPU_HDP_FLUSH_DONE__RSVD_ENG6_MASK, 359 .ref_and_mask_sdma6 = GPU_HDP_FLUSH_DONE__RSVD_ENG7_MASK, 360 .ref_and_mask_sdma7 = GPU_HDP_FLUSH_DONE__RSVD_ENG8_MASK, 361 }; 362 363 static void nbio_v7_4_init_registers(struct amdgpu_device *adev) 364 { 365 if (amdgpu_sriov_vf(adev)) 366 adev->rmmio_remap.reg_offset = SOC15_REG_OFFSET(NBIO, 0, 367 mmBIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_FLUSH_CNTL) << 2; 368 } 369 370 static void nbio_v7_4_handle_ras_controller_intr_no_bifring(struct amdgpu_device *adev) 371 { 372 uint32_t bif_doorbell_intr_cntl; 373 struct ras_manager *obj = amdgpu_ras_find_obj(adev, adev->nbio.ras_if); 374 struct ras_err_data err_data = {0, 0, 0, NULL}; 375 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); 376 377 if (adev->asic_type == CHIP_ALDEBARAN) 378 bif_doorbell_intr_cntl = RREG32_SOC15(NBIO, 0, mmBIF_DOORBELL_INT_CNTL_ALDE); 379 else 380 bif_doorbell_intr_cntl = RREG32_SOC15(NBIO, 0, mmBIF_DOORBELL_INT_CNTL); 381 382 if (REG_GET_FIELD(bif_doorbell_intr_cntl, 383 BIF_DOORBELL_INT_CNTL, RAS_CNTLR_INTERRUPT_STATUS)) { 384 /* driver has to clear the interrupt status when bif ring is disabled */ 385 bif_doorbell_intr_cntl = REG_SET_FIELD(bif_doorbell_intr_cntl, 386 BIF_DOORBELL_INT_CNTL, 387 RAS_CNTLR_INTERRUPT_CLEAR, 1); 388 if (adev->asic_type == CHIP_ALDEBARAN) 389 WREG32_SOC15(NBIO, 0, mmBIF_DOORBELL_INT_CNTL_ALDE, bif_doorbell_intr_cntl); 390 else 391 WREG32_SOC15(NBIO, 0, mmBIF_DOORBELL_INT_CNTL, bif_doorbell_intr_cntl); 392 393 if (!ras->disable_ras_err_cnt_harvest) { 394 /* 395 * clear error status after ras_controller_intr 396 * according to hw team and count ue number 397 * for query 398 */ 399 nbio_v7_4_query_ras_error_count(adev, &err_data); 400 401 /* logging on error cnt and printing for awareness */ 402 obj->err_data.ue_count += err_data.ue_count; 403 obj->err_data.ce_count += err_data.ce_count; 404 405 if (err_data.ce_count) 406 dev_info(adev->dev, "%ld correctable hardware " 407 "errors detected in %s block, " 408 "no user action is needed.\n", 409 obj->err_data.ce_count, 410 get_ras_block_str(adev->nbio.ras_if)); 411 412 if (err_data.ue_count) 413 dev_info(adev->dev, "%ld uncorrectable hardware " 414 "errors detected in %s block\n", 415 obj->err_data.ue_count, 416 get_ras_block_str(adev->nbio.ras_if)); 417 } 418 419 dev_info(adev->dev, "RAS controller interrupt triggered " 420 "by NBIF error\n"); 421 422 /* ras_controller_int is dedicated for nbif ras error, 423 * not the global interrupt for sync flood 424 */ 425 amdgpu_ras_reset_gpu(adev); 426 } 427 } 428 429 static void nbio_v7_4_handle_ras_err_event_athub_intr_no_bifring(struct amdgpu_device *adev) 430 { 431 uint32_t bif_doorbell_intr_cntl; 432 433 if (adev->asic_type == CHIP_ALDEBARAN) 434 bif_doorbell_intr_cntl = RREG32_SOC15(NBIO, 0, mmBIF_DOORBELL_INT_CNTL_ALDE); 435 else 436 bif_doorbell_intr_cntl = RREG32_SOC15(NBIO, 0, mmBIF_DOORBELL_INT_CNTL); 437 438 if (REG_GET_FIELD(bif_doorbell_intr_cntl, 439 BIF_DOORBELL_INT_CNTL, RAS_ATHUB_ERR_EVENT_INTERRUPT_STATUS)) { 440 /* driver has to clear the interrupt status when bif ring is disabled */ 441 bif_doorbell_intr_cntl = REG_SET_FIELD(bif_doorbell_intr_cntl, 442 BIF_DOORBELL_INT_CNTL, 443 RAS_ATHUB_ERR_EVENT_INTERRUPT_CLEAR, 1); 444 445 if (adev->asic_type == CHIP_ALDEBARAN) 446 WREG32_SOC15(NBIO, 0, mmBIF_DOORBELL_INT_CNTL_ALDE, bif_doorbell_intr_cntl); 447 else 448 WREG32_SOC15(NBIO, 0, mmBIF_DOORBELL_INT_CNTL, bif_doorbell_intr_cntl); 449 450 amdgpu_ras_global_ras_isr(adev); 451 } 452 } 453 454 455 static int nbio_v7_4_set_ras_controller_irq_state(struct amdgpu_device *adev, 456 struct amdgpu_irq_src *src, 457 unsigned type, 458 enum amdgpu_interrupt_state state) 459 { 460 /* The ras_controller_irq enablement should be done in psp bl when it 461 * tries to enable ras feature. Driver only need to set the correct interrupt 462 * vector for bare-metal and sriov use case respectively 463 */ 464 uint32_t bif_intr_cntl; 465 466 if (adev->asic_type == CHIP_ALDEBARAN) 467 bif_intr_cntl = RREG32_SOC15(NBIO, 0, mmBIF_INTR_CNTL_ALDE); 468 else 469 bif_intr_cntl = RREG32_SOC15(NBIO, 0, mmBIF_INTR_CNTL); 470 471 if (state == AMDGPU_IRQ_STATE_ENABLE) { 472 /* set interrupt vector select bit to 0 to select 473 * vetcor 1 for bare metal case */ 474 bif_intr_cntl = REG_SET_FIELD(bif_intr_cntl, 475 BIF_INTR_CNTL, 476 RAS_INTR_VEC_SEL, 0); 477 478 if (adev->asic_type == CHIP_ALDEBARAN) 479 WREG32_SOC15(NBIO, 0, mmBIF_INTR_CNTL_ALDE, bif_intr_cntl); 480 else 481 WREG32_SOC15(NBIO, 0, mmBIF_INTR_CNTL, bif_intr_cntl); 482 483 } 484 485 return 0; 486 } 487 488 static int nbio_v7_4_process_ras_controller_irq(struct amdgpu_device *adev, 489 struct amdgpu_irq_src *source, 490 struct amdgpu_iv_entry *entry) 491 { 492 /* By design, the ih cookie for ras_controller_irq should be written 493 * to BIFring instead of general iv ring. However, due to known bif ring 494 * hw bug, it has to be disabled. There is no chance the process function 495 * will be involked. Just left it as a dummy one. 496 */ 497 return 0; 498 } 499 500 static int nbio_v7_4_set_ras_err_event_athub_irq_state(struct amdgpu_device *adev, 501 struct amdgpu_irq_src *src, 502 unsigned type, 503 enum amdgpu_interrupt_state state) 504 { 505 /* The ras_controller_irq enablement should be done in psp bl when it 506 * tries to enable ras feature. Driver only need to set the correct interrupt 507 * vector for bare-metal and sriov use case respectively 508 */ 509 uint32_t bif_intr_cntl; 510 511 if (adev->asic_type == CHIP_ALDEBARAN) 512 bif_intr_cntl = RREG32_SOC15(NBIO, 0, mmBIF_INTR_CNTL_ALDE); 513 else 514 bif_intr_cntl = RREG32_SOC15(NBIO, 0, mmBIF_INTR_CNTL); 515 516 if (state == AMDGPU_IRQ_STATE_ENABLE) { 517 /* set interrupt vector select bit to 0 to select 518 * vetcor 1 for bare metal case */ 519 bif_intr_cntl = REG_SET_FIELD(bif_intr_cntl, 520 BIF_INTR_CNTL, 521 RAS_INTR_VEC_SEL, 0); 522 523 if (adev->asic_type == CHIP_ALDEBARAN) 524 WREG32_SOC15(NBIO, 0, mmBIF_INTR_CNTL_ALDE, bif_intr_cntl); 525 else 526 WREG32_SOC15(NBIO, 0, mmBIF_INTR_CNTL, bif_intr_cntl); 527 } 528 529 return 0; 530 } 531 532 static int nbio_v7_4_process_err_event_athub_irq(struct amdgpu_device *adev, 533 struct amdgpu_irq_src *source, 534 struct amdgpu_iv_entry *entry) 535 { 536 /* By design, the ih cookie for err_event_athub_irq should be written 537 * to BIFring instead of general iv ring. However, due to known bif ring 538 * hw bug, it has to be disabled. There is no chance the process function 539 * will be involked. Just left it as a dummy one. 540 */ 541 return 0; 542 } 543 544 static const struct amdgpu_irq_src_funcs nbio_v7_4_ras_controller_irq_funcs = { 545 .set = nbio_v7_4_set_ras_controller_irq_state, 546 .process = nbio_v7_4_process_ras_controller_irq, 547 }; 548 549 static const struct amdgpu_irq_src_funcs nbio_v7_4_ras_err_event_athub_irq_funcs = { 550 .set = nbio_v7_4_set_ras_err_event_athub_irq_state, 551 .process = nbio_v7_4_process_err_event_athub_irq, 552 }; 553 554 static int nbio_v7_4_init_ras_controller_interrupt (struct amdgpu_device *adev) 555 { 556 int r; 557 558 /* init the irq funcs */ 559 adev->nbio.ras_controller_irq.funcs = 560 &nbio_v7_4_ras_controller_irq_funcs; 561 adev->nbio.ras_controller_irq.num_types = 1; 562 563 /* register ras controller interrupt */ 564 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_BIF, 565 NBIF_7_4__SRCID__RAS_CONTROLLER_INTERRUPT, 566 &adev->nbio.ras_controller_irq); 567 568 return r; 569 } 570 571 static int nbio_v7_4_init_ras_err_event_athub_interrupt (struct amdgpu_device *adev) 572 { 573 574 int r; 575 576 /* init the irq funcs */ 577 adev->nbio.ras_err_event_athub_irq.funcs = 578 &nbio_v7_4_ras_err_event_athub_irq_funcs; 579 adev->nbio.ras_err_event_athub_irq.num_types = 1; 580 581 /* register ras err event athub interrupt */ 582 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_BIF, 583 NBIF_7_4__SRCID__ERREVENT_ATHUB_INTERRUPT, 584 &adev->nbio.ras_err_event_athub_irq); 585 586 return r; 587 } 588 589 #define smnPARITY_ERROR_STATUS_UNCORR_GRP2 0x13a20030 590 #define smnPARITY_ERROR_STATUS_UNCORR_GRP2_ALDE 0x13b20030 591 #define smnRAS_GLOBAL_STATUS_LO_ALDE 0x13b20020 592 593 static void nbio_v7_4_query_ras_error_count(struct amdgpu_device *adev, 594 void *ras_error_status) 595 { 596 uint32_t global_sts, central_sts, int_eoi, parity_sts; 597 uint32_t corr, fatal, non_fatal; 598 struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status; 599 600 if (adev->asic_type == CHIP_ALDEBARAN) 601 global_sts = RREG32_PCIE(smnRAS_GLOBAL_STATUS_LO_ALDE); 602 else 603 global_sts = RREG32_PCIE(smnRAS_GLOBAL_STATUS_LO); 604 605 corr = REG_GET_FIELD(global_sts, RAS_GLOBAL_STATUS_LO, ParityErrCorr); 606 fatal = REG_GET_FIELD(global_sts, RAS_GLOBAL_STATUS_LO, ParityErrFatal); 607 non_fatal = REG_GET_FIELD(global_sts, RAS_GLOBAL_STATUS_LO, 608 ParityErrNonFatal); 609 610 if (adev->asic_type == CHIP_ALDEBARAN) 611 parity_sts = RREG32_PCIE(smnPARITY_ERROR_STATUS_UNCORR_GRP2_ALDE); 612 else 613 parity_sts = RREG32_PCIE(smnPARITY_ERROR_STATUS_UNCORR_GRP2); 614 615 if (corr) 616 err_data->ce_count++; 617 if (fatal) 618 err_data->ue_count++; 619 620 if (corr || fatal || non_fatal) { 621 central_sts = RREG32_PCIE(smnBIFL_RAS_CENTRAL_STATUS); 622 623 /* clear error status register */ 624 if (adev->asic_type == CHIP_ALDEBARAN) 625 WREG32_PCIE(smnRAS_GLOBAL_STATUS_LO_ALDE, global_sts); 626 else 627 WREG32_PCIE(smnRAS_GLOBAL_STATUS_LO, global_sts); 628 629 if (fatal) 630 { 631 /* clear parity fatal error indication field */ 632 if (adev->asic_type == CHIP_ALDEBARAN) 633 WREG32_PCIE(smnPARITY_ERROR_STATUS_UNCORR_GRP2_ALDE, parity_sts); 634 else 635 WREG32_PCIE(smnPARITY_ERROR_STATUS_UNCORR_GRP2, parity_sts); 636 } 637 638 if (REG_GET_FIELD(central_sts, BIFL_RAS_CENTRAL_STATUS, 639 BIFL_RasContller_Intr_Recv)) { 640 /* clear interrupt status register */ 641 WREG32_PCIE(smnBIFL_RAS_CENTRAL_STATUS, central_sts); 642 int_eoi = RREG32_PCIE(smnIOHC_INTERRUPT_EOI); 643 int_eoi = REG_SET_FIELD(int_eoi, 644 IOHC_INTERRUPT_EOI, SMI_EOI, 1); 645 WREG32_PCIE(smnIOHC_INTERRUPT_EOI, int_eoi); 646 } 647 } 648 } 649 650 static void nbio_v7_4_enable_doorbell_interrupt(struct amdgpu_device *adev, 651 bool enable) 652 { 653 if (adev->asic_type == CHIP_ALDEBARAN) 654 WREG32_FIELD15(NBIO, 0, BIF_DOORBELL_INT_CNTL_ALDE, 655 DOORBELL_INTERRUPT_DISABLE, enable ? 0 : 1); 656 else 657 WREG32_FIELD15(NBIO, 0, BIF_DOORBELL_INT_CNTL, 658 DOORBELL_INTERRUPT_DISABLE, enable ? 0 : 1); 659 } 660 661 const struct amdgpu_nbio_ras_funcs nbio_v7_4_ras_funcs = { 662 .handle_ras_controller_intr_no_bifring = nbio_v7_4_handle_ras_controller_intr_no_bifring, 663 .handle_ras_err_event_athub_intr_no_bifring = nbio_v7_4_handle_ras_err_event_athub_intr_no_bifring, 664 .init_ras_controller_interrupt = nbio_v7_4_init_ras_controller_interrupt, 665 .init_ras_err_event_athub_interrupt = nbio_v7_4_init_ras_err_event_athub_interrupt, 666 .query_ras_error_count = nbio_v7_4_query_ras_error_count, 667 .ras_late_init = amdgpu_nbio_ras_late_init, 668 .ras_fini = amdgpu_nbio_ras_fini, 669 }; 670 671 static void nbio_v7_4_program_ltr(struct amdgpu_device *adev) 672 { 673 uint32_t def, data; 674 675 WREG32_PCIE(smnRCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL, 0x75EB); 676 677 def = data = RREG32_PCIE(smnRCC_BIF_STRAP2); 678 data &= ~RCC_BIF_STRAP2__STRAP_LTR_IN_ASPML1_DIS_MASK; 679 if (def != data) 680 WREG32_PCIE(smnRCC_BIF_STRAP2, data); 681 682 def = data = RREG32_PCIE(smnRCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL); 683 data &= ~EP_PCIE_TX_LTR_CNTL__LTR_PRIV_MSG_DIS_IN_PM_NON_D0_MASK; 684 if (def != data) 685 WREG32_PCIE(smnRCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL, data); 686 687 def = data = RREG32_PCIE(smnBIF_CFG_DEV0_EPF0_DEVICE_CNTL2); 688 data |= BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__LTR_EN_MASK; 689 if (def != data) 690 WREG32_PCIE(smnBIF_CFG_DEV0_EPF0_DEVICE_CNTL2, data); 691 } 692 693 static void nbio_v7_4_program_aspm(struct amdgpu_device *adev) 694 { 695 uint32_t def, data; 696 697 def = data = RREG32_PCIE(smnPCIE_LC_CNTL); 698 data &= ~PCIE_LC_CNTL__LC_L1_INACTIVITY_MASK; 699 data &= ~PCIE_LC_CNTL__LC_L0S_INACTIVITY_MASK; 700 data |= PCIE_LC_CNTL__LC_PMI_TO_L1_DIS_MASK; 701 if (def != data) 702 WREG32_PCIE(smnPCIE_LC_CNTL, data); 703 704 def = data = RREG32_PCIE(smnPCIE_LC_CNTL7); 705 data |= PCIE_LC_CNTL7__LC_NBIF_ASPM_INPUT_EN_MASK; 706 if (def != data) 707 WREG32_PCIE(smnPCIE_LC_CNTL7, data); 708 709 def = data = RREG32_PCIE(smnNBIF_MGCG_CTRL_LCLK); 710 data |= NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_REG_DIS_LCLK_MASK; 711 if (def != data) 712 WREG32_PCIE(smnNBIF_MGCG_CTRL_LCLK, data); 713 714 def = data = RREG32_PCIE(smnPCIE_LC_CNTL3); 715 data |= PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK_MASK; 716 if (def != data) 717 WREG32_PCIE(smnPCIE_LC_CNTL3, data); 718 719 def = data = RREG32_PCIE(smnRCC_BIF_STRAP3); 720 data &= ~RCC_BIF_STRAP3__STRAP_VLINK_ASPM_IDLE_TIMER_MASK; 721 data &= ~RCC_BIF_STRAP3__STRAP_VLINK_PM_L1_ENTRY_TIMER_MASK; 722 if (def != data) 723 WREG32_PCIE(smnRCC_BIF_STRAP3, data); 724 725 def = data = RREG32_PCIE(smnRCC_BIF_STRAP5); 726 data &= ~RCC_BIF_STRAP5__STRAP_VLINK_LDN_ENTRY_TIMER_MASK; 727 if (def != data) 728 WREG32_PCIE(smnRCC_BIF_STRAP5, data); 729 730 def = data = RREG32_PCIE(smnBIF_CFG_DEV0_EPF0_DEVICE_CNTL2); 731 data &= ~BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__LTR_EN_MASK; 732 if (def != data) 733 WREG32_PCIE(smnBIF_CFG_DEV0_EPF0_DEVICE_CNTL2, data); 734 735 WREG32_PCIE(smnBIF_CFG_DEV0_EPF0_PCIE_LTR_CAP, 0x10011001); 736 737 def = data = RREG32_PCIE(smnPSWUSP0_PCIE_LC_CNTL2); 738 data |= PSWUSP0_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1_MASK | 739 PSWUSP0_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23_MASK; 740 data &= ~PSWUSP0_PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS_MASK; 741 if (def != data) 742 WREG32_PCIE(smnPSWUSP0_PCIE_LC_CNTL2, data); 743 744 def = data = RREG32_PCIE(smnPCIE_LC_CNTL6); 745 data |= PCIE_LC_CNTL6__LC_L1_POWERDOWN_MASK | 746 PCIE_LC_CNTL6__LC_RX_L0S_STANDBY_EN_MASK; 747 if (def != data) 748 WREG32_PCIE(smnPCIE_LC_CNTL6, data); 749 750 nbio_v7_4_program_ltr(adev); 751 752 def = data = RREG32_PCIE(smnRCC_BIF_STRAP3); 753 data |= 0x5DE0 << RCC_BIF_STRAP3__STRAP_VLINK_ASPM_IDLE_TIMER__SHIFT; 754 data |= 0x0010 << RCC_BIF_STRAP3__STRAP_VLINK_PM_L1_ENTRY_TIMER__SHIFT; 755 if (def != data) 756 WREG32_PCIE(smnRCC_BIF_STRAP3, data); 757 758 def = data = RREG32_PCIE(smnRCC_BIF_STRAP5); 759 data |= 0x0010 << RCC_BIF_STRAP5__STRAP_VLINK_LDN_ENTRY_TIMER__SHIFT; 760 if (def != data) 761 WREG32_PCIE(smnRCC_BIF_STRAP5, data); 762 763 def = data = RREG32_PCIE(smnPCIE_LC_CNTL); 764 data &= ~PCIE_LC_CNTL__LC_L0S_INACTIVITY_MASK; 765 data |= 0x9 << PCIE_LC_CNTL__LC_L1_INACTIVITY__SHIFT; 766 data |= 0x1 << PCIE_LC_CNTL__LC_PMI_TO_L1_DIS__SHIFT; 767 if (def != data) 768 WREG32_PCIE(smnPCIE_LC_CNTL, data); 769 770 def = data = RREG32_PCIE(smnPCIE_LC_CNTL3); 771 data &= ~PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK_MASK; 772 if (def != data) 773 WREG32_PCIE(smnPCIE_LC_CNTL3, data); 774 } 775 776 const struct amdgpu_nbio_funcs nbio_v7_4_funcs = { 777 .get_hdp_flush_req_offset = nbio_v7_4_get_hdp_flush_req_offset, 778 .get_hdp_flush_done_offset = nbio_v7_4_get_hdp_flush_done_offset, 779 .get_pcie_index_offset = nbio_v7_4_get_pcie_index_offset, 780 .get_pcie_data_offset = nbio_v7_4_get_pcie_data_offset, 781 .get_rev_id = nbio_v7_4_get_rev_id, 782 .mc_access_enable = nbio_v7_4_mc_access_enable, 783 .get_memsize = nbio_v7_4_get_memsize, 784 .sdma_doorbell_range = nbio_v7_4_sdma_doorbell_range, 785 .vcn_doorbell_range = nbio_v7_4_vcn_doorbell_range, 786 .enable_doorbell_aperture = nbio_v7_4_enable_doorbell_aperture, 787 .enable_doorbell_selfring_aperture = nbio_v7_4_enable_doorbell_selfring_aperture, 788 .ih_doorbell_range = nbio_v7_4_ih_doorbell_range, 789 .enable_doorbell_interrupt = nbio_v7_4_enable_doorbell_interrupt, 790 .update_medium_grain_clock_gating = nbio_v7_4_update_medium_grain_clock_gating, 791 .update_medium_grain_light_sleep = nbio_v7_4_update_medium_grain_light_sleep, 792 .get_clockgating_state = nbio_v7_4_get_clockgating_state, 793 .ih_control = nbio_v7_4_ih_control, 794 .init_registers = nbio_v7_4_init_registers, 795 .remap_hdp_registers = nbio_v7_4_remap_hdp_registers, 796 .program_aspm = nbio_v7_4_program_aspm, 797 }; 798