1 /* 2 * Copyright 2018 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include "amdgpu.h" 24 #include "amdgpu_atombios.h" 25 #include "nbio_v7_4.h" 26 27 #include "nbio/nbio_7_4_offset.h" 28 #include "nbio/nbio_7_4_sh_mask.h" 29 30 #define smnNBIF_MGCG_CTRL_LCLK 0x1013a21c 31 32 #define smnCPM_CONTROL 0x11180460 33 #define smnPCIE_CNTL2 0x11180070 34 #define smnPCIE_CI_CNTL 0x11180080 35 36 static u32 nbio_v7_4_get_rev_id(struct amdgpu_device *adev) 37 { 38 u32 tmp = RREG32_SOC15(NBIO, 0, mmRCC_DEV0_EPF0_STRAP0); 39 40 tmp &= RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0_MASK; 41 tmp >>= RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0__SHIFT; 42 43 return tmp; 44 } 45 46 static void nbio_v7_4_mc_access_enable(struct amdgpu_device *adev, bool enable) 47 { 48 if (enable) 49 WREG32_SOC15(NBIO, 0, mmBIF_FB_EN, 50 BIF_FB_EN__FB_READ_EN_MASK | BIF_FB_EN__FB_WRITE_EN_MASK); 51 else 52 WREG32_SOC15(NBIO, 0, mmBIF_FB_EN, 0); 53 } 54 55 static void nbio_v7_4_hdp_flush(struct amdgpu_device *adev, 56 struct amdgpu_ring *ring) 57 { 58 if (!ring || !ring->funcs->emit_wreg) 59 WREG32_SOC15_NO_KIQ(NBIO, 0, mmHDP_MEM_COHERENCY_FLUSH_CNTL, 0); 60 else 61 amdgpu_ring_emit_wreg(ring, SOC15_REG_OFFSET( 62 NBIO, 0, mmHDP_MEM_COHERENCY_FLUSH_CNTL), 0); 63 } 64 65 static u32 nbio_v7_4_get_memsize(struct amdgpu_device *adev) 66 { 67 return RREG32_SOC15(NBIO, 0, mmRCC_CONFIG_MEMSIZE); 68 } 69 70 static void nbio_v7_4_sdma_doorbell_range(struct amdgpu_device *adev, int instance, 71 bool use_doorbell, int doorbell_index) 72 { 73 u32 reg = instance == 0 ? SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA0_DOORBELL_RANGE) : 74 SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA1_DOORBELL_RANGE); 75 76 u32 doorbell_range = RREG32(reg); 77 78 if (use_doorbell) { 79 doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, OFFSET, doorbell_index); 80 doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, SIZE, 2); 81 } else 82 doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, SIZE, 0); 83 84 WREG32(reg, doorbell_range); 85 } 86 87 static void nbio_v7_4_enable_doorbell_aperture(struct amdgpu_device *adev, 88 bool enable) 89 { 90 WREG32_FIELD15(NBIO, 0, RCC_DOORBELL_APER_EN, BIF_DOORBELL_APER_EN, enable ? 1 : 0); 91 } 92 93 static void nbio_v7_4_enable_doorbell_selfring_aperture(struct amdgpu_device *adev, 94 bool enable) 95 { 96 97 } 98 99 static void nbio_v7_4_ih_doorbell_range(struct amdgpu_device *adev, 100 bool use_doorbell, int doorbell_index) 101 { 102 u32 ih_doorbell_range = RREG32_SOC15(NBIO, 0 , mmBIF_IH_DOORBELL_RANGE); 103 104 if (use_doorbell) { 105 ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, BIF_IH_DOORBELL_RANGE, OFFSET, doorbell_index); 106 ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, BIF_IH_DOORBELL_RANGE, SIZE, 2); 107 } else 108 ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, BIF_IH_DOORBELL_RANGE, SIZE, 0); 109 110 WREG32_SOC15(NBIO, 0, mmBIF_IH_DOORBELL_RANGE, ih_doorbell_range); 111 } 112 113 114 static void nbio_v7_4_update_medium_grain_clock_gating(struct amdgpu_device *adev, 115 bool enable) 116 { 117 //TODO: Add support for v7.4 118 } 119 120 static void nbio_v7_4_update_medium_grain_light_sleep(struct amdgpu_device *adev, 121 bool enable) 122 { 123 uint32_t def, data; 124 125 def = data = RREG32_PCIE(smnPCIE_CNTL2); 126 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_LS)) { 127 data |= (PCIE_CNTL2__SLV_MEM_LS_EN_MASK | 128 PCIE_CNTL2__MST_MEM_LS_EN_MASK | 129 PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK); 130 } else { 131 data &= ~(PCIE_CNTL2__SLV_MEM_LS_EN_MASK | 132 PCIE_CNTL2__MST_MEM_LS_EN_MASK | 133 PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK); 134 } 135 136 if (def != data) 137 WREG32_PCIE(smnPCIE_CNTL2, data); 138 } 139 140 static void nbio_v7_4_get_clockgating_state(struct amdgpu_device *adev, 141 u32 *flags) 142 { 143 int data; 144 145 /* AMD_CG_SUPPORT_BIF_MGCG */ 146 data = RREG32_PCIE(smnCPM_CONTROL); 147 if (data & CPM_CONTROL__LCLK_DYN_GATE_ENABLE_MASK) 148 *flags |= AMD_CG_SUPPORT_BIF_MGCG; 149 150 /* AMD_CG_SUPPORT_BIF_LS */ 151 data = RREG32_PCIE(smnPCIE_CNTL2); 152 if (data & PCIE_CNTL2__SLV_MEM_LS_EN_MASK) 153 *flags |= AMD_CG_SUPPORT_BIF_LS; 154 } 155 156 static void nbio_v7_4_ih_control(struct amdgpu_device *adev) 157 { 158 u32 interrupt_cntl; 159 160 /* setup interrupt control */ 161 WREG32_SOC15(NBIO, 0, mmINTERRUPT_CNTL2, adev->dummy_page_addr >> 8); 162 interrupt_cntl = RREG32_SOC15(NBIO, 0, mmINTERRUPT_CNTL); 163 /* INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=0 - dummy read disabled with msi, enabled without msi 164 * INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=1 - dummy read controlled by IH_DUMMY_RD_EN 165 */ 166 interrupt_cntl = REG_SET_FIELD(interrupt_cntl, INTERRUPT_CNTL, IH_DUMMY_RD_OVERRIDE, 0); 167 /* INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN_MASK=1 if ring is in non-cacheable memory, e.g., vram */ 168 interrupt_cntl = REG_SET_FIELD(interrupt_cntl, INTERRUPT_CNTL, IH_REQ_NONSNOOP_EN, 0); 169 WREG32_SOC15(NBIO, 0, mmINTERRUPT_CNTL, interrupt_cntl); 170 } 171 172 static u32 nbio_v7_4_get_hdp_flush_req_offset(struct amdgpu_device *adev) 173 { 174 return SOC15_REG_OFFSET(NBIO, 0, mmGPU_HDP_FLUSH_REQ); 175 } 176 177 static u32 nbio_v7_4_get_hdp_flush_done_offset(struct amdgpu_device *adev) 178 { 179 return SOC15_REG_OFFSET(NBIO, 0, mmGPU_HDP_FLUSH_DONE); 180 } 181 182 static u32 nbio_v7_4_get_pcie_index_offset(struct amdgpu_device *adev) 183 { 184 return SOC15_REG_OFFSET(NBIO, 0, mmPCIE_INDEX2); 185 } 186 187 static u32 nbio_v7_4_get_pcie_data_offset(struct amdgpu_device *adev) 188 { 189 return SOC15_REG_OFFSET(NBIO, 0, mmPCIE_DATA2); 190 } 191 192 static const struct nbio_hdp_flush_reg nbio_v7_4_hdp_flush_reg = { 193 .ref_and_mask_cp0 = GPU_HDP_FLUSH_DONE__CP0_MASK, 194 .ref_and_mask_cp1 = GPU_HDP_FLUSH_DONE__CP1_MASK, 195 .ref_and_mask_cp2 = GPU_HDP_FLUSH_DONE__CP2_MASK, 196 .ref_and_mask_cp3 = GPU_HDP_FLUSH_DONE__CP3_MASK, 197 .ref_and_mask_cp4 = GPU_HDP_FLUSH_DONE__CP4_MASK, 198 .ref_and_mask_cp5 = GPU_HDP_FLUSH_DONE__CP5_MASK, 199 .ref_and_mask_cp6 = GPU_HDP_FLUSH_DONE__CP6_MASK, 200 .ref_and_mask_cp7 = GPU_HDP_FLUSH_DONE__CP7_MASK, 201 .ref_and_mask_cp8 = GPU_HDP_FLUSH_DONE__CP8_MASK, 202 .ref_and_mask_cp9 = GPU_HDP_FLUSH_DONE__CP9_MASK, 203 .ref_and_mask_sdma0 = GPU_HDP_FLUSH_DONE__SDMA0_MASK, 204 .ref_and_mask_sdma1 = GPU_HDP_FLUSH_DONE__SDMA1_MASK, 205 }; 206 207 static void nbio_v7_4_detect_hw_virt(struct amdgpu_device *adev) 208 { 209 uint32_t reg; 210 211 reg = RREG32_SOC15(NBIO, 0, mmRCC_IOV_FUNC_IDENTIFIER); 212 if (reg & 1) 213 adev->virt.caps |= AMDGPU_SRIOV_CAPS_IS_VF; 214 215 if (reg & 0x80000000) 216 adev->virt.caps |= AMDGPU_SRIOV_CAPS_ENABLE_IOV; 217 218 if (!reg) { 219 if (is_virtual_machine()) /* passthrough mode exclus sriov mod */ 220 adev->virt.caps |= AMDGPU_PASSTHROUGH_MODE; 221 } 222 } 223 224 static void nbio_v7_4_init_registers(struct amdgpu_device *adev) 225 { 226 uint32_t def, data; 227 228 def = data = RREG32_PCIE(smnPCIE_CI_CNTL); 229 data = REG_SET_FIELD(data, PCIE_CI_CNTL, CI_SLV_ORDERING_DIS, 1); 230 231 if (def != data) 232 WREG32_PCIE(smnPCIE_CI_CNTL, data); 233 } 234 235 const struct amdgpu_nbio_funcs nbio_v7_4_funcs = { 236 .hdp_flush_reg = &nbio_v7_4_hdp_flush_reg, 237 .get_hdp_flush_req_offset = nbio_v7_4_get_hdp_flush_req_offset, 238 .get_hdp_flush_done_offset = nbio_v7_4_get_hdp_flush_done_offset, 239 .get_pcie_index_offset = nbio_v7_4_get_pcie_index_offset, 240 .get_pcie_data_offset = nbio_v7_4_get_pcie_data_offset, 241 .get_rev_id = nbio_v7_4_get_rev_id, 242 .mc_access_enable = nbio_v7_4_mc_access_enable, 243 .hdp_flush = nbio_v7_4_hdp_flush, 244 .get_memsize = nbio_v7_4_get_memsize, 245 .sdma_doorbell_range = nbio_v7_4_sdma_doorbell_range, 246 .enable_doorbell_aperture = nbio_v7_4_enable_doorbell_aperture, 247 .enable_doorbell_selfring_aperture = nbio_v7_4_enable_doorbell_selfring_aperture, 248 .ih_doorbell_range = nbio_v7_4_ih_doorbell_range, 249 .update_medium_grain_clock_gating = nbio_v7_4_update_medium_grain_clock_gating, 250 .update_medium_grain_light_sleep = nbio_v7_4_update_medium_grain_light_sleep, 251 .get_clockgating_state = nbio_v7_4_get_clockgating_state, 252 .ih_control = nbio_v7_4_ih_control, 253 .init_registers = nbio_v7_4_init_registers, 254 .detect_hw_virt = nbio_v7_4_detect_hw_virt, 255 }; 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