1 /* 2 * Copyright 2018 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include "amdgpu.h" 24 #include "amdgpu_atombios.h" 25 #include "nbio_v7_4.h" 26 #include "amdgpu_ras.h" 27 28 #include "nbio/nbio_7_4_offset.h" 29 #include "nbio/nbio_7_4_sh_mask.h" 30 #include "nbio/nbio_7_4_0_smn.h" 31 #include "ivsrcid/nbio/irqsrcs_nbif_7_4.h" 32 #include <uapi/linux/kfd_ioctl.h> 33 34 #define smnPCIE_LC_CNTL 0x11140280 35 #define smnPCIE_LC_CNTL3 0x111402d4 36 #define smnPCIE_LC_CNTL6 0x111402ec 37 #define smnPCIE_LC_CNTL7 0x111402f0 38 #define smnNBIF_MGCG_CTRL_LCLK 0x1013a21c 39 #define smnRCC_BIF_STRAP3 0x1012348c 40 #define RCC_BIF_STRAP3__STRAP_VLINK_ASPM_IDLE_TIMER_MASK 0x0000FFFFL 41 #define RCC_BIF_STRAP3__STRAP_VLINK_PM_L1_ENTRY_TIMER_MASK 0xFFFF0000L 42 #define smnRCC_BIF_STRAP5 0x10123494 43 #define RCC_BIF_STRAP5__STRAP_VLINK_LDN_ENTRY_TIMER_MASK 0x0000FFFFL 44 #define smnBIF_CFG_DEV0_EPF0_DEVICE_CNTL2 0x1014008c 45 #define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__LTR_EN_MASK 0x0400L 46 #define smnBIF_CFG_DEV0_EPF0_PCIE_LTR_CAP 0x10140324 47 #define smnPSWUSP0_PCIE_LC_CNTL2 0x111402c4 48 #define smnRCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL 0x10123538 49 #define smnRCC_BIF_STRAP2 0x10123488 50 #define RCC_BIF_STRAP2__STRAP_LTR_IN_ASPML1_DIS_MASK 0x00004000L 51 #define RCC_BIF_STRAP3__STRAP_VLINK_ASPM_IDLE_TIMER__SHIFT 0x0 52 #define RCC_BIF_STRAP3__STRAP_VLINK_PM_L1_ENTRY_TIMER__SHIFT 0x10 53 #define RCC_BIF_STRAP5__STRAP_VLINK_LDN_ENTRY_TIMER__SHIFT 0x0 54 55 /* 56 * These are nbio v7_4_1 registers mask. Temporarily define these here since 57 * nbio v7_4_1 header is incomplete. 58 */ 59 #define GPU_HDP_FLUSH_DONE__RSVD_ENG0_MASK 0x00001000L 60 #define GPU_HDP_FLUSH_DONE__RSVD_ENG1_MASK 0x00002000L 61 #define GPU_HDP_FLUSH_DONE__RSVD_ENG2_MASK 0x00004000L 62 #define GPU_HDP_FLUSH_DONE__RSVD_ENG3_MASK 0x00008000L 63 #define GPU_HDP_FLUSH_DONE__RSVD_ENG4_MASK 0x00010000L 64 #define GPU_HDP_FLUSH_DONE__RSVD_ENG5_MASK 0x00020000L 65 66 #define mmBIF_MMSCH1_DOORBELL_RANGE 0x01dc 67 #define mmBIF_MMSCH1_DOORBELL_RANGE_BASE_IDX 2 68 //BIF_MMSCH1_DOORBELL_RANGE 69 #define BIF_MMSCH1_DOORBELL_RANGE__OFFSET__SHIFT 0x2 70 #define BIF_MMSCH1_DOORBELL_RANGE__SIZE__SHIFT 0x10 71 #define BIF_MMSCH1_DOORBELL_RANGE__OFFSET_MASK 0x00000FFCL 72 #define BIF_MMSCH1_DOORBELL_RANGE__SIZE_MASK 0x001F0000L 73 74 #define BIF_MMSCH1_DOORBELL_RANGE__OFFSET_MASK 0x00000FFCL 75 #define BIF_MMSCH1_DOORBELL_RANGE__SIZE_MASK 0x001F0000L 76 77 #define mmBIF_MMSCH1_DOORBELL_RANGE_ALDE 0x01d8 78 #define mmBIF_MMSCH1_DOORBELL_RANGE_ALDE_BASE_IDX 2 79 //BIF_MMSCH1_DOORBELL_ALDE_RANGE 80 #define BIF_MMSCH1_DOORBELL_RANGE_ALDE__OFFSET__SHIFT 0x2 81 #define BIF_MMSCH1_DOORBELL_RANGE_ALDE__SIZE__SHIFT 0x10 82 #define BIF_MMSCH1_DOORBELL_RANGE_ALDE__OFFSET_MASK 0x00000FFCL 83 #define BIF_MMSCH1_DOORBELL_RANGE_ALDE__SIZE_MASK 0x001F0000L 84 85 #define mmRCC_DEV0_EPF0_STRAP0_ALDE 0x0015 86 #define mmRCC_DEV0_EPF0_STRAP0_ALDE_BASE_IDX 2 87 88 static void nbio_v7_4_query_ras_error_count(struct amdgpu_device *adev, 89 void *ras_error_status); 90 91 static void nbio_v7_4_remap_hdp_registers(struct amdgpu_device *adev) 92 { 93 WREG32_SOC15(NBIO, 0, mmREMAP_HDP_MEM_FLUSH_CNTL, 94 adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL); 95 WREG32_SOC15(NBIO, 0, mmREMAP_HDP_REG_FLUSH_CNTL, 96 adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_REG_FLUSH_CNTL); 97 } 98 99 static u32 nbio_v7_4_get_rev_id(struct amdgpu_device *adev) 100 { 101 u32 tmp; 102 103 if (adev->asic_type == CHIP_ALDEBARAN) 104 tmp = RREG32_SOC15(NBIO, 0, mmRCC_DEV0_EPF0_STRAP0_ALDE); 105 else 106 tmp = RREG32_SOC15(NBIO, 0, mmRCC_DEV0_EPF0_STRAP0); 107 108 tmp &= RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0_MASK; 109 tmp >>= RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0__SHIFT; 110 111 return tmp; 112 } 113 114 static void nbio_v7_4_mc_access_enable(struct amdgpu_device *adev, bool enable) 115 { 116 if (enable) 117 WREG32_SOC15(NBIO, 0, mmBIF_FB_EN, 118 BIF_FB_EN__FB_READ_EN_MASK | BIF_FB_EN__FB_WRITE_EN_MASK); 119 else 120 WREG32_SOC15(NBIO, 0, mmBIF_FB_EN, 0); 121 } 122 123 static u32 nbio_v7_4_get_memsize(struct amdgpu_device *adev) 124 { 125 return RREG32_SOC15(NBIO, 0, mmRCC_CONFIG_MEMSIZE); 126 } 127 128 static void nbio_v7_4_sdma_doorbell_range(struct amdgpu_device *adev, int instance, 129 bool use_doorbell, int doorbell_index, int doorbell_size) 130 { 131 u32 reg, doorbell_range; 132 133 if (instance < 2) { 134 reg = instance + 135 SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA0_DOORBELL_RANGE); 136 } else { 137 /* 138 * These registers address of SDMA2~7 is not consecutive 139 * from SDMA0~1. Need plus 4 dwords offset. 140 * 141 * BIF_SDMA0_DOORBELL_RANGE: 0x3bc0 142 * BIF_SDMA1_DOORBELL_RANGE: 0x3bc4 143 * BIF_SDMA2_DOORBELL_RANGE: 0x3bd8 144 + * BIF_SDMA4_DOORBELL_RANGE: 145 + * ARCTURUS: 0x3be0 146 + * ALDEBARAN: 0x3be4 147 */ 148 if (adev->asic_type == CHIP_ALDEBARAN && instance == 4) 149 reg = instance + 0x4 + 0x1 + 150 SOC15_REG_OFFSET(NBIO, 0, 151 mmBIF_SDMA0_DOORBELL_RANGE); 152 else 153 reg = instance + 0x4 + 154 SOC15_REG_OFFSET(NBIO, 0, 155 mmBIF_SDMA0_DOORBELL_RANGE); 156 } 157 158 doorbell_range = RREG32(reg); 159 160 if (use_doorbell) { 161 doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, OFFSET, doorbell_index); 162 doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, SIZE, doorbell_size); 163 } else 164 doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, SIZE, 0); 165 166 WREG32(reg, doorbell_range); 167 } 168 169 static void nbio_v7_4_vcn_doorbell_range(struct amdgpu_device *adev, bool use_doorbell, 170 int doorbell_index, int instance) 171 { 172 u32 reg; 173 u32 doorbell_range; 174 175 if (instance) { 176 if (adev->asic_type == CHIP_ALDEBARAN) 177 reg = SOC15_REG_OFFSET(NBIO, 0, mmBIF_MMSCH1_DOORBELL_RANGE_ALDE); 178 else 179 reg = SOC15_REG_OFFSET(NBIO, 0, mmBIF_MMSCH1_DOORBELL_RANGE); 180 } else 181 reg = SOC15_REG_OFFSET(NBIO, 0, mmBIF_MMSCH0_DOORBELL_RANGE); 182 183 doorbell_range = RREG32(reg); 184 185 if (use_doorbell) { 186 doorbell_range = REG_SET_FIELD(doorbell_range, 187 BIF_MMSCH0_DOORBELL_RANGE, OFFSET, 188 doorbell_index); 189 doorbell_range = REG_SET_FIELD(doorbell_range, 190 BIF_MMSCH0_DOORBELL_RANGE, SIZE, 8); 191 } else 192 doorbell_range = REG_SET_FIELD(doorbell_range, 193 BIF_MMSCH0_DOORBELL_RANGE, SIZE, 0); 194 195 WREG32(reg, doorbell_range); 196 } 197 198 static void nbio_v7_4_enable_doorbell_aperture(struct amdgpu_device *adev, 199 bool enable) 200 { 201 WREG32_FIELD15(NBIO, 0, RCC_DOORBELL_APER_EN, BIF_DOORBELL_APER_EN, enable ? 1 : 0); 202 } 203 204 static void nbio_v7_4_enable_doorbell_selfring_aperture(struct amdgpu_device *adev, 205 bool enable) 206 { 207 u32 tmp = 0; 208 209 if (enable) { 210 tmp = REG_SET_FIELD(tmp, DOORBELL_SELFRING_GPA_APER_CNTL, DOORBELL_SELFRING_GPA_APER_EN, 1) | 211 REG_SET_FIELD(tmp, DOORBELL_SELFRING_GPA_APER_CNTL, DOORBELL_SELFRING_GPA_APER_MODE, 1) | 212 REG_SET_FIELD(tmp, DOORBELL_SELFRING_GPA_APER_CNTL, DOORBELL_SELFRING_GPA_APER_SIZE, 0); 213 214 WREG32_SOC15(NBIO, 0, mmDOORBELL_SELFRING_GPA_APER_BASE_LOW, 215 lower_32_bits(adev->doorbell.base)); 216 WREG32_SOC15(NBIO, 0, mmDOORBELL_SELFRING_GPA_APER_BASE_HIGH, 217 upper_32_bits(adev->doorbell.base)); 218 } 219 220 WREG32_SOC15(NBIO, 0, mmDOORBELL_SELFRING_GPA_APER_CNTL, tmp); 221 } 222 223 static void nbio_v7_4_ih_doorbell_range(struct amdgpu_device *adev, 224 bool use_doorbell, int doorbell_index) 225 { 226 u32 ih_doorbell_range = RREG32_SOC15(NBIO, 0 , mmBIF_IH_DOORBELL_RANGE); 227 228 if (use_doorbell) { 229 ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, BIF_IH_DOORBELL_RANGE, OFFSET, doorbell_index); 230 ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, BIF_IH_DOORBELL_RANGE, SIZE, 4); 231 } else 232 ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, BIF_IH_DOORBELL_RANGE, SIZE, 0); 233 234 WREG32_SOC15(NBIO, 0, mmBIF_IH_DOORBELL_RANGE, ih_doorbell_range); 235 } 236 237 238 static void nbio_v7_4_update_medium_grain_clock_gating(struct amdgpu_device *adev, 239 bool enable) 240 { 241 //TODO: Add support for v7.4 242 } 243 244 static void nbio_v7_4_update_medium_grain_light_sleep(struct amdgpu_device *adev, 245 bool enable) 246 { 247 uint32_t def, data; 248 249 def = data = RREG32_PCIE(smnPCIE_CNTL2); 250 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_LS)) { 251 data |= (PCIE_CNTL2__SLV_MEM_LS_EN_MASK | 252 PCIE_CNTL2__MST_MEM_LS_EN_MASK | 253 PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK); 254 } else { 255 data &= ~(PCIE_CNTL2__SLV_MEM_LS_EN_MASK | 256 PCIE_CNTL2__MST_MEM_LS_EN_MASK | 257 PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK); 258 } 259 260 if (def != data) 261 WREG32_PCIE(smnPCIE_CNTL2, data); 262 } 263 264 static void nbio_v7_4_get_clockgating_state(struct amdgpu_device *adev, 265 u32 *flags) 266 { 267 int data; 268 269 /* AMD_CG_SUPPORT_BIF_MGCG */ 270 data = RREG32_PCIE(smnCPM_CONTROL); 271 if (data & CPM_CONTROL__LCLK_DYN_GATE_ENABLE_MASK) 272 *flags |= AMD_CG_SUPPORT_BIF_MGCG; 273 274 /* AMD_CG_SUPPORT_BIF_LS */ 275 data = RREG32_PCIE(smnPCIE_CNTL2); 276 if (data & PCIE_CNTL2__SLV_MEM_LS_EN_MASK) 277 *flags |= AMD_CG_SUPPORT_BIF_LS; 278 } 279 280 static void nbio_v7_4_ih_control(struct amdgpu_device *adev) 281 { 282 u32 interrupt_cntl; 283 284 /* setup interrupt control */ 285 WREG32_SOC15(NBIO, 0, mmINTERRUPT_CNTL2, adev->dummy_page_addr >> 8); 286 interrupt_cntl = RREG32_SOC15(NBIO, 0, mmINTERRUPT_CNTL); 287 /* INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=0 - dummy read disabled with msi, enabled without msi 288 * INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=1 - dummy read controlled by IH_DUMMY_RD_EN 289 */ 290 interrupt_cntl = REG_SET_FIELD(interrupt_cntl, INTERRUPT_CNTL, IH_DUMMY_RD_OVERRIDE, 0); 291 /* INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN_MASK=1 if ring is in non-cacheable memory, e.g., vram */ 292 interrupt_cntl = REG_SET_FIELD(interrupt_cntl, INTERRUPT_CNTL, IH_REQ_NONSNOOP_EN, 0); 293 WREG32_SOC15(NBIO, 0, mmINTERRUPT_CNTL, interrupt_cntl); 294 } 295 296 static u32 nbio_v7_4_get_hdp_flush_req_offset(struct amdgpu_device *adev) 297 { 298 return SOC15_REG_OFFSET(NBIO, 0, mmGPU_HDP_FLUSH_REQ); 299 } 300 301 static u32 nbio_v7_4_get_hdp_flush_done_offset(struct amdgpu_device *adev) 302 { 303 return SOC15_REG_OFFSET(NBIO, 0, mmGPU_HDP_FLUSH_DONE); 304 } 305 306 static u32 nbio_v7_4_get_pcie_index_offset(struct amdgpu_device *adev) 307 { 308 return SOC15_REG_OFFSET(NBIO, 0, mmPCIE_INDEX2); 309 } 310 311 static u32 nbio_v7_4_get_pcie_data_offset(struct amdgpu_device *adev) 312 { 313 return SOC15_REG_OFFSET(NBIO, 0, mmPCIE_DATA2); 314 } 315 316 const struct nbio_hdp_flush_reg nbio_v7_4_hdp_flush_reg = { 317 .ref_and_mask_cp0 = GPU_HDP_FLUSH_DONE__CP0_MASK, 318 .ref_and_mask_cp1 = GPU_HDP_FLUSH_DONE__CP1_MASK, 319 .ref_and_mask_cp2 = GPU_HDP_FLUSH_DONE__CP2_MASK, 320 .ref_and_mask_cp3 = GPU_HDP_FLUSH_DONE__CP3_MASK, 321 .ref_and_mask_cp4 = GPU_HDP_FLUSH_DONE__CP4_MASK, 322 .ref_and_mask_cp5 = GPU_HDP_FLUSH_DONE__CP5_MASK, 323 .ref_and_mask_cp6 = GPU_HDP_FLUSH_DONE__CP6_MASK, 324 .ref_and_mask_cp7 = GPU_HDP_FLUSH_DONE__CP7_MASK, 325 .ref_and_mask_cp8 = GPU_HDP_FLUSH_DONE__CP8_MASK, 326 .ref_and_mask_cp9 = GPU_HDP_FLUSH_DONE__CP9_MASK, 327 .ref_and_mask_sdma0 = GPU_HDP_FLUSH_DONE__SDMA0_MASK, 328 .ref_and_mask_sdma1 = GPU_HDP_FLUSH_DONE__SDMA1_MASK, 329 .ref_and_mask_sdma2 = GPU_HDP_FLUSH_DONE__RSVD_ENG0_MASK, 330 .ref_and_mask_sdma3 = GPU_HDP_FLUSH_DONE__RSVD_ENG1_MASK, 331 .ref_and_mask_sdma4 = GPU_HDP_FLUSH_DONE__RSVD_ENG2_MASK, 332 .ref_and_mask_sdma5 = GPU_HDP_FLUSH_DONE__RSVD_ENG3_MASK, 333 .ref_and_mask_sdma6 = GPU_HDP_FLUSH_DONE__RSVD_ENG4_MASK, 334 .ref_and_mask_sdma7 = GPU_HDP_FLUSH_DONE__RSVD_ENG5_MASK, 335 }; 336 337 static void nbio_v7_4_init_registers(struct amdgpu_device *adev) 338 { 339 340 } 341 342 static void nbio_v7_4_handle_ras_controller_intr_no_bifring(struct amdgpu_device *adev) 343 { 344 uint32_t bif_doorbell_intr_cntl; 345 struct ras_manager *obj = amdgpu_ras_find_obj(adev, adev->nbio.ras_if); 346 struct ras_err_data err_data = {0, 0, 0, NULL}; 347 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); 348 349 bif_doorbell_intr_cntl = RREG32_SOC15(NBIO, 0, mmBIF_DOORBELL_INT_CNTL); 350 if (REG_GET_FIELD(bif_doorbell_intr_cntl, 351 BIF_DOORBELL_INT_CNTL, RAS_CNTLR_INTERRUPT_STATUS)) { 352 /* driver has to clear the interrupt status when bif ring is disabled */ 353 bif_doorbell_intr_cntl = REG_SET_FIELD(bif_doorbell_intr_cntl, 354 BIF_DOORBELL_INT_CNTL, 355 RAS_CNTLR_INTERRUPT_CLEAR, 1); 356 WREG32_SOC15(NBIO, 0, mmBIF_DOORBELL_INT_CNTL, bif_doorbell_intr_cntl); 357 358 if (!ras->disable_ras_err_cnt_harvest) { 359 /* 360 * clear error status after ras_controller_intr 361 * according to hw team and count ue number 362 * for query 363 */ 364 nbio_v7_4_query_ras_error_count(adev, &err_data); 365 366 /* logging on error cnt and printing for awareness */ 367 obj->err_data.ue_count += err_data.ue_count; 368 obj->err_data.ce_count += err_data.ce_count; 369 370 if (err_data.ce_count) 371 dev_info(adev->dev, "%ld correctable hardware " 372 "errors detected in %s block, " 373 "no user action is needed.\n", 374 obj->err_data.ce_count, 375 adev->nbio.ras_if->name); 376 377 if (err_data.ue_count) 378 dev_info(adev->dev, "%ld uncorrectable hardware " 379 "errors detected in %s block\n", 380 obj->err_data.ue_count, 381 adev->nbio.ras_if->name); 382 } 383 384 dev_info(adev->dev, "RAS controller interrupt triggered " 385 "by NBIF error\n"); 386 387 /* ras_controller_int is dedicated for nbif ras error, 388 * not the global interrupt for sync flood 389 */ 390 amdgpu_ras_reset_gpu(adev); 391 } 392 } 393 394 static void nbio_v7_4_handle_ras_err_event_athub_intr_no_bifring(struct amdgpu_device *adev) 395 { 396 uint32_t bif_doorbell_intr_cntl; 397 398 bif_doorbell_intr_cntl = RREG32_SOC15(NBIO, 0, mmBIF_DOORBELL_INT_CNTL); 399 if (REG_GET_FIELD(bif_doorbell_intr_cntl, 400 BIF_DOORBELL_INT_CNTL, RAS_ATHUB_ERR_EVENT_INTERRUPT_STATUS)) { 401 /* driver has to clear the interrupt status when bif ring is disabled */ 402 bif_doorbell_intr_cntl = REG_SET_FIELD(bif_doorbell_intr_cntl, 403 BIF_DOORBELL_INT_CNTL, 404 RAS_ATHUB_ERR_EVENT_INTERRUPT_CLEAR, 1); 405 WREG32_SOC15(NBIO, 0, mmBIF_DOORBELL_INT_CNTL, bif_doorbell_intr_cntl); 406 407 amdgpu_ras_global_ras_isr(adev); 408 } 409 } 410 411 412 static int nbio_v7_4_set_ras_controller_irq_state(struct amdgpu_device *adev, 413 struct amdgpu_irq_src *src, 414 unsigned type, 415 enum amdgpu_interrupt_state state) 416 { 417 /* The ras_controller_irq enablement should be done in psp bl when it 418 * tries to enable ras feature. Driver only need to set the correct interrupt 419 * vector for bare-metal and sriov use case respectively 420 */ 421 uint32_t bif_intr_cntl; 422 423 bif_intr_cntl = RREG32_SOC15(NBIO, 0, mmBIF_INTR_CNTL); 424 if (state == AMDGPU_IRQ_STATE_ENABLE) { 425 /* set interrupt vector select bit to 0 to select 426 * vetcor 1 for bare metal case */ 427 bif_intr_cntl = REG_SET_FIELD(bif_intr_cntl, 428 BIF_INTR_CNTL, 429 RAS_INTR_VEC_SEL, 0); 430 WREG32_SOC15(NBIO, 0, mmBIF_INTR_CNTL, bif_intr_cntl); 431 } 432 433 return 0; 434 } 435 436 static int nbio_v7_4_process_ras_controller_irq(struct amdgpu_device *adev, 437 struct amdgpu_irq_src *source, 438 struct amdgpu_iv_entry *entry) 439 { 440 /* By design, the ih cookie for ras_controller_irq should be written 441 * to BIFring instead of general iv ring. However, due to known bif ring 442 * hw bug, it has to be disabled. There is no chance the process function 443 * will be involked. Just left it as a dummy one. 444 */ 445 return 0; 446 } 447 448 static int nbio_v7_4_set_ras_err_event_athub_irq_state(struct amdgpu_device *adev, 449 struct amdgpu_irq_src *src, 450 unsigned type, 451 enum amdgpu_interrupt_state state) 452 { 453 /* The ras_controller_irq enablement should be done in psp bl when it 454 * tries to enable ras feature. Driver only need to set the correct interrupt 455 * vector for bare-metal and sriov use case respectively 456 */ 457 uint32_t bif_intr_cntl; 458 459 bif_intr_cntl = RREG32_SOC15(NBIO, 0, mmBIF_INTR_CNTL); 460 if (state == AMDGPU_IRQ_STATE_ENABLE) { 461 /* set interrupt vector select bit to 0 to select 462 * vetcor 1 for bare metal case */ 463 bif_intr_cntl = REG_SET_FIELD(bif_intr_cntl, 464 BIF_INTR_CNTL, 465 RAS_INTR_VEC_SEL, 0); 466 WREG32_SOC15(NBIO, 0, mmBIF_INTR_CNTL, bif_intr_cntl); 467 } 468 469 return 0; 470 } 471 472 static int nbio_v7_4_process_err_event_athub_irq(struct amdgpu_device *adev, 473 struct amdgpu_irq_src *source, 474 struct amdgpu_iv_entry *entry) 475 { 476 /* By design, the ih cookie for err_event_athub_irq should be written 477 * to BIFring instead of general iv ring. However, due to known bif ring 478 * hw bug, it has to be disabled. There is no chance the process function 479 * will be involked. Just left it as a dummy one. 480 */ 481 return 0; 482 } 483 484 static const struct amdgpu_irq_src_funcs nbio_v7_4_ras_controller_irq_funcs = { 485 .set = nbio_v7_4_set_ras_controller_irq_state, 486 .process = nbio_v7_4_process_ras_controller_irq, 487 }; 488 489 static const struct amdgpu_irq_src_funcs nbio_v7_4_ras_err_event_athub_irq_funcs = { 490 .set = nbio_v7_4_set_ras_err_event_athub_irq_state, 491 .process = nbio_v7_4_process_err_event_athub_irq, 492 }; 493 494 static int nbio_v7_4_init_ras_controller_interrupt (struct amdgpu_device *adev) 495 { 496 int r; 497 498 /* init the irq funcs */ 499 adev->nbio.ras_controller_irq.funcs = 500 &nbio_v7_4_ras_controller_irq_funcs; 501 adev->nbio.ras_controller_irq.num_types = 1; 502 503 /* register ras controller interrupt */ 504 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_BIF, 505 NBIF_7_4__SRCID__RAS_CONTROLLER_INTERRUPT, 506 &adev->nbio.ras_controller_irq); 507 508 return r; 509 } 510 511 static int nbio_v7_4_init_ras_err_event_athub_interrupt (struct amdgpu_device *adev) 512 { 513 514 int r; 515 516 /* init the irq funcs */ 517 adev->nbio.ras_err_event_athub_irq.funcs = 518 &nbio_v7_4_ras_err_event_athub_irq_funcs; 519 adev->nbio.ras_err_event_athub_irq.num_types = 1; 520 521 /* register ras err event athub interrupt */ 522 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_BIF, 523 NBIF_7_4__SRCID__ERREVENT_ATHUB_INTERRUPT, 524 &adev->nbio.ras_err_event_athub_irq); 525 526 return r; 527 } 528 529 #define smnPARITY_ERROR_STATUS_UNCORR_GRP2 0x13a20030 530 531 static void nbio_v7_4_query_ras_error_count(struct amdgpu_device *adev, 532 void *ras_error_status) 533 { 534 uint32_t global_sts, central_sts, int_eoi, parity_sts; 535 uint32_t corr, fatal, non_fatal; 536 struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status; 537 538 global_sts = RREG32_PCIE(smnRAS_GLOBAL_STATUS_LO); 539 corr = REG_GET_FIELD(global_sts, RAS_GLOBAL_STATUS_LO, ParityErrCorr); 540 fatal = REG_GET_FIELD(global_sts, RAS_GLOBAL_STATUS_LO, ParityErrFatal); 541 non_fatal = REG_GET_FIELD(global_sts, RAS_GLOBAL_STATUS_LO, 542 ParityErrNonFatal); 543 parity_sts = RREG32_PCIE(smnPARITY_ERROR_STATUS_UNCORR_GRP2); 544 545 if (corr) 546 err_data->ce_count++; 547 if (fatal) 548 err_data->ue_count++; 549 550 if (corr || fatal || non_fatal) { 551 central_sts = RREG32_PCIE(smnBIFL_RAS_CENTRAL_STATUS); 552 /* clear error status register */ 553 WREG32_PCIE(smnRAS_GLOBAL_STATUS_LO, global_sts); 554 555 if (fatal) 556 /* clear parity fatal error indication field */ 557 WREG32_PCIE(smnPARITY_ERROR_STATUS_UNCORR_GRP2, 558 parity_sts); 559 560 if (REG_GET_FIELD(central_sts, BIFL_RAS_CENTRAL_STATUS, 561 BIFL_RasContller_Intr_Recv)) { 562 /* clear interrupt status register */ 563 WREG32_PCIE(smnBIFL_RAS_CENTRAL_STATUS, central_sts); 564 int_eoi = RREG32_PCIE(smnIOHC_INTERRUPT_EOI); 565 int_eoi = REG_SET_FIELD(int_eoi, 566 IOHC_INTERRUPT_EOI, SMI_EOI, 1); 567 WREG32_PCIE(smnIOHC_INTERRUPT_EOI, int_eoi); 568 } 569 } 570 } 571 572 static void nbio_v7_4_enable_doorbell_interrupt(struct amdgpu_device *adev, 573 bool enable) 574 { 575 WREG32_FIELD15(NBIO, 0, BIF_DOORBELL_INT_CNTL, 576 DOORBELL_INTERRUPT_DISABLE, enable ? 0 : 1); 577 } 578 579 const struct amdgpu_nbio_ras_funcs nbio_v7_4_ras_funcs = { 580 .handle_ras_controller_intr_no_bifring = nbio_v7_4_handle_ras_controller_intr_no_bifring, 581 .handle_ras_err_event_athub_intr_no_bifring = nbio_v7_4_handle_ras_err_event_athub_intr_no_bifring, 582 .init_ras_controller_interrupt = nbio_v7_4_init_ras_controller_interrupt, 583 .init_ras_err_event_athub_interrupt = nbio_v7_4_init_ras_err_event_athub_interrupt, 584 .query_ras_error_count = nbio_v7_4_query_ras_error_count, 585 .ras_late_init = amdgpu_nbio_ras_late_init, 586 .ras_fini = amdgpu_nbio_ras_fini, 587 }; 588 589 static void nbio_v7_4_program_ltr(struct amdgpu_device *adev) 590 { 591 uint32_t def, data; 592 593 WREG32_PCIE(smnRCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL, 0x75EB); 594 595 def = data = RREG32_PCIE(smnRCC_BIF_STRAP2); 596 data &= ~RCC_BIF_STRAP2__STRAP_LTR_IN_ASPML1_DIS_MASK; 597 if (def != data) 598 WREG32_PCIE(smnRCC_BIF_STRAP2, data); 599 600 def = data = RREG32_PCIE(smnRCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL); 601 data &= ~EP_PCIE_TX_LTR_CNTL__LTR_PRIV_MSG_DIS_IN_PM_NON_D0_MASK; 602 if (def != data) 603 WREG32_PCIE(smnRCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL, data); 604 605 def = data = RREG32_PCIE(smnBIF_CFG_DEV0_EPF0_DEVICE_CNTL2); 606 data |= BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__LTR_EN_MASK; 607 if (def != data) 608 WREG32_PCIE(smnBIF_CFG_DEV0_EPF0_DEVICE_CNTL2, data); 609 } 610 611 static void nbio_v7_4_program_aspm(struct amdgpu_device *adev) 612 { 613 uint32_t def, data; 614 615 def = data = RREG32_PCIE(smnPCIE_LC_CNTL); 616 data &= ~PCIE_LC_CNTL__LC_L1_INACTIVITY_MASK; 617 data &= ~PCIE_LC_CNTL__LC_L0S_INACTIVITY_MASK; 618 data |= PCIE_LC_CNTL__LC_PMI_TO_L1_DIS_MASK; 619 if (def != data) 620 WREG32_PCIE(smnPCIE_LC_CNTL, data); 621 622 def = data = RREG32_PCIE(smnPCIE_LC_CNTL7); 623 data |= PCIE_LC_CNTL7__LC_NBIF_ASPM_INPUT_EN_MASK; 624 if (def != data) 625 WREG32_PCIE(smnPCIE_LC_CNTL7, data); 626 627 def = data = RREG32_PCIE(smnNBIF_MGCG_CTRL_LCLK); 628 data |= NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_REG_DIS_LCLK_MASK; 629 if (def != data) 630 WREG32_PCIE(smnNBIF_MGCG_CTRL_LCLK, data); 631 632 def = data = RREG32_PCIE(smnPCIE_LC_CNTL3); 633 data |= PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK_MASK; 634 if (def != data) 635 WREG32_PCIE(smnPCIE_LC_CNTL3, data); 636 637 def = data = RREG32_PCIE(smnRCC_BIF_STRAP3); 638 data &= ~RCC_BIF_STRAP3__STRAP_VLINK_ASPM_IDLE_TIMER_MASK; 639 data &= ~RCC_BIF_STRAP3__STRAP_VLINK_PM_L1_ENTRY_TIMER_MASK; 640 if (def != data) 641 WREG32_PCIE(smnRCC_BIF_STRAP3, data); 642 643 def = data = RREG32_PCIE(smnRCC_BIF_STRAP5); 644 data &= ~RCC_BIF_STRAP5__STRAP_VLINK_LDN_ENTRY_TIMER_MASK; 645 if (def != data) 646 WREG32_PCIE(smnRCC_BIF_STRAP5, data); 647 648 def = data = RREG32_PCIE(smnBIF_CFG_DEV0_EPF0_DEVICE_CNTL2); 649 data &= ~BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__LTR_EN_MASK; 650 if (def != data) 651 WREG32_PCIE(smnBIF_CFG_DEV0_EPF0_DEVICE_CNTL2, data); 652 653 WREG32_PCIE(smnBIF_CFG_DEV0_EPF0_PCIE_LTR_CAP, 0x10011001); 654 655 def = data = RREG32_PCIE(smnPSWUSP0_PCIE_LC_CNTL2); 656 data |= PSWUSP0_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1_MASK | 657 PSWUSP0_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23_MASK; 658 data &= ~PSWUSP0_PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS_MASK; 659 if (def != data) 660 WREG32_PCIE(smnPSWUSP0_PCIE_LC_CNTL2, data); 661 662 def = data = RREG32_PCIE(smnPCIE_LC_CNTL6); 663 data |= PCIE_LC_CNTL6__LC_L1_POWERDOWN_MASK | 664 PCIE_LC_CNTL6__LC_RX_L0S_STANDBY_EN_MASK; 665 if (def != data) 666 WREG32_PCIE(smnPCIE_LC_CNTL6, data); 667 668 nbio_v7_4_program_ltr(adev); 669 670 def = data = RREG32_PCIE(smnRCC_BIF_STRAP3); 671 data |= 0x5DE0 << RCC_BIF_STRAP3__STRAP_VLINK_ASPM_IDLE_TIMER__SHIFT; 672 data |= 0x0010 << RCC_BIF_STRAP3__STRAP_VLINK_PM_L1_ENTRY_TIMER__SHIFT; 673 if (def != data) 674 WREG32_PCIE(smnRCC_BIF_STRAP3, data); 675 676 def = data = RREG32_PCIE(smnRCC_BIF_STRAP5); 677 data |= 0x0010 << RCC_BIF_STRAP5__STRAP_VLINK_LDN_ENTRY_TIMER__SHIFT; 678 if (def != data) 679 WREG32_PCIE(smnRCC_BIF_STRAP5, data); 680 681 def = data = RREG32_PCIE(smnPCIE_LC_CNTL); 682 data &= ~PCIE_LC_CNTL__LC_L0S_INACTIVITY_MASK; 683 data |= 0x9 << PCIE_LC_CNTL__LC_L1_INACTIVITY__SHIFT; 684 data |= 0x1 << PCIE_LC_CNTL__LC_PMI_TO_L1_DIS__SHIFT; 685 if (def != data) 686 WREG32_PCIE(smnPCIE_LC_CNTL, data); 687 688 def = data = RREG32_PCIE(smnPCIE_LC_CNTL3); 689 data &= ~PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK_MASK; 690 if (def != data) 691 WREG32_PCIE(smnPCIE_LC_CNTL3, data); 692 } 693 694 const struct amdgpu_nbio_funcs nbio_v7_4_funcs = { 695 .get_hdp_flush_req_offset = nbio_v7_4_get_hdp_flush_req_offset, 696 .get_hdp_flush_done_offset = nbio_v7_4_get_hdp_flush_done_offset, 697 .get_pcie_index_offset = nbio_v7_4_get_pcie_index_offset, 698 .get_pcie_data_offset = nbio_v7_4_get_pcie_data_offset, 699 .get_rev_id = nbio_v7_4_get_rev_id, 700 .mc_access_enable = nbio_v7_4_mc_access_enable, 701 .get_memsize = nbio_v7_4_get_memsize, 702 .sdma_doorbell_range = nbio_v7_4_sdma_doorbell_range, 703 .vcn_doorbell_range = nbio_v7_4_vcn_doorbell_range, 704 .enable_doorbell_aperture = nbio_v7_4_enable_doorbell_aperture, 705 .enable_doorbell_selfring_aperture = nbio_v7_4_enable_doorbell_selfring_aperture, 706 .ih_doorbell_range = nbio_v7_4_ih_doorbell_range, 707 .enable_doorbell_interrupt = nbio_v7_4_enable_doorbell_interrupt, 708 .update_medium_grain_clock_gating = nbio_v7_4_update_medium_grain_clock_gating, 709 .update_medium_grain_light_sleep = nbio_v7_4_update_medium_grain_light_sleep, 710 .get_clockgating_state = nbio_v7_4_get_clockgating_state, 711 .ih_control = nbio_v7_4_ih_control, 712 .init_registers = nbio_v7_4_init_registers, 713 .remap_hdp_registers = nbio_v7_4_remap_hdp_registers, 714 .program_aspm = nbio_v7_4_program_aspm, 715 }; 716