1fe3c9489SFeifei Xu /* 2fe3c9489SFeifei Xu * Copyright 2018 Advanced Micro Devices, Inc. 3fe3c9489SFeifei Xu * 4fe3c9489SFeifei Xu * Permission is hereby granted, free of charge, to any person obtaining a 5fe3c9489SFeifei Xu * copy of this software and associated documentation files (the "Software"), 6fe3c9489SFeifei Xu * to deal in the Software without restriction, including without limitation 7fe3c9489SFeifei Xu * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8fe3c9489SFeifei Xu * and/or sell copies of the Software, and to permit persons to whom the 9fe3c9489SFeifei Xu * Software is furnished to do so, subject to the following conditions: 10fe3c9489SFeifei Xu * 11fe3c9489SFeifei Xu * The above copyright notice and this permission notice shall be included in 12fe3c9489SFeifei Xu * all copies or substantial portions of the Software. 13fe3c9489SFeifei Xu * 14fe3c9489SFeifei Xu * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15fe3c9489SFeifei Xu * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16fe3c9489SFeifei Xu * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17fe3c9489SFeifei Xu * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18fe3c9489SFeifei Xu * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19fe3c9489SFeifei Xu * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20fe3c9489SFeifei Xu * OTHER DEALINGS IN THE SOFTWARE. 21fe3c9489SFeifei Xu * 22fe3c9489SFeifei Xu */ 23fe3c9489SFeifei Xu #include "amdgpu.h" 24fe3c9489SFeifei Xu #include "amdgpu_atombios.h" 25fe3c9489SFeifei Xu #include "nbio_v7_4.h" 269ad1dc29SHawking Zhang #include "amdgpu_ras.h" 27fe3c9489SFeifei Xu 28fe3c9489SFeifei Xu #include "nbio/nbio_7_4_offset.h" 29fe3c9489SFeifei Xu #include "nbio/nbio_7_4_sh_mask.h" 30a0bb79e2SKent Russell #include "nbio/nbio_7_4_0_smn.h" 314e644fffSHawking Zhang #include "ivsrcid/nbio/irqsrcs_nbif_7_4.h" 3288807dc8SOak Zeng #include <uapi/linux/kfd_ioctl.h> 33fe3c9489SFeifei Xu 34fe3c9489SFeifei Xu #define smnNBIF_MGCG_CTRL_LCLK 0x1013a21c 35fe3c9489SFeifei Xu 360fe6a7b4SLe Ma /* 370fe6a7b4SLe Ma * These are nbio v7_4_1 registers mask. Temporarily define these here since 380fe6a7b4SLe Ma * nbio v7_4_1 header is incomplete. 390fe6a7b4SLe Ma */ 400fe6a7b4SLe Ma #define GPU_HDP_FLUSH_DONE__RSVD_ENG0_MASK 0x00001000L 410fe6a7b4SLe Ma #define GPU_HDP_FLUSH_DONE__RSVD_ENG1_MASK 0x00002000L 420fe6a7b4SLe Ma #define GPU_HDP_FLUSH_DONE__RSVD_ENG2_MASK 0x00004000L 430fe6a7b4SLe Ma #define GPU_HDP_FLUSH_DONE__RSVD_ENG3_MASK 0x00008000L 440fe6a7b4SLe Ma #define GPU_HDP_FLUSH_DONE__RSVD_ENG4_MASK 0x00010000L 450fe6a7b4SLe Ma #define GPU_HDP_FLUSH_DONE__RSVD_ENG5_MASK 0x00020000L 460fe6a7b4SLe Ma 47989b6a05SJames Zhu #define mmBIF_MMSCH1_DOORBELL_RANGE 0x01dc 48989b6a05SJames Zhu #define mmBIF_MMSCH1_DOORBELL_RANGE_BASE_IDX 2 49989b6a05SJames Zhu //BIF_MMSCH1_DOORBELL_RANGE 50989b6a05SJames Zhu #define BIF_MMSCH1_DOORBELL_RANGE__OFFSET__SHIFT 0x2 51989b6a05SJames Zhu #define BIF_MMSCH1_DOORBELL_RANGE__SIZE__SHIFT 0x10 52989b6a05SJames Zhu #define BIF_MMSCH1_DOORBELL_RANGE__OFFSET_MASK 0x00000FFCL 53989b6a05SJames Zhu #define BIF_MMSCH1_DOORBELL_RANGE__SIZE_MASK 0x001F0000L 54989b6a05SJames Zhu 55*7ce29357SJames Zhu #define BIF_MMSCH1_DOORBELL_RANGE__OFFSET_MASK 0x00000FFCL 56*7ce29357SJames Zhu #define BIF_MMSCH1_DOORBELL_RANGE__SIZE_MASK 0x001F0000L 57*7ce29357SJames Zhu 58*7ce29357SJames Zhu #define mmBIF_MMSCH1_DOORBELL_RANGE_ALDE 0x01d8 59*7ce29357SJames Zhu #define mmBIF_MMSCH1_DOORBELL_RANGE_ALDE_BASE_IDX 2 60*7ce29357SJames Zhu //BIF_MMSCH1_DOORBELL_ALDE_RANGE 61*7ce29357SJames Zhu #define BIF_MMSCH1_DOORBELL_RANGE_ALDE__OFFSET__SHIFT 0x2 62*7ce29357SJames Zhu #define BIF_MMSCH1_DOORBELL_RANGE_ALDE__SIZE__SHIFT 0x10 63*7ce29357SJames Zhu #define BIF_MMSCH1_DOORBELL_RANGE_ALDE__OFFSET_MASK 0x00000FFCL 64*7ce29357SJames Zhu #define BIF_MMSCH1_DOORBELL_RANGE_ALDE__SIZE_MASK 0x001F0000L 65*7ce29357SJames Zhu 66f8a98f16SHawking Zhang #define mmRCC_DEV0_EPF0_STRAP0_ALDE 0x0015 67f8a98f16SHawking Zhang #define mmRCC_DEV0_EPF0_STRAP0_ALDE_BASE_IDX 2 68f8a98f16SHawking Zhang 6928f87950SLe Ma static void nbio_v7_4_query_ras_error_count(struct amdgpu_device *adev, 7028f87950SLe Ma void *ras_error_status); 7128f87950SLe Ma 7288807dc8SOak Zeng static void nbio_v7_4_remap_hdp_registers(struct amdgpu_device *adev) 7388807dc8SOak Zeng { 7488807dc8SOak Zeng WREG32_SOC15(NBIO, 0, mmREMAP_HDP_MEM_FLUSH_CNTL, 7588807dc8SOak Zeng adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL); 7688807dc8SOak Zeng WREG32_SOC15(NBIO, 0, mmREMAP_HDP_REG_FLUSH_CNTL, 7788807dc8SOak Zeng adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_REG_FLUSH_CNTL); 7888807dc8SOak Zeng } 7988807dc8SOak Zeng 80fe3c9489SFeifei Xu static u32 nbio_v7_4_get_rev_id(struct amdgpu_device *adev) 81fe3c9489SFeifei Xu { 82f8a98f16SHawking Zhang u32 tmp; 83f8a98f16SHawking Zhang 84f8a98f16SHawking Zhang if (adev->asic_type == CHIP_ALDEBARAN) 85f8a98f16SHawking Zhang tmp = RREG32_SOC15(NBIO, 0, mmRCC_DEV0_EPF0_STRAP0_ALDE); 86f8a98f16SHawking Zhang else 87f8a98f16SHawking Zhang tmp = RREG32_SOC15(NBIO, 0, mmRCC_DEV0_EPF0_STRAP0); 88fe3c9489SFeifei Xu 89fe3c9489SFeifei Xu tmp &= RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0_MASK; 90fe3c9489SFeifei Xu tmp >>= RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0__SHIFT; 91fe3c9489SFeifei Xu 92fe3c9489SFeifei Xu return tmp; 93fe3c9489SFeifei Xu } 94fe3c9489SFeifei Xu 95fe3c9489SFeifei Xu static void nbio_v7_4_mc_access_enable(struct amdgpu_device *adev, bool enable) 96fe3c9489SFeifei Xu { 97fe3c9489SFeifei Xu if (enable) 98fe3c9489SFeifei Xu WREG32_SOC15(NBIO, 0, mmBIF_FB_EN, 99fe3c9489SFeifei Xu BIF_FB_EN__FB_READ_EN_MASK | BIF_FB_EN__FB_WRITE_EN_MASK); 100fe3c9489SFeifei Xu else 101fe3c9489SFeifei Xu WREG32_SOC15(NBIO, 0, mmBIF_FB_EN, 0); 102fe3c9489SFeifei Xu } 103fe3c9489SFeifei Xu 104fe3c9489SFeifei Xu static u32 nbio_v7_4_get_memsize(struct amdgpu_device *adev) 105fe3c9489SFeifei Xu { 106fe3c9489SFeifei Xu return RREG32_SOC15(NBIO, 0, mmRCC_CONFIG_MEMSIZE); 107fe3c9489SFeifei Xu } 108fe3c9489SFeifei Xu 109fe3c9489SFeifei Xu static void nbio_v7_4_sdma_doorbell_range(struct amdgpu_device *adev, int instance, 1108987e2e2SOak Zeng bool use_doorbell, int doorbell_index, int doorbell_size) 111fe3c9489SFeifei Xu { 1123d81f67aSLe Ma u32 reg, doorbell_range; 113fe3c9489SFeifei Xu 114759eb38eSLe Ma if (instance < 2) { 1153d81f67aSLe Ma reg = instance + 1163d81f67aSLe Ma SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA0_DOORBELL_RANGE); 117759eb38eSLe Ma } else { 1183d81f67aSLe Ma /* 1193d81f67aSLe Ma * These registers address of SDMA2~7 is not consecutive 1203d81f67aSLe Ma * from SDMA0~1. Need plus 4 dwords offset. 1213d81f67aSLe Ma * 1223d81f67aSLe Ma * BIF_SDMA0_DOORBELL_RANGE: 0x3bc0 1233d81f67aSLe Ma * BIF_SDMA1_DOORBELL_RANGE: 0x3bc4 1243d81f67aSLe Ma * BIF_SDMA2_DOORBELL_RANGE: 0x3bd8 125759eb38eSLe Ma + * BIF_SDMA4_DOORBELL_RANGE: 126759eb38eSLe Ma + * ARCTURUS: 0x3be0 127759eb38eSLe Ma + * ALDEBARAN: 0x3be4 1283d81f67aSLe Ma */ 129759eb38eSLe Ma if (adev->asic_type == CHIP_ALDEBARAN && instance == 4) 130759eb38eSLe Ma reg = instance + 0x4 + 0x1 + 131759eb38eSLe Ma SOC15_REG_OFFSET(NBIO, 0, 132759eb38eSLe Ma mmBIF_SDMA0_DOORBELL_RANGE); 133759eb38eSLe Ma else 1343d81f67aSLe Ma reg = instance + 0x4 + 135759eb38eSLe Ma SOC15_REG_OFFSET(NBIO, 0, 136759eb38eSLe Ma mmBIF_SDMA0_DOORBELL_RANGE); 137759eb38eSLe Ma } 1383d81f67aSLe Ma 1393d81f67aSLe Ma doorbell_range = RREG32(reg); 140fe3c9489SFeifei Xu 141fe3c9489SFeifei Xu if (use_doorbell) { 142fe3c9489SFeifei Xu doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, OFFSET, doorbell_index); 1438987e2e2SOak Zeng doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, SIZE, doorbell_size); 144fe3c9489SFeifei Xu } else 145fe3c9489SFeifei Xu doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, SIZE, 0); 146fe3c9489SFeifei Xu 147fe3c9489SFeifei Xu WREG32(reg, doorbell_range); 148fe3c9489SFeifei Xu } 149fe3c9489SFeifei Xu 15039a5053fSLeo Liu static void nbio_v7_4_vcn_doorbell_range(struct amdgpu_device *adev, bool use_doorbell, 151989b6a05SJames Zhu int doorbell_index, int instance) 15239a5053fSLeo Liu { 153989b6a05SJames Zhu u32 reg; 154989b6a05SJames Zhu u32 doorbell_range; 15539a5053fSLeo Liu 156*7ce29357SJames Zhu if (instance) { 157*7ce29357SJames Zhu if (adev->asic_type == CHIP_ALDEBARAN) 158*7ce29357SJames Zhu reg = SOC15_REG_OFFSET(NBIO, 0, mmBIF_MMSCH1_DOORBELL_RANGE_ALDE); 159989b6a05SJames Zhu else 160*7ce29357SJames Zhu reg = SOC15_REG_OFFSET(NBIO, 0, mmBIF_MMSCH1_DOORBELL_RANGE); 161*7ce29357SJames Zhu } else 162989b6a05SJames Zhu reg = SOC15_REG_OFFSET(NBIO, 0, mmBIF_MMSCH0_DOORBELL_RANGE); 163989b6a05SJames Zhu 164989b6a05SJames Zhu doorbell_range = RREG32(reg); 16539a5053fSLeo Liu 16639a5053fSLeo Liu if (use_doorbell) { 16739a5053fSLeo Liu doorbell_range = REG_SET_FIELD(doorbell_range, 16839a5053fSLeo Liu BIF_MMSCH0_DOORBELL_RANGE, OFFSET, 16939a5053fSLeo Liu doorbell_index); 17039a5053fSLeo Liu doorbell_range = REG_SET_FIELD(doorbell_range, 17139a5053fSLeo Liu BIF_MMSCH0_DOORBELL_RANGE, SIZE, 8); 17239a5053fSLeo Liu } else 17339a5053fSLeo Liu doorbell_range = REG_SET_FIELD(doorbell_range, 17439a5053fSLeo Liu BIF_MMSCH0_DOORBELL_RANGE, SIZE, 0); 17539a5053fSLeo Liu 17639a5053fSLeo Liu WREG32(reg, doorbell_range); 17739a5053fSLeo Liu } 17839a5053fSLeo Liu 179fe3c9489SFeifei Xu static void nbio_v7_4_enable_doorbell_aperture(struct amdgpu_device *adev, 180fe3c9489SFeifei Xu bool enable) 181fe3c9489SFeifei Xu { 182fe3c9489SFeifei Xu WREG32_FIELD15(NBIO, 0, RCC_DOORBELL_APER_EN, BIF_DOORBELL_APER_EN, enable ? 1 : 0); 183fe3c9489SFeifei Xu } 184fe3c9489SFeifei Xu 185fe3c9489SFeifei Xu static void nbio_v7_4_enable_doorbell_selfring_aperture(struct amdgpu_device *adev, 186fe3c9489SFeifei Xu bool enable) 187fe3c9489SFeifei Xu { 18812292519SJay Cornwall u32 tmp = 0; 189fe3c9489SFeifei Xu 19012292519SJay Cornwall if (enable) { 19112292519SJay Cornwall tmp = REG_SET_FIELD(tmp, DOORBELL_SELFRING_GPA_APER_CNTL, DOORBELL_SELFRING_GPA_APER_EN, 1) | 19212292519SJay Cornwall REG_SET_FIELD(tmp, DOORBELL_SELFRING_GPA_APER_CNTL, DOORBELL_SELFRING_GPA_APER_MODE, 1) | 19312292519SJay Cornwall REG_SET_FIELD(tmp, DOORBELL_SELFRING_GPA_APER_CNTL, DOORBELL_SELFRING_GPA_APER_SIZE, 0); 19412292519SJay Cornwall 19512292519SJay Cornwall WREG32_SOC15(NBIO, 0, mmDOORBELL_SELFRING_GPA_APER_BASE_LOW, 19612292519SJay Cornwall lower_32_bits(adev->doorbell.base)); 19712292519SJay Cornwall WREG32_SOC15(NBIO, 0, mmDOORBELL_SELFRING_GPA_APER_BASE_HIGH, 19812292519SJay Cornwall upper_32_bits(adev->doorbell.base)); 19912292519SJay Cornwall } 20012292519SJay Cornwall 20112292519SJay Cornwall WREG32_SOC15(NBIO, 0, mmDOORBELL_SELFRING_GPA_APER_CNTL, tmp); 202fe3c9489SFeifei Xu } 203fe3c9489SFeifei Xu 204fe3c9489SFeifei Xu static void nbio_v7_4_ih_doorbell_range(struct amdgpu_device *adev, 205fe3c9489SFeifei Xu bool use_doorbell, int doorbell_index) 206fe3c9489SFeifei Xu { 207fe3c9489SFeifei Xu u32 ih_doorbell_range = RREG32_SOC15(NBIO, 0 , mmBIF_IH_DOORBELL_RANGE); 208fe3c9489SFeifei Xu 209fe3c9489SFeifei Xu if (use_doorbell) { 210fe3c9489SFeifei Xu ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, BIF_IH_DOORBELL_RANGE, OFFSET, doorbell_index); 211b635ae87SAlex Sierra ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, BIF_IH_DOORBELL_RANGE, SIZE, 4); 212fe3c9489SFeifei Xu } else 213fe3c9489SFeifei Xu ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, BIF_IH_DOORBELL_RANGE, SIZE, 0); 214fe3c9489SFeifei Xu 215fe3c9489SFeifei Xu WREG32_SOC15(NBIO, 0, mmBIF_IH_DOORBELL_RANGE, ih_doorbell_range); 216fe3c9489SFeifei Xu } 217fe3c9489SFeifei Xu 218fe3c9489SFeifei Xu 219fe3c9489SFeifei Xu static void nbio_v7_4_update_medium_grain_clock_gating(struct amdgpu_device *adev, 220fe3c9489SFeifei Xu bool enable) 221fe3c9489SFeifei Xu { 222fe3c9489SFeifei Xu //TODO: Add support for v7.4 223fe3c9489SFeifei Xu } 224fe3c9489SFeifei Xu 225fe3c9489SFeifei Xu static void nbio_v7_4_update_medium_grain_light_sleep(struct amdgpu_device *adev, 226fe3c9489SFeifei Xu bool enable) 227fe3c9489SFeifei Xu { 228fe3c9489SFeifei Xu uint32_t def, data; 229fe3c9489SFeifei Xu 230fe3c9489SFeifei Xu def = data = RREG32_PCIE(smnPCIE_CNTL2); 231fe3c9489SFeifei Xu if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_LS)) { 232fe3c9489SFeifei Xu data |= (PCIE_CNTL2__SLV_MEM_LS_EN_MASK | 233fe3c9489SFeifei Xu PCIE_CNTL2__MST_MEM_LS_EN_MASK | 234fe3c9489SFeifei Xu PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK); 235fe3c9489SFeifei Xu } else { 236fe3c9489SFeifei Xu data &= ~(PCIE_CNTL2__SLV_MEM_LS_EN_MASK | 237fe3c9489SFeifei Xu PCIE_CNTL2__MST_MEM_LS_EN_MASK | 238fe3c9489SFeifei Xu PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK); 239fe3c9489SFeifei Xu } 240fe3c9489SFeifei Xu 241fe3c9489SFeifei Xu if (def != data) 242fe3c9489SFeifei Xu WREG32_PCIE(smnPCIE_CNTL2, data); 243fe3c9489SFeifei Xu } 244fe3c9489SFeifei Xu 245fe3c9489SFeifei Xu static void nbio_v7_4_get_clockgating_state(struct amdgpu_device *adev, 246fe3c9489SFeifei Xu u32 *flags) 247fe3c9489SFeifei Xu { 248fe3c9489SFeifei Xu int data; 249fe3c9489SFeifei Xu 250fe3c9489SFeifei Xu /* AMD_CG_SUPPORT_BIF_MGCG */ 251fe3c9489SFeifei Xu data = RREG32_PCIE(smnCPM_CONTROL); 252fe3c9489SFeifei Xu if (data & CPM_CONTROL__LCLK_DYN_GATE_ENABLE_MASK) 253fe3c9489SFeifei Xu *flags |= AMD_CG_SUPPORT_BIF_MGCG; 254fe3c9489SFeifei Xu 255fe3c9489SFeifei Xu /* AMD_CG_SUPPORT_BIF_LS */ 256fe3c9489SFeifei Xu data = RREG32_PCIE(smnPCIE_CNTL2); 257fe3c9489SFeifei Xu if (data & PCIE_CNTL2__SLV_MEM_LS_EN_MASK) 258fe3c9489SFeifei Xu *flags |= AMD_CG_SUPPORT_BIF_LS; 259fe3c9489SFeifei Xu } 260fe3c9489SFeifei Xu 261fe3c9489SFeifei Xu static void nbio_v7_4_ih_control(struct amdgpu_device *adev) 262fe3c9489SFeifei Xu { 263fe3c9489SFeifei Xu u32 interrupt_cntl; 264fe3c9489SFeifei Xu 265fe3c9489SFeifei Xu /* setup interrupt control */ 266fe3c9489SFeifei Xu WREG32_SOC15(NBIO, 0, mmINTERRUPT_CNTL2, adev->dummy_page_addr >> 8); 267fe3c9489SFeifei Xu interrupt_cntl = RREG32_SOC15(NBIO, 0, mmINTERRUPT_CNTL); 268fe3c9489SFeifei Xu /* INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=0 - dummy read disabled with msi, enabled without msi 269fe3c9489SFeifei Xu * INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=1 - dummy read controlled by IH_DUMMY_RD_EN 270fe3c9489SFeifei Xu */ 271fe3c9489SFeifei Xu interrupt_cntl = REG_SET_FIELD(interrupt_cntl, INTERRUPT_CNTL, IH_DUMMY_RD_OVERRIDE, 0); 272fe3c9489SFeifei Xu /* INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN_MASK=1 if ring is in non-cacheable memory, e.g., vram */ 273fe3c9489SFeifei Xu interrupt_cntl = REG_SET_FIELD(interrupt_cntl, INTERRUPT_CNTL, IH_REQ_NONSNOOP_EN, 0); 274fe3c9489SFeifei Xu WREG32_SOC15(NBIO, 0, mmINTERRUPT_CNTL, interrupt_cntl); 275fe3c9489SFeifei Xu } 276fe3c9489SFeifei Xu 277fe3c9489SFeifei Xu static u32 nbio_v7_4_get_hdp_flush_req_offset(struct amdgpu_device *adev) 278fe3c9489SFeifei Xu { 279fe3c9489SFeifei Xu return SOC15_REG_OFFSET(NBIO, 0, mmGPU_HDP_FLUSH_REQ); 280fe3c9489SFeifei Xu } 281fe3c9489SFeifei Xu 282fe3c9489SFeifei Xu static u32 nbio_v7_4_get_hdp_flush_done_offset(struct amdgpu_device *adev) 283fe3c9489SFeifei Xu { 284fe3c9489SFeifei Xu return SOC15_REG_OFFSET(NBIO, 0, mmGPU_HDP_FLUSH_DONE); 285fe3c9489SFeifei Xu } 286fe3c9489SFeifei Xu 287fe3c9489SFeifei Xu static u32 nbio_v7_4_get_pcie_index_offset(struct amdgpu_device *adev) 288fe3c9489SFeifei Xu { 289fe3c9489SFeifei Xu return SOC15_REG_OFFSET(NBIO, 0, mmPCIE_INDEX2); 290fe3c9489SFeifei Xu } 291fe3c9489SFeifei Xu 292fe3c9489SFeifei Xu static u32 nbio_v7_4_get_pcie_data_offset(struct amdgpu_device *adev) 293fe3c9489SFeifei Xu { 294fe3c9489SFeifei Xu return SOC15_REG_OFFSET(NBIO, 0, mmPCIE_DATA2); 295fe3c9489SFeifei Xu } 296fe3c9489SFeifei Xu 297bebc0762SHawking Zhang const struct nbio_hdp_flush_reg nbio_v7_4_hdp_flush_reg = { 298fe3c9489SFeifei Xu .ref_and_mask_cp0 = GPU_HDP_FLUSH_DONE__CP0_MASK, 299fe3c9489SFeifei Xu .ref_and_mask_cp1 = GPU_HDP_FLUSH_DONE__CP1_MASK, 300fe3c9489SFeifei Xu .ref_and_mask_cp2 = GPU_HDP_FLUSH_DONE__CP2_MASK, 301fe3c9489SFeifei Xu .ref_and_mask_cp3 = GPU_HDP_FLUSH_DONE__CP3_MASK, 302fe3c9489SFeifei Xu .ref_and_mask_cp4 = GPU_HDP_FLUSH_DONE__CP4_MASK, 303fe3c9489SFeifei Xu .ref_and_mask_cp5 = GPU_HDP_FLUSH_DONE__CP5_MASK, 304fe3c9489SFeifei Xu .ref_and_mask_cp6 = GPU_HDP_FLUSH_DONE__CP6_MASK, 305fe3c9489SFeifei Xu .ref_and_mask_cp7 = GPU_HDP_FLUSH_DONE__CP7_MASK, 306fe3c9489SFeifei Xu .ref_and_mask_cp8 = GPU_HDP_FLUSH_DONE__CP8_MASK, 307fe3c9489SFeifei Xu .ref_and_mask_cp9 = GPU_HDP_FLUSH_DONE__CP9_MASK, 308fe3c9489SFeifei Xu .ref_and_mask_sdma0 = GPU_HDP_FLUSH_DONE__SDMA0_MASK, 309fe3c9489SFeifei Xu .ref_and_mask_sdma1 = GPU_HDP_FLUSH_DONE__SDMA1_MASK, 3100fe6a7b4SLe Ma .ref_and_mask_sdma2 = GPU_HDP_FLUSH_DONE__RSVD_ENG0_MASK, 3110fe6a7b4SLe Ma .ref_and_mask_sdma3 = GPU_HDP_FLUSH_DONE__RSVD_ENG1_MASK, 3120fe6a7b4SLe Ma .ref_and_mask_sdma4 = GPU_HDP_FLUSH_DONE__RSVD_ENG2_MASK, 3130fe6a7b4SLe Ma .ref_and_mask_sdma5 = GPU_HDP_FLUSH_DONE__RSVD_ENG3_MASK, 3140fe6a7b4SLe Ma .ref_and_mask_sdma6 = GPU_HDP_FLUSH_DONE__RSVD_ENG4_MASK, 3150fe6a7b4SLe Ma .ref_and_mask_sdma7 = GPU_HDP_FLUSH_DONE__RSVD_ENG5_MASK, 316fe3c9489SFeifei Xu }; 317fe3c9489SFeifei Xu 318fe3c9489SFeifei Xu static void nbio_v7_4_init_registers(struct amdgpu_device *adev) 319fe3c9489SFeifei Xu { 320fe3c9489SFeifei Xu 321fe3c9489SFeifei Xu } 322fe3c9489SFeifei Xu 3234241863aSHawking Zhang static void nbio_v7_4_handle_ras_controller_intr_no_bifring(struct amdgpu_device *adev) 3244241863aSHawking Zhang { 3254241863aSHawking Zhang uint32_t bif_doorbell_intr_cntl; 32628f87950SLe Ma struct ras_manager *obj = amdgpu_ras_find_obj(adev, adev->nbio.ras_if); 3273cd4f618SGuchun Chen struct ras_err_data err_data = {0, 0, 0, NULL}; 328f75e94d8SGuchun Chen struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); 3294241863aSHawking Zhang 3304241863aSHawking Zhang bif_doorbell_intr_cntl = RREG32_SOC15(NBIO, 0, mmBIF_DOORBELL_INT_CNTL); 3314241863aSHawking Zhang if (REG_GET_FIELD(bif_doorbell_intr_cntl, 3324241863aSHawking Zhang BIF_DOORBELL_INT_CNTL, RAS_CNTLR_INTERRUPT_STATUS)) { 3334241863aSHawking Zhang /* driver has to clear the interrupt status when bif ring is disabled */ 3344241863aSHawking Zhang bif_doorbell_intr_cntl = REG_SET_FIELD(bif_doorbell_intr_cntl, 3354241863aSHawking Zhang BIF_DOORBELL_INT_CNTL, 3364241863aSHawking Zhang RAS_CNTLR_INTERRUPT_CLEAR, 1); 3374241863aSHawking Zhang WREG32_SOC15(NBIO, 0, mmBIF_DOORBELL_INT_CNTL, bif_doorbell_intr_cntl); 3387c6e68c7SAndrey Grodzovsky 339f75e94d8SGuchun Chen if (!ras->disable_ras_err_cnt_harvest) { 34028f87950SLe Ma /* 341f75e94d8SGuchun Chen * clear error status after ras_controller_intr 342f75e94d8SGuchun Chen * according to hw team and count ue number 343f75e94d8SGuchun Chen * for query 34428f87950SLe Ma */ 3453cd4f618SGuchun Chen nbio_v7_4_query_ras_error_count(adev, &err_data); 3463cd4f618SGuchun Chen 347f75e94d8SGuchun Chen /* logging on error cnt and printing for awareness */ 3483cd4f618SGuchun Chen obj->err_data.ue_count += err_data.ue_count; 3493cd4f618SGuchun Chen obj->err_data.ce_count += err_data.ce_count; 3503cd4f618SGuchun Chen 3513cd4f618SGuchun Chen if (err_data.ce_count) 3526952e99cSGuchun Chen dev_info(adev->dev, "%ld correctable hardware " 3536952e99cSGuchun Chen "errors detected in %s block, " 3546952e99cSGuchun Chen "no user action is needed.\n", 3556952e99cSGuchun Chen obj->err_data.ce_count, 3566952e99cSGuchun Chen adev->nbio.ras_if->name); 3573cd4f618SGuchun Chen 3583cd4f618SGuchun Chen if (err_data.ue_count) 3596952e99cSGuchun Chen dev_info(adev->dev, "%ld uncorrectable hardware " 3606952e99cSGuchun Chen "errors detected in %s block\n", 3616952e99cSGuchun Chen obj->err_data.ue_count, 3626952e99cSGuchun Chen adev->nbio.ras_if->name); 363f75e94d8SGuchun Chen } 36428f87950SLe Ma 3656952e99cSGuchun Chen dev_info(adev->dev, "RAS controller interrupt triggered " 3666952e99cSGuchun Chen "by NBIF error\n"); 3674a2d9356SLe Ma 3684a2d9356SLe Ma /* ras_controller_int is dedicated for nbif ras error, 3694a2d9356SLe Ma * not the global interrupt for sync flood 3704a2d9356SLe Ma */ 37161934624SGuchun Chen amdgpu_ras_reset_gpu(adev); 3724241863aSHawking Zhang } 3734241863aSHawking Zhang } 3744241863aSHawking Zhang 3754241863aSHawking Zhang static void nbio_v7_4_handle_ras_err_event_athub_intr_no_bifring(struct amdgpu_device *adev) 3764241863aSHawking Zhang { 3774241863aSHawking Zhang uint32_t bif_doorbell_intr_cntl; 3784241863aSHawking Zhang 3794241863aSHawking Zhang bif_doorbell_intr_cntl = RREG32_SOC15(NBIO, 0, mmBIF_DOORBELL_INT_CNTL); 3804241863aSHawking Zhang if (REG_GET_FIELD(bif_doorbell_intr_cntl, 3814241863aSHawking Zhang BIF_DOORBELL_INT_CNTL, RAS_ATHUB_ERR_EVENT_INTERRUPT_STATUS)) { 3824241863aSHawking Zhang /* driver has to clear the interrupt status when bif ring is disabled */ 3834241863aSHawking Zhang bif_doorbell_intr_cntl = REG_SET_FIELD(bif_doorbell_intr_cntl, 3844241863aSHawking Zhang BIF_DOORBELL_INT_CNTL, 3854241863aSHawking Zhang RAS_ATHUB_ERR_EVENT_INTERRUPT_CLEAR, 1); 3864241863aSHawking Zhang WREG32_SOC15(NBIO, 0, mmBIF_DOORBELL_INT_CNTL, bif_doorbell_intr_cntl); 3877c6e68c7SAndrey Grodzovsky 3887c6e68c7SAndrey Grodzovsky amdgpu_ras_global_ras_isr(adev); 3894241863aSHawking Zhang } 3904241863aSHawking Zhang } 3914241863aSHawking Zhang 3924e644fffSHawking Zhang 3934e644fffSHawking Zhang static int nbio_v7_4_set_ras_controller_irq_state(struct amdgpu_device *adev, 3944e644fffSHawking Zhang struct amdgpu_irq_src *src, 3954e644fffSHawking Zhang unsigned type, 3964e644fffSHawking Zhang enum amdgpu_interrupt_state state) 3974e644fffSHawking Zhang { 3984e644fffSHawking Zhang /* The ras_controller_irq enablement should be done in psp bl when it 3994e644fffSHawking Zhang * tries to enable ras feature. Driver only need to set the correct interrupt 4004e644fffSHawking Zhang * vector for bare-metal and sriov use case respectively 4014e644fffSHawking Zhang */ 4024e644fffSHawking Zhang uint32_t bif_intr_cntl; 4034e644fffSHawking Zhang 4044e644fffSHawking Zhang bif_intr_cntl = RREG32_SOC15(NBIO, 0, mmBIF_INTR_CNTL); 4054e644fffSHawking Zhang if (state == AMDGPU_IRQ_STATE_ENABLE) { 4064e644fffSHawking Zhang /* set interrupt vector select bit to 0 to select 4074e644fffSHawking Zhang * vetcor 1 for bare metal case */ 4084e644fffSHawking Zhang bif_intr_cntl = REG_SET_FIELD(bif_intr_cntl, 4094e644fffSHawking Zhang BIF_INTR_CNTL, 4104e644fffSHawking Zhang RAS_INTR_VEC_SEL, 0); 4114e644fffSHawking Zhang WREG32_SOC15(NBIO, 0, mmBIF_INTR_CNTL, bif_intr_cntl); 4124e644fffSHawking Zhang } 4134e644fffSHawking Zhang 4144e644fffSHawking Zhang return 0; 4154e644fffSHawking Zhang } 4164e644fffSHawking Zhang 4174e644fffSHawking Zhang static int nbio_v7_4_process_ras_controller_irq(struct amdgpu_device *adev, 4184e644fffSHawking Zhang struct amdgpu_irq_src *source, 4194e644fffSHawking Zhang struct amdgpu_iv_entry *entry) 4204e644fffSHawking Zhang { 4214e644fffSHawking Zhang /* By design, the ih cookie for ras_controller_irq should be written 4224e644fffSHawking Zhang * to BIFring instead of general iv ring. However, due to known bif ring 4234e644fffSHawking Zhang * hw bug, it has to be disabled. There is no chance the process function 4244e644fffSHawking Zhang * will be involked. Just left it as a dummy one. 4254e644fffSHawking Zhang */ 4264e644fffSHawking Zhang return 0; 4274e644fffSHawking Zhang } 4284e644fffSHawking Zhang 4294e644fffSHawking Zhang static int nbio_v7_4_set_ras_err_event_athub_irq_state(struct amdgpu_device *adev, 4304e644fffSHawking Zhang struct amdgpu_irq_src *src, 4314e644fffSHawking Zhang unsigned type, 4324e644fffSHawking Zhang enum amdgpu_interrupt_state state) 4334e644fffSHawking Zhang { 4344e644fffSHawking Zhang /* The ras_controller_irq enablement should be done in psp bl when it 4354e644fffSHawking Zhang * tries to enable ras feature. Driver only need to set the correct interrupt 4364e644fffSHawking Zhang * vector for bare-metal and sriov use case respectively 4374e644fffSHawking Zhang */ 4384e644fffSHawking Zhang uint32_t bif_intr_cntl; 4394e644fffSHawking Zhang 4404e644fffSHawking Zhang bif_intr_cntl = RREG32_SOC15(NBIO, 0, mmBIF_INTR_CNTL); 4414e644fffSHawking Zhang if (state == AMDGPU_IRQ_STATE_ENABLE) { 4424e644fffSHawking Zhang /* set interrupt vector select bit to 0 to select 4434e644fffSHawking Zhang * vetcor 1 for bare metal case */ 4444e644fffSHawking Zhang bif_intr_cntl = REG_SET_FIELD(bif_intr_cntl, 4454e644fffSHawking Zhang BIF_INTR_CNTL, 4464e644fffSHawking Zhang RAS_INTR_VEC_SEL, 0); 4474e644fffSHawking Zhang WREG32_SOC15(NBIO, 0, mmBIF_INTR_CNTL, bif_intr_cntl); 4484e644fffSHawking Zhang } 4494e644fffSHawking Zhang 4504e644fffSHawking Zhang return 0; 4514e644fffSHawking Zhang } 4524e644fffSHawking Zhang 4534e644fffSHawking Zhang static int nbio_v7_4_process_err_event_athub_irq(struct amdgpu_device *adev, 4544e644fffSHawking Zhang struct amdgpu_irq_src *source, 4554e644fffSHawking Zhang struct amdgpu_iv_entry *entry) 4564e644fffSHawking Zhang { 4574e644fffSHawking Zhang /* By design, the ih cookie for err_event_athub_irq should be written 4584e644fffSHawking Zhang * to BIFring instead of general iv ring. However, due to known bif ring 4594e644fffSHawking Zhang * hw bug, it has to be disabled. There is no chance the process function 4604e644fffSHawking Zhang * will be involked. Just left it as a dummy one. 4614e644fffSHawking Zhang */ 4624e644fffSHawking Zhang return 0; 4634e644fffSHawking Zhang } 4644e644fffSHawking Zhang 4654e644fffSHawking Zhang static const struct amdgpu_irq_src_funcs nbio_v7_4_ras_controller_irq_funcs = { 4664e644fffSHawking Zhang .set = nbio_v7_4_set_ras_controller_irq_state, 4674e644fffSHawking Zhang .process = nbio_v7_4_process_ras_controller_irq, 4684e644fffSHawking Zhang }; 4694e644fffSHawking Zhang 4704e644fffSHawking Zhang static const struct amdgpu_irq_src_funcs nbio_v7_4_ras_err_event_athub_irq_funcs = { 4714e644fffSHawking Zhang .set = nbio_v7_4_set_ras_err_event_athub_irq_state, 4724e644fffSHawking Zhang .process = nbio_v7_4_process_err_event_athub_irq, 4734e644fffSHawking Zhang }; 4744e644fffSHawking Zhang 4754e644fffSHawking Zhang static int nbio_v7_4_init_ras_controller_interrupt (struct amdgpu_device *adev) 4764e644fffSHawking Zhang { 4774e644fffSHawking Zhang int r; 4784e644fffSHawking Zhang 4794e644fffSHawking Zhang /* init the irq funcs */ 4804e644fffSHawking Zhang adev->nbio.ras_controller_irq.funcs = 4814e644fffSHawking Zhang &nbio_v7_4_ras_controller_irq_funcs; 4824e644fffSHawking Zhang adev->nbio.ras_controller_irq.num_types = 1; 4834e644fffSHawking Zhang 4844e644fffSHawking Zhang /* register ras controller interrupt */ 4854e644fffSHawking Zhang r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_BIF, 4864e644fffSHawking Zhang NBIF_7_4__SRCID__RAS_CONTROLLER_INTERRUPT, 4874e644fffSHawking Zhang &adev->nbio.ras_controller_irq); 4884e644fffSHawking Zhang 4898831fa6eSGuchun Chen return r; 4904e644fffSHawking Zhang } 4914e644fffSHawking Zhang 4924e644fffSHawking Zhang static int nbio_v7_4_init_ras_err_event_athub_interrupt (struct amdgpu_device *adev) 4934e644fffSHawking Zhang { 4944e644fffSHawking Zhang 4954e644fffSHawking Zhang int r; 4964e644fffSHawking Zhang 4974e644fffSHawking Zhang /* init the irq funcs */ 4984e644fffSHawking Zhang adev->nbio.ras_err_event_athub_irq.funcs = 4994e644fffSHawking Zhang &nbio_v7_4_ras_err_event_athub_irq_funcs; 5004e644fffSHawking Zhang adev->nbio.ras_err_event_athub_irq.num_types = 1; 5014e644fffSHawking Zhang 5024e644fffSHawking Zhang /* register ras err event athub interrupt */ 5034e644fffSHawking Zhang r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_BIF, 5044e644fffSHawking Zhang NBIF_7_4__SRCID__ERREVENT_ATHUB_INTERRUPT, 5054e644fffSHawking Zhang &adev->nbio.ras_err_event_athub_irq); 5064e644fffSHawking Zhang 5078831fa6eSGuchun Chen return r; 5084e644fffSHawking Zhang } 5094e644fffSHawking Zhang 5105c39d600SLe Ma #define smnPARITY_ERROR_STATUS_UNCORR_GRP2 0x13a20030 5115c39d600SLe Ma 51252652ef2SGuchun Chen static void nbio_v7_4_query_ras_error_count(struct amdgpu_device *adev, 51352652ef2SGuchun Chen void *ras_error_status) 51452652ef2SGuchun Chen { 5155c39d600SLe Ma uint32_t global_sts, central_sts, int_eoi, parity_sts; 5161a3f2e8cSGuchun Chen uint32_t corr, fatal, non_fatal; 5171a3f2e8cSGuchun Chen struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status; 5181a3f2e8cSGuchun Chen 5191a3f2e8cSGuchun Chen global_sts = RREG32_PCIE(smnRAS_GLOBAL_STATUS_LO); 5201a3f2e8cSGuchun Chen corr = REG_GET_FIELD(global_sts, RAS_GLOBAL_STATUS_LO, ParityErrCorr); 5211a3f2e8cSGuchun Chen fatal = REG_GET_FIELD(global_sts, RAS_GLOBAL_STATUS_LO, ParityErrFatal); 5221a3f2e8cSGuchun Chen non_fatal = REG_GET_FIELD(global_sts, RAS_GLOBAL_STATUS_LO, 5231a3f2e8cSGuchun Chen ParityErrNonFatal); 5245c39d600SLe Ma parity_sts = RREG32_PCIE(smnPARITY_ERROR_STATUS_UNCORR_GRP2); 5251a3f2e8cSGuchun Chen 5261a3f2e8cSGuchun Chen if (corr) 5271a3f2e8cSGuchun Chen err_data->ce_count++; 5281a3f2e8cSGuchun Chen if (fatal) 5291a3f2e8cSGuchun Chen err_data->ue_count++; 5301a3f2e8cSGuchun Chen 5311a3f2e8cSGuchun Chen if (corr || fatal || non_fatal) { 5321a3f2e8cSGuchun Chen central_sts = RREG32_PCIE(smnBIFL_RAS_CENTRAL_STATUS); 5331a3f2e8cSGuchun Chen /* clear error status register */ 5341a3f2e8cSGuchun Chen WREG32_PCIE(smnRAS_GLOBAL_STATUS_LO, global_sts); 5351a3f2e8cSGuchun Chen 5365c39d600SLe Ma if (fatal) 5375c39d600SLe Ma /* clear parity fatal error indication field */ 5385c39d600SLe Ma WREG32_PCIE(smnPARITY_ERROR_STATUS_UNCORR_GRP2, 5395c39d600SLe Ma parity_sts); 5405c39d600SLe Ma 5411a3f2e8cSGuchun Chen if (REG_GET_FIELD(central_sts, BIFL_RAS_CENTRAL_STATUS, 5421a3f2e8cSGuchun Chen BIFL_RasContller_Intr_Recv)) { 5431a3f2e8cSGuchun Chen /* clear interrupt status register */ 5441a3f2e8cSGuchun Chen WREG32_PCIE(smnBIFL_RAS_CENTRAL_STATUS, central_sts); 5451a3f2e8cSGuchun Chen int_eoi = RREG32_PCIE(smnIOHC_INTERRUPT_EOI); 5461a3f2e8cSGuchun Chen int_eoi = REG_SET_FIELD(int_eoi, 5471a3f2e8cSGuchun Chen IOHC_INTERRUPT_EOI, SMI_EOI, 1); 5481a3f2e8cSGuchun Chen WREG32_PCIE(smnIOHC_INTERRUPT_EOI, int_eoi); 5491a3f2e8cSGuchun Chen } 5501a3f2e8cSGuchun Chen } 55152652ef2SGuchun Chen } 55252652ef2SGuchun Chen 553956f6705SLe Ma static void nbio_v7_4_enable_doorbell_interrupt(struct amdgpu_device *adev, 554956f6705SLe Ma bool enable) 555956f6705SLe Ma { 556956f6705SLe Ma WREG32_FIELD15(NBIO, 0, BIF_DOORBELL_INT_CNTL, 557956f6705SLe Ma DOORBELL_INTERRUPT_DISABLE, enable ? 0 : 1); 558956f6705SLe Ma } 559956f6705SLe Ma 560fe3c9489SFeifei Xu const struct amdgpu_nbio_funcs nbio_v7_4_funcs = { 561fe3c9489SFeifei Xu .get_hdp_flush_req_offset = nbio_v7_4_get_hdp_flush_req_offset, 562fe3c9489SFeifei Xu .get_hdp_flush_done_offset = nbio_v7_4_get_hdp_flush_done_offset, 563fe3c9489SFeifei Xu .get_pcie_index_offset = nbio_v7_4_get_pcie_index_offset, 564fe3c9489SFeifei Xu .get_pcie_data_offset = nbio_v7_4_get_pcie_data_offset, 565fe3c9489SFeifei Xu .get_rev_id = nbio_v7_4_get_rev_id, 566fe3c9489SFeifei Xu .mc_access_enable = nbio_v7_4_mc_access_enable, 567fe3c9489SFeifei Xu .get_memsize = nbio_v7_4_get_memsize, 568fe3c9489SFeifei Xu .sdma_doorbell_range = nbio_v7_4_sdma_doorbell_range, 56939a5053fSLeo Liu .vcn_doorbell_range = nbio_v7_4_vcn_doorbell_range, 570fe3c9489SFeifei Xu .enable_doorbell_aperture = nbio_v7_4_enable_doorbell_aperture, 571fe3c9489SFeifei Xu .enable_doorbell_selfring_aperture = nbio_v7_4_enable_doorbell_selfring_aperture, 572fe3c9489SFeifei Xu .ih_doorbell_range = nbio_v7_4_ih_doorbell_range, 573956f6705SLe Ma .enable_doorbell_interrupt = nbio_v7_4_enable_doorbell_interrupt, 574fe3c9489SFeifei Xu .update_medium_grain_clock_gating = nbio_v7_4_update_medium_grain_clock_gating, 575fe3c9489SFeifei Xu .update_medium_grain_light_sleep = nbio_v7_4_update_medium_grain_light_sleep, 576fe3c9489SFeifei Xu .get_clockgating_state = nbio_v7_4_get_clockgating_state, 577fe3c9489SFeifei Xu .ih_control = nbio_v7_4_ih_control, 578fe3c9489SFeifei Xu .init_registers = nbio_v7_4_init_registers, 57988807dc8SOak Zeng .remap_hdp_registers = nbio_v7_4_remap_hdp_registers, 5804241863aSHawking Zhang .handle_ras_controller_intr_no_bifring = nbio_v7_4_handle_ras_controller_intr_no_bifring, 5814241863aSHawking Zhang .handle_ras_err_event_athub_intr_no_bifring = nbio_v7_4_handle_ras_err_event_athub_intr_no_bifring, 5824e644fffSHawking Zhang .init_ras_controller_interrupt = nbio_v7_4_init_ras_controller_interrupt, 5834e644fffSHawking Zhang .init_ras_err_event_athub_interrupt = nbio_v7_4_init_ras_err_event_athub_interrupt, 58452652ef2SGuchun Chen .query_ras_error_count = nbio_v7_4_query_ras_error_count, 5851c70d3d9SHawking Zhang .ras_late_init = amdgpu_nbio_ras_late_init, 586fe3c9489SFeifei Xu }; 587