1fe3c9489SFeifei Xu /* 2fe3c9489SFeifei Xu * Copyright 2018 Advanced Micro Devices, Inc. 3fe3c9489SFeifei Xu * 4fe3c9489SFeifei Xu * Permission is hereby granted, free of charge, to any person obtaining a 5fe3c9489SFeifei Xu * copy of this software and associated documentation files (the "Software"), 6fe3c9489SFeifei Xu * to deal in the Software without restriction, including without limitation 7fe3c9489SFeifei Xu * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8fe3c9489SFeifei Xu * and/or sell copies of the Software, and to permit persons to whom the 9fe3c9489SFeifei Xu * Software is furnished to do so, subject to the following conditions: 10fe3c9489SFeifei Xu * 11fe3c9489SFeifei Xu * The above copyright notice and this permission notice shall be included in 12fe3c9489SFeifei Xu * all copies or substantial portions of the Software. 13fe3c9489SFeifei Xu * 14fe3c9489SFeifei Xu * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15fe3c9489SFeifei Xu * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16fe3c9489SFeifei Xu * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17fe3c9489SFeifei Xu * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18fe3c9489SFeifei Xu * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19fe3c9489SFeifei Xu * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20fe3c9489SFeifei Xu * OTHER DEALINGS IN THE SOFTWARE. 21fe3c9489SFeifei Xu * 22fe3c9489SFeifei Xu */ 23fe3c9489SFeifei Xu #include "amdgpu.h" 24fe3c9489SFeifei Xu #include "amdgpu_atombios.h" 25fe3c9489SFeifei Xu #include "nbio_v7_4.h" 269ad1dc29SHawking Zhang #include "amdgpu_ras.h" 27fe3c9489SFeifei Xu 28fe3c9489SFeifei Xu #include "nbio/nbio_7_4_offset.h" 29fe3c9489SFeifei Xu #include "nbio/nbio_7_4_sh_mask.h" 30a0bb79e2SKent Russell #include "nbio/nbio_7_4_0_smn.h" 314e644fffSHawking Zhang #include "ivsrcid/nbio/irqsrcs_nbif_7_4.h" 3288807dc8SOak Zeng #include <uapi/linux/kfd_ioctl.h> 33fe3c9489SFeifei Xu 349d015c0dSKenneth Feng #define smnPCIE_LC_CNTL 0x11140280 359d015c0dSKenneth Feng #define smnPCIE_LC_CNTL3 0x111402d4 369d015c0dSKenneth Feng #define smnPCIE_LC_CNTL6 0x111402ec 379d015c0dSKenneth Feng #define smnPCIE_LC_CNTL7 0x111402f0 38fe3c9489SFeifei Xu #define smnNBIF_MGCG_CTRL_LCLK 0x1013a21c 399d015c0dSKenneth Feng #define smnRCC_BIF_STRAP3 0x1012348c 409d015c0dSKenneth Feng #define RCC_BIF_STRAP3__STRAP_VLINK_ASPM_IDLE_TIMER_MASK 0x0000FFFFL 419d015c0dSKenneth Feng #define RCC_BIF_STRAP3__STRAP_VLINK_PM_L1_ENTRY_TIMER_MASK 0xFFFF0000L 429d015c0dSKenneth Feng #define smnRCC_BIF_STRAP5 0x10123494 439d015c0dSKenneth Feng #define RCC_BIF_STRAP5__STRAP_VLINK_LDN_ENTRY_TIMER_MASK 0x0000FFFFL 449d015c0dSKenneth Feng #define smnBIF_CFG_DEV0_EPF0_DEVICE_CNTL2 0x1014008c 459d015c0dSKenneth Feng #define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__LTR_EN_MASK 0x0400L 469d015c0dSKenneth Feng #define smnBIF_CFG_DEV0_EPF0_PCIE_LTR_CAP 0x10140324 479d015c0dSKenneth Feng #define smnPSWUSP0_PCIE_LC_CNTL2 0x111402c4 489d015c0dSKenneth Feng #define smnRCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL 0x10123538 499d015c0dSKenneth Feng #define smnRCC_BIF_STRAP2 0x10123488 509d015c0dSKenneth Feng #define RCC_BIF_STRAP2__STRAP_LTR_IN_ASPML1_DIS_MASK 0x00004000L 519d015c0dSKenneth Feng #define RCC_BIF_STRAP3__STRAP_VLINK_ASPM_IDLE_TIMER__SHIFT 0x0 529d015c0dSKenneth Feng #define RCC_BIF_STRAP3__STRAP_VLINK_PM_L1_ENTRY_TIMER__SHIFT 0x10 539d015c0dSKenneth Feng #define RCC_BIF_STRAP5__STRAP_VLINK_LDN_ENTRY_TIMER__SHIFT 0x0 54fe3c9489SFeifei Xu 550fe6a7b4SLe Ma /* 560fe6a7b4SLe Ma * These are nbio v7_4_1 registers mask. Temporarily define these here since 570fe6a7b4SLe Ma * nbio v7_4_1 header is incomplete. 580fe6a7b4SLe Ma */ 590fe6a7b4SLe Ma #define GPU_HDP_FLUSH_DONE__RSVD_ENG0_MASK 0x00001000L 600fe6a7b4SLe Ma #define GPU_HDP_FLUSH_DONE__RSVD_ENG1_MASK 0x00002000L 610fe6a7b4SLe Ma #define GPU_HDP_FLUSH_DONE__RSVD_ENG2_MASK 0x00004000L 620fe6a7b4SLe Ma #define GPU_HDP_FLUSH_DONE__RSVD_ENG3_MASK 0x00008000L 630fe6a7b4SLe Ma #define GPU_HDP_FLUSH_DONE__RSVD_ENG4_MASK 0x00010000L 640fe6a7b4SLe Ma #define GPU_HDP_FLUSH_DONE__RSVD_ENG5_MASK 0x00020000L 650fe6a7b4SLe Ma 66989b6a05SJames Zhu #define mmBIF_MMSCH1_DOORBELL_RANGE 0x01dc 67989b6a05SJames Zhu #define mmBIF_MMSCH1_DOORBELL_RANGE_BASE_IDX 2 68989b6a05SJames Zhu //BIF_MMSCH1_DOORBELL_RANGE 69989b6a05SJames Zhu #define BIF_MMSCH1_DOORBELL_RANGE__OFFSET__SHIFT 0x2 70989b6a05SJames Zhu #define BIF_MMSCH1_DOORBELL_RANGE__SIZE__SHIFT 0x10 71989b6a05SJames Zhu #define BIF_MMSCH1_DOORBELL_RANGE__OFFSET_MASK 0x00000FFCL 72989b6a05SJames Zhu #define BIF_MMSCH1_DOORBELL_RANGE__SIZE_MASK 0x001F0000L 73989b6a05SJames Zhu 747ce29357SJames Zhu #define BIF_MMSCH1_DOORBELL_RANGE__OFFSET_MASK 0x00000FFCL 757ce29357SJames Zhu #define BIF_MMSCH1_DOORBELL_RANGE__SIZE_MASK 0x001F0000L 767ce29357SJames Zhu 777ce29357SJames Zhu #define mmBIF_MMSCH1_DOORBELL_RANGE_ALDE 0x01d8 787ce29357SJames Zhu #define mmBIF_MMSCH1_DOORBELL_RANGE_ALDE_BASE_IDX 2 797ce29357SJames Zhu //BIF_MMSCH1_DOORBELL_ALDE_RANGE 807ce29357SJames Zhu #define BIF_MMSCH1_DOORBELL_RANGE_ALDE__OFFSET__SHIFT 0x2 817ce29357SJames Zhu #define BIF_MMSCH1_DOORBELL_RANGE_ALDE__SIZE__SHIFT 0x10 827ce29357SJames Zhu #define BIF_MMSCH1_DOORBELL_RANGE_ALDE__OFFSET_MASK 0x00000FFCL 837ce29357SJames Zhu #define BIF_MMSCH1_DOORBELL_RANGE_ALDE__SIZE_MASK 0x001F0000L 847ce29357SJames Zhu 85f8a98f16SHawking Zhang #define mmRCC_DEV0_EPF0_STRAP0_ALDE 0x0015 86f8a98f16SHawking Zhang #define mmRCC_DEV0_EPF0_STRAP0_ALDE_BASE_IDX 2 87f8a98f16SHawking Zhang 88*54e6badbSJohn Clements #define mmBIF_DOORBELL_INT_CNTL_ALDE 0x3878 89*54e6badbSJohn Clements #define mmBIF_DOORBELL_INT_CNTL_ALDE_BASE_IDX 2 90*54e6badbSJohn Clements #define BIF_DOORBELL_INT_CNTL_ALDE__DOORBELL_INTERRUPT_DISABLE__SHIFT 0x18 91*54e6badbSJohn Clements #define BIF_DOORBELL_INT_CNTL_ALDE__DOORBELL_INTERRUPT_DISABLE_MASK 0x01000000L 92*54e6badbSJohn Clements 9328f87950SLe Ma static void nbio_v7_4_query_ras_error_count(struct amdgpu_device *adev, 9428f87950SLe Ma void *ras_error_status); 9528f87950SLe Ma 9688807dc8SOak Zeng static void nbio_v7_4_remap_hdp_registers(struct amdgpu_device *adev) 9788807dc8SOak Zeng { 9888807dc8SOak Zeng WREG32_SOC15(NBIO, 0, mmREMAP_HDP_MEM_FLUSH_CNTL, 9988807dc8SOak Zeng adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL); 10088807dc8SOak Zeng WREG32_SOC15(NBIO, 0, mmREMAP_HDP_REG_FLUSH_CNTL, 10188807dc8SOak Zeng adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_REG_FLUSH_CNTL); 10288807dc8SOak Zeng } 10388807dc8SOak Zeng 104fe3c9489SFeifei Xu static u32 nbio_v7_4_get_rev_id(struct amdgpu_device *adev) 105fe3c9489SFeifei Xu { 106f8a98f16SHawking Zhang u32 tmp; 107f8a98f16SHawking Zhang 108f8a98f16SHawking Zhang if (adev->asic_type == CHIP_ALDEBARAN) 109f8a98f16SHawking Zhang tmp = RREG32_SOC15(NBIO, 0, mmRCC_DEV0_EPF0_STRAP0_ALDE); 110f8a98f16SHawking Zhang else 111f8a98f16SHawking Zhang tmp = RREG32_SOC15(NBIO, 0, mmRCC_DEV0_EPF0_STRAP0); 112fe3c9489SFeifei Xu 113fe3c9489SFeifei Xu tmp &= RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0_MASK; 114fe3c9489SFeifei Xu tmp >>= RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0__SHIFT; 115fe3c9489SFeifei Xu 116fe3c9489SFeifei Xu return tmp; 117fe3c9489SFeifei Xu } 118fe3c9489SFeifei Xu 119fe3c9489SFeifei Xu static void nbio_v7_4_mc_access_enable(struct amdgpu_device *adev, bool enable) 120fe3c9489SFeifei Xu { 121fe3c9489SFeifei Xu if (enable) 122fe3c9489SFeifei Xu WREG32_SOC15(NBIO, 0, mmBIF_FB_EN, 123fe3c9489SFeifei Xu BIF_FB_EN__FB_READ_EN_MASK | BIF_FB_EN__FB_WRITE_EN_MASK); 124fe3c9489SFeifei Xu else 125fe3c9489SFeifei Xu WREG32_SOC15(NBIO, 0, mmBIF_FB_EN, 0); 126fe3c9489SFeifei Xu } 127fe3c9489SFeifei Xu 128fe3c9489SFeifei Xu static u32 nbio_v7_4_get_memsize(struct amdgpu_device *adev) 129fe3c9489SFeifei Xu { 130fe3c9489SFeifei Xu return RREG32_SOC15(NBIO, 0, mmRCC_CONFIG_MEMSIZE); 131fe3c9489SFeifei Xu } 132fe3c9489SFeifei Xu 133fe3c9489SFeifei Xu static void nbio_v7_4_sdma_doorbell_range(struct amdgpu_device *adev, int instance, 1348987e2e2SOak Zeng bool use_doorbell, int doorbell_index, int doorbell_size) 135fe3c9489SFeifei Xu { 1363d81f67aSLe Ma u32 reg, doorbell_range; 137fe3c9489SFeifei Xu 138759eb38eSLe Ma if (instance < 2) { 1393d81f67aSLe Ma reg = instance + 1403d81f67aSLe Ma SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA0_DOORBELL_RANGE); 141759eb38eSLe Ma } else { 1423d81f67aSLe Ma /* 1433d81f67aSLe Ma * These registers address of SDMA2~7 is not consecutive 1443d81f67aSLe Ma * from SDMA0~1. Need plus 4 dwords offset. 1453d81f67aSLe Ma * 1463d81f67aSLe Ma * BIF_SDMA0_DOORBELL_RANGE: 0x3bc0 1473d81f67aSLe Ma * BIF_SDMA1_DOORBELL_RANGE: 0x3bc4 1483d81f67aSLe Ma * BIF_SDMA2_DOORBELL_RANGE: 0x3bd8 149759eb38eSLe Ma + * BIF_SDMA4_DOORBELL_RANGE: 150759eb38eSLe Ma + * ARCTURUS: 0x3be0 151759eb38eSLe Ma + * ALDEBARAN: 0x3be4 1523d81f67aSLe Ma */ 153759eb38eSLe Ma if (adev->asic_type == CHIP_ALDEBARAN && instance == 4) 154759eb38eSLe Ma reg = instance + 0x4 + 0x1 + 155759eb38eSLe Ma SOC15_REG_OFFSET(NBIO, 0, 156759eb38eSLe Ma mmBIF_SDMA0_DOORBELL_RANGE); 157759eb38eSLe Ma else 1583d81f67aSLe Ma reg = instance + 0x4 + 159759eb38eSLe Ma SOC15_REG_OFFSET(NBIO, 0, 160759eb38eSLe Ma mmBIF_SDMA0_DOORBELL_RANGE); 161759eb38eSLe Ma } 1623d81f67aSLe Ma 1633d81f67aSLe Ma doorbell_range = RREG32(reg); 164fe3c9489SFeifei Xu 165fe3c9489SFeifei Xu if (use_doorbell) { 166fe3c9489SFeifei Xu doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, OFFSET, doorbell_index); 1678987e2e2SOak Zeng doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, SIZE, doorbell_size); 168fe3c9489SFeifei Xu } else 169fe3c9489SFeifei Xu doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, SIZE, 0); 170fe3c9489SFeifei Xu 171fe3c9489SFeifei Xu WREG32(reg, doorbell_range); 172fe3c9489SFeifei Xu } 173fe3c9489SFeifei Xu 17439a5053fSLeo Liu static void nbio_v7_4_vcn_doorbell_range(struct amdgpu_device *adev, bool use_doorbell, 175989b6a05SJames Zhu int doorbell_index, int instance) 17639a5053fSLeo Liu { 177989b6a05SJames Zhu u32 reg; 178989b6a05SJames Zhu u32 doorbell_range; 17939a5053fSLeo Liu 1807ce29357SJames Zhu if (instance) { 1817ce29357SJames Zhu if (adev->asic_type == CHIP_ALDEBARAN) 1827ce29357SJames Zhu reg = SOC15_REG_OFFSET(NBIO, 0, mmBIF_MMSCH1_DOORBELL_RANGE_ALDE); 183989b6a05SJames Zhu else 1847ce29357SJames Zhu reg = SOC15_REG_OFFSET(NBIO, 0, mmBIF_MMSCH1_DOORBELL_RANGE); 1857ce29357SJames Zhu } else 186989b6a05SJames Zhu reg = SOC15_REG_OFFSET(NBIO, 0, mmBIF_MMSCH0_DOORBELL_RANGE); 187989b6a05SJames Zhu 188989b6a05SJames Zhu doorbell_range = RREG32(reg); 18939a5053fSLeo Liu 19039a5053fSLeo Liu if (use_doorbell) { 19139a5053fSLeo Liu doorbell_range = REG_SET_FIELD(doorbell_range, 19239a5053fSLeo Liu BIF_MMSCH0_DOORBELL_RANGE, OFFSET, 19339a5053fSLeo Liu doorbell_index); 19439a5053fSLeo Liu doorbell_range = REG_SET_FIELD(doorbell_range, 19539a5053fSLeo Liu BIF_MMSCH0_DOORBELL_RANGE, SIZE, 8); 19639a5053fSLeo Liu } else 19739a5053fSLeo Liu doorbell_range = REG_SET_FIELD(doorbell_range, 19839a5053fSLeo Liu BIF_MMSCH0_DOORBELL_RANGE, SIZE, 0); 19939a5053fSLeo Liu 20039a5053fSLeo Liu WREG32(reg, doorbell_range); 20139a5053fSLeo Liu } 20239a5053fSLeo Liu 203fe3c9489SFeifei Xu static void nbio_v7_4_enable_doorbell_aperture(struct amdgpu_device *adev, 204fe3c9489SFeifei Xu bool enable) 205fe3c9489SFeifei Xu { 206fe3c9489SFeifei Xu WREG32_FIELD15(NBIO, 0, RCC_DOORBELL_APER_EN, BIF_DOORBELL_APER_EN, enable ? 1 : 0); 207fe3c9489SFeifei Xu } 208fe3c9489SFeifei Xu 209fe3c9489SFeifei Xu static void nbio_v7_4_enable_doorbell_selfring_aperture(struct amdgpu_device *adev, 210fe3c9489SFeifei Xu bool enable) 211fe3c9489SFeifei Xu { 21212292519SJay Cornwall u32 tmp = 0; 213fe3c9489SFeifei Xu 21412292519SJay Cornwall if (enable) { 21512292519SJay Cornwall tmp = REG_SET_FIELD(tmp, DOORBELL_SELFRING_GPA_APER_CNTL, DOORBELL_SELFRING_GPA_APER_EN, 1) | 21612292519SJay Cornwall REG_SET_FIELD(tmp, DOORBELL_SELFRING_GPA_APER_CNTL, DOORBELL_SELFRING_GPA_APER_MODE, 1) | 21712292519SJay Cornwall REG_SET_FIELD(tmp, DOORBELL_SELFRING_GPA_APER_CNTL, DOORBELL_SELFRING_GPA_APER_SIZE, 0); 21812292519SJay Cornwall 21912292519SJay Cornwall WREG32_SOC15(NBIO, 0, mmDOORBELL_SELFRING_GPA_APER_BASE_LOW, 22012292519SJay Cornwall lower_32_bits(adev->doorbell.base)); 22112292519SJay Cornwall WREG32_SOC15(NBIO, 0, mmDOORBELL_SELFRING_GPA_APER_BASE_HIGH, 22212292519SJay Cornwall upper_32_bits(adev->doorbell.base)); 22312292519SJay Cornwall } 22412292519SJay Cornwall 22512292519SJay Cornwall WREG32_SOC15(NBIO, 0, mmDOORBELL_SELFRING_GPA_APER_CNTL, tmp); 226fe3c9489SFeifei Xu } 227fe3c9489SFeifei Xu 228fe3c9489SFeifei Xu static void nbio_v7_4_ih_doorbell_range(struct amdgpu_device *adev, 229fe3c9489SFeifei Xu bool use_doorbell, int doorbell_index) 230fe3c9489SFeifei Xu { 231fe3c9489SFeifei Xu u32 ih_doorbell_range = RREG32_SOC15(NBIO, 0 , mmBIF_IH_DOORBELL_RANGE); 232fe3c9489SFeifei Xu 233fe3c9489SFeifei Xu if (use_doorbell) { 234fe3c9489SFeifei Xu ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, BIF_IH_DOORBELL_RANGE, OFFSET, doorbell_index); 235b635ae87SAlex Sierra ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, BIF_IH_DOORBELL_RANGE, SIZE, 4); 236fe3c9489SFeifei Xu } else 237fe3c9489SFeifei Xu ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, BIF_IH_DOORBELL_RANGE, SIZE, 0); 238fe3c9489SFeifei Xu 239fe3c9489SFeifei Xu WREG32_SOC15(NBIO, 0, mmBIF_IH_DOORBELL_RANGE, ih_doorbell_range); 240fe3c9489SFeifei Xu } 241fe3c9489SFeifei Xu 242fe3c9489SFeifei Xu 243fe3c9489SFeifei Xu static void nbio_v7_4_update_medium_grain_clock_gating(struct amdgpu_device *adev, 244fe3c9489SFeifei Xu bool enable) 245fe3c9489SFeifei Xu { 246fe3c9489SFeifei Xu //TODO: Add support for v7.4 247fe3c9489SFeifei Xu } 248fe3c9489SFeifei Xu 249fe3c9489SFeifei Xu static void nbio_v7_4_update_medium_grain_light_sleep(struct amdgpu_device *adev, 250fe3c9489SFeifei Xu bool enable) 251fe3c9489SFeifei Xu { 252fe3c9489SFeifei Xu uint32_t def, data; 253fe3c9489SFeifei Xu 254fe3c9489SFeifei Xu def = data = RREG32_PCIE(smnPCIE_CNTL2); 255fe3c9489SFeifei Xu if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_LS)) { 256fe3c9489SFeifei Xu data |= (PCIE_CNTL2__SLV_MEM_LS_EN_MASK | 257fe3c9489SFeifei Xu PCIE_CNTL2__MST_MEM_LS_EN_MASK | 258fe3c9489SFeifei Xu PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK); 259fe3c9489SFeifei Xu } else { 260fe3c9489SFeifei Xu data &= ~(PCIE_CNTL2__SLV_MEM_LS_EN_MASK | 261fe3c9489SFeifei Xu PCIE_CNTL2__MST_MEM_LS_EN_MASK | 262fe3c9489SFeifei Xu PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK); 263fe3c9489SFeifei Xu } 264fe3c9489SFeifei Xu 265fe3c9489SFeifei Xu if (def != data) 266fe3c9489SFeifei Xu WREG32_PCIE(smnPCIE_CNTL2, data); 267fe3c9489SFeifei Xu } 268fe3c9489SFeifei Xu 269fe3c9489SFeifei Xu static void nbio_v7_4_get_clockgating_state(struct amdgpu_device *adev, 270fe3c9489SFeifei Xu u32 *flags) 271fe3c9489SFeifei Xu { 272fe3c9489SFeifei Xu int data; 273fe3c9489SFeifei Xu 274fe3c9489SFeifei Xu /* AMD_CG_SUPPORT_BIF_MGCG */ 275fe3c9489SFeifei Xu data = RREG32_PCIE(smnCPM_CONTROL); 276fe3c9489SFeifei Xu if (data & CPM_CONTROL__LCLK_DYN_GATE_ENABLE_MASK) 277fe3c9489SFeifei Xu *flags |= AMD_CG_SUPPORT_BIF_MGCG; 278fe3c9489SFeifei Xu 279fe3c9489SFeifei Xu /* AMD_CG_SUPPORT_BIF_LS */ 280fe3c9489SFeifei Xu data = RREG32_PCIE(smnPCIE_CNTL2); 281fe3c9489SFeifei Xu if (data & PCIE_CNTL2__SLV_MEM_LS_EN_MASK) 282fe3c9489SFeifei Xu *flags |= AMD_CG_SUPPORT_BIF_LS; 283fe3c9489SFeifei Xu } 284fe3c9489SFeifei Xu 285fe3c9489SFeifei Xu static void nbio_v7_4_ih_control(struct amdgpu_device *adev) 286fe3c9489SFeifei Xu { 287fe3c9489SFeifei Xu u32 interrupt_cntl; 288fe3c9489SFeifei Xu 289fe3c9489SFeifei Xu /* setup interrupt control */ 290fe3c9489SFeifei Xu WREG32_SOC15(NBIO, 0, mmINTERRUPT_CNTL2, adev->dummy_page_addr >> 8); 291fe3c9489SFeifei Xu interrupt_cntl = RREG32_SOC15(NBIO, 0, mmINTERRUPT_CNTL); 292fe3c9489SFeifei Xu /* INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=0 - dummy read disabled with msi, enabled without msi 293fe3c9489SFeifei Xu * INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=1 - dummy read controlled by IH_DUMMY_RD_EN 294fe3c9489SFeifei Xu */ 295fe3c9489SFeifei Xu interrupt_cntl = REG_SET_FIELD(interrupt_cntl, INTERRUPT_CNTL, IH_DUMMY_RD_OVERRIDE, 0); 296fe3c9489SFeifei Xu /* INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN_MASK=1 if ring is in non-cacheable memory, e.g., vram */ 297fe3c9489SFeifei Xu interrupt_cntl = REG_SET_FIELD(interrupt_cntl, INTERRUPT_CNTL, IH_REQ_NONSNOOP_EN, 0); 298fe3c9489SFeifei Xu WREG32_SOC15(NBIO, 0, mmINTERRUPT_CNTL, interrupt_cntl); 299fe3c9489SFeifei Xu } 300fe3c9489SFeifei Xu 301fe3c9489SFeifei Xu static u32 nbio_v7_4_get_hdp_flush_req_offset(struct amdgpu_device *adev) 302fe3c9489SFeifei Xu { 303fe3c9489SFeifei Xu return SOC15_REG_OFFSET(NBIO, 0, mmGPU_HDP_FLUSH_REQ); 304fe3c9489SFeifei Xu } 305fe3c9489SFeifei Xu 306fe3c9489SFeifei Xu static u32 nbio_v7_4_get_hdp_flush_done_offset(struct amdgpu_device *adev) 307fe3c9489SFeifei Xu { 308fe3c9489SFeifei Xu return SOC15_REG_OFFSET(NBIO, 0, mmGPU_HDP_FLUSH_DONE); 309fe3c9489SFeifei Xu } 310fe3c9489SFeifei Xu 311fe3c9489SFeifei Xu static u32 nbio_v7_4_get_pcie_index_offset(struct amdgpu_device *adev) 312fe3c9489SFeifei Xu { 313fe3c9489SFeifei Xu return SOC15_REG_OFFSET(NBIO, 0, mmPCIE_INDEX2); 314fe3c9489SFeifei Xu } 315fe3c9489SFeifei Xu 316fe3c9489SFeifei Xu static u32 nbio_v7_4_get_pcie_data_offset(struct amdgpu_device *adev) 317fe3c9489SFeifei Xu { 318fe3c9489SFeifei Xu return SOC15_REG_OFFSET(NBIO, 0, mmPCIE_DATA2); 319fe3c9489SFeifei Xu } 320fe3c9489SFeifei Xu 321bebc0762SHawking Zhang const struct nbio_hdp_flush_reg nbio_v7_4_hdp_flush_reg = { 322fe3c9489SFeifei Xu .ref_and_mask_cp0 = GPU_HDP_FLUSH_DONE__CP0_MASK, 323fe3c9489SFeifei Xu .ref_and_mask_cp1 = GPU_HDP_FLUSH_DONE__CP1_MASK, 324fe3c9489SFeifei Xu .ref_and_mask_cp2 = GPU_HDP_FLUSH_DONE__CP2_MASK, 325fe3c9489SFeifei Xu .ref_and_mask_cp3 = GPU_HDP_FLUSH_DONE__CP3_MASK, 326fe3c9489SFeifei Xu .ref_and_mask_cp4 = GPU_HDP_FLUSH_DONE__CP4_MASK, 327fe3c9489SFeifei Xu .ref_and_mask_cp5 = GPU_HDP_FLUSH_DONE__CP5_MASK, 328fe3c9489SFeifei Xu .ref_and_mask_cp6 = GPU_HDP_FLUSH_DONE__CP6_MASK, 329fe3c9489SFeifei Xu .ref_and_mask_cp7 = GPU_HDP_FLUSH_DONE__CP7_MASK, 330fe3c9489SFeifei Xu .ref_and_mask_cp8 = GPU_HDP_FLUSH_DONE__CP8_MASK, 331fe3c9489SFeifei Xu .ref_and_mask_cp9 = GPU_HDP_FLUSH_DONE__CP9_MASK, 332fe3c9489SFeifei Xu .ref_and_mask_sdma0 = GPU_HDP_FLUSH_DONE__SDMA0_MASK, 333fe3c9489SFeifei Xu .ref_and_mask_sdma1 = GPU_HDP_FLUSH_DONE__SDMA1_MASK, 3340fe6a7b4SLe Ma .ref_and_mask_sdma2 = GPU_HDP_FLUSH_DONE__RSVD_ENG0_MASK, 3350fe6a7b4SLe Ma .ref_and_mask_sdma3 = GPU_HDP_FLUSH_DONE__RSVD_ENG1_MASK, 3360fe6a7b4SLe Ma .ref_and_mask_sdma4 = GPU_HDP_FLUSH_DONE__RSVD_ENG2_MASK, 3370fe6a7b4SLe Ma .ref_and_mask_sdma5 = GPU_HDP_FLUSH_DONE__RSVD_ENG3_MASK, 3380fe6a7b4SLe Ma .ref_and_mask_sdma6 = GPU_HDP_FLUSH_DONE__RSVD_ENG4_MASK, 3390fe6a7b4SLe Ma .ref_and_mask_sdma7 = GPU_HDP_FLUSH_DONE__RSVD_ENG5_MASK, 340fe3c9489SFeifei Xu }; 341fe3c9489SFeifei Xu 342fe3c9489SFeifei Xu static void nbio_v7_4_init_registers(struct amdgpu_device *adev) 343fe3c9489SFeifei Xu { 344fe3c9489SFeifei Xu 345fe3c9489SFeifei Xu } 346fe3c9489SFeifei Xu 3474241863aSHawking Zhang static void nbio_v7_4_handle_ras_controller_intr_no_bifring(struct amdgpu_device *adev) 3484241863aSHawking Zhang { 3494241863aSHawking Zhang uint32_t bif_doorbell_intr_cntl; 35028f87950SLe Ma struct ras_manager *obj = amdgpu_ras_find_obj(adev, adev->nbio.ras_if); 3513cd4f618SGuchun Chen struct ras_err_data err_data = {0, 0, 0, NULL}; 352f75e94d8SGuchun Chen struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); 3534241863aSHawking Zhang 354*54e6badbSJohn Clements if (adev->asic_type == CHIP_ALDEBARAN) 355*54e6badbSJohn Clements bif_doorbell_intr_cntl = RREG32_SOC15(NBIO, 0, mmBIF_DOORBELL_INT_CNTL_ALDE); 356*54e6badbSJohn Clements else 3574241863aSHawking Zhang bif_doorbell_intr_cntl = RREG32_SOC15(NBIO, 0, mmBIF_DOORBELL_INT_CNTL); 358*54e6badbSJohn Clements 3594241863aSHawking Zhang if (REG_GET_FIELD(bif_doorbell_intr_cntl, 3604241863aSHawking Zhang BIF_DOORBELL_INT_CNTL, RAS_CNTLR_INTERRUPT_STATUS)) { 3614241863aSHawking Zhang /* driver has to clear the interrupt status when bif ring is disabled */ 3624241863aSHawking Zhang bif_doorbell_intr_cntl = REG_SET_FIELD(bif_doorbell_intr_cntl, 3634241863aSHawking Zhang BIF_DOORBELL_INT_CNTL, 3644241863aSHawking Zhang RAS_CNTLR_INTERRUPT_CLEAR, 1); 365*54e6badbSJohn Clements if (adev->asic_type == CHIP_ALDEBARAN) 366*54e6badbSJohn Clements WREG32_SOC15(NBIO, 0, mmBIF_DOORBELL_INT_CNTL_ALDE, bif_doorbell_intr_cntl); 367*54e6badbSJohn Clements else 3684241863aSHawking Zhang WREG32_SOC15(NBIO, 0, mmBIF_DOORBELL_INT_CNTL, bif_doorbell_intr_cntl); 3697c6e68c7SAndrey Grodzovsky 370f75e94d8SGuchun Chen if (!ras->disable_ras_err_cnt_harvest) { 37128f87950SLe Ma /* 372f75e94d8SGuchun Chen * clear error status after ras_controller_intr 373f75e94d8SGuchun Chen * according to hw team and count ue number 374f75e94d8SGuchun Chen * for query 37528f87950SLe Ma */ 3763cd4f618SGuchun Chen nbio_v7_4_query_ras_error_count(adev, &err_data); 3773cd4f618SGuchun Chen 378f75e94d8SGuchun Chen /* logging on error cnt and printing for awareness */ 3793cd4f618SGuchun Chen obj->err_data.ue_count += err_data.ue_count; 3803cd4f618SGuchun Chen obj->err_data.ce_count += err_data.ce_count; 3813cd4f618SGuchun Chen 3823cd4f618SGuchun Chen if (err_data.ce_count) 3836952e99cSGuchun Chen dev_info(adev->dev, "%ld correctable hardware " 3846952e99cSGuchun Chen "errors detected in %s block, " 3856952e99cSGuchun Chen "no user action is needed.\n", 3866952e99cSGuchun Chen obj->err_data.ce_count, 387893cf382SCandice Li ras_block_str(adev->nbio.ras_if->block)); 3883cd4f618SGuchun Chen 3893cd4f618SGuchun Chen if (err_data.ue_count) 3906952e99cSGuchun Chen dev_info(adev->dev, "%ld uncorrectable hardware " 3916952e99cSGuchun Chen "errors detected in %s block\n", 3926952e99cSGuchun Chen obj->err_data.ue_count, 393893cf382SCandice Li ras_block_str(adev->nbio.ras_if->block)); 394f75e94d8SGuchun Chen } 39528f87950SLe Ma 3966952e99cSGuchun Chen dev_info(adev->dev, "RAS controller interrupt triggered " 3976952e99cSGuchun Chen "by NBIF error\n"); 3984a2d9356SLe Ma 3994a2d9356SLe Ma /* ras_controller_int is dedicated for nbif ras error, 4004a2d9356SLe Ma * not the global interrupt for sync flood 4014a2d9356SLe Ma */ 40261934624SGuchun Chen amdgpu_ras_reset_gpu(adev); 4034241863aSHawking Zhang } 4044241863aSHawking Zhang } 4054241863aSHawking Zhang 4064241863aSHawking Zhang static void nbio_v7_4_handle_ras_err_event_athub_intr_no_bifring(struct amdgpu_device *adev) 4074241863aSHawking Zhang { 4084241863aSHawking Zhang uint32_t bif_doorbell_intr_cntl; 4094241863aSHawking Zhang 410*54e6badbSJohn Clements if (adev->asic_type == CHIP_ALDEBARAN) 411*54e6badbSJohn Clements bif_doorbell_intr_cntl = RREG32_SOC15(NBIO, 0, mmBIF_DOORBELL_INT_CNTL_ALDE); 412*54e6badbSJohn Clements else 4134241863aSHawking Zhang bif_doorbell_intr_cntl = RREG32_SOC15(NBIO, 0, mmBIF_DOORBELL_INT_CNTL); 414*54e6badbSJohn Clements 4154241863aSHawking Zhang if (REG_GET_FIELD(bif_doorbell_intr_cntl, 4164241863aSHawking Zhang BIF_DOORBELL_INT_CNTL, RAS_ATHUB_ERR_EVENT_INTERRUPT_STATUS)) { 4174241863aSHawking Zhang /* driver has to clear the interrupt status when bif ring is disabled */ 4184241863aSHawking Zhang bif_doorbell_intr_cntl = REG_SET_FIELD(bif_doorbell_intr_cntl, 4194241863aSHawking Zhang BIF_DOORBELL_INT_CNTL, 4204241863aSHawking Zhang RAS_ATHUB_ERR_EVENT_INTERRUPT_CLEAR, 1); 421*54e6badbSJohn Clements 422*54e6badbSJohn Clements if (adev->asic_type == CHIP_ALDEBARAN) 423*54e6badbSJohn Clements WREG32_SOC15(NBIO, 0, mmBIF_DOORBELL_INT_CNTL_ALDE, bif_doorbell_intr_cntl); 424*54e6badbSJohn Clements else 4254241863aSHawking Zhang WREG32_SOC15(NBIO, 0, mmBIF_DOORBELL_INT_CNTL, bif_doorbell_intr_cntl); 4267c6e68c7SAndrey Grodzovsky 4277c6e68c7SAndrey Grodzovsky amdgpu_ras_global_ras_isr(adev); 4284241863aSHawking Zhang } 4294241863aSHawking Zhang } 4304241863aSHawking Zhang 4314e644fffSHawking Zhang 4324e644fffSHawking Zhang static int nbio_v7_4_set_ras_controller_irq_state(struct amdgpu_device *adev, 4334e644fffSHawking Zhang struct amdgpu_irq_src *src, 4344e644fffSHawking Zhang unsigned type, 4354e644fffSHawking Zhang enum amdgpu_interrupt_state state) 4364e644fffSHawking Zhang { 4374e644fffSHawking Zhang /* The ras_controller_irq enablement should be done in psp bl when it 4384e644fffSHawking Zhang * tries to enable ras feature. Driver only need to set the correct interrupt 4394e644fffSHawking Zhang * vector for bare-metal and sriov use case respectively 4404e644fffSHawking Zhang */ 4414e644fffSHawking Zhang uint32_t bif_intr_cntl; 4424e644fffSHawking Zhang 4434e644fffSHawking Zhang bif_intr_cntl = RREG32_SOC15(NBIO, 0, mmBIF_INTR_CNTL); 4444e644fffSHawking Zhang if (state == AMDGPU_IRQ_STATE_ENABLE) { 4454e644fffSHawking Zhang /* set interrupt vector select bit to 0 to select 4464e644fffSHawking Zhang * vetcor 1 for bare metal case */ 4474e644fffSHawking Zhang bif_intr_cntl = REG_SET_FIELD(bif_intr_cntl, 4484e644fffSHawking Zhang BIF_INTR_CNTL, 4494e644fffSHawking Zhang RAS_INTR_VEC_SEL, 0); 4504e644fffSHawking Zhang WREG32_SOC15(NBIO, 0, mmBIF_INTR_CNTL, bif_intr_cntl); 4514e644fffSHawking Zhang } 4524e644fffSHawking Zhang 4534e644fffSHawking Zhang return 0; 4544e644fffSHawking Zhang } 4554e644fffSHawking Zhang 4564e644fffSHawking Zhang static int nbio_v7_4_process_ras_controller_irq(struct amdgpu_device *adev, 4574e644fffSHawking Zhang struct amdgpu_irq_src *source, 4584e644fffSHawking Zhang struct amdgpu_iv_entry *entry) 4594e644fffSHawking Zhang { 4604e644fffSHawking Zhang /* By design, the ih cookie for ras_controller_irq should be written 4614e644fffSHawking Zhang * to BIFring instead of general iv ring. However, due to known bif ring 4624e644fffSHawking Zhang * hw bug, it has to be disabled. There is no chance the process function 4634e644fffSHawking Zhang * will be involked. Just left it as a dummy one. 4644e644fffSHawking Zhang */ 4654e644fffSHawking Zhang return 0; 4664e644fffSHawking Zhang } 4674e644fffSHawking Zhang 4684e644fffSHawking Zhang static int nbio_v7_4_set_ras_err_event_athub_irq_state(struct amdgpu_device *adev, 4694e644fffSHawking Zhang struct amdgpu_irq_src *src, 4704e644fffSHawking Zhang unsigned type, 4714e644fffSHawking Zhang enum amdgpu_interrupt_state state) 4724e644fffSHawking Zhang { 4734e644fffSHawking Zhang /* The ras_controller_irq enablement should be done in psp bl when it 4744e644fffSHawking Zhang * tries to enable ras feature. Driver only need to set the correct interrupt 4754e644fffSHawking Zhang * vector for bare-metal and sriov use case respectively 4764e644fffSHawking Zhang */ 4774e644fffSHawking Zhang uint32_t bif_intr_cntl; 4784e644fffSHawking Zhang 4794e644fffSHawking Zhang bif_intr_cntl = RREG32_SOC15(NBIO, 0, mmBIF_INTR_CNTL); 4804e644fffSHawking Zhang if (state == AMDGPU_IRQ_STATE_ENABLE) { 4814e644fffSHawking Zhang /* set interrupt vector select bit to 0 to select 4824e644fffSHawking Zhang * vetcor 1 for bare metal case */ 4834e644fffSHawking Zhang bif_intr_cntl = REG_SET_FIELD(bif_intr_cntl, 4844e644fffSHawking Zhang BIF_INTR_CNTL, 4854e644fffSHawking Zhang RAS_INTR_VEC_SEL, 0); 4864e644fffSHawking Zhang WREG32_SOC15(NBIO, 0, mmBIF_INTR_CNTL, bif_intr_cntl); 4874e644fffSHawking Zhang } 4884e644fffSHawking Zhang 4894e644fffSHawking Zhang return 0; 4904e644fffSHawking Zhang } 4914e644fffSHawking Zhang 4924e644fffSHawking Zhang static int nbio_v7_4_process_err_event_athub_irq(struct amdgpu_device *adev, 4934e644fffSHawking Zhang struct amdgpu_irq_src *source, 4944e644fffSHawking Zhang struct amdgpu_iv_entry *entry) 4954e644fffSHawking Zhang { 4964e644fffSHawking Zhang /* By design, the ih cookie for err_event_athub_irq should be written 4974e644fffSHawking Zhang * to BIFring instead of general iv ring. However, due to known bif ring 4984e644fffSHawking Zhang * hw bug, it has to be disabled. There is no chance the process function 4994e644fffSHawking Zhang * will be involked. Just left it as a dummy one. 5004e644fffSHawking Zhang */ 5014e644fffSHawking Zhang return 0; 5024e644fffSHawking Zhang } 5034e644fffSHawking Zhang 5044e644fffSHawking Zhang static const struct amdgpu_irq_src_funcs nbio_v7_4_ras_controller_irq_funcs = { 5054e644fffSHawking Zhang .set = nbio_v7_4_set_ras_controller_irq_state, 5064e644fffSHawking Zhang .process = nbio_v7_4_process_ras_controller_irq, 5074e644fffSHawking Zhang }; 5084e644fffSHawking Zhang 5094e644fffSHawking Zhang static const struct amdgpu_irq_src_funcs nbio_v7_4_ras_err_event_athub_irq_funcs = { 5104e644fffSHawking Zhang .set = nbio_v7_4_set_ras_err_event_athub_irq_state, 5114e644fffSHawking Zhang .process = nbio_v7_4_process_err_event_athub_irq, 5124e644fffSHawking Zhang }; 5134e644fffSHawking Zhang 5144e644fffSHawking Zhang static int nbio_v7_4_init_ras_controller_interrupt (struct amdgpu_device *adev) 5154e644fffSHawking Zhang { 5164e644fffSHawking Zhang int r; 5174e644fffSHawking Zhang 5184e644fffSHawking Zhang /* init the irq funcs */ 5194e644fffSHawking Zhang adev->nbio.ras_controller_irq.funcs = 5204e644fffSHawking Zhang &nbio_v7_4_ras_controller_irq_funcs; 5214e644fffSHawking Zhang adev->nbio.ras_controller_irq.num_types = 1; 5224e644fffSHawking Zhang 5234e644fffSHawking Zhang /* register ras controller interrupt */ 5244e644fffSHawking Zhang r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_BIF, 5254e644fffSHawking Zhang NBIF_7_4__SRCID__RAS_CONTROLLER_INTERRUPT, 5264e644fffSHawking Zhang &adev->nbio.ras_controller_irq); 5274e644fffSHawking Zhang 5288831fa6eSGuchun Chen return r; 5294e644fffSHawking Zhang } 5304e644fffSHawking Zhang 5314e644fffSHawking Zhang static int nbio_v7_4_init_ras_err_event_athub_interrupt (struct amdgpu_device *adev) 5324e644fffSHawking Zhang { 5334e644fffSHawking Zhang 5344e644fffSHawking Zhang int r; 5354e644fffSHawking Zhang 5364e644fffSHawking Zhang /* init the irq funcs */ 5374e644fffSHawking Zhang adev->nbio.ras_err_event_athub_irq.funcs = 5384e644fffSHawking Zhang &nbio_v7_4_ras_err_event_athub_irq_funcs; 5394e644fffSHawking Zhang adev->nbio.ras_err_event_athub_irq.num_types = 1; 5404e644fffSHawking Zhang 5414e644fffSHawking Zhang /* register ras err event athub interrupt */ 5424e644fffSHawking Zhang r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_BIF, 5434e644fffSHawking Zhang NBIF_7_4__SRCID__ERREVENT_ATHUB_INTERRUPT, 5444e644fffSHawking Zhang &adev->nbio.ras_err_event_athub_irq); 5454e644fffSHawking Zhang 5468831fa6eSGuchun Chen return r; 5474e644fffSHawking Zhang } 5484e644fffSHawking Zhang 5495c39d600SLe Ma #define smnPARITY_ERROR_STATUS_UNCORR_GRP2 0x13a20030 5505c39d600SLe Ma 55152652ef2SGuchun Chen static void nbio_v7_4_query_ras_error_count(struct amdgpu_device *adev, 55252652ef2SGuchun Chen void *ras_error_status) 55352652ef2SGuchun Chen { 5545c39d600SLe Ma uint32_t global_sts, central_sts, int_eoi, parity_sts; 5551a3f2e8cSGuchun Chen uint32_t corr, fatal, non_fatal; 5561a3f2e8cSGuchun Chen struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status; 5571a3f2e8cSGuchun Chen 5581a3f2e8cSGuchun Chen global_sts = RREG32_PCIE(smnRAS_GLOBAL_STATUS_LO); 5591a3f2e8cSGuchun Chen corr = REG_GET_FIELD(global_sts, RAS_GLOBAL_STATUS_LO, ParityErrCorr); 5601a3f2e8cSGuchun Chen fatal = REG_GET_FIELD(global_sts, RAS_GLOBAL_STATUS_LO, ParityErrFatal); 5611a3f2e8cSGuchun Chen non_fatal = REG_GET_FIELD(global_sts, RAS_GLOBAL_STATUS_LO, 5621a3f2e8cSGuchun Chen ParityErrNonFatal); 5635c39d600SLe Ma parity_sts = RREG32_PCIE(smnPARITY_ERROR_STATUS_UNCORR_GRP2); 5641a3f2e8cSGuchun Chen 5651a3f2e8cSGuchun Chen if (corr) 5661a3f2e8cSGuchun Chen err_data->ce_count++; 5671a3f2e8cSGuchun Chen if (fatal) 5681a3f2e8cSGuchun Chen err_data->ue_count++; 5691a3f2e8cSGuchun Chen 5701a3f2e8cSGuchun Chen if (corr || fatal || non_fatal) { 5711a3f2e8cSGuchun Chen central_sts = RREG32_PCIE(smnBIFL_RAS_CENTRAL_STATUS); 5721a3f2e8cSGuchun Chen /* clear error status register */ 5731a3f2e8cSGuchun Chen WREG32_PCIE(smnRAS_GLOBAL_STATUS_LO, global_sts); 5741a3f2e8cSGuchun Chen 5755c39d600SLe Ma if (fatal) 5765c39d600SLe Ma /* clear parity fatal error indication field */ 5775c39d600SLe Ma WREG32_PCIE(smnPARITY_ERROR_STATUS_UNCORR_GRP2, 5785c39d600SLe Ma parity_sts); 5795c39d600SLe Ma 5801a3f2e8cSGuchun Chen if (REG_GET_FIELD(central_sts, BIFL_RAS_CENTRAL_STATUS, 5811a3f2e8cSGuchun Chen BIFL_RasContller_Intr_Recv)) { 5821a3f2e8cSGuchun Chen /* clear interrupt status register */ 5831a3f2e8cSGuchun Chen WREG32_PCIE(smnBIFL_RAS_CENTRAL_STATUS, central_sts); 5841a3f2e8cSGuchun Chen int_eoi = RREG32_PCIE(smnIOHC_INTERRUPT_EOI); 5851a3f2e8cSGuchun Chen int_eoi = REG_SET_FIELD(int_eoi, 5861a3f2e8cSGuchun Chen IOHC_INTERRUPT_EOI, SMI_EOI, 1); 5871a3f2e8cSGuchun Chen WREG32_PCIE(smnIOHC_INTERRUPT_EOI, int_eoi); 5881a3f2e8cSGuchun Chen } 5891a3f2e8cSGuchun Chen } 59052652ef2SGuchun Chen } 59152652ef2SGuchun Chen 592956f6705SLe Ma static void nbio_v7_4_enable_doorbell_interrupt(struct amdgpu_device *adev, 593956f6705SLe Ma bool enable) 594956f6705SLe Ma { 595*54e6badbSJohn Clements if (adev->asic_type == CHIP_ALDEBARAN) 596*54e6badbSJohn Clements WREG32_FIELD15(NBIO, 0, BIF_DOORBELL_INT_CNTL_ALDE, 597*54e6badbSJohn Clements DOORBELL_INTERRUPT_DISABLE, enable ? 0 : 1); 598*54e6badbSJohn Clements else 599956f6705SLe Ma WREG32_FIELD15(NBIO, 0, BIF_DOORBELL_INT_CNTL, 600956f6705SLe Ma DOORBELL_INTERRUPT_DISABLE, enable ? 0 : 1); 601956f6705SLe Ma } 602956f6705SLe Ma 6036e36f231SHawking Zhang const struct amdgpu_nbio_ras_funcs nbio_v7_4_ras_funcs = { 6046e36f231SHawking Zhang .handle_ras_controller_intr_no_bifring = nbio_v7_4_handle_ras_controller_intr_no_bifring, 6056e36f231SHawking Zhang .handle_ras_err_event_athub_intr_no_bifring = nbio_v7_4_handle_ras_err_event_athub_intr_no_bifring, 6066e36f231SHawking Zhang .init_ras_controller_interrupt = nbio_v7_4_init_ras_controller_interrupt, 6076e36f231SHawking Zhang .init_ras_err_event_athub_interrupt = nbio_v7_4_init_ras_err_event_athub_interrupt, 6086e36f231SHawking Zhang .query_ras_error_count = nbio_v7_4_query_ras_error_count, 6096e36f231SHawking Zhang .ras_late_init = amdgpu_nbio_ras_late_init, 6106e36f231SHawking Zhang .ras_fini = amdgpu_nbio_ras_fini, 6116e36f231SHawking Zhang }; 6126e36f231SHawking Zhang 6139d015c0dSKenneth Feng static void nbio_v7_4_program_ltr(struct amdgpu_device *adev) 6149d015c0dSKenneth Feng { 6159d015c0dSKenneth Feng uint32_t def, data; 6169d015c0dSKenneth Feng 6179d015c0dSKenneth Feng WREG32_PCIE(smnRCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL, 0x75EB); 6189d015c0dSKenneth Feng 6199d015c0dSKenneth Feng def = data = RREG32_PCIE(smnRCC_BIF_STRAP2); 6209d015c0dSKenneth Feng data &= ~RCC_BIF_STRAP2__STRAP_LTR_IN_ASPML1_DIS_MASK; 6219d015c0dSKenneth Feng if (def != data) 6229d015c0dSKenneth Feng WREG32_PCIE(smnRCC_BIF_STRAP2, data); 6239d015c0dSKenneth Feng 6249d015c0dSKenneth Feng def = data = RREG32_PCIE(smnRCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL); 6259d015c0dSKenneth Feng data &= ~EP_PCIE_TX_LTR_CNTL__LTR_PRIV_MSG_DIS_IN_PM_NON_D0_MASK; 6269d015c0dSKenneth Feng if (def != data) 6279d015c0dSKenneth Feng WREG32_PCIE(smnRCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL, data); 6289d015c0dSKenneth Feng 6299d015c0dSKenneth Feng def = data = RREG32_PCIE(smnBIF_CFG_DEV0_EPF0_DEVICE_CNTL2); 6309d015c0dSKenneth Feng data |= BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__LTR_EN_MASK; 6319d015c0dSKenneth Feng if (def != data) 6329d015c0dSKenneth Feng WREG32_PCIE(smnBIF_CFG_DEV0_EPF0_DEVICE_CNTL2, data); 6339d015c0dSKenneth Feng } 6349d015c0dSKenneth Feng 6359d015c0dSKenneth Feng static void nbio_v7_4_program_aspm(struct amdgpu_device *adev) 6369d015c0dSKenneth Feng { 6379d015c0dSKenneth Feng uint32_t def, data; 6389d015c0dSKenneth Feng 6399d015c0dSKenneth Feng def = data = RREG32_PCIE(smnPCIE_LC_CNTL); 6409d015c0dSKenneth Feng data &= ~PCIE_LC_CNTL__LC_L1_INACTIVITY_MASK; 6419d015c0dSKenneth Feng data &= ~PCIE_LC_CNTL__LC_L0S_INACTIVITY_MASK; 6429d015c0dSKenneth Feng data |= PCIE_LC_CNTL__LC_PMI_TO_L1_DIS_MASK; 6439d015c0dSKenneth Feng if (def != data) 6449d015c0dSKenneth Feng WREG32_PCIE(smnPCIE_LC_CNTL, data); 6459d015c0dSKenneth Feng 6469d015c0dSKenneth Feng def = data = RREG32_PCIE(smnPCIE_LC_CNTL7); 6479d015c0dSKenneth Feng data |= PCIE_LC_CNTL7__LC_NBIF_ASPM_INPUT_EN_MASK; 6489d015c0dSKenneth Feng if (def != data) 6499d015c0dSKenneth Feng WREG32_PCIE(smnPCIE_LC_CNTL7, data); 6509d015c0dSKenneth Feng 6519d015c0dSKenneth Feng def = data = RREG32_PCIE(smnNBIF_MGCG_CTRL_LCLK); 6529d015c0dSKenneth Feng data |= NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_REG_DIS_LCLK_MASK; 6539d015c0dSKenneth Feng if (def != data) 6549d015c0dSKenneth Feng WREG32_PCIE(smnNBIF_MGCG_CTRL_LCLK, data); 6559d015c0dSKenneth Feng 6569d015c0dSKenneth Feng def = data = RREG32_PCIE(smnPCIE_LC_CNTL3); 6579d015c0dSKenneth Feng data |= PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK_MASK; 6589d015c0dSKenneth Feng if (def != data) 6599d015c0dSKenneth Feng WREG32_PCIE(smnPCIE_LC_CNTL3, data); 6609d015c0dSKenneth Feng 6619d015c0dSKenneth Feng def = data = RREG32_PCIE(smnRCC_BIF_STRAP3); 6629d015c0dSKenneth Feng data &= ~RCC_BIF_STRAP3__STRAP_VLINK_ASPM_IDLE_TIMER_MASK; 6639d015c0dSKenneth Feng data &= ~RCC_BIF_STRAP3__STRAP_VLINK_PM_L1_ENTRY_TIMER_MASK; 6649d015c0dSKenneth Feng if (def != data) 6659d015c0dSKenneth Feng WREG32_PCIE(smnRCC_BIF_STRAP3, data); 6669d015c0dSKenneth Feng 6679d015c0dSKenneth Feng def = data = RREG32_PCIE(smnRCC_BIF_STRAP5); 6689d015c0dSKenneth Feng data &= ~RCC_BIF_STRAP5__STRAP_VLINK_LDN_ENTRY_TIMER_MASK; 6699d015c0dSKenneth Feng if (def != data) 6709d015c0dSKenneth Feng WREG32_PCIE(smnRCC_BIF_STRAP5, data); 6719d015c0dSKenneth Feng 6729d015c0dSKenneth Feng def = data = RREG32_PCIE(smnBIF_CFG_DEV0_EPF0_DEVICE_CNTL2); 6739d015c0dSKenneth Feng data &= ~BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__LTR_EN_MASK; 6749d015c0dSKenneth Feng if (def != data) 6759d015c0dSKenneth Feng WREG32_PCIE(smnBIF_CFG_DEV0_EPF0_DEVICE_CNTL2, data); 6769d015c0dSKenneth Feng 6779d015c0dSKenneth Feng WREG32_PCIE(smnBIF_CFG_DEV0_EPF0_PCIE_LTR_CAP, 0x10011001); 6789d015c0dSKenneth Feng 6799d015c0dSKenneth Feng def = data = RREG32_PCIE(smnPSWUSP0_PCIE_LC_CNTL2); 6809d015c0dSKenneth Feng data |= PSWUSP0_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1_MASK | 6819d015c0dSKenneth Feng PSWUSP0_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23_MASK; 6829d015c0dSKenneth Feng data &= ~PSWUSP0_PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS_MASK; 6839d015c0dSKenneth Feng if (def != data) 6849d015c0dSKenneth Feng WREG32_PCIE(smnPSWUSP0_PCIE_LC_CNTL2, data); 6859d015c0dSKenneth Feng 6869d015c0dSKenneth Feng def = data = RREG32_PCIE(smnPCIE_LC_CNTL6); 6879d015c0dSKenneth Feng data |= PCIE_LC_CNTL6__LC_L1_POWERDOWN_MASK | 6889d015c0dSKenneth Feng PCIE_LC_CNTL6__LC_RX_L0S_STANDBY_EN_MASK; 6899d015c0dSKenneth Feng if (def != data) 6909d015c0dSKenneth Feng WREG32_PCIE(smnPCIE_LC_CNTL6, data); 6919d015c0dSKenneth Feng 6929d015c0dSKenneth Feng nbio_v7_4_program_ltr(adev); 6939d015c0dSKenneth Feng 6949d015c0dSKenneth Feng def = data = RREG32_PCIE(smnRCC_BIF_STRAP3); 6959d015c0dSKenneth Feng data |= 0x5DE0 << RCC_BIF_STRAP3__STRAP_VLINK_ASPM_IDLE_TIMER__SHIFT; 6969d015c0dSKenneth Feng data |= 0x0010 << RCC_BIF_STRAP3__STRAP_VLINK_PM_L1_ENTRY_TIMER__SHIFT; 6979d015c0dSKenneth Feng if (def != data) 6989d015c0dSKenneth Feng WREG32_PCIE(smnRCC_BIF_STRAP3, data); 6999d015c0dSKenneth Feng 7009d015c0dSKenneth Feng def = data = RREG32_PCIE(smnRCC_BIF_STRAP5); 7019d015c0dSKenneth Feng data |= 0x0010 << RCC_BIF_STRAP5__STRAP_VLINK_LDN_ENTRY_TIMER__SHIFT; 7029d015c0dSKenneth Feng if (def != data) 7039d015c0dSKenneth Feng WREG32_PCIE(smnRCC_BIF_STRAP5, data); 7049d015c0dSKenneth Feng 7059d015c0dSKenneth Feng def = data = RREG32_PCIE(smnPCIE_LC_CNTL); 7069d015c0dSKenneth Feng data &= ~PCIE_LC_CNTL__LC_L0S_INACTIVITY_MASK; 7079d015c0dSKenneth Feng data |= 0x9 << PCIE_LC_CNTL__LC_L1_INACTIVITY__SHIFT; 7089d015c0dSKenneth Feng data |= 0x1 << PCIE_LC_CNTL__LC_PMI_TO_L1_DIS__SHIFT; 7099d015c0dSKenneth Feng if (def != data) 7109d015c0dSKenneth Feng WREG32_PCIE(smnPCIE_LC_CNTL, data); 7119d015c0dSKenneth Feng 7129d015c0dSKenneth Feng def = data = RREG32_PCIE(smnPCIE_LC_CNTL3); 7139d015c0dSKenneth Feng data &= ~PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK_MASK; 7149d015c0dSKenneth Feng if (def != data) 7159d015c0dSKenneth Feng WREG32_PCIE(smnPCIE_LC_CNTL3, data); 7169d015c0dSKenneth Feng } 7179d015c0dSKenneth Feng 718fe3c9489SFeifei Xu const struct amdgpu_nbio_funcs nbio_v7_4_funcs = { 719fe3c9489SFeifei Xu .get_hdp_flush_req_offset = nbio_v7_4_get_hdp_flush_req_offset, 720fe3c9489SFeifei Xu .get_hdp_flush_done_offset = nbio_v7_4_get_hdp_flush_done_offset, 721fe3c9489SFeifei Xu .get_pcie_index_offset = nbio_v7_4_get_pcie_index_offset, 722fe3c9489SFeifei Xu .get_pcie_data_offset = nbio_v7_4_get_pcie_data_offset, 723fe3c9489SFeifei Xu .get_rev_id = nbio_v7_4_get_rev_id, 724fe3c9489SFeifei Xu .mc_access_enable = nbio_v7_4_mc_access_enable, 725fe3c9489SFeifei Xu .get_memsize = nbio_v7_4_get_memsize, 726fe3c9489SFeifei Xu .sdma_doorbell_range = nbio_v7_4_sdma_doorbell_range, 72739a5053fSLeo Liu .vcn_doorbell_range = nbio_v7_4_vcn_doorbell_range, 728fe3c9489SFeifei Xu .enable_doorbell_aperture = nbio_v7_4_enable_doorbell_aperture, 729fe3c9489SFeifei Xu .enable_doorbell_selfring_aperture = nbio_v7_4_enable_doorbell_selfring_aperture, 730fe3c9489SFeifei Xu .ih_doorbell_range = nbio_v7_4_ih_doorbell_range, 731956f6705SLe Ma .enable_doorbell_interrupt = nbio_v7_4_enable_doorbell_interrupt, 732fe3c9489SFeifei Xu .update_medium_grain_clock_gating = nbio_v7_4_update_medium_grain_clock_gating, 733fe3c9489SFeifei Xu .update_medium_grain_light_sleep = nbio_v7_4_update_medium_grain_light_sleep, 734fe3c9489SFeifei Xu .get_clockgating_state = nbio_v7_4_get_clockgating_state, 735fe3c9489SFeifei Xu .ih_control = nbio_v7_4_ih_control, 736fe3c9489SFeifei Xu .init_registers = nbio_v7_4_init_registers, 73788807dc8SOak Zeng .remap_hdp_registers = nbio_v7_4_remap_hdp_registers, 7389d015c0dSKenneth Feng .program_aspm = nbio_v7_4_program_aspm, 739fe3c9489SFeifei Xu }; 740