1fe3c9489SFeifei Xu /* 2fe3c9489SFeifei Xu * Copyright 2018 Advanced Micro Devices, Inc. 3fe3c9489SFeifei Xu * 4fe3c9489SFeifei Xu * Permission is hereby granted, free of charge, to any person obtaining a 5fe3c9489SFeifei Xu * copy of this software and associated documentation files (the "Software"), 6fe3c9489SFeifei Xu * to deal in the Software without restriction, including without limitation 7fe3c9489SFeifei Xu * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8fe3c9489SFeifei Xu * and/or sell copies of the Software, and to permit persons to whom the 9fe3c9489SFeifei Xu * Software is furnished to do so, subject to the following conditions: 10fe3c9489SFeifei Xu * 11fe3c9489SFeifei Xu * The above copyright notice and this permission notice shall be included in 12fe3c9489SFeifei Xu * all copies or substantial portions of the Software. 13fe3c9489SFeifei Xu * 14fe3c9489SFeifei Xu * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15fe3c9489SFeifei Xu * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16fe3c9489SFeifei Xu * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17fe3c9489SFeifei Xu * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18fe3c9489SFeifei Xu * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19fe3c9489SFeifei Xu * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20fe3c9489SFeifei Xu * OTHER DEALINGS IN THE SOFTWARE. 21fe3c9489SFeifei Xu * 22fe3c9489SFeifei Xu */ 23fe3c9489SFeifei Xu #include "amdgpu.h" 24fe3c9489SFeifei Xu #include "amdgpu_atombios.h" 25fe3c9489SFeifei Xu #include "nbio_v7_4.h" 26fe3c9489SFeifei Xu 27fe3c9489SFeifei Xu #include "nbio/nbio_7_4_offset.h" 28fe3c9489SFeifei Xu #include "nbio/nbio_7_4_sh_mask.h" 29a0bb79e2SKent Russell #include "nbio/nbio_7_4_0_smn.h" 304e644fffSHawking Zhang #include "ivsrcid/nbio/irqsrcs_nbif_7_4.h" 3188807dc8SOak Zeng #include <uapi/linux/kfd_ioctl.h> 32fe3c9489SFeifei Xu 33fe3c9489SFeifei Xu #define smnNBIF_MGCG_CTRL_LCLK 0x1013a21c 34fe3c9489SFeifei Xu 350fe6a7b4SLe Ma /* 360fe6a7b4SLe Ma * These are nbio v7_4_1 registers mask. Temporarily define these here since 370fe6a7b4SLe Ma * nbio v7_4_1 header is incomplete. 380fe6a7b4SLe Ma */ 390fe6a7b4SLe Ma #define GPU_HDP_FLUSH_DONE__RSVD_ENG0_MASK 0x00001000L 400fe6a7b4SLe Ma #define GPU_HDP_FLUSH_DONE__RSVD_ENG1_MASK 0x00002000L 410fe6a7b4SLe Ma #define GPU_HDP_FLUSH_DONE__RSVD_ENG2_MASK 0x00004000L 420fe6a7b4SLe Ma #define GPU_HDP_FLUSH_DONE__RSVD_ENG3_MASK 0x00008000L 430fe6a7b4SLe Ma #define GPU_HDP_FLUSH_DONE__RSVD_ENG4_MASK 0x00010000L 440fe6a7b4SLe Ma #define GPU_HDP_FLUSH_DONE__RSVD_ENG5_MASK 0x00020000L 450fe6a7b4SLe Ma 46989b6a05SJames Zhu #define mmBIF_MMSCH1_DOORBELL_RANGE 0x01dc 47989b6a05SJames Zhu #define mmBIF_MMSCH1_DOORBELL_RANGE_BASE_IDX 2 48989b6a05SJames Zhu //BIF_MMSCH1_DOORBELL_RANGE 49989b6a05SJames Zhu #define BIF_MMSCH1_DOORBELL_RANGE__OFFSET__SHIFT 0x2 50989b6a05SJames Zhu #define BIF_MMSCH1_DOORBELL_RANGE__SIZE__SHIFT 0x10 51989b6a05SJames Zhu #define BIF_MMSCH1_DOORBELL_RANGE__OFFSET_MASK 0x00000FFCL 52989b6a05SJames Zhu #define BIF_MMSCH1_DOORBELL_RANGE__SIZE_MASK 0x001F0000L 53989b6a05SJames Zhu 5488807dc8SOak Zeng static void nbio_v7_4_remap_hdp_registers(struct amdgpu_device *adev) 5588807dc8SOak Zeng { 5688807dc8SOak Zeng WREG32_SOC15(NBIO, 0, mmREMAP_HDP_MEM_FLUSH_CNTL, 5788807dc8SOak Zeng adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL); 5888807dc8SOak Zeng WREG32_SOC15(NBIO, 0, mmREMAP_HDP_REG_FLUSH_CNTL, 5988807dc8SOak Zeng adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_REG_FLUSH_CNTL); 6088807dc8SOak Zeng } 6188807dc8SOak Zeng 62fe3c9489SFeifei Xu static u32 nbio_v7_4_get_rev_id(struct amdgpu_device *adev) 63fe3c9489SFeifei Xu { 64fe3c9489SFeifei Xu u32 tmp = RREG32_SOC15(NBIO, 0, mmRCC_DEV0_EPF0_STRAP0); 65fe3c9489SFeifei Xu 66fe3c9489SFeifei Xu tmp &= RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0_MASK; 67fe3c9489SFeifei Xu tmp >>= RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0__SHIFT; 68fe3c9489SFeifei Xu 69fe3c9489SFeifei Xu return tmp; 70fe3c9489SFeifei Xu } 71fe3c9489SFeifei Xu 72fe3c9489SFeifei Xu static void nbio_v7_4_mc_access_enable(struct amdgpu_device *adev, bool enable) 73fe3c9489SFeifei Xu { 74fe3c9489SFeifei Xu if (enable) 75fe3c9489SFeifei Xu WREG32_SOC15(NBIO, 0, mmBIF_FB_EN, 76fe3c9489SFeifei Xu BIF_FB_EN__FB_READ_EN_MASK | BIF_FB_EN__FB_WRITE_EN_MASK); 77fe3c9489SFeifei Xu else 78fe3c9489SFeifei Xu WREG32_SOC15(NBIO, 0, mmBIF_FB_EN, 0); 79fe3c9489SFeifei Xu } 80fe3c9489SFeifei Xu 81fe3c9489SFeifei Xu static void nbio_v7_4_hdp_flush(struct amdgpu_device *adev, 82fe3c9489SFeifei Xu struct amdgpu_ring *ring) 83fe3c9489SFeifei Xu { 84fe3c9489SFeifei Xu if (!ring || !ring->funcs->emit_wreg) 8588807dc8SOak Zeng WREG32_NO_KIQ((adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2, 0); 86fe3c9489SFeifei Xu else 8788807dc8SOak Zeng amdgpu_ring_emit_wreg(ring, (adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2, 0); 88fe3c9489SFeifei Xu } 89fe3c9489SFeifei Xu 90fe3c9489SFeifei Xu static u32 nbio_v7_4_get_memsize(struct amdgpu_device *adev) 91fe3c9489SFeifei Xu { 92fe3c9489SFeifei Xu return RREG32_SOC15(NBIO, 0, mmRCC_CONFIG_MEMSIZE); 93fe3c9489SFeifei Xu } 94fe3c9489SFeifei Xu 95fe3c9489SFeifei Xu static void nbio_v7_4_sdma_doorbell_range(struct amdgpu_device *adev, int instance, 968987e2e2SOak Zeng bool use_doorbell, int doorbell_index, int doorbell_size) 97fe3c9489SFeifei Xu { 983d81f67aSLe Ma u32 reg, doorbell_range; 99fe3c9489SFeifei Xu 1003d81f67aSLe Ma if (instance < 2) 1013d81f67aSLe Ma reg = instance + 1023d81f67aSLe Ma SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA0_DOORBELL_RANGE); 1033d81f67aSLe Ma else 1043d81f67aSLe Ma /* 1053d81f67aSLe Ma * These registers address of SDMA2~7 is not consecutive 1063d81f67aSLe Ma * from SDMA0~1. Need plus 4 dwords offset. 1073d81f67aSLe Ma * 1083d81f67aSLe Ma * BIF_SDMA0_DOORBELL_RANGE: 0x3bc0 1093d81f67aSLe Ma * BIF_SDMA1_DOORBELL_RANGE: 0x3bc4 1103d81f67aSLe Ma * BIF_SDMA2_DOORBELL_RANGE: 0x3bd8 1113d81f67aSLe Ma */ 1123d81f67aSLe Ma reg = instance + 0x4 + 1133d81f67aSLe Ma SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA0_DOORBELL_RANGE); 1143d81f67aSLe Ma 1153d81f67aSLe Ma doorbell_range = RREG32(reg); 116fe3c9489SFeifei Xu 117fe3c9489SFeifei Xu if (use_doorbell) { 118fe3c9489SFeifei Xu doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, OFFSET, doorbell_index); 1198987e2e2SOak Zeng doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, SIZE, doorbell_size); 120fe3c9489SFeifei Xu } else 121fe3c9489SFeifei Xu doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, SIZE, 0); 122fe3c9489SFeifei Xu 123fe3c9489SFeifei Xu WREG32(reg, doorbell_range); 124fe3c9489SFeifei Xu } 125fe3c9489SFeifei Xu 12639a5053fSLeo Liu static void nbio_v7_4_vcn_doorbell_range(struct amdgpu_device *adev, bool use_doorbell, 127989b6a05SJames Zhu int doorbell_index, int instance) 12839a5053fSLeo Liu { 129989b6a05SJames Zhu u32 reg; 130989b6a05SJames Zhu u32 doorbell_range; 13139a5053fSLeo Liu 132989b6a05SJames Zhu if (instance) 133989b6a05SJames Zhu reg = SOC15_REG_OFFSET(NBIO, 0, mmBIF_MMSCH1_DOORBELL_RANGE); 134989b6a05SJames Zhu else 135989b6a05SJames Zhu reg = SOC15_REG_OFFSET(NBIO, 0, mmBIF_MMSCH0_DOORBELL_RANGE); 136989b6a05SJames Zhu 137989b6a05SJames Zhu doorbell_range = RREG32(reg); 13839a5053fSLeo Liu 13939a5053fSLeo Liu if (use_doorbell) { 14039a5053fSLeo Liu doorbell_range = REG_SET_FIELD(doorbell_range, 14139a5053fSLeo Liu BIF_MMSCH0_DOORBELL_RANGE, OFFSET, 14239a5053fSLeo Liu doorbell_index); 14339a5053fSLeo Liu doorbell_range = REG_SET_FIELD(doorbell_range, 14439a5053fSLeo Liu BIF_MMSCH0_DOORBELL_RANGE, SIZE, 8); 14539a5053fSLeo Liu } else 14639a5053fSLeo Liu doorbell_range = REG_SET_FIELD(doorbell_range, 14739a5053fSLeo Liu BIF_MMSCH0_DOORBELL_RANGE, SIZE, 0); 14839a5053fSLeo Liu 14939a5053fSLeo Liu WREG32(reg, doorbell_range); 15039a5053fSLeo Liu } 15139a5053fSLeo Liu 152fe3c9489SFeifei Xu static void nbio_v7_4_enable_doorbell_aperture(struct amdgpu_device *adev, 153fe3c9489SFeifei Xu bool enable) 154fe3c9489SFeifei Xu { 155fe3c9489SFeifei Xu WREG32_FIELD15(NBIO, 0, RCC_DOORBELL_APER_EN, BIF_DOORBELL_APER_EN, enable ? 1 : 0); 156fe3c9489SFeifei Xu } 157fe3c9489SFeifei Xu 158fe3c9489SFeifei Xu static void nbio_v7_4_enable_doorbell_selfring_aperture(struct amdgpu_device *adev, 159fe3c9489SFeifei Xu bool enable) 160fe3c9489SFeifei Xu { 16112292519SJay Cornwall u32 tmp = 0; 162fe3c9489SFeifei Xu 16312292519SJay Cornwall if (enable) { 16412292519SJay Cornwall tmp = REG_SET_FIELD(tmp, DOORBELL_SELFRING_GPA_APER_CNTL, DOORBELL_SELFRING_GPA_APER_EN, 1) | 16512292519SJay Cornwall REG_SET_FIELD(tmp, DOORBELL_SELFRING_GPA_APER_CNTL, DOORBELL_SELFRING_GPA_APER_MODE, 1) | 16612292519SJay Cornwall REG_SET_FIELD(tmp, DOORBELL_SELFRING_GPA_APER_CNTL, DOORBELL_SELFRING_GPA_APER_SIZE, 0); 16712292519SJay Cornwall 16812292519SJay Cornwall WREG32_SOC15(NBIO, 0, mmDOORBELL_SELFRING_GPA_APER_BASE_LOW, 16912292519SJay Cornwall lower_32_bits(adev->doorbell.base)); 17012292519SJay Cornwall WREG32_SOC15(NBIO, 0, mmDOORBELL_SELFRING_GPA_APER_BASE_HIGH, 17112292519SJay Cornwall upper_32_bits(adev->doorbell.base)); 17212292519SJay Cornwall } 17312292519SJay Cornwall 17412292519SJay Cornwall WREG32_SOC15(NBIO, 0, mmDOORBELL_SELFRING_GPA_APER_CNTL, tmp); 175fe3c9489SFeifei Xu } 176fe3c9489SFeifei Xu 177fe3c9489SFeifei Xu static void nbio_v7_4_ih_doorbell_range(struct amdgpu_device *adev, 178fe3c9489SFeifei Xu bool use_doorbell, int doorbell_index) 179fe3c9489SFeifei Xu { 180fe3c9489SFeifei Xu u32 ih_doorbell_range = RREG32_SOC15(NBIO, 0 , mmBIF_IH_DOORBELL_RANGE); 181fe3c9489SFeifei Xu 182fe3c9489SFeifei Xu if (use_doorbell) { 183fe3c9489SFeifei Xu ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, BIF_IH_DOORBELL_RANGE, OFFSET, doorbell_index); 184fe3c9489SFeifei Xu ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, BIF_IH_DOORBELL_RANGE, SIZE, 2); 185fe3c9489SFeifei Xu } else 186fe3c9489SFeifei Xu ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, BIF_IH_DOORBELL_RANGE, SIZE, 0); 187fe3c9489SFeifei Xu 188fe3c9489SFeifei Xu WREG32_SOC15(NBIO, 0, mmBIF_IH_DOORBELL_RANGE, ih_doorbell_range); 189fe3c9489SFeifei Xu } 190fe3c9489SFeifei Xu 191fe3c9489SFeifei Xu 192fe3c9489SFeifei Xu static void nbio_v7_4_update_medium_grain_clock_gating(struct amdgpu_device *adev, 193fe3c9489SFeifei Xu bool enable) 194fe3c9489SFeifei Xu { 195fe3c9489SFeifei Xu //TODO: Add support for v7.4 196fe3c9489SFeifei Xu } 197fe3c9489SFeifei Xu 198fe3c9489SFeifei Xu static void nbio_v7_4_update_medium_grain_light_sleep(struct amdgpu_device *adev, 199fe3c9489SFeifei Xu bool enable) 200fe3c9489SFeifei Xu { 201fe3c9489SFeifei Xu uint32_t def, data; 202fe3c9489SFeifei Xu 203fe3c9489SFeifei Xu def = data = RREG32_PCIE(smnPCIE_CNTL2); 204fe3c9489SFeifei Xu if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_LS)) { 205fe3c9489SFeifei Xu data |= (PCIE_CNTL2__SLV_MEM_LS_EN_MASK | 206fe3c9489SFeifei Xu PCIE_CNTL2__MST_MEM_LS_EN_MASK | 207fe3c9489SFeifei Xu PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK); 208fe3c9489SFeifei Xu } else { 209fe3c9489SFeifei Xu data &= ~(PCIE_CNTL2__SLV_MEM_LS_EN_MASK | 210fe3c9489SFeifei Xu PCIE_CNTL2__MST_MEM_LS_EN_MASK | 211fe3c9489SFeifei Xu PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK); 212fe3c9489SFeifei Xu } 213fe3c9489SFeifei Xu 214fe3c9489SFeifei Xu if (def != data) 215fe3c9489SFeifei Xu WREG32_PCIE(smnPCIE_CNTL2, data); 216fe3c9489SFeifei Xu } 217fe3c9489SFeifei Xu 218fe3c9489SFeifei Xu static void nbio_v7_4_get_clockgating_state(struct amdgpu_device *adev, 219fe3c9489SFeifei Xu u32 *flags) 220fe3c9489SFeifei Xu { 221fe3c9489SFeifei Xu int data; 222fe3c9489SFeifei Xu 223fe3c9489SFeifei Xu /* AMD_CG_SUPPORT_BIF_MGCG */ 224fe3c9489SFeifei Xu data = RREG32_PCIE(smnCPM_CONTROL); 225fe3c9489SFeifei Xu if (data & CPM_CONTROL__LCLK_DYN_GATE_ENABLE_MASK) 226fe3c9489SFeifei Xu *flags |= AMD_CG_SUPPORT_BIF_MGCG; 227fe3c9489SFeifei Xu 228fe3c9489SFeifei Xu /* AMD_CG_SUPPORT_BIF_LS */ 229fe3c9489SFeifei Xu data = RREG32_PCIE(smnPCIE_CNTL2); 230fe3c9489SFeifei Xu if (data & PCIE_CNTL2__SLV_MEM_LS_EN_MASK) 231fe3c9489SFeifei Xu *flags |= AMD_CG_SUPPORT_BIF_LS; 232fe3c9489SFeifei Xu } 233fe3c9489SFeifei Xu 234fe3c9489SFeifei Xu static void nbio_v7_4_ih_control(struct amdgpu_device *adev) 235fe3c9489SFeifei Xu { 236fe3c9489SFeifei Xu u32 interrupt_cntl; 237fe3c9489SFeifei Xu 238fe3c9489SFeifei Xu /* setup interrupt control */ 239fe3c9489SFeifei Xu WREG32_SOC15(NBIO, 0, mmINTERRUPT_CNTL2, adev->dummy_page_addr >> 8); 240fe3c9489SFeifei Xu interrupt_cntl = RREG32_SOC15(NBIO, 0, mmINTERRUPT_CNTL); 241fe3c9489SFeifei Xu /* INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=0 - dummy read disabled with msi, enabled without msi 242fe3c9489SFeifei Xu * INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=1 - dummy read controlled by IH_DUMMY_RD_EN 243fe3c9489SFeifei Xu */ 244fe3c9489SFeifei Xu interrupt_cntl = REG_SET_FIELD(interrupt_cntl, INTERRUPT_CNTL, IH_DUMMY_RD_OVERRIDE, 0); 245fe3c9489SFeifei Xu /* INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN_MASK=1 if ring is in non-cacheable memory, e.g., vram */ 246fe3c9489SFeifei Xu interrupt_cntl = REG_SET_FIELD(interrupt_cntl, INTERRUPT_CNTL, IH_REQ_NONSNOOP_EN, 0); 247fe3c9489SFeifei Xu WREG32_SOC15(NBIO, 0, mmINTERRUPT_CNTL, interrupt_cntl); 248fe3c9489SFeifei Xu } 249fe3c9489SFeifei Xu 250fe3c9489SFeifei Xu static u32 nbio_v7_4_get_hdp_flush_req_offset(struct amdgpu_device *adev) 251fe3c9489SFeifei Xu { 252fe3c9489SFeifei Xu return SOC15_REG_OFFSET(NBIO, 0, mmGPU_HDP_FLUSH_REQ); 253fe3c9489SFeifei Xu } 254fe3c9489SFeifei Xu 255fe3c9489SFeifei Xu static u32 nbio_v7_4_get_hdp_flush_done_offset(struct amdgpu_device *adev) 256fe3c9489SFeifei Xu { 257fe3c9489SFeifei Xu return SOC15_REG_OFFSET(NBIO, 0, mmGPU_HDP_FLUSH_DONE); 258fe3c9489SFeifei Xu } 259fe3c9489SFeifei Xu 260fe3c9489SFeifei Xu static u32 nbio_v7_4_get_pcie_index_offset(struct amdgpu_device *adev) 261fe3c9489SFeifei Xu { 262fe3c9489SFeifei Xu return SOC15_REG_OFFSET(NBIO, 0, mmPCIE_INDEX2); 263fe3c9489SFeifei Xu } 264fe3c9489SFeifei Xu 265fe3c9489SFeifei Xu static u32 nbio_v7_4_get_pcie_data_offset(struct amdgpu_device *adev) 266fe3c9489SFeifei Xu { 267fe3c9489SFeifei Xu return SOC15_REG_OFFSET(NBIO, 0, mmPCIE_DATA2); 268fe3c9489SFeifei Xu } 269fe3c9489SFeifei Xu 270bebc0762SHawking Zhang const struct nbio_hdp_flush_reg nbio_v7_4_hdp_flush_reg = { 271fe3c9489SFeifei Xu .ref_and_mask_cp0 = GPU_HDP_FLUSH_DONE__CP0_MASK, 272fe3c9489SFeifei Xu .ref_and_mask_cp1 = GPU_HDP_FLUSH_DONE__CP1_MASK, 273fe3c9489SFeifei Xu .ref_and_mask_cp2 = GPU_HDP_FLUSH_DONE__CP2_MASK, 274fe3c9489SFeifei Xu .ref_and_mask_cp3 = GPU_HDP_FLUSH_DONE__CP3_MASK, 275fe3c9489SFeifei Xu .ref_and_mask_cp4 = GPU_HDP_FLUSH_DONE__CP4_MASK, 276fe3c9489SFeifei Xu .ref_and_mask_cp5 = GPU_HDP_FLUSH_DONE__CP5_MASK, 277fe3c9489SFeifei Xu .ref_and_mask_cp6 = GPU_HDP_FLUSH_DONE__CP6_MASK, 278fe3c9489SFeifei Xu .ref_and_mask_cp7 = GPU_HDP_FLUSH_DONE__CP7_MASK, 279fe3c9489SFeifei Xu .ref_and_mask_cp8 = GPU_HDP_FLUSH_DONE__CP8_MASK, 280fe3c9489SFeifei Xu .ref_and_mask_cp9 = GPU_HDP_FLUSH_DONE__CP9_MASK, 281fe3c9489SFeifei Xu .ref_and_mask_sdma0 = GPU_HDP_FLUSH_DONE__SDMA0_MASK, 282fe3c9489SFeifei Xu .ref_and_mask_sdma1 = GPU_HDP_FLUSH_DONE__SDMA1_MASK, 2830fe6a7b4SLe Ma .ref_and_mask_sdma2 = GPU_HDP_FLUSH_DONE__RSVD_ENG0_MASK, 2840fe6a7b4SLe Ma .ref_and_mask_sdma3 = GPU_HDP_FLUSH_DONE__RSVD_ENG1_MASK, 2850fe6a7b4SLe Ma .ref_and_mask_sdma4 = GPU_HDP_FLUSH_DONE__RSVD_ENG2_MASK, 2860fe6a7b4SLe Ma .ref_and_mask_sdma5 = GPU_HDP_FLUSH_DONE__RSVD_ENG3_MASK, 2870fe6a7b4SLe Ma .ref_and_mask_sdma6 = GPU_HDP_FLUSH_DONE__RSVD_ENG4_MASK, 2880fe6a7b4SLe Ma .ref_and_mask_sdma7 = GPU_HDP_FLUSH_DONE__RSVD_ENG5_MASK, 289fe3c9489SFeifei Xu }; 290fe3c9489SFeifei Xu 291fe3c9489SFeifei Xu static void nbio_v7_4_detect_hw_virt(struct amdgpu_device *adev) 292fe3c9489SFeifei Xu { 293a2045ee6SFrank Min uint32_t reg; 294a2045ee6SFrank Min 295a2045ee6SFrank Min reg = RREG32_SOC15(NBIO, 0, mmRCC_IOV_FUNC_IDENTIFIER); 296a2045ee6SFrank Min if (reg & 1) 297a2045ee6SFrank Min adev->virt.caps |= AMDGPU_SRIOV_CAPS_IS_VF; 298a2045ee6SFrank Min 299a2045ee6SFrank Min if (reg & 0x80000000) 300a2045ee6SFrank Min adev->virt.caps |= AMDGPU_SRIOV_CAPS_ENABLE_IOV; 301a2045ee6SFrank Min 302a2045ee6SFrank Min if (!reg) { 303fe3c9489SFeifei Xu if (is_virtual_machine()) /* passthrough mode exclus sriov mod */ 304fe3c9489SFeifei Xu adev->virt.caps |= AMDGPU_PASSTHROUGH_MODE; 305fe3c9489SFeifei Xu } 306a2045ee6SFrank Min } 307fe3c9489SFeifei Xu 308fe3c9489SFeifei Xu static void nbio_v7_4_init_registers(struct amdgpu_device *adev) 309fe3c9489SFeifei Xu { 310e01f2d41SAlex Deucher uint32_t def, data; 311fe3c9489SFeifei Xu 312e01f2d41SAlex Deucher def = data = RREG32_PCIE(smnPCIE_CI_CNTL); 313e01f2d41SAlex Deucher data = REG_SET_FIELD(data, PCIE_CI_CNTL, CI_SLV_ORDERING_DIS, 1); 314e01f2d41SAlex Deucher 315e01f2d41SAlex Deucher if (def != data) 316e01f2d41SAlex Deucher WREG32_PCIE(smnPCIE_CI_CNTL, data); 317fe3c9489SFeifei Xu } 318fe3c9489SFeifei Xu 3194241863aSHawking Zhang static void nbio_v7_4_handle_ras_controller_intr_no_bifring(struct amdgpu_device *adev) 3204241863aSHawking Zhang { 3214241863aSHawking Zhang uint32_t bif_doorbell_intr_cntl; 3224241863aSHawking Zhang 3234241863aSHawking Zhang bif_doorbell_intr_cntl = RREG32_SOC15(NBIO, 0, mmBIF_DOORBELL_INT_CNTL); 3244241863aSHawking Zhang if (REG_GET_FIELD(bif_doorbell_intr_cntl, 3254241863aSHawking Zhang BIF_DOORBELL_INT_CNTL, RAS_CNTLR_INTERRUPT_STATUS)) { 3264241863aSHawking Zhang /* driver has to clear the interrupt status when bif ring is disabled */ 3274241863aSHawking Zhang bif_doorbell_intr_cntl = REG_SET_FIELD(bif_doorbell_intr_cntl, 3284241863aSHawking Zhang BIF_DOORBELL_INT_CNTL, 3294241863aSHawking Zhang RAS_CNTLR_INTERRUPT_CLEAR, 1); 3304241863aSHawking Zhang WREG32_SOC15(NBIO, 0, mmBIF_DOORBELL_INT_CNTL, bif_doorbell_intr_cntl); 3314241863aSHawking Zhang } 3324241863aSHawking Zhang } 3334241863aSHawking Zhang 3344241863aSHawking Zhang static void nbio_v7_4_handle_ras_err_event_athub_intr_no_bifring(struct amdgpu_device *adev) 3354241863aSHawking Zhang { 3364241863aSHawking Zhang uint32_t bif_doorbell_intr_cntl; 3374241863aSHawking Zhang 3384241863aSHawking Zhang bif_doorbell_intr_cntl = RREG32_SOC15(NBIO, 0, mmBIF_DOORBELL_INT_CNTL); 3394241863aSHawking Zhang if (REG_GET_FIELD(bif_doorbell_intr_cntl, 3404241863aSHawking Zhang BIF_DOORBELL_INT_CNTL, RAS_ATHUB_ERR_EVENT_INTERRUPT_STATUS)) { 3414241863aSHawking Zhang /* driver has to clear the interrupt status when bif ring is disabled */ 3424241863aSHawking Zhang bif_doorbell_intr_cntl = REG_SET_FIELD(bif_doorbell_intr_cntl, 3434241863aSHawking Zhang BIF_DOORBELL_INT_CNTL, 3444241863aSHawking Zhang RAS_ATHUB_ERR_EVENT_INTERRUPT_CLEAR, 1); 3454241863aSHawking Zhang WREG32_SOC15(NBIO, 0, mmBIF_DOORBELL_INT_CNTL, bif_doorbell_intr_cntl); 3464241863aSHawking Zhang } 3474241863aSHawking Zhang } 3484241863aSHawking Zhang 3494e644fffSHawking Zhang 3504e644fffSHawking Zhang static int nbio_v7_4_set_ras_controller_irq_state(struct amdgpu_device *adev, 3514e644fffSHawking Zhang struct amdgpu_irq_src *src, 3524e644fffSHawking Zhang unsigned type, 3534e644fffSHawking Zhang enum amdgpu_interrupt_state state) 3544e644fffSHawking Zhang { 3554e644fffSHawking Zhang /* The ras_controller_irq enablement should be done in psp bl when it 3564e644fffSHawking Zhang * tries to enable ras feature. Driver only need to set the correct interrupt 3574e644fffSHawking Zhang * vector for bare-metal and sriov use case respectively 3584e644fffSHawking Zhang */ 3594e644fffSHawking Zhang uint32_t bif_intr_cntl; 3604e644fffSHawking Zhang 3614e644fffSHawking Zhang bif_intr_cntl = RREG32_SOC15(NBIO, 0, mmBIF_INTR_CNTL); 3624e644fffSHawking Zhang if (state == AMDGPU_IRQ_STATE_ENABLE) { 3634e644fffSHawking Zhang /* set interrupt vector select bit to 0 to select 3644e644fffSHawking Zhang * vetcor 1 for bare metal case */ 3654e644fffSHawking Zhang bif_intr_cntl = REG_SET_FIELD(bif_intr_cntl, 3664e644fffSHawking Zhang BIF_INTR_CNTL, 3674e644fffSHawking Zhang RAS_INTR_VEC_SEL, 0); 3684e644fffSHawking Zhang WREG32_SOC15(NBIO, 0, mmBIF_INTR_CNTL, bif_intr_cntl); 3694e644fffSHawking Zhang } 3704e644fffSHawking Zhang 3714e644fffSHawking Zhang return 0; 3724e644fffSHawking Zhang } 3734e644fffSHawking Zhang 3744e644fffSHawking Zhang static int nbio_v7_4_process_ras_controller_irq(struct amdgpu_device *adev, 3754e644fffSHawking Zhang struct amdgpu_irq_src *source, 3764e644fffSHawking Zhang struct amdgpu_iv_entry *entry) 3774e644fffSHawking Zhang { 3784e644fffSHawking Zhang /* By design, the ih cookie for ras_controller_irq should be written 3794e644fffSHawking Zhang * to BIFring instead of general iv ring. However, due to known bif ring 3804e644fffSHawking Zhang * hw bug, it has to be disabled. There is no chance the process function 3814e644fffSHawking Zhang * will be involked. Just left it as a dummy one. 3824e644fffSHawking Zhang */ 3834e644fffSHawking Zhang return 0; 3844e644fffSHawking Zhang } 3854e644fffSHawking Zhang 3864e644fffSHawking Zhang static int nbio_v7_4_set_ras_err_event_athub_irq_state(struct amdgpu_device *adev, 3874e644fffSHawking Zhang struct amdgpu_irq_src *src, 3884e644fffSHawking Zhang unsigned type, 3894e644fffSHawking Zhang enum amdgpu_interrupt_state state) 3904e644fffSHawking Zhang { 3914e644fffSHawking Zhang /* The ras_controller_irq enablement should be done in psp bl when it 3924e644fffSHawking Zhang * tries to enable ras feature. Driver only need to set the correct interrupt 3934e644fffSHawking Zhang * vector for bare-metal and sriov use case respectively 3944e644fffSHawking Zhang */ 3954e644fffSHawking Zhang uint32_t bif_intr_cntl; 3964e644fffSHawking Zhang 3974e644fffSHawking Zhang bif_intr_cntl = RREG32_SOC15(NBIO, 0, mmBIF_INTR_CNTL); 3984e644fffSHawking Zhang if (state == AMDGPU_IRQ_STATE_ENABLE) { 3994e644fffSHawking Zhang /* set interrupt vector select bit to 0 to select 4004e644fffSHawking Zhang * vetcor 1 for bare metal case */ 4014e644fffSHawking Zhang bif_intr_cntl = REG_SET_FIELD(bif_intr_cntl, 4024e644fffSHawking Zhang BIF_INTR_CNTL, 4034e644fffSHawking Zhang RAS_INTR_VEC_SEL, 0); 4044e644fffSHawking Zhang WREG32_SOC15(NBIO, 0, mmBIF_INTR_CNTL, bif_intr_cntl); 4054e644fffSHawking Zhang } 4064e644fffSHawking Zhang 4074e644fffSHawking Zhang return 0; 4084e644fffSHawking Zhang } 4094e644fffSHawking Zhang 4104e644fffSHawking Zhang static int nbio_v7_4_process_err_event_athub_irq(struct amdgpu_device *adev, 4114e644fffSHawking Zhang struct amdgpu_irq_src *source, 4124e644fffSHawking Zhang struct amdgpu_iv_entry *entry) 4134e644fffSHawking Zhang { 4144e644fffSHawking Zhang /* By design, the ih cookie for err_event_athub_irq should be written 4154e644fffSHawking Zhang * to BIFring instead of general iv ring. However, due to known bif ring 4164e644fffSHawking Zhang * hw bug, it has to be disabled. There is no chance the process function 4174e644fffSHawking Zhang * will be involked. Just left it as a dummy one. 4184e644fffSHawking Zhang */ 4194e644fffSHawking Zhang return 0; 4204e644fffSHawking Zhang } 4214e644fffSHawking Zhang 4224e644fffSHawking Zhang static const struct amdgpu_irq_src_funcs nbio_v7_4_ras_controller_irq_funcs = { 4234e644fffSHawking Zhang .set = nbio_v7_4_set_ras_controller_irq_state, 4244e644fffSHawking Zhang .process = nbio_v7_4_process_ras_controller_irq, 4254e644fffSHawking Zhang }; 4264e644fffSHawking Zhang 4274e644fffSHawking Zhang static const struct amdgpu_irq_src_funcs nbio_v7_4_ras_err_event_athub_irq_funcs = { 4284e644fffSHawking Zhang .set = nbio_v7_4_set_ras_err_event_athub_irq_state, 4294e644fffSHawking Zhang .process = nbio_v7_4_process_err_event_athub_irq, 4304e644fffSHawking Zhang }; 4314e644fffSHawking Zhang 4324e644fffSHawking Zhang static int nbio_v7_4_init_ras_controller_interrupt (struct amdgpu_device *adev) 4334e644fffSHawking Zhang { 4344e644fffSHawking Zhang int r; 4354e644fffSHawking Zhang 4364e644fffSHawking Zhang /* init the irq funcs */ 4374e644fffSHawking Zhang adev->nbio.ras_controller_irq.funcs = 4384e644fffSHawking Zhang &nbio_v7_4_ras_controller_irq_funcs; 4394e644fffSHawking Zhang adev->nbio.ras_controller_irq.num_types = 1; 4404e644fffSHawking Zhang 4414e644fffSHawking Zhang /* register ras controller interrupt */ 4424e644fffSHawking Zhang r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_BIF, 4434e644fffSHawking Zhang NBIF_7_4__SRCID__RAS_CONTROLLER_INTERRUPT, 4444e644fffSHawking Zhang &adev->nbio.ras_controller_irq); 4454e644fffSHawking Zhang if (r) 4464e644fffSHawking Zhang return r; 4474e644fffSHawking Zhang 4484e644fffSHawking Zhang return 0; 4494e644fffSHawking Zhang } 4504e644fffSHawking Zhang 4514e644fffSHawking Zhang static int nbio_v7_4_init_ras_err_event_athub_interrupt (struct amdgpu_device *adev) 4524e644fffSHawking Zhang { 4534e644fffSHawking Zhang 4544e644fffSHawking Zhang int r; 4554e644fffSHawking Zhang 4564e644fffSHawking Zhang /* init the irq funcs */ 4574e644fffSHawking Zhang adev->nbio.ras_err_event_athub_irq.funcs = 4584e644fffSHawking Zhang &nbio_v7_4_ras_err_event_athub_irq_funcs; 4594e644fffSHawking Zhang adev->nbio.ras_err_event_athub_irq.num_types = 1; 4604e644fffSHawking Zhang 4614e644fffSHawking Zhang /* register ras err event athub interrupt */ 4624e644fffSHawking Zhang r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_BIF, 4634e644fffSHawking Zhang NBIF_7_4__SRCID__ERREVENT_ATHUB_INTERRUPT, 4644e644fffSHawking Zhang &adev->nbio.ras_err_event_athub_irq); 4654e644fffSHawking Zhang if (r) 4664e644fffSHawking Zhang return r; 4674e644fffSHawking Zhang 4684e644fffSHawking Zhang return 0; 4694e644fffSHawking Zhang } 4704e644fffSHawking Zhang 471fe3c9489SFeifei Xu const struct amdgpu_nbio_funcs nbio_v7_4_funcs = { 472fe3c9489SFeifei Xu .get_hdp_flush_req_offset = nbio_v7_4_get_hdp_flush_req_offset, 473fe3c9489SFeifei Xu .get_hdp_flush_done_offset = nbio_v7_4_get_hdp_flush_done_offset, 474fe3c9489SFeifei Xu .get_pcie_index_offset = nbio_v7_4_get_pcie_index_offset, 475fe3c9489SFeifei Xu .get_pcie_data_offset = nbio_v7_4_get_pcie_data_offset, 476fe3c9489SFeifei Xu .get_rev_id = nbio_v7_4_get_rev_id, 477fe3c9489SFeifei Xu .mc_access_enable = nbio_v7_4_mc_access_enable, 478fe3c9489SFeifei Xu .hdp_flush = nbio_v7_4_hdp_flush, 479fe3c9489SFeifei Xu .get_memsize = nbio_v7_4_get_memsize, 480fe3c9489SFeifei Xu .sdma_doorbell_range = nbio_v7_4_sdma_doorbell_range, 48139a5053fSLeo Liu .vcn_doorbell_range = nbio_v7_4_vcn_doorbell_range, 482fe3c9489SFeifei Xu .enable_doorbell_aperture = nbio_v7_4_enable_doorbell_aperture, 483fe3c9489SFeifei Xu .enable_doorbell_selfring_aperture = nbio_v7_4_enable_doorbell_selfring_aperture, 484fe3c9489SFeifei Xu .ih_doorbell_range = nbio_v7_4_ih_doorbell_range, 485fe3c9489SFeifei Xu .update_medium_grain_clock_gating = nbio_v7_4_update_medium_grain_clock_gating, 486fe3c9489SFeifei Xu .update_medium_grain_light_sleep = nbio_v7_4_update_medium_grain_light_sleep, 487fe3c9489SFeifei Xu .get_clockgating_state = nbio_v7_4_get_clockgating_state, 488fe3c9489SFeifei Xu .ih_control = nbio_v7_4_ih_control, 489fe3c9489SFeifei Xu .init_registers = nbio_v7_4_init_registers, 490fe3c9489SFeifei Xu .detect_hw_virt = nbio_v7_4_detect_hw_virt, 49188807dc8SOak Zeng .remap_hdp_registers = nbio_v7_4_remap_hdp_registers, 4924241863aSHawking Zhang .handle_ras_controller_intr_no_bifring = nbio_v7_4_handle_ras_controller_intr_no_bifring, 4934241863aSHawking Zhang .handle_ras_err_event_athub_intr_no_bifring = nbio_v7_4_handle_ras_err_event_athub_intr_no_bifring, 4944e644fffSHawking Zhang .init_ras_controller_interrupt = nbio_v7_4_init_ras_controller_interrupt, 4954e644fffSHawking Zhang .init_ras_err_event_athub_interrupt = nbio_v7_4_init_ras_err_event_athub_interrupt, 496fe3c9489SFeifei Xu }; 497