1fe3c9489SFeifei Xu /* 2fe3c9489SFeifei Xu * Copyright 2018 Advanced Micro Devices, Inc. 3fe3c9489SFeifei Xu * 4fe3c9489SFeifei Xu * Permission is hereby granted, free of charge, to any person obtaining a 5fe3c9489SFeifei Xu * copy of this software and associated documentation files (the "Software"), 6fe3c9489SFeifei Xu * to deal in the Software without restriction, including without limitation 7fe3c9489SFeifei Xu * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8fe3c9489SFeifei Xu * and/or sell copies of the Software, and to permit persons to whom the 9fe3c9489SFeifei Xu * Software is furnished to do so, subject to the following conditions: 10fe3c9489SFeifei Xu * 11fe3c9489SFeifei Xu * The above copyright notice and this permission notice shall be included in 12fe3c9489SFeifei Xu * all copies or substantial portions of the Software. 13fe3c9489SFeifei Xu * 14fe3c9489SFeifei Xu * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15fe3c9489SFeifei Xu * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16fe3c9489SFeifei Xu * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17fe3c9489SFeifei Xu * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18fe3c9489SFeifei Xu * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19fe3c9489SFeifei Xu * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20fe3c9489SFeifei Xu * OTHER DEALINGS IN THE SOFTWARE. 21fe3c9489SFeifei Xu * 22fe3c9489SFeifei Xu */ 23fe3c9489SFeifei Xu #include "amdgpu.h" 24fe3c9489SFeifei Xu #include "amdgpu_atombios.h" 25fe3c9489SFeifei Xu #include "nbio_v7_4.h" 26fe3c9489SFeifei Xu 27fe3c9489SFeifei Xu #include "nbio/nbio_7_4_offset.h" 28fe3c9489SFeifei Xu #include "nbio/nbio_7_4_sh_mask.h" 29a0bb79e2SKent Russell #include "nbio/nbio_7_4_0_smn.h" 3088807dc8SOak Zeng #include <uapi/linux/kfd_ioctl.h> 31fe3c9489SFeifei Xu 32fe3c9489SFeifei Xu #define smnNBIF_MGCG_CTRL_LCLK 0x1013a21c 33fe3c9489SFeifei Xu 340fe6a7b4SLe Ma /* 350fe6a7b4SLe Ma * These are nbio v7_4_1 registers mask. Temporarily define these here since 360fe6a7b4SLe Ma * nbio v7_4_1 header is incomplete. 370fe6a7b4SLe Ma */ 380fe6a7b4SLe Ma #define GPU_HDP_FLUSH_DONE__RSVD_ENG0_MASK 0x00001000L 390fe6a7b4SLe Ma #define GPU_HDP_FLUSH_DONE__RSVD_ENG1_MASK 0x00002000L 400fe6a7b4SLe Ma #define GPU_HDP_FLUSH_DONE__RSVD_ENG2_MASK 0x00004000L 410fe6a7b4SLe Ma #define GPU_HDP_FLUSH_DONE__RSVD_ENG3_MASK 0x00008000L 420fe6a7b4SLe Ma #define GPU_HDP_FLUSH_DONE__RSVD_ENG4_MASK 0x00010000L 430fe6a7b4SLe Ma #define GPU_HDP_FLUSH_DONE__RSVD_ENG5_MASK 0x00020000L 440fe6a7b4SLe Ma 4588807dc8SOak Zeng static void nbio_v7_4_remap_hdp_registers(struct amdgpu_device *adev) 4688807dc8SOak Zeng { 4788807dc8SOak Zeng WREG32_SOC15(NBIO, 0, mmREMAP_HDP_MEM_FLUSH_CNTL, 4888807dc8SOak Zeng adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL); 4988807dc8SOak Zeng WREG32_SOC15(NBIO, 0, mmREMAP_HDP_REG_FLUSH_CNTL, 5088807dc8SOak Zeng adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_REG_FLUSH_CNTL); 5188807dc8SOak Zeng } 5288807dc8SOak Zeng 53fe3c9489SFeifei Xu static u32 nbio_v7_4_get_rev_id(struct amdgpu_device *adev) 54fe3c9489SFeifei Xu { 55fe3c9489SFeifei Xu u32 tmp = RREG32_SOC15(NBIO, 0, mmRCC_DEV0_EPF0_STRAP0); 56fe3c9489SFeifei Xu 57fe3c9489SFeifei Xu tmp &= RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0_MASK; 58fe3c9489SFeifei Xu tmp >>= RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0__SHIFT; 59fe3c9489SFeifei Xu 60fe3c9489SFeifei Xu return tmp; 61fe3c9489SFeifei Xu } 62fe3c9489SFeifei Xu 63fe3c9489SFeifei Xu static void nbio_v7_4_mc_access_enable(struct amdgpu_device *adev, bool enable) 64fe3c9489SFeifei Xu { 65fe3c9489SFeifei Xu if (enable) 66fe3c9489SFeifei Xu WREG32_SOC15(NBIO, 0, mmBIF_FB_EN, 67fe3c9489SFeifei Xu BIF_FB_EN__FB_READ_EN_MASK | BIF_FB_EN__FB_WRITE_EN_MASK); 68fe3c9489SFeifei Xu else 69fe3c9489SFeifei Xu WREG32_SOC15(NBIO, 0, mmBIF_FB_EN, 0); 70fe3c9489SFeifei Xu } 71fe3c9489SFeifei Xu 72fe3c9489SFeifei Xu static void nbio_v7_4_hdp_flush(struct amdgpu_device *adev, 73fe3c9489SFeifei Xu struct amdgpu_ring *ring) 74fe3c9489SFeifei Xu { 75fe3c9489SFeifei Xu if (!ring || !ring->funcs->emit_wreg) 7688807dc8SOak Zeng WREG32_NO_KIQ((adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2, 0); 77fe3c9489SFeifei Xu else 7888807dc8SOak Zeng amdgpu_ring_emit_wreg(ring, (adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2, 0); 79fe3c9489SFeifei Xu } 80fe3c9489SFeifei Xu 81fe3c9489SFeifei Xu static u32 nbio_v7_4_get_memsize(struct amdgpu_device *adev) 82fe3c9489SFeifei Xu { 83fe3c9489SFeifei Xu return RREG32_SOC15(NBIO, 0, mmRCC_CONFIG_MEMSIZE); 84fe3c9489SFeifei Xu } 85fe3c9489SFeifei Xu 86fe3c9489SFeifei Xu static void nbio_v7_4_sdma_doorbell_range(struct amdgpu_device *adev, int instance, 878987e2e2SOak Zeng bool use_doorbell, int doorbell_index, int doorbell_size) 88fe3c9489SFeifei Xu { 893d81f67aSLe Ma u32 reg, doorbell_range; 90fe3c9489SFeifei Xu 913d81f67aSLe Ma if (instance < 2) 923d81f67aSLe Ma reg = instance + 933d81f67aSLe Ma SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA0_DOORBELL_RANGE); 943d81f67aSLe Ma else 953d81f67aSLe Ma /* 963d81f67aSLe Ma * These registers address of SDMA2~7 is not consecutive 973d81f67aSLe Ma * from SDMA0~1. Need plus 4 dwords offset. 983d81f67aSLe Ma * 993d81f67aSLe Ma * BIF_SDMA0_DOORBELL_RANGE: 0x3bc0 1003d81f67aSLe Ma * BIF_SDMA1_DOORBELL_RANGE: 0x3bc4 1013d81f67aSLe Ma * BIF_SDMA2_DOORBELL_RANGE: 0x3bd8 1023d81f67aSLe Ma */ 1033d81f67aSLe Ma reg = instance + 0x4 + 1043d81f67aSLe Ma SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA0_DOORBELL_RANGE); 1053d81f67aSLe Ma 1063d81f67aSLe Ma doorbell_range = RREG32(reg); 107fe3c9489SFeifei Xu 108fe3c9489SFeifei Xu if (use_doorbell) { 109fe3c9489SFeifei Xu doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, OFFSET, doorbell_index); 1108987e2e2SOak Zeng doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, SIZE, doorbell_size); 111fe3c9489SFeifei Xu } else 112fe3c9489SFeifei Xu doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, SIZE, 0); 113fe3c9489SFeifei Xu 114fe3c9489SFeifei Xu WREG32(reg, doorbell_range); 115fe3c9489SFeifei Xu } 116fe3c9489SFeifei Xu 117fe3c9489SFeifei Xu static void nbio_v7_4_enable_doorbell_aperture(struct amdgpu_device *adev, 118fe3c9489SFeifei Xu bool enable) 119fe3c9489SFeifei Xu { 120fe3c9489SFeifei Xu WREG32_FIELD15(NBIO, 0, RCC_DOORBELL_APER_EN, BIF_DOORBELL_APER_EN, enable ? 1 : 0); 121fe3c9489SFeifei Xu } 122fe3c9489SFeifei Xu 123fe3c9489SFeifei Xu static void nbio_v7_4_enable_doorbell_selfring_aperture(struct amdgpu_device *adev, 124fe3c9489SFeifei Xu bool enable) 125fe3c9489SFeifei Xu { 12612292519SJay Cornwall u32 tmp = 0; 127fe3c9489SFeifei Xu 12812292519SJay Cornwall if (enable) { 12912292519SJay Cornwall tmp = REG_SET_FIELD(tmp, DOORBELL_SELFRING_GPA_APER_CNTL, DOORBELL_SELFRING_GPA_APER_EN, 1) | 13012292519SJay Cornwall REG_SET_FIELD(tmp, DOORBELL_SELFRING_GPA_APER_CNTL, DOORBELL_SELFRING_GPA_APER_MODE, 1) | 13112292519SJay Cornwall REG_SET_FIELD(tmp, DOORBELL_SELFRING_GPA_APER_CNTL, DOORBELL_SELFRING_GPA_APER_SIZE, 0); 13212292519SJay Cornwall 13312292519SJay Cornwall WREG32_SOC15(NBIO, 0, mmDOORBELL_SELFRING_GPA_APER_BASE_LOW, 13412292519SJay Cornwall lower_32_bits(adev->doorbell.base)); 13512292519SJay Cornwall WREG32_SOC15(NBIO, 0, mmDOORBELL_SELFRING_GPA_APER_BASE_HIGH, 13612292519SJay Cornwall upper_32_bits(adev->doorbell.base)); 13712292519SJay Cornwall } 13812292519SJay Cornwall 13912292519SJay Cornwall WREG32_SOC15(NBIO, 0, mmDOORBELL_SELFRING_GPA_APER_CNTL, tmp); 140fe3c9489SFeifei Xu } 141fe3c9489SFeifei Xu 142fe3c9489SFeifei Xu static void nbio_v7_4_ih_doorbell_range(struct amdgpu_device *adev, 143fe3c9489SFeifei Xu bool use_doorbell, int doorbell_index) 144fe3c9489SFeifei Xu { 145fe3c9489SFeifei Xu u32 ih_doorbell_range = RREG32_SOC15(NBIO, 0 , mmBIF_IH_DOORBELL_RANGE); 146fe3c9489SFeifei Xu 147fe3c9489SFeifei Xu if (use_doorbell) { 148fe3c9489SFeifei Xu ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, BIF_IH_DOORBELL_RANGE, OFFSET, doorbell_index); 149fe3c9489SFeifei Xu ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, BIF_IH_DOORBELL_RANGE, SIZE, 2); 150fe3c9489SFeifei Xu } else 151fe3c9489SFeifei Xu ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, BIF_IH_DOORBELL_RANGE, SIZE, 0); 152fe3c9489SFeifei Xu 153fe3c9489SFeifei Xu WREG32_SOC15(NBIO, 0, mmBIF_IH_DOORBELL_RANGE, ih_doorbell_range); 154fe3c9489SFeifei Xu } 155fe3c9489SFeifei Xu 156fe3c9489SFeifei Xu 157fe3c9489SFeifei Xu static void nbio_v7_4_update_medium_grain_clock_gating(struct amdgpu_device *adev, 158fe3c9489SFeifei Xu bool enable) 159fe3c9489SFeifei Xu { 160fe3c9489SFeifei Xu //TODO: Add support for v7.4 161fe3c9489SFeifei Xu } 162fe3c9489SFeifei Xu 163fe3c9489SFeifei Xu static void nbio_v7_4_update_medium_grain_light_sleep(struct amdgpu_device *adev, 164fe3c9489SFeifei Xu bool enable) 165fe3c9489SFeifei Xu { 166fe3c9489SFeifei Xu uint32_t def, data; 167fe3c9489SFeifei Xu 168fe3c9489SFeifei Xu def = data = RREG32_PCIE(smnPCIE_CNTL2); 169fe3c9489SFeifei Xu if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_LS)) { 170fe3c9489SFeifei Xu data |= (PCIE_CNTL2__SLV_MEM_LS_EN_MASK | 171fe3c9489SFeifei Xu PCIE_CNTL2__MST_MEM_LS_EN_MASK | 172fe3c9489SFeifei Xu PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK); 173fe3c9489SFeifei Xu } else { 174fe3c9489SFeifei Xu data &= ~(PCIE_CNTL2__SLV_MEM_LS_EN_MASK | 175fe3c9489SFeifei Xu PCIE_CNTL2__MST_MEM_LS_EN_MASK | 176fe3c9489SFeifei Xu PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK); 177fe3c9489SFeifei Xu } 178fe3c9489SFeifei Xu 179fe3c9489SFeifei Xu if (def != data) 180fe3c9489SFeifei Xu WREG32_PCIE(smnPCIE_CNTL2, data); 181fe3c9489SFeifei Xu } 182fe3c9489SFeifei Xu 183fe3c9489SFeifei Xu static void nbio_v7_4_get_clockgating_state(struct amdgpu_device *adev, 184fe3c9489SFeifei Xu u32 *flags) 185fe3c9489SFeifei Xu { 186fe3c9489SFeifei Xu int data; 187fe3c9489SFeifei Xu 188fe3c9489SFeifei Xu /* AMD_CG_SUPPORT_BIF_MGCG */ 189fe3c9489SFeifei Xu data = RREG32_PCIE(smnCPM_CONTROL); 190fe3c9489SFeifei Xu if (data & CPM_CONTROL__LCLK_DYN_GATE_ENABLE_MASK) 191fe3c9489SFeifei Xu *flags |= AMD_CG_SUPPORT_BIF_MGCG; 192fe3c9489SFeifei Xu 193fe3c9489SFeifei Xu /* AMD_CG_SUPPORT_BIF_LS */ 194fe3c9489SFeifei Xu data = RREG32_PCIE(smnPCIE_CNTL2); 195fe3c9489SFeifei Xu if (data & PCIE_CNTL2__SLV_MEM_LS_EN_MASK) 196fe3c9489SFeifei Xu *flags |= AMD_CG_SUPPORT_BIF_LS; 197fe3c9489SFeifei Xu } 198fe3c9489SFeifei Xu 199fe3c9489SFeifei Xu static void nbio_v7_4_ih_control(struct amdgpu_device *adev) 200fe3c9489SFeifei Xu { 201fe3c9489SFeifei Xu u32 interrupt_cntl; 202fe3c9489SFeifei Xu 203fe3c9489SFeifei Xu /* setup interrupt control */ 204fe3c9489SFeifei Xu WREG32_SOC15(NBIO, 0, mmINTERRUPT_CNTL2, adev->dummy_page_addr >> 8); 205fe3c9489SFeifei Xu interrupt_cntl = RREG32_SOC15(NBIO, 0, mmINTERRUPT_CNTL); 206fe3c9489SFeifei Xu /* INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=0 - dummy read disabled with msi, enabled without msi 207fe3c9489SFeifei Xu * INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=1 - dummy read controlled by IH_DUMMY_RD_EN 208fe3c9489SFeifei Xu */ 209fe3c9489SFeifei Xu interrupt_cntl = REG_SET_FIELD(interrupt_cntl, INTERRUPT_CNTL, IH_DUMMY_RD_OVERRIDE, 0); 210fe3c9489SFeifei Xu /* INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN_MASK=1 if ring is in non-cacheable memory, e.g., vram */ 211fe3c9489SFeifei Xu interrupt_cntl = REG_SET_FIELD(interrupt_cntl, INTERRUPT_CNTL, IH_REQ_NONSNOOP_EN, 0); 212fe3c9489SFeifei Xu WREG32_SOC15(NBIO, 0, mmINTERRUPT_CNTL, interrupt_cntl); 213fe3c9489SFeifei Xu } 214fe3c9489SFeifei Xu 215fe3c9489SFeifei Xu static u32 nbio_v7_4_get_hdp_flush_req_offset(struct amdgpu_device *adev) 216fe3c9489SFeifei Xu { 217fe3c9489SFeifei Xu return SOC15_REG_OFFSET(NBIO, 0, mmGPU_HDP_FLUSH_REQ); 218fe3c9489SFeifei Xu } 219fe3c9489SFeifei Xu 220fe3c9489SFeifei Xu static u32 nbio_v7_4_get_hdp_flush_done_offset(struct amdgpu_device *adev) 221fe3c9489SFeifei Xu { 222fe3c9489SFeifei Xu return SOC15_REG_OFFSET(NBIO, 0, mmGPU_HDP_FLUSH_DONE); 223fe3c9489SFeifei Xu } 224fe3c9489SFeifei Xu 225fe3c9489SFeifei Xu static u32 nbio_v7_4_get_pcie_index_offset(struct amdgpu_device *adev) 226fe3c9489SFeifei Xu { 227fe3c9489SFeifei Xu return SOC15_REG_OFFSET(NBIO, 0, mmPCIE_INDEX2); 228fe3c9489SFeifei Xu } 229fe3c9489SFeifei Xu 230fe3c9489SFeifei Xu static u32 nbio_v7_4_get_pcie_data_offset(struct amdgpu_device *adev) 231fe3c9489SFeifei Xu { 232fe3c9489SFeifei Xu return SOC15_REG_OFFSET(NBIO, 0, mmPCIE_DATA2); 233fe3c9489SFeifei Xu } 234fe3c9489SFeifei Xu 235fe3c9489SFeifei Xu static const struct nbio_hdp_flush_reg nbio_v7_4_hdp_flush_reg = { 236fe3c9489SFeifei Xu .ref_and_mask_cp0 = GPU_HDP_FLUSH_DONE__CP0_MASK, 237fe3c9489SFeifei Xu .ref_and_mask_cp1 = GPU_HDP_FLUSH_DONE__CP1_MASK, 238fe3c9489SFeifei Xu .ref_and_mask_cp2 = GPU_HDP_FLUSH_DONE__CP2_MASK, 239fe3c9489SFeifei Xu .ref_and_mask_cp3 = GPU_HDP_FLUSH_DONE__CP3_MASK, 240fe3c9489SFeifei Xu .ref_and_mask_cp4 = GPU_HDP_FLUSH_DONE__CP4_MASK, 241fe3c9489SFeifei Xu .ref_and_mask_cp5 = GPU_HDP_FLUSH_DONE__CP5_MASK, 242fe3c9489SFeifei Xu .ref_and_mask_cp6 = GPU_HDP_FLUSH_DONE__CP6_MASK, 243fe3c9489SFeifei Xu .ref_and_mask_cp7 = GPU_HDP_FLUSH_DONE__CP7_MASK, 244fe3c9489SFeifei Xu .ref_and_mask_cp8 = GPU_HDP_FLUSH_DONE__CP8_MASK, 245fe3c9489SFeifei Xu .ref_and_mask_cp9 = GPU_HDP_FLUSH_DONE__CP9_MASK, 246fe3c9489SFeifei Xu .ref_and_mask_sdma0 = GPU_HDP_FLUSH_DONE__SDMA0_MASK, 247fe3c9489SFeifei Xu .ref_and_mask_sdma1 = GPU_HDP_FLUSH_DONE__SDMA1_MASK, 2480fe6a7b4SLe Ma .ref_and_mask_sdma2 = GPU_HDP_FLUSH_DONE__RSVD_ENG0_MASK, 2490fe6a7b4SLe Ma .ref_and_mask_sdma3 = GPU_HDP_FLUSH_DONE__RSVD_ENG1_MASK, 2500fe6a7b4SLe Ma .ref_and_mask_sdma4 = GPU_HDP_FLUSH_DONE__RSVD_ENG2_MASK, 2510fe6a7b4SLe Ma .ref_and_mask_sdma5 = GPU_HDP_FLUSH_DONE__RSVD_ENG3_MASK, 2520fe6a7b4SLe Ma .ref_and_mask_sdma6 = GPU_HDP_FLUSH_DONE__RSVD_ENG4_MASK, 2530fe6a7b4SLe Ma .ref_and_mask_sdma7 = GPU_HDP_FLUSH_DONE__RSVD_ENG5_MASK, 254fe3c9489SFeifei Xu }; 255fe3c9489SFeifei Xu 256fe3c9489SFeifei Xu static void nbio_v7_4_detect_hw_virt(struct amdgpu_device *adev) 257fe3c9489SFeifei Xu { 258a2045ee6SFrank Min uint32_t reg; 259a2045ee6SFrank Min 260a2045ee6SFrank Min reg = RREG32_SOC15(NBIO, 0, mmRCC_IOV_FUNC_IDENTIFIER); 261a2045ee6SFrank Min if (reg & 1) 262a2045ee6SFrank Min adev->virt.caps |= AMDGPU_SRIOV_CAPS_IS_VF; 263a2045ee6SFrank Min 264a2045ee6SFrank Min if (reg & 0x80000000) 265a2045ee6SFrank Min adev->virt.caps |= AMDGPU_SRIOV_CAPS_ENABLE_IOV; 266a2045ee6SFrank Min 267a2045ee6SFrank Min if (!reg) { 268fe3c9489SFeifei Xu if (is_virtual_machine()) /* passthrough mode exclus sriov mod */ 269fe3c9489SFeifei Xu adev->virt.caps |= AMDGPU_PASSTHROUGH_MODE; 270fe3c9489SFeifei Xu } 271a2045ee6SFrank Min } 272fe3c9489SFeifei Xu 273fe3c9489SFeifei Xu static void nbio_v7_4_init_registers(struct amdgpu_device *adev) 274fe3c9489SFeifei Xu { 275e01f2d41SAlex Deucher uint32_t def, data; 276fe3c9489SFeifei Xu 277e01f2d41SAlex Deucher def = data = RREG32_PCIE(smnPCIE_CI_CNTL); 278e01f2d41SAlex Deucher data = REG_SET_FIELD(data, PCIE_CI_CNTL, CI_SLV_ORDERING_DIS, 1); 279e01f2d41SAlex Deucher 280e01f2d41SAlex Deucher if (def != data) 281e01f2d41SAlex Deucher WREG32_PCIE(smnPCIE_CI_CNTL, data); 282fe3c9489SFeifei Xu } 283fe3c9489SFeifei Xu 284fe3c9489SFeifei Xu const struct amdgpu_nbio_funcs nbio_v7_4_funcs = { 285fe3c9489SFeifei Xu .hdp_flush_reg = &nbio_v7_4_hdp_flush_reg, 286fe3c9489SFeifei Xu .get_hdp_flush_req_offset = nbio_v7_4_get_hdp_flush_req_offset, 287fe3c9489SFeifei Xu .get_hdp_flush_done_offset = nbio_v7_4_get_hdp_flush_done_offset, 288fe3c9489SFeifei Xu .get_pcie_index_offset = nbio_v7_4_get_pcie_index_offset, 289fe3c9489SFeifei Xu .get_pcie_data_offset = nbio_v7_4_get_pcie_data_offset, 290fe3c9489SFeifei Xu .get_rev_id = nbio_v7_4_get_rev_id, 291fe3c9489SFeifei Xu .mc_access_enable = nbio_v7_4_mc_access_enable, 292fe3c9489SFeifei Xu .hdp_flush = nbio_v7_4_hdp_flush, 293fe3c9489SFeifei Xu .get_memsize = nbio_v7_4_get_memsize, 294fe3c9489SFeifei Xu .sdma_doorbell_range = nbio_v7_4_sdma_doorbell_range, 295fe3c9489SFeifei Xu .enable_doorbell_aperture = nbio_v7_4_enable_doorbell_aperture, 296fe3c9489SFeifei Xu .enable_doorbell_selfring_aperture = nbio_v7_4_enable_doorbell_selfring_aperture, 297fe3c9489SFeifei Xu .ih_doorbell_range = nbio_v7_4_ih_doorbell_range, 298fe3c9489SFeifei Xu .update_medium_grain_clock_gating = nbio_v7_4_update_medium_grain_clock_gating, 299fe3c9489SFeifei Xu .update_medium_grain_light_sleep = nbio_v7_4_update_medium_grain_light_sleep, 300fe3c9489SFeifei Xu .get_clockgating_state = nbio_v7_4_get_clockgating_state, 301fe3c9489SFeifei Xu .ih_control = nbio_v7_4_ih_control, 302fe3c9489SFeifei Xu .init_registers = nbio_v7_4_init_registers, 303fe3c9489SFeifei Xu .detect_hw_virt = nbio_v7_4_detect_hw_virt, 30488807dc8SOak Zeng .remap_hdp_registers = nbio_v7_4_remap_hdp_registers, 305fe3c9489SFeifei Xu }; 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