1fe3c9489SFeifei Xu /* 2fe3c9489SFeifei Xu * Copyright 2018 Advanced Micro Devices, Inc. 3fe3c9489SFeifei Xu * 4fe3c9489SFeifei Xu * Permission is hereby granted, free of charge, to any person obtaining a 5fe3c9489SFeifei Xu * copy of this software and associated documentation files (the "Software"), 6fe3c9489SFeifei Xu * to deal in the Software without restriction, including without limitation 7fe3c9489SFeifei Xu * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8fe3c9489SFeifei Xu * and/or sell copies of the Software, and to permit persons to whom the 9fe3c9489SFeifei Xu * Software is furnished to do so, subject to the following conditions: 10fe3c9489SFeifei Xu * 11fe3c9489SFeifei Xu * The above copyright notice and this permission notice shall be included in 12fe3c9489SFeifei Xu * all copies or substantial portions of the Software. 13fe3c9489SFeifei Xu * 14fe3c9489SFeifei Xu * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15fe3c9489SFeifei Xu * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16fe3c9489SFeifei Xu * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17fe3c9489SFeifei Xu * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18fe3c9489SFeifei Xu * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19fe3c9489SFeifei Xu * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20fe3c9489SFeifei Xu * OTHER DEALINGS IN THE SOFTWARE. 21fe3c9489SFeifei Xu * 22fe3c9489SFeifei Xu */ 23fe3c9489SFeifei Xu #include "amdgpu.h" 24fe3c9489SFeifei Xu #include "amdgpu_atombios.h" 25fe3c9489SFeifei Xu #include "nbio_v7_4.h" 269ad1dc29SHawking Zhang #include "amdgpu_ras.h" 27fe3c9489SFeifei Xu 28fe3c9489SFeifei Xu #include "nbio/nbio_7_4_offset.h" 29fe3c9489SFeifei Xu #include "nbio/nbio_7_4_sh_mask.h" 30a0bb79e2SKent Russell #include "nbio/nbio_7_4_0_smn.h" 314e644fffSHawking Zhang #include "ivsrcid/nbio/irqsrcs_nbif_7_4.h" 3288807dc8SOak Zeng #include <uapi/linux/kfd_ioctl.h> 337c6e68c7SAndrey Grodzovsky #include "amdgpu_ras.h" 34fe3c9489SFeifei Xu 35fe3c9489SFeifei Xu #define smnNBIF_MGCG_CTRL_LCLK 0x1013a21c 36fe3c9489SFeifei Xu 370fe6a7b4SLe Ma /* 380fe6a7b4SLe Ma * These are nbio v7_4_1 registers mask. Temporarily define these here since 390fe6a7b4SLe Ma * nbio v7_4_1 header is incomplete. 400fe6a7b4SLe Ma */ 410fe6a7b4SLe Ma #define GPU_HDP_FLUSH_DONE__RSVD_ENG0_MASK 0x00001000L 420fe6a7b4SLe Ma #define GPU_HDP_FLUSH_DONE__RSVD_ENG1_MASK 0x00002000L 430fe6a7b4SLe Ma #define GPU_HDP_FLUSH_DONE__RSVD_ENG2_MASK 0x00004000L 440fe6a7b4SLe Ma #define GPU_HDP_FLUSH_DONE__RSVD_ENG3_MASK 0x00008000L 450fe6a7b4SLe Ma #define GPU_HDP_FLUSH_DONE__RSVD_ENG4_MASK 0x00010000L 460fe6a7b4SLe Ma #define GPU_HDP_FLUSH_DONE__RSVD_ENG5_MASK 0x00020000L 470fe6a7b4SLe Ma 48989b6a05SJames Zhu #define mmBIF_MMSCH1_DOORBELL_RANGE 0x01dc 49989b6a05SJames Zhu #define mmBIF_MMSCH1_DOORBELL_RANGE_BASE_IDX 2 50989b6a05SJames Zhu //BIF_MMSCH1_DOORBELL_RANGE 51989b6a05SJames Zhu #define BIF_MMSCH1_DOORBELL_RANGE__OFFSET__SHIFT 0x2 52989b6a05SJames Zhu #define BIF_MMSCH1_DOORBELL_RANGE__SIZE__SHIFT 0x10 53989b6a05SJames Zhu #define BIF_MMSCH1_DOORBELL_RANGE__OFFSET_MASK 0x00000FFCL 54989b6a05SJames Zhu #define BIF_MMSCH1_DOORBELL_RANGE__SIZE_MASK 0x001F0000L 55989b6a05SJames Zhu 5688807dc8SOak Zeng static void nbio_v7_4_remap_hdp_registers(struct amdgpu_device *adev) 5788807dc8SOak Zeng { 5888807dc8SOak Zeng WREG32_SOC15(NBIO, 0, mmREMAP_HDP_MEM_FLUSH_CNTL, 5988807dc8SOak Zeng adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL); 6088807dc8SOak Zeng WREG32_SOC15(NBIO, 0, mmREMAP_HDP_REG_FLUSH_CNTL, 6188807dc8SOak Zeng adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_REG_FLUSH_CNTL); 6288807dc8SOak Zeng } 6388807dc8SOak Zeng 64fe3c9489SFeifei Xu static u32 nbio_v7_4_get_rev_id(struct amdgpu_device *adev) 65fe3c9489SFeifei Xu { 66fe3c9489SFeifei Xu u32 tmp = RREG32_SOC15(NBIO, 0, mmRCC_DEV0_EPF0_STRAP0); 67fe3c9489SFeifei Xu 68fe3c9489SFeifei Xu tmp &= RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0_MASK; 69fe3c9489SFeifei Xu tmp >>= RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0__SHIFT; 70fe3c9489SFeifei Xu 71fe3c9489SFeifei Xu return tmp; 72fe3c9489SFeifei Xu } 73fe3c9489SFeifei Xu 74fe3c9489SFeifei Xu static void nbio_v7_4_mc_access_enable(struct amdgpu_device *adev, bool enable) 75fe3c9489SFeifei Xu { 76fe3c9489SFeifei Xu if (enable) 77fe3c9489SFeifei Xu WREG32_SOC15(NBIO, 0, mmBIF_FB_EN, 78fe3c9489SFeifei Xu BIF_FB_EN__FB_READ_EN_MASK | BIF_FB_EN__FB_WRITE_EN_MASK); 79fe3c9489SFeifei Xu else 80fe3c9489SFeifei Xu WREG32_SOC15(NBIO, 0, mmBIF_FB_EN, 0); 81fe3c9489SFeifei Xu } 82fe3c9489SFeifei Xu 83fe3c9489SFeifei Xu static void nbio_v7_4_hdp_flush(struct amdgpu_device *adev, 84fe3c9489SFeifei Xu struct amdgpu_ring *ring) 85fe3c9489SFeifei Xu { 86fe3c9489SFeifei Xu if (!ring || !ring->funcs->emit_wreg) 8788807dc8SOak Zeng WREG32_NO_KIQ((adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2, 0); 88fe3c9489SFeifei Xu else 8988807dc8SOak Zeng amdgpu_ring_emit_wreg(ring, (adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2, 0); 90fe3c9489SFeifei Xu } 91fe3c9489SFeifei Xu 92fe3c9489SFeifei Xu static u32 nbio_v7_4_get_memsize(struct amdgpu_device *adev) 93fe3c9489SFeifei Xu { 94fe3c9489SFeifei Xu return RREG32_SOC15(NBIO, 0, mmRCC_CONFIG_MEMSIZE); 95fe3c9489SFeifei Xu } 96fe3c9489SFeifei Xu 97fe3c9489SFeifei Xu static void nbio_v7_4_sdma_doorbell_range(struct amdgpu_device *adev, int instance, 988987e2e2SOak Zeng bool use_doorbell, int doorbell_index, int doorbell_size) 99fe3c9489SFeifei Xu { 1003d81f67aSLe Ma u32 reg, doorbell_range; 101fe3c9489SFeifei Xu 1023d81f67aSLe Ma if (instance < 2) 1033d81f67aSLe Ma reg = instance + 1043d81f67aSLe Ma SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA0_DOORBELL_RANGE); 1053d81f67aSLe Ma else 1063d81f67aSLe Ma /* 1073d81f67aSLe Ma * These registers address of SDMA2~7 is not consecutive 1083d81f67aSLe Ma * from SDMA0~1. Need plus 4 dwords offset. 1093d81f67aSLe Ma * 1103d81f67aSLe Ma * BIF_SDMA0_DOORBELL_RANGE: 0x3bc0 1113d81f67aSLe Ma * BIF_SDMA1_DOORBELL_RANGE: 0x3bc4 1123d81f67aSLe Ma * BIF_SDMA2_DOORBELL_RANGE: 0x3bd8 1133d81f67aSLe Ma */ 1143d81f67aSLe Ma reg = instance + 0x4 + 1153d81f67aSLe Ma SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA0_DOORBELL_RANGE); 1163d81f67aSLe Ma 1173d81f67aSLe Ma doorbell_range = RREG32(reg); 118fe3c9489SFeifei Xu 119fe3c9489SFeifei Xu if (use_doorbell) { 120fe3c9489SFeifei Xu doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, OFFSET, doorbell_index); 1218987e2e2SOak Zeng doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, SIZE, doorbell_size); 122fe3c9489SFeifei Xu } else 123fe3c9489SFeifei Xu doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, SIZE, 0); 124fe3c9489SFeifei Xu 125fe3c9489SFeifei Xu WREG32(reg, doorbell_range); 126fe3c9489SFeifei Xu } 127fe3c9489SFeifei Xu 12839a5053fSLeo Liu static void nbio_v7_4_vcn_doorbell_range(struct amdgpu_device *adev, bool use_doorbell, 129989b6a05SJames Zhu int doorbell_index, int instance) 13039a5053fSLeo Liu { 131989b6a05SJames Zhu u32 reg; 132989b6a05SJames Zhu u32 doorbell_range; 13339a5053fSLeo Liu 134989b6a05SJames Zhu if (instance) 135989b6a05SJames Zhu reg = SOC15_REG_OFFSET(NBIO, 0, mmBIF_MMSCH1_DOORBELL_RANGE); 136989b6a05SJames Zhu else 137989b6a05SJames Zhu reg = SOC15_REG_OFFSET(NBIO, 0, mmBIF_MMSCH0_DOORBELL_RANGE); 138989b6a05SJames Zhu 139989b6a05SJames Zhu doorbell_range = RREG32(reg); 14039a5053fSLeo Liu 14139a5053fSLeo Liu if (use_doorbell) { 14239a5053fSLeo Liu doorbell_range = REG_SET_FIELD(doorbell_range, 14339a5053fSLeo Liu BIF_MMSCH0_DOORBELL_RANGE, OFFSET, 14439a5053fSLeo Liu doorbell_index); 14539a5053fSLeo Liu doorbell_range = REG_SET_FIELD(doorbell_range, 14639a5053fSLeo Liu BIF_MMSCH0_DOORBELL_RANGE, SIZE, 8); 14739a5053fSLeo Liu } else 14839a5053fSLeo Liu doorbell_range = REG_SET_FIELD(doorbell_range, 14939a5053fSLeo Liu BIF_MMSCH0_DOORBELL_RANGE, SIZE, 0); 15039a5053fSLeo Liu 15139a5053fSLeo Liu WREG32(reg, doorbell_range); 15239a5053fSLeo Liu } 15339a5053fSLeo Liu 154fe3c9489SFeifei Xu static void nbio_v7_4_enable_doorbell_aperture(struct amdgpu_device *adev, 155fe3c9489SFeifei Xu bool enable) 156fe3c9489SFeifei Xu { 157fe3c9489SFeifei Xu WREG32_FIELD15(NBIO, 0, RCC_DOORBELL_APER_EN, BIF_DOORBELL_APER_EN, enable ? 1 : 0); 158fe3c9489SFeifei Xu } 159fe3c9489SFeifei Xu 160fe3c9489SFeifei Xu static void nbio_v7_4_enable_doorbell_selfring_aperture(struct amdgpu_device *adev, 161fe3c9489SFeifei Xu bool enable) 162fe3c9489SFeifei Xu { 16312292519SJay Cornwall u32 tmp = 0; 164fe3c9489SFeifei Xu 16512292519SJay Cornwall if (enable) { 16612292519SJay Cornwall tmp = REG_SET_FIELD(tmp, DOORBELL_SELFRING_GPA_APER_CNTL, DOORBELL_SELFRING_GPA_APER_EN, 1) | 16712292519SJay Cornwall REG_SET_FIELD(tmp, DOORBELL_SELFRING_GPA_APER_CNTL, DOORBELL_SELFRING_GPA_APER_MODE, 1) | 16812292519SJay Cornwall REG_SET_FIELD(tmp, DOORBELL_SELFRING_GPA_APER_CNTL, DOORBELL_SELFRING_GPA_APER_SIZE, 0); 16912292519SJay Cornwall 17012292519SJay Cornwall WREG32_SOC15(NBIO, 0, mmDOORBELL_SELFRING_GPA_APER_BASE_LOW, 17112292519SJay Cornwall lower_32_bits(adev->doorbell.base)); 17212292519SJay Cornwall WREG32_SOC15(NBIO, 0, mmDOORBELL_SELFRING_GPA_APER_BASE_HIGH, 17312292519SJay Cornwall upper_32_bits(adev->doorbell.base)); 17412292519SJay Cornwall } 17512292519SJay Cornwall 17612292519SJay Cornwall WREG32_SOC15(NBIO, 0, mmDOORBELL_SELFRING_GPA_APER_CNTL, tmp); 177fe3c9489SFeifei Xu } 178fe3c9489SFeifei Xu 179fe3c9489SFeifei Xu static void nbio_v7_4_ih_doorbell_range(struct amdgpu_device *adev, 180fe3c9489SFeifei Xu bool use_doorbell, int doorbell_index) 181fe3c9489SFeifei Xu { 182fe3c9489SFeifei Xu u32 ih_doorbell_range = RREG32_SOC15(NBIO, 0 , mmBIF_IH_DOORBELL_RANGE); 183fe3c9489SFeifei Xu 184fe3c9489SFeifei Xu if (use_doorbell) { 185fe3c9489SFeifei Xu ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, BIF_IH_DOORBELL_RANGE, OFFSET, doorbell_index); 186fe3c9489SFeifei Xu ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, BIF_IH_DOORBELL_RANGE, SIZE, 2); 187fe3c9489SFeifei Xu } else 188fe3c9489SFeifei Xu ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, BIF_IH_DOORBELL_RANGE, SIZE, 0); 189fe3c9489SFeifei Xu 190fe3c9489SFeifei Xu WREG32_SOC15(NBIO, 0, mmBIF_IH_DOORBELL_RANGE, ih_doorbell_range); 191fe3c9489SFeifei Xu } 192fe3c9489SFeifei Xu 193fe3c9489SFeifei Xu 194fe3c9489SFeifei Xu static void nbio_v7_4_update_medium_grain_clock_gating(struct amdgpu_device *adev, 195fe3c9489SFeifei Xu bool enable) 196fe3c9489SFeifei Xu { 197fe3c9489SFeifei Xu //TODO: Add support for v7.4 198fe3c9489SFeifei Xu } 199fe3c9489SFeifei Xu 200fe3c9489SFeifei Xu static void nbio_v7_4_update_medium_grain_light_sleep(struct amdgpu_device *adev, 201fe3c9489SFeifei Xu bool enable) 202fe3c9489SFeifei Xu { 203fe3c9489SFeifei Xu uint32_t def, data; 204fe3c9489SFeifei Xu 205fe3c9489SFeifei Xu def = data = RREG32_PCIE(smnPCIE_CNTL2); 206fe3c9489SFeifei Xu if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_LS)) { 207fe3c9489SFeifei Xu data |= (PCIE_CNTL2__SLV_MEM_LS_EN_MASK | 208fe3c9489SFeifei Xu PCIE_CNTL2__MST_MEM_LS_EN_MASK | 209fe3c9489SFeifei Xu PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK); 210fe3c9489SFeifei Xu } else { 211fe3c9489SFeifei Xu data &= ~(PCIE_CNTL2__SLV_MEM_LS_EN_MASK | 212fe3c9489SFeifei Xu PCIE_CNTL2__MST_MEM_LS_EN_MASK | 213fe3c9489SFeifei Xu PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK); 214fe3c9489SFeifei Xu } 215fe3c9489SFeifei Xu 216fe3c9489SFeifei Xu if (def != data) 217fe3c9489SFeifei Xu WREG32_PCIE(smnPCIE_CNTL2, data); 218fe3c9489SFeifei Xu } 219fe3c9489SFeifei Xu 220fe3c9489SFeifei Xu static void nbio_v7_4_get_clockgating_state(struct amdgpu_device *adev, 221fe3c9489SFeifei Xu u32 *flags) 222fe3c9489SFeifei Xu { 223fe3c9489SFeifei Xu int data; 224fe3c9489SFeifei Xu 225fe3c9489SFeifei Xu /* AMD_CG_SUPPORT_BIF_MGCG */ 226fe3c9489SFeifei Xu data = RREG32_PCIE(smnCPM_CONTROL); 227fe3c9489SFeifei Xu if (data & CPM_CONTROL__LCLK_DYN_GATE_ENABLE_MASK) 228fe3c9489SFeifei Xu *flags |= AMD_CG_SUPPORT_BIF_MGCG; 229fe3c9489SFeifei Xu 230fe3c9489SFeifei Xu /* AMD_CG_SUPPORT_BIF_LS */ 231fe3c9489SFeifei Xu data = RREG32_PCIE(smnPCIE_CNTL2); 232fe3c9489SFeifei Xu if (data & PCIE_CNTL2__SLV_MEM_LS_EN_MASK) 233fe3c9489SFeifei Xu *flags |= AMD_CG_SUPPORT_BIF_LS; 234fe3c9489SFeifei Xu } 235fe3c9489SFeifei Xu 236fe3c9489SFeifei Xu static void nbio_v7_4_ih_control(struct amdgpu_device *adev) 237fe3c9489SFeifei Xu { 238fe3c9489SFeifei Xu u32 interrupt_cntl; 239fe3c9489SFeifei Xu 240fe3c9489SFeifei Xu /* setup interrupt control */ 241fe3c9489SFeifei Xu WREG32_SOC15(NBIO, 0, mmINTERRUPT_CNTL2, adev->dummy_page_addr >> 8); 242fe3c9489SFeifei Xu interrupt_cntl = RREG32_SOC15(NBIO, 0, mmINTERRUPT_CNTL); 243fe3c9489SFeifei Xu /* INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=0 - dummy read disabled with msi, enabled without msi 244fe3c9489SFeifei Xu * INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=1 - dummy read controlled by IH_DUMMY_RD_EN 245fe3c9489SFeifei Xu */ 246fe3c9489SFeifei Xu interrupt_cntl = REG_SET_FIELD(interrupt_cntl, INTERRUPT_CNTL, IH_DUMMY_RD_OVERRIDE, 0); 247fe3c9489SFeifei Xu /* INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN_MASK=1 if ring is in non-cacheable memory, e.g., vram */ 248fe3c9489SFeifei Xu interrupt_cntl = REG_SET_FIELD(interrupt_cntl, INTERRUPT_CNTL, IH_REQ_NONSNOOP_EN, 0); 249fe3c9489SFeifei Xu WREG32_SOC15(NBIO, 0, mmINTERRUPT_CNTL, interrupt_cntl); 250fe3c9489SFeifei Xu } 251fe3c9489SFeifei Xu 252fe3c9489SFeifei Xu static u32 nbio_v7_4_get_hdp_flush_req_offset(struct amdgpu_device *adev) 253fe3c9489SFeifei Xu { 254fe3c9489SFeifei Xu return SOC15_REG_OFFSET(NBIO, 0, mmGPU_HDP_FLUSH_REQ); 255fe3c9489SFeifei Xu } 256fe3c9489SFeifei Xu 257fe3c9489SFeifei Xu static u32 nbio_v7_4_get_hdp_flush_done_offset(struct amdgpu_device *adev) 258fe3c9489SFeifei Xu { 259fe3c9489SFeifei Xu return SOC15_REG_OFFSET(NBIO, 0, mmGPU_HDP_FLUSH_DONE); 260fe3c9489SFeifei Xu } 261fe3c9489SFeifei Xu 262fe3c9489SFeifei Xu static u32 nbio_v7_4_get_pcie_index_offset(struct amdgpu_device *adev) 263fe3c9489SFeifei Xu { 264fe3c9489SFeifei Xu return SOC15_REG_OFFSET(NBIO, 0, mmPCIE_INDEX2); 265fe3c9489SFeifei Xu } 266fe3c9489SFeifei Xu 267fe3c9489SFeifei Xu static u32 nbio_v7_4_get_pcie_data_offset(struct amdgpu_device *adev) 268fe3c9489SFeifei Xu { 269fe3c9489SFeifei Xu return SOC15_REG_OFFSET(NBIO, 0, mmPCIE_DATA2); 270fe3c9489SFeifei Xu } 271fe3c9489SFeifei Xu 272bebc0762SHawking Zhang const struct nbio_hdp_flush_reg nbio_v7_4_hdp_flush_reg = { 273fe3c9489SFeifei Xu .ref_and_mask_cp0 = GPU_HDP_FLUSH_DONE__CP0_MASK, 274fe3c9489SFeifei Xu .ref_and_mask_cp1 = GPU_HDP_FLUSH_DONE__CP1_MASK, 275fe3c9489SFeifei Xu .ref_and_mask_cp2 = GPU_HDP_FLUSH_DONE__CP2_MASK, 276fe3c9489SFeifei Xu .ref_and_mask_cp3 = GPU_HDP_FLUSH_DONE__CP3_MASK, 277fe3c9489SFeifei Xu .ref_and_mask_cp4 = GPU_HDP_FLUSH_DONE__CP4_MASK, 278fe3c9489SFeifei Xu .ref_and_mask_cp5 = GPU_HDP_FLUSH_DONE__CP5_MASK, 279fe3c9489SFeifei Xu .ref_and_mask_cp6 = GPU_HDP_FLUSH_DONE__CP6_MASK, 280fe3c9489SFeifei Xu .ref_and_mask_cp7 = GPU_HDP_FLUSH_DONE__CP7_MASK, 281fe3c9489SFeifei Xu .ref_and_mask_cp8 = GPU_HDP_FLUSH_DONE__CP8_MASK, 282fe3c9489SFeifei Xu .ref_and_mask_cp9 = GPU_HDP_FLUSH_DONE__CP9_MASK, 283fe3c9489SFeifei Xu .ref_and_mask_sdma0 = GPU_HDP_FLUSH_DONE__SDMA0_MASK, 284fe3c9489SFeifei Xu .ref_and_mask_sdma1 = GPU_HDP_FLUSH_DONE__SDMA1_MASK, 2850fe6a7b4SLe Ma .ref_and_mask_sdma2 = GPU_HDP_FLUSH_DONE__RSVD_ENG0_MASK, 2860fe6a7b4SLe Ma .ref_and_mask_sdma3 = GPU_HDP_FLUSH_DONE__RSVD_ENG1_MASK, 2870fe6a7b4SLe Ma .ref_and_mask_sdma4 = GPU_HDP_FLUSH_DONE__RSVD_ENG2_MASK, 2880fe6a7b4SLe Ma .ref_and_mask_sdma5 = GPU_HDP_FLUSH_DONE__RSVD_ENG3_MASK, 2890fe6a7b4SLe Ma .ref_and_mask_sdma6 = GPU_HDP_FLUSH_DONE__RSVD_ENG4_MASK, 2900fe6a7b4SLe Ma .ref_and_mask_sdma7 = GPU_HDP_FLUSH_DONE__RSVD_ENG5_MASK, 291fe3c9489SFeifei Xu }; 292fe3c9489SFeifei Xu 293fe3c9489SFeifei Xu static void nbio_v7_4_detect_hw_virt(struct amdgpu_device *adev) 294fe3c9489SFeifei Xu { 295a2045ee6SFrank Min uint32_t reg; 296a2045ee6SFrank Min 297a2045ee6SFrank Min reg = RREG32_SOC15(NBIO, 0, mmRCC_IOV_FUNC_IDENTIFIER); 298a2045ee6SFrank Min if (reg & 1) 299a2045ee6SFrank Min adev->virt.caps |= AMDGPU_SRIOV_CAPS_IS_VF; 300a2045ee6SFrank Min 301a2045ee6SFrank Min if (reg & 0x80000000) 302a2045ee6SFrank Min adev->virt.caps |= AMDGPU_SRIOV_CAPS_ENABLE_IOV; 303a2045ee6SFrank Min 304a2045ee6SFrank Min if (!reg) { 305fe3c9489SFeifei Xu if (is_virtual_machine()) /* passthrough mode exclus sriov mod */ 306fe3c9489SFeifei Xu adev->virt.caps |= AMDGPU_PASSTHROUGH_MODE; 307fe3c9489SFeifei Xu } 308a2045ee6SFrank Min } 309fe3c9489SFeifei Xu 310fe3c9489SFeifei Xu static void nbio_v7_4_init_registers(struct amdgpu_device *adev) 311fe3c9489SFeifei Xu { 312e01f2d41SAlex Deucher uint32_t def, data; 313fe3c9489SFeifei Xu 314e01f2d41SAlex Deucher def = data = RREG32_PCIE(smnPCIE_CI_CNTL); 315e01f2d41SAlex Deucher data = REG_SET_FIELD(data, PCIE_CI_CNTL, CI_SLV_ORDERING_DIS, 1); 316e01f2d41SAlex Deucher 317e01f2d41SAlex Deucher if (def != data) 318e01f2d41SAlex Deucher WREG32_PCIE(smnPCIE_CI_CNTL, data); 319fe3c9489SFeifei Xu } 320fe3c9489SFeifei Xu 3214241863aSHawking Zhang static void nbio_v7_4_handle_ras_controller_intr_no_bifring(struct amdgpu_device *adev) 3224241863aSHawking Zhang { 3234241863aSHawking Zhang uint32_t bif_doorbell_intr_cntl; 3244241863aSHawking Zhang 3254241863aSHawking Zhang bif_doorbell_intr_cntl = RREG32_SOC15(NBIO, 0, mmBIF_DOORBELL_INT_CNTL); 3264241863aSHawking Zhang if (REG_GET_FIELD(bif_doorbell_intr_cntl, 3274241863aSHawking Zhang BIF_DOORBELL_INT_CNTL, RAS_CNTLR_INTERRUPT_STATUS)) { 3284241863aSHawking Zhang /* driver has to clear the interrupt status when bif ring is disabled */ 3294241863aSHawking Zhang bif_doorbell_intr_cntl = REG_SET_FIELD(bif_doorbell_intr_cntl, 3304241863aSHawking Zhang BIF_DOORBELL_INT_CNTL, 3314241863aSHawking Zhang RAS_CNTLR_INTERRUPT_CLEAR, 1); 3324241863aSHawking Zhang WREG32_SOC15(NBIO, 0, mmBIF_DOORBELL_INT_CNTL, bif_doorbell_intr_cntl); 3337c6e68c7SAndrey Grodzovsky 3347c6e68c7SAndrey Grodzovsky amdgpu_ras_global_ras_isr(adev); 3354241863aSHawking Zhang } 3364241863aSHawking Zhang } 3374241863aSHawking Zhang 3384241863aSHawking Zhang static void nbio_v7_4_handle_ras_err_event_athub_intr_no_bifring(struct amdgpu_device *adev) 3394241863aSHawking Zhang { 3404241863aSHawking Zhang uint32_t bif_doorbell_intr_cntl; 3414241863aSHawking Zhang 3424241863aSHawking Zhang bif_doorbell_intr_cntl = RREG32_SOC15(NBIO, 0, mmBIF_DOORBELL_INT_CNTL); 3434241863aSHawking Zhang if (REG_GET_FIELD(bif_doorbell_intr_cntl, 3444241863aSHawking Zhang BIF_DOORBELL_INT_CNTL, RAS_ATHUB_ERR_EVENT_INTERRUPT_STATUS)) { 3454241863aSHawking Zhang /* driver has to clear the interrupt status when bif ring is disabled */ 3464241863aSHawking Zhang bif_doorbell_intr_cntl = REG_SET_FIELD(bif_doorbell_intr_cntl, 3474241863aSHawking Zhang BIF_DOORBELL_INT_CNTL, 3484241863aSHawking Zhang RAS_ATHUB_ERR_EVENT_INTERRUPT_CLEAR, 1); 3494241863aSHawking Zhang WREG32_SOC15(NBIO, 0, mmBIF_DOORBELL_INT_CNTL, bif_doorbell_intr_cntl); 3507c6e68c7SAndrey Grodzovsky 3517c6e68c7SAndrey Grodzovsky amdgpu_ras_global_ras_isr(adev); 3524241863aSHawking Zhang } 3534241863aSHawking Zhang } 3544241863aSHawking Zhang 3554e644fffSHawking Zhang 3564e644fffSHawking Zhang static int nbio_v7_4_set_ras_controller_irq_state(struct amdgpu_device *adev, 3574e644fffSHawking Zhang struct amdgpu_irq_src *src, 3584e644fffSHawking Zhang unsigned type, 3594e644fffSHawking Zhang enum amdgpu_interrupt_state state) 3604e644fffSHawking Zhang { 3614e644fffSHawking Zhang /* The ras_controller_irq enablement should be done in psp bl when it 3624e644fffSHawking Zhang * tries to enable ras feature. Driver only need to set the correct interrupt 3634e644fffSHawking Zhang * vector for bare-metal and sriov use case respectively 3644e644fffSHawking Zhang */ 3654e644fffSHawking Zhang uint32_t bif_intr_cntl; 3664e644fffSHawking Zhang 3674e644fffSHawking Zhang bif_intr_cntl = RREG32_SOC15(NBIO, 0, mmBIF_INTR_CNTL); 3684e644fffSHawking Zhang if (state == AMDGPU_IRQ_STATE_ENABLE) { 3694e644fffSHawking Zhang /* set interrupt vector select bit to 0 to select 3704e644fffSHawking Zhang * vetcor 1 for bare metal case */ 3714e644fffSHawking Zhang bif_intr_cntl = REG_SET_FIELD(bif_intr_cntl, 3724e644fffSHawking Zhang BIF_INTR_CNTL, 3734e644fffSHawking Zhang RAS_INTR_VEC_SEL, 0); 3744e644fffSHawking Zhang WREG32_SOC15(NBIO, 0, mmBIF_INTR_CNTL, bif_intr_cntl); 3754e644fffSHawking Zhang } 3764e644fffSHawking Zhang 3774e644fffSHawking Zhang return 0; 3784e644fffSHawking Zhang } 3794e644fffSHawking Zhang 3804e644fffSHawking Zhang static int nbio_v7_4_process_ras_controller_irq(struct amdgpu_device *adev, 3814e644fffSHawking Zhang struct amdgpu_irq_src *source, 3824e644fffSHawking Zhang struct amdgpu_iv_entry *entry) 3834e644fffSHawking Zhang { 3844e644fffSHawking Zhang /* By design, the ih cookie for ras_controller_irq should be written 3854e644fffSHawking Zhang * to BIFring instead of general iv ring. However, due to known bif ring 3864e644fffSHawking Zhang * hw bug, it has to be disabled. There is no chance the process function 3874e644fffSHawking Zhang * will be involked. Just left it as a dummy one. 3884e644fffSHawking Zhang */ 3894e644fffSHawking Zhang return 0; 3904e644fffSHawking Zhang } 3914e644fffSHawking Zhang 3924e644fffSHawking Zhang static int nbio_v7_4_set_ras_err_event_athub_irq_state(struct amdgpu_device *adev, 3934e644fffSHawking Zhang struct amdgpu_irq_src *src, 3944e644fffSHawking Zhang unsigned type, 3954e644fffSHawking Zhang enum amdgpu_interrupt_state state) 3964e644fffSHawking Zhang { 3974e644fffSHawking Zhang /* The ras_controller_irq enablement should be done in psp bl when it 3984e644fffSHawking Zhang * tries to enable ras feature. Driver only need to set the correct interrupt 3994e644fffSHawking Zhang * vector for bare-metal and sriov use case respectively 4004e644fffSHawking Zhang */ 4014e644fffSHawking Zhang uint32_t bif_intr_cntl; 4024e644fffSHawking Zhang 4034e644fffSHawking Zhang bif_intr_cntl = RREG32_SOC15(NBIO, 0, mmBIF_INTR_CNTL); 4044e644fffSHawking Zhang if (state == AMDGPU_IRQ_STATE_ENABLE) { 4054e644fffSHawking Zhang /* set interrupt vector select bit to 0 to select 4064e644fffSHawking Zhang * vetcor 1 for bare metal case */ 4074e644fffSHawking Zhang bif_intr_cntl = REG_SET_FIELD(bif_intr_cntl, 4084e644fffSHawking Zhang BIF_INTR_CNTL, 4094e644fffSHawking Zhang RAS_INTR_VEC_SEL, 0); 4104e644fffSHawking Zhang WREG32_SOC15(NBIO, 0, mmBIF_INTR_CNTL, bif_intr_cntl); 4114e644fffSHawking Zhang } 4124e644fffSHawking Zhang 4134e644fffSHawking Zhang return 0; 4144e644fffSHawking Zhang } 4154e644fffSHawking Zhang 4164e644fffSHawking Zhang static int nbio_v7_4_process_err_event_athub_irq(struct amdgpu_device *adev, 4174e644fffSHawking Zhang struct amdgpu_irq_src *source, 4184e644fffSHawking Zhang struct amdgpu_iv_entry *entry) 4194e644fffSHawking Zhang { 4204e644fffSHawking Zhang /* By design, the ih cookie for err_event_athub_irq should be written 4214e644fffSHawking Zhang * to BIFring instead of general iv ring. However, due to known bif ring 4224e644fffSHawking Zhang * hw bug, it has to be disabled. There is no chance the process function 4234e644fffSHawking Zhang * will be involked. Just left it as a dummy one. 4244e644fffSHawking Zhang */ 4254e644fffSHawking Zhang return 0; 4264e644fffSHawking Zhang } 4274e644fffSHawking Zhang 4284e644fffSHawking Zhang static const struct amdgpu_irq_src_funcs nbio_v7_4_ras_controller_irq_funcs = { 4294e644fffSHawking Zhang .set = nbio_v7_4_set_ras_controller_irq_state, 4304e644fffSHawking Zhang .process = nbio_v7_4_process_ras_controller_irq, 4314e644fffSHawking Zhang }; 4324e644fffSHawking Zhang 4334e644fffSHawking Zhang static const struct amdgpu_irq_src_funcs nbio_v7_4_ras_err_event_athub_irq_funcs = { 4344e644fffSHawking Zhang .set = nbio_v7_4_set_ras_err_event_athub_irq_state, 4354e644fffSHawking Zhang .process = nbio_v7_4_process_err_event_athub_irq, 4364e644fffSHawking Zhang }; 4374e644fffSHawking Zhang 4384e644fffSHawking Zhang static int nbio_v7_4_init_ras_controller_interrupt (struct amdgpu_device *adev) 4394e644fffSHawking Zhang { 4404e644fffSHawking Zhang int r; 4414e644fffSHawking Zhang 4424e644fffSHawking Zhang /* init the irq funcs */ 4434e644fffSHawking Zhang adev->nbio.ras_controller_irq.funcs = 4444e644fffSHawking Zhang &nbio_v7_4_ras_controller_irq_funcs; 4454e644fffSHawking Zhang adev->nbio.ras_controller_irq.num_types = 1; 4464e644fffSHawking Zhang 4474e644fffSHawking Zhang /* register ras controller interrupt */ 4484e644fffSHawking Zhang r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_BIF, 4494e644fffSHawking Zhang NBIF_7_4__SRCID__RAS_CONTROLLER_INTERRUPT, 4504e644fffSHawking Zhang &adev->nbio.ras_controller_irq); 4514e644fffSHawking Zhang if (r) 4524e644fffSHawking Zhang return r; 4534e644fffSHawking Zhang 4544e644fffSHawking Zhang return 0; 4554e644fffSHawking Zhang } 4564e644fffSHawking Zhang 4574e644fffSHawking Zhang static int nbio_v7_4_init_ras_err_event_athub_interrupt (struct amdgpu_device *adev) 4584e644fffSHawking Zhang { 4594e644fffSHawking Zhang 4604e644fffSHawking Zhang int r; 4614e644fffSHawking Zhang 4624e644fffSHawking Zhang /* init the irq funcs */ 4634e644fffSHawking Zhang adev->nbio.ras_err_event_athub_irq.funcs = 4644e644fffSHawking Zhang &nbio_v7_4_ras_err_event_athub_irq_funcs; 4654e644fffSHawking Zhang adev->nbio.ras_err_event_athub_irq.num_types = 1; 4664e644fffSHawking Zhang 4674e644fffSHawking Zhang /* register ras err event athub interrupt */ 4684e644fffSHawking Zhang r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_BIF, 4694e644fffSHawking Zhang NBIF_7_4__SRCID__ERREVENT_ATHUB_INTERRUPT, 4704e644fffSHawking Zhang &adev->nbio.ras_err_event_athub_irq); 4714e644fffSHawking Zhang if (r) 4724e644fffSHawking Zhang return r; 4734e644fffSHawking Zhang 4744e644fffSHawking Zhang return 0; 4754e644fffSHawking Zhang } 4764e644fffSHawking Zhang 477fe3c9489SFeifei Xu const struct amdgpu_nbio_funcs nbio_v7_4_funcs = { 478fe3c9489SFeifei Xu .get_hdp_flush_req_offset = nbio_v7_4_get_hdp_flush_req_offset, 479fe3c9489SFeifei Xu .get_hdp_flush_done_offset = nbio_v7_4_get_hdp_flush_done_offset, 480fe3c9489SFeifei Xu .get_pcie_index_offset = nbio_v7_4_get_pcie_index_offset, 481fe3c9489SFeifei Xu .get_pcie_data_offset = nbio_v7_4_get_pcie_data_offset, 482fe3c9489SFeifei Xu .get_rev_id = nbio_v7_4_get_rev_id, 483fe3c9489SFeifei Xu .mc_access_enable = nbio_v7_4_mc_access_enable, 484fe3c9489SFeifei Xu .hdp_flush = nbio_v7_4_hdp_flush, 485fe3c9489SFeifei Xu .get_memsize = nbio_v7_4_get_memsize, 486fe3c9489SFeifei Xu .sdma_doorbell_range = nbio_v7_4_sdma_doorbell_range, 48739a5053fSLeo Liu .vcn_doorbell_range = nbio_v7_4_vcn_doorbell_range, 488fe3c9489SFeifei Xu .enable_doorbell_aperture = nbio_v7_4_enable_doorbell_aperture, 489fe3c9489SFeifei Xu .enable_doorbell_selfring_aperture = nbio_v7_4_enable_doorbell_selfring_aperture, 490fe3c9489SFeifei Xu .ih_doorbell_range = nbio_v7_4_ih_doorbell_range, 491fe3c9489SFeifei Xu .update_medium_grain_clock_gating = nbio_v7_4_update_medium_grain_clock_gating, 492fe3c9489SFeifei Xu .update_medium_grain_light_sleep = nbio_v7_4_update_medium_grain_light_sleep, 493fe3c9489SFeifei Xu .get_clockgating_state = nbio_v7_4_get_clockgating_state, 494fe3c9489SFeifei Xu .ih_control = nbio_v7_4_ih_control, 495fe3c9489SFeifei Xu .init_registers = nbio_v7_4_init_registers, 496fe3c9489SFeifei Xu .detect_hw_virt = nbio_v7_4_detect_hw_virt, 49788807dc8SOak Zeng .remap_hdp_registers = nbio_v7_4_remap_hdp_registers, 4984241863aSHawking Zhang .handle_ras_controller_intr_no_bifring = nbio_v7_4_handle_ras_controller_intr_no_bifring, 4994241863aSHawking Zhang .handle_ras_err_event_athub_intr_no_bifring = nbio_v7_4_handle_ras_err_event_athub_intr_no_bifring, 5004e644fffSHawking Zhang .init_ras_controller_interrupt = nbio_v7_4_init_ras_controller_interrupt, 5014e644fffSHawking Zhang .init_ras_err_event_athub_interrupt = nbio_v7_4_init_ras_err_event_athub_interrupt, 5021c70d3d9SHawking Zhang .ras_late_init = amdgpu_nbio_ras_late_init, 503fe3c9489SFeifei Xu }; 504