1 /* 2 * Copyright 2020 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include "amdgpu.h" 24 #include "amdgpu_atombios.h" 25 #include "nbio_v7_2.h" 26 27 #include "nbio/nbio_7_2_0_offset.h" 28 #include "nbio/nbio_7_2_0_sh_mask.h" 29 #include <uapi/linux/kfd_ioctl.h> 30 31 #define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP0_YC 0x0015 32 #define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP0_YC_BASE_IDX 2 33 #define regBIF_BX0_BIF_FB_EN_YC 0x0100 34 #define regBIF_BX0_BIF_FB_EN_YC_BASE_IDX 2 35 #define regBIF1_PCIE_MST_CTRL_3 0x4601c6 36 #define regBIF1_PCIE_MST_CTRL_3_BASE_IDX 5 37 #define BIF1_PCIE_MST_CTRL_3__CI_SWUS_MAX_READ_REQUEST_SIZE_MODE__SHIFT \ 38 0x1b 39 #define BIF1_PCIE_MST_CTRL_3__CI_SWUS_MAX_READ_REQUEST_SIZE_PRIV__SHIFT \ 40 0x1c 41 #define BIF1_PCIE_MST_CTRL_3__CI_SWUS_MAX_READ_REQUEST_SIZE_MODE_MASK \ 42 0x08000000L 43 #define BIF1_PCIE_MST_CTRL_3__CI_SWUS_MAX_READ_REQUEST_SIZE_PRIV_MASK \ 44 0x30000000L 45 #define regBIF1_PCIE_TX_POWER_CTRL_1 0x460187 46 #define regBIF1_PCIE_TX_POWER_CTRL_1_BASE_IDX 5 47 #define BIF1_PCIE_TX_POWER_CTRL_1__MST_MEM_LS_EN_MASK 0x00000001L 48 #define BIF1_PCIE_TX_POWER_CTRL_1__REPLAY_MEM_LS_EN_MASK 0x00000008L 49 50 static void nbio_v7_2_remap_hdp_registers(struct amdgpu_device *adev) 51 { 52 WREG32_SOC15(NBIO, 0, regBIF_BX0_REMAP_HDP_MEM_FLUSH_CNTL, 53 adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL); 54 WREG32_SOC15(NBIO, 0, regBIF_BX0_REMAP_HDP_REG_FLUSH_CNTL, 55 adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_REG_FLUSH_CNTL); 56 } 57 58 static u32 nbio_v7_2_get_rev_id(struct amdgpu_device *adev) 59 { 60 u32 tmp; 61 62 if (adev->asic_type == CHIP_YELLOW_CARP) 63 tmp = RREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_DEV0_EPF0_STRAP0_YC); 64 else 65 tmp = RREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_DEV0_EPF0_STRAP0); 66 67 tmp &= RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0_MASK; 68 tmp >>= RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0__SHIFT; 69 70 return tmp; 71 } 72 73 static void nbio_v7_2_mc_access_enable(struct amdgpu_device *adev, bool enable) 74 { 75 if (enable) 76 if (adev->asic_type == CHIP_YELLOW_CARP) 77 WREG32_SOC15(NBIO, 0, regBIF_BX0_BIF_FB_EN_YC, 78 BIF_BX0_BIF_FB_EN__FB_READ_EN_MASK | 79 BIF_BX0_BIF_FB_EN__FB_WRITE_EN_MASK); 80 else 81 WREG32_SOC15(NBIO, 0, regBIF_BX0_BIF_FB_EN, 82 BIF_BX0_BIF_FB_EN__FB_READ_EN_MASK | 83 BIF_BX0_BIF_FB_EN__FB_WRITE_EN_MASK); 84 else 85 if (adev->asic_type == CHIP_YELLOW_CARP) 86 WREG32_SOC15(NBIO, 0, regBIF_BX0_BIF_FB_EN_YC, 0); 87 else 88 WREG32_SOC15(NBIO, 0, regBIF_BX0_BIF_FB_EN, 0); 89 } 90 91 static u32 nbio_v7_2_get_memsize(struct amdgpu_device *adev) 92 { 93 return RREG32_SOC15(NBIO, 0, regRCC_DEV0_EPF0_0_RCC_CONFIG_MEMSIZE); 94 } 95 96 static void nbio_v7_2_sdma_doorbell_range(struct amdgpu_device *adev, int instance, 97 bool use_doorbell, int doorbell_index, 98 int doorbell_size) 99 { 100 u32 reg = SOC15_REG_OFFSET(NBIO, 0, regGDC0_BIF_SDMA0_DOORBELL_RANGE); 101 u32 doorbell_range = RREG32_PCIE_PORT(reg); 102 103 if (use_doorbell) { 104 doorbell_range = REG_SET_FIELD(doorbell_range, 105 GDC0_BIF_SDMA0_DOORBELL_RANGE, 106 OFFSET, doorbell_index); 107 doorbell_range = REG_SET_FIELD(doorbell_range, 108 GDC0_BIF_SDMA0_DOORBELL_RANGE, 109 SIZE, doorbell_size); 110 } else { 111 doorbell_range = REG_SET_FIELD(doorbell_range, 112 GDC0_BIF_SDMA0_DOORBELL_RANGE, 113 SIZE, 0); 114 } 115 116 WREG32_PCIE_PORT(reg, doorbell_range); 117 } 118 119 static void nbio_v7_2_vcn_doorbell_range(struct amdgpu_device *adev, bool use_doorbell, 120 int doorbell_index, int instance) 121 { 122 u32 reg = SOC15_REG_OFFSET(NBIO, 0, regGDC0_BIF_VCN0_DOORBELL_RANGE); 123 u32 doorbell_range = RREG32_PCIE_PORT(reg); 124 125 if (use_doorbell) { 126 doorbell_range = REG_SET_FIELD(doorbell_range, 127 GDC0_BIF_VCN0_DOORBELL_RANGE, OFFSET, 128 doorbell_index); 129 doorbell_range = REG_SET_FIELD(doorbell_range, 130 GDC0_BIF_VCN0_DOORBELL_RANGE, SIZE, 8); 131 } else { 132 doorbell_range = REG_SET_FIELD(doorbell_range, 133 GDC0_BIF_VCN0_DOORBELL_RANGE, SIZE, 0); 134 } 135 136 WREG32_PCIE_PORT(reg, doorbell_range); 137 } 138 139 static void nbio_v7_2_enable_doorbell_aperture(struct amdgpu_device *adev, 140 bool enable) 141 { 142 u32 reg; 143 144 reg = RREG32_SOC15(NBIO, 0, regRCC_DEV0_EPF0_0_RCC_DOORBELL_APER_EN); 145 reg = REG_SET_FIELD(reg, RCC_DEV0_EPF0_0_RCC_DOORBELL_APER_EN, 146 BIF_DOORBELL_APER_EN, enable ? 1 : 0); 147 148 WREG32_SOC15(NBIO, 0, regRCC_DEV0_EPF0_0_RCC_DOORBELL_APER_EN, reg); 149 } 150 151 static void nbio_v7_2_enable_doorbell_selfring_aperture(struct amdgpu_device *adev, 152 bool enable) 153 { 154 u32 tmp = 0; 155 156 if (enable) { 157 tmp = REG_SET_FIELD(tmp, BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL, 158 DOORBELL_SELFRING_GPA_APER_EN, 1) | 159 REG_SET_FIELD(tmp, BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL, 160 DOORBELL_SELFRING_GPA_APER_MODE, 1) | 161 REG_SET_FIELD(tmp, BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL, 162 DOORBELL_SELFRING_GPA_APER_SIZE, 0); 163 164 WREG32_SOC15(NBIO, 0, 165 regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW, 166 lower_32_bits(adev->doorbell.base)); 167 WREG32_SOC15(NBIO, 0, 168 regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH, 169 upper_32_bits(adev->doorbell.base)); 170 } 171 172 WREG32_SOC15(NBIO, 0, regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL, 173 tmp); 174 } 175 176 177 static void nbio_v7_2_ih_doorbell_range(struct amdgpu_device *adev, 178 bool use_doorbell, int doorbell_index) 179 { 180 u32 ih_doorbell_range = RREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regGDC0_BIF_IH_DOORBELL_RANGE)); 181 182 if (use_doorbell) { 183 ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, 184 GDC0_BIF_IH_DOORBELL_RANGE, OFFSET, 185 doorbell_index); 186 ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, 187 GDC0_BIF_IH_DOORBELL_RANGE, SIZE, 188 2); 189 } else { 190 ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, 191 GDC0_BIF_IH_DOORBELL_RANGE, SIZE, 192 0); 193 } 194 195 WREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regGDC0_BIF_IH_DOORBELL_RANGE), 196 ih_doorbell_range); 197 } 198 199 static void nbio_v7_2_ih_control(struct amdgpu_device *adev) 200 { 201 u32 interrupt_cntl; 202 203 /* setup interrupt control */ 204 WREG32_SOC15(NBIO, 0, regBIF_BX0_INTERRUPT_CNTL2, 205 adev->dummy_page_addr >> 8); 206 207 interrupt_cntl = RREG32_SOC15(NBIO, 0, regBIF_BX0_INTERRUPT_CNTL); 208 /* 209 * INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=0 - dummy read disabled with msi, enabled without msi 210 * INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=1 - dummy read controlled by IH_DUMMY_RD_EN 211 */ 212 interrupt_cntl = REG_SET_FIELD(interrupt_cntl, BIF_BX0_INTERRUPT_CNTL, 213 IH_DUMMY_RD_OVERRIDE, 0); 214 215 /* INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN_MASK=1 if ring is in non-cacheable memory, e.g., vram */ 216 interrupt_cntl = REG_SET_FIELD(interrupt_cntl, BIF_BX0_INTERRUPT_CNTL, 217 IH_REQ_NONSNOOP_EN, 0); 218 219 WREG32_SOC15(NBIO, 0, regBIF_BX0_INTERRUPT_CNTL, interrupt_cntl); 220 } 221 222 static void nbio_v7_2_update_medium_grain_clock_gating(struct amdgpu_device *adev, 223 bool enable) 224 { 225 uint32_t def, data; 226 227 def = data = RREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regCPM_CONTROL)); 228 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_MGCG)) { 229 data |= (CPM_CONTROL__LCLK_DYN_GATE_ENABLE_MASK | 230 CPM_CONTROL__TXCLK_DYN_GATE_ENABLE_MASK | 231 CPM_CONTROL__TXCLK_LCNT_GATE_ENABLE_MASK | 232 CPM_CONTROL__TXCLK_REGS_GATE_ENABLE_MASK | 233 CPM_CONTROL__TXCLK_PRBS_GATE_ENABLE_MASK | 234 CPM_CONTROL__REFCLK_REGS_GATE_ENABLE_MASK); 235 } else { 236 data &= ~(CPM_CONTROL__LCLK_DYN_GATE_ENABLE_MASK | 237 CPM_CONTROL__TXCLK_DYN_GATE_ENABLE_MASK | 238 CPM_CONTROL__TXCLK_LCNT_GATE_ENABLE_MASK | 239 CPM_CONTROL__TXCLK_REGS_GATE_ENABLE_MASK | 240 CPM_CONTROL__TXCLK_PRBS_GATE_ENABLE_MASK | 241 CPM_CONTROL__REFCLK_REGS_GATE_ENABLE_MASK); 242 } 243 244 if (def != data) 245 WREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regCPM_CONTROL), data); 246 } 247 248 static void nbio_v7_2_update_medium_grain_light_sleep(struct amdgpu_device *adev, 249 bool enable) 250 { 251 uint32_t def, data; 252 253 if (adev->asic_type == CHIP_YELLOW_CARP) { 254 def = data = RREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regPCIE_CNTL2)); 255 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_LS)) 256 data |= PCIE_CNTL2__SLV_MEM_LS_EN_MASK; 257 else 258 data &= ~PCIE_CNTL2__SLV_MEM_LS_EN_MASK; 259 260 if (def != data) 261 WREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regPCIE_CNTL2), data); 262 263 data = RREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regBIF1_PCIE_TX_POWER_CTRL_1)); 264 def = data; 265 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_LS)) 266 data |= (BIF1_PCIE_TX_POWER_CTRL_1__MST_MEM_LS_EN_MASK | 267 BIF1_PCIE_TX_POWER_CTRL_1__REPLAY_MEM_LS_EN_MASK); 268 else 269 data &= ~(BIF1_PCIE_TX_POWER_CTRL_1__MST_MEM_LS_EN_MASK | 270 BIF1_PCIE_TX_POWER_CTRL_1__REPLAY_MEM_LS_EN_MASK); 271 272 if (def != data) 273 WREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regBIF1_PCIE_TX_POWER_CTRL_1), 274 data); 275 } else { 276 def = data = RREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regPCIE_CNTL2)); 277 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_LS)) 278 data |= (PCIE_CNTL2__SLV_MEM_LS_EN_MASK | 279 PCIE_CNTL2__MST_MEM_LS_EN_MASK | 280 PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK); 281 else 282 data &= ~(PCIE_CNTL2__SLV_MEM_LS_EN_MASK | 283 PCIE_CNTL2__MST_MEM_LS_EN_MASK | 284 PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK); 285 286 if (def != data) 287 WREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regPCIE_CNTL2), data); 288 } 289 } 290 291 static void nbio_v7_2_get_clockgating_state(struct amdgpu_device *adev, 292 u32 *flags) 293 { 294 int data; 295 296 /* AMD_CG_SUPPORT_BIF_MGCG */ 297 data = RREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regCPM_CONTROL)); 298 if (data & CPM_CONTROL__LCLK_DYN_GATE_ENABLE_MASK) 299 *flags |= AMD_CG_SUPPORT_BIF_MGCG; 300 301 /* AMD_CG_SUPPORT_BIF_LS */ 302 data = RREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regPCIE_CNTL2)); 303 if (data & PCIE_CNTL2__SLV_MEM_LS_EN_MASK) 304 *flags |= AMD_CG_SUPPORT_BIF_LS; 305 } 306 307 static u32 nbio_v7_2_get_hdp_flush_req_offset(struct amdgpu_device *adev) 308 { 309 return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX_PF0_GPU_HDP_FLUSH_REQ); 310 } 311 312 static u32 nbio_v7_2_get_hdp_flush_done_offset(struct amdgpu_device *adev) 313 { 314 return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX_PF0_GPU_HDP_FLUSH_DONE); 315 } 316 317 static u32 nbio_v7_2_get_pcie_index_offset(struct amdgpu_device *adev) 318 { 319 return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX0_PCIE_INDEX2); 320 } 321 322 static u32 nbio_v7_2_get_pcie_data_offset(struct amdgpu_device *adev) 323 { 324 return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX0_PCIE_DATA2); 325 } 326 327 static u32 nbio_v7_2_get_pcie_port_index_offset(struct amdgpu_device *adev) 328 { 329 return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX_PF0_RSMU_INDEX); 330 } 331 332 static u32 nbio_v7_2_get_pcie_port_data_offset(struct amdgpu_device *adev) 333 { 334 return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX_PF0_RSMU_DATA); 335 } 336 337 const struct nbio_hdp_flush_reg nbio_v7_2_hdp_flush_reg = { 338 .ref_and_mask_cp0 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP0_MASK, 339 .ref_and_mask_cp1 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP1_MASK, 340 .ref_and_mask_cp2 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP2_MASK, 341 .ref_and_mask_cp3 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP3_MASK, 342 .ref_and_mask_cp4 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP4_MASK, 343 .ref_and_mask_cp5 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP5_MASK, 344 .ref_and_mask_cp6 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP6_MASK, 345 .ref_and_mask_cp7 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP7_MASK, 346 .ref_and_mask_cp8 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP8_MASK, 347 .ref_and_mask_cp9 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP9_MASK, 348 .ref_and_mask_sdma0 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__SDMA0_MASK, 349 .ref_and_mask_sdma1 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__SDMA1_MASK, 350 }; 351 352 static void nbio_v7_2_init_registers(struct amdgpu_device *adev) 353 { 354 uint32_t def, data; 355 if (adev->asic_type == CHIP_YELLOW_CARP) { 356 def = data = RREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regBIF1_PCIE_MST_CTRL_3)); 357 data = REG_SET_FIELD(data, BIF1_PCIE_MST_CTRL_3, 358 CI_SWUS_MAX_READ_REQUEST_SIZE_MODE, 1); 359 data = REG_SET_FIELD(data, BIF1_PCIE_MST_CTRL_3, 360 CI_SWUS_MAX_READ_REQUEST_SIZE_PRIV, 1); 361 362 if (def != data) 363 WREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regBIF1_PCIE_MST_CTRL_3), data); 364 } else { 365 def = data = RREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regPCIE_CONFIG_CNTL)); 366 data = REG_SET_FIELD(data, PCIE_CONFIG_CNTL, 367 CI_SWUS_MAX_READ_REQUEST_SIZE_MODE, 1); 368 data = REG_SET_FIELD(data, PCIE_CONFIG_CNTL, 369 CI_SWUS_MAX_READ_REQUEST_SIZE_PRIV, 1); 370 371 if (def != data) 372 WREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regPCIE_CONFIG_CNTL), data); 373 } 374 375 if (amdgpu_sriov_vf(adev)) 376 adev->rmmio_remap.reg_offset = SOC15_REG_OFFSET(NBIO, 0, 377 regBIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_CNTL) << 2; 378 } 379 380 const struct amdgpu_nbio_funcs nbio_v7_2_funcs = { 381 .get_hdp_flush_req_offset = nbio_v7_2_get_hdp_flush_req_offset, 382 .get_hdp_flush_done_offset = nbio_v7_2_get_hdp_flush_done_offset, 383 .get_pcie_index_offset = nbio_v7_2_get_pcie_index_offset, 384 .get_pcie_data_offset = nbio_v7_2_get_pcie_data_offset, 385 .get_pcie_port_index_offset = nbio_v7_2_get_pcie_port_index_offset, 386 .get_pcie_port_data_offset = nbio_v7_2_get_pcie_port_data_offset, 387 .get_rev_id = nbio_v7_2_get_rev_id, 388 .mc_access_enable = nbio_v7_2_mc_access_enable, 389 .get_memsize = nbio_v7_2_get_memsize, 390 .sdma_doorbell_range = nbio_v7_2_sdma_doorbell_range, 391 .vcn_doorbell_range = nbio_v7_2_vcn_doorbell_range, 392 .enable_doorbell_aperture = nbio_v7_2_enable_doorbell_aperture, 393 .enable_doorbell_selfring_aperture = nbio_v7_2_enable_doorbell_selfring_aperture, 394 .ih_doorbell_range = nbio_v7_2_ih_doorbell_range, 395 .update_medium_grain_clock_gating = nbio_v7_2_update_medium_grain_clock_gating, 396 .update_medium_grain_light_sleep = nbio_v7_2_update_medium_grain_light_sleep, 397 .get_clockgating_state = nbio_v7_2_get_clockgating_state, 398 .ih_control = nbio_v7_2_ih_control, 399 .init_registers = nbio_v7_2_init_registers, 400 .remap_hdp_registers = nbio_v7_2_remap_hdp_registers, 401 }; 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