1a7e91bd7SHuang Rui /* 2a7e91bd7SHuang Rui * Copyright 2020 Advanced Micro Devices, Inc. 3a7e91bd7SHuang Rui * 4a7e91bd7SHuang Rui * Permission is hereby granted, free of charge, to any person obtaining a 5a7e91bd7SHuang Rui * copy of this software and associated documentation files (the "Software"), 6a7e91bd7SHuang Rui * to deal in the Software without restriction, including without limitation 7a7e91bd7SHuang Rui * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8a7e91bd7SHuang Rui * and/or sell copies of the Software, and to permit persons to whom the 9a7e91bd7SHuang Rui * Software is furnished to do so, subject to the following conditions: 10a7e91bd7SHuang Rui * 11a7e91bd7SHuang Rui * The above copyright notice and this permission notice shall be included in 12a7e91bd7SHuang Rui * all copies or substantial portions of the Software. 13a7e91bd7SHuang Rui * 14a7e91bd7SHuang Rui * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15a7e91bd7SHuang Rui * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16a7e91bd7SHuang Rui * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17a7e91bd7SHuang Rui * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18a7e91bd7SHuang Rui * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19a7e91bd7SHuang Rui * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20a7e91bd7SHuang Rui * OTHER DEALINGS IN THE SOFTWARE. 21a7e91bd7SHuang Rui * 22a7e91bd7SHuang Rui */ 23a7e91bd7SHuang Rui #include "amdgpu.h" 24a7e91bd7SHuang Rui #include "amdgpu_atombios.h" 25a7e91bd7SHuang Rui #include "nbio_v7_2.h" 26a7e91bd7SHuang Rui 27a7e91bd7SHuang Rui #include "nbio/nbio_7_2_0_offset.h" 28a7e91bd7SHuang Rui #include "nbio/nbio_7_2_0_sh_mask.h" 29a7e91bd7SHuang Rui #include <uapi/linux/kfd_ioctl.h> 30a7e91bd7SHuang Rui 31*011b514fSAaron Liu #define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP0_YC 0x0015 32*011b514fSAaron Liu #define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP0_YC_BASE_IDX 2 33*011b514fSAaron Liu #define regBIF_BX0_BIF_FB_EN_YC 0x0100 34*011b514fSAaron Liu #define regBIF_BX0_BIF_FB_EN_YC_BASE_IDX 2 35*011b514fSAaron Liu #define regBIF1_PCIE_MST_CTRL_3 0x4601c6 36*011b514fSAaron Liu #define regBIF1_PCIE_MST_CTRL_3_BASE_IDX 5 37*011b514fSAaron Liu #define BIF1_PCIE_MST_CTRL_3__CI_SWUS_MAX_READ_REQUEST_SIZE_MODE__SHIFT \ 38*011b514fSAaron Liu 0x1b 39*011b514fSAaron Liu #define BIF1_PCIE_MST_CTRL_3__CI_SWUS_MAX_READ_REQUEST_SIZE_PRIV__SHIFT \ 40*011b514fSAaron Liu 0x1c 41*011b514fSAaron Liu #define BIF1_PCIE_MST_CTRL_3__CI_SWUS_MAX_READ_REQUEST_SIZE_MODE_MASK \ 42*011b514fSAaron Liu 0x08000000L 43*011b514fSAaron Liu #define BIF1_PCIE_MST_CTRL_3__CI_SWUS_MAX_READ_REQUEST_SIZE_PRIV_MASK \ 44*011b514fSAaron Liu 0x30000000L 45*011b514fSAaron Liu #define regBIF1_PCIE_TX_POWER_CTRL_1 0x460187 46*011b514fSAaron Liu #define regBIF1_PCIE_TX_POWER_CTRL_1_BASE_IDX 5 47*011b514fSAaron Liu #define BIF1_PCIE_TX_POWER_CTRL_1__MST_MEM_LS_EN_MASK 0x00000001L 48*011b514fSAaron Liu #define BIF1_PCIE_TX_POWER_CTRL_1__REPLAY_MEM_LS_EN_MASK 0x00000008L 49*011b514fSAaron Liu 50a7e91bd7SHuang Rui static void nbio_v7_2_remap_hdp_registers(struct amdgpu_device *adev) 51a7e91bd7SHuang Rui { 52a7e91bd7SHuang Rui WREG32_SOC15(NBIO, 0, regBIF_BX0_REMAP_HDP_MEM_FLUSH_CNTL, 53a7e91bd7SHuang Rui adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL); 54a7e91bd7SHuang Rui WREG32_SOC15(NBIO, 0, regBIF_BX0_REMAP_HDP_REG_FLUSH_CNTL, 55a7e91bd7SHuang Rui adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_REG_FLUSH_CNTL); 56a7e91bd7SHuang Rui } 57a7e91bd7SHuang Rui 58a7e91bd7SHuang Rui static u32 nbio_v7_2_get_rev_id(struct amdgpu_device *adev) 59a7e91bd7SHuang Rui { 60*011b514fSAaron Liu u32 tmp; 61*011b514fSAaron Liu 62*011b514fSAaron Liu if (adev->asic_type == CHIP_YELLOW_CARP) 63*011b514fSAaron Liu tmp = RREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_DEV0_EPF0_STRAP0_YC); 64*011b514fSAaron Liu else 65*011b514fSAaron Liu tmp = RREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_DEV0_EPF0_STRAP0); 66a7e91bd7SHuang Rui 67a7e91bd7SHuang Rui tmp &= RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0_MASK; 68a7e91bd7SHuang Rui tmp >>= RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0__SHIFT; 69a7e91bd7SHuang Rui 70a7e91bd7SHuang Rui return tmp; 71a7e91bd7SHuang Rui } 72a7e91bd7SHuang Rui 73a7e91bd7SHuang Rui static void nbio_v7_2_mc_access_enable(struct amdgpu_device *adev, bool enable) 74a7e91bd7SHuang Rui { 75a7e91bd7SHuang Rui if (enable) 76*011b514fSAaron Liu if (adev->asic_type == CHIP_YELLOW_CARP) 77*011b514fSAaron Liu WREG32_SOC15(NBIO, 0, regBIF_BX0_BIF_FB_EN_YC, 78*011b514fSAaron Liu BIF_BX0_BIF_FB_EN__FB_READ_EN_MASK | 79*011b514fSAaron Liu BIF_BX0_BIF_FB_EN__FB_WRITE_EN_MASK); 80*011b514fSAaron Liu else 81a7e91bd7SHuang Rui WREG32_SOC15(NBIO, 0, regBIF_BX0_BIF_FB_EN, 82a7e91bd7SHuang Rui BIF_BX0_BIF_FB_EN__FB_READ_EN_MASK | 83a7e91bd7SHuang Rui BIF_BX0_BIF_FB_EN__FB_WRITE_EN_MASK); 84a7e91bd7SHuang Rui else 85*011b514fSAaron Liu if (adev->asic_type == CHIP_YELLOW_CARP) 86*011b514fSAaron Liu WREG32_SOC15(NBIO, 0, regBIF_BX0_BIF_FB_EN_YC, 0); 87*011b514fSAaron Liu else 88a7e91bd7SHuang Rui WREG32_SOC15(NBIO, 0, regBIF_BX0_BIF_FB_EN, 0); 89a7e91bd7SHuang Rui } 90a7e91bd7SHuang Rui 91a7e91bd7SHuang Rui static u32 nbio_v7_2_get_memsize(struct amdgpu_device *adev) 92a7e91bd7SHuang Rui { 93a7e91bd7SHuang Rui return RREG32_SOC15(NBIO, 0, regRCC_DEV0_EPF0_0_RCC_CONFIG_MEMSIZE); 94a7e91bd7SHuang Rui } 95a7e91bd7SHuang Rui 96a7e91bd7SHuang Rui static void nbio_v7_2_sdma_doorbell_range(struct amdgpu_device *adev, int instance, 97a7e91bd7SHuang Rui bool use_doorbell, int doorbell_index, 98a7e91bd7SHuang Rui int doorbell_size) 99a7e91bd7SHuang Rui { 100a7e91bd7SHuang Rui u32 reg = SOC15_REG_OFFSET(NBIO, 0, regGDC0_BIF_SDMA0_DOORBELL_RANGE); 101a7e91bd7SHuang Rui u32 doorbell_range = RREG32_PCIE_PORT(reg); 102a7e91bd7SHuang Rui 103a7e91bd7SHuang Rui if (use_doorbell) { 104a7e91bd7SHuang Rui doorbell_range = REG_SET_FIELD(doorbell_range, 105a7e91bd7SHuang Rui GDC0_BIF_SDMA0_DOORBELL_RANGE, 106a7e91bd7SHuang Rui OFFSET, doorbell_index); 107a7e91bd7SHuang Rui doorbell_range = REG_SET_FIELD(doorbell_range, 108a7e91bd7SHuang Rui GDC0_BIF_SDMA0_DOORBELL_RANGE, 109a7e91bd7SHuang Rui SIZE, doorbell_size); 110a7e91bd7SHuang Rui } else { 111a7e91bd7SHuang Rui doorbell_range = REG_SET_FIELD(doorbell_range, 112a7e91bd7SHuang Rui GDC0_BIF_SDMA0_DOORBELL_RANGE, 113a7e91bd7SHuang Rui SIZE, 0); 114a7e91bd7SHuang Rui } 115a7e91bd7SHuang Rui 116a7e91bd7SHuang Rui WREG32_PCIE_PORT(reg, doorbell_range); 117a7e91bd7SHuang Rui } 118a7e91bd7SHuang Rui 119a7e91bd7SHuang Rui static void nbio_v7_2_vcn_doorbell_range(struct amdgpu_device *adev, bool use_doorbell, 120a7e91bd7SHuang Rui int doorbell_index, int instance) 121a7e91bd7SHuang Rui { 122a7e91bd7SHuang Rui u32 reg = SOC15_REG_OFFSET(NBIO, 0, regGDC0_BIF_VCN0_DOORBELL_RANGE); 123a7e91bd7SHuang Rui u32 doorbell_range = RREG32_PCIE_PORT(reg); 124a7e91bd7SHuang Rui 125a7e91bd7SHuang Rui if (use_doorbell) { 126a7e91bd7SHuang Rui doorbell_range = REG_SET_FIELD(doorbell_range, 127a7e91bd7SHuang Rui GDC0_BIF_VCN0_DOORBELL_RANGE, OFFSET, 128a7e91bd7SHuang Rui doorbell_index); 129a7e91bd7SHuang Rui doorbell_range = REG_SET_FIELD(doorbell_range, 130a7e91bd7SHuang Rui GDC0_BIF_VCN0_DOORBELL_RANGE, SIZE, 8); 131a7e91bd7SHuang Rui } else { 132a7e91bd7SHuang Rui doorbell_range = REG_SET_FIELD(doorbell_range, 133a7e91bd7SHuang Rui GDC0_BIF_VCN0_DOORBELL_RANGE, SIZE, 0); 134a7e91bd7SHuang Rui } 135a7e91bd7SHuang Rui 136a7e91bd7SHuang Rui WREG32_PCIE_PORT(reg, doorbell_range); 137a7e91bd7SHuang Rui } 138a7e91bd7SHuang Rui 139a7e91bd7SHuang Rui static void nbio_v7_2_enable_doorbell_aperture(struct amdgpu_device *adev, 140a7e91bd7SHuang Rui bool enable) 141a7e91bd7SHuang Rui { 142a7e91bd7SHuang Rui u32 reg; 143a7e91bd7SHuang Rui 144a7e91bd7SHuang Rui reg = RREG32_SOC15(NBIO, 0, regRCC_DEV0_EPF0_0_RCC_DOORBELL_APER_EN); 145a7e91bd7SHuang Rui reg = REG_SET_FIELD(reg, RCC_DEV0_EPF0_0_RCC_DOORBELL_APER_EN, 146a7e91bd7SHuang Rui BIF_DOORBELL_APER_EN, enable ? 1 : 0); 147a7e91bd7SHuang Rui 148a7e91bd7SHuang Rui WREG32_SOC15(NBIO, 0, regRCC_DEV0_EPF0_0_RCC_DOORBELL_APER_EN, reg); 149a7e91bd7SHuang Rui } 150a7e91bd7SHuang Rui 151a7e91bd7SHuang Rui static void nbio_v7_2_enable_doorbell_selfring_aperture(struct amdgpu_device *adev, 152a7e91bd7SHuang Rui bool enable) 153a7e91bd7SHuang Rui { 154a7e91bd7SHuang Rui u32 tmp = 0; 155a7e91bd7SHuang Rui 156a7e91bd7SHuang Rui if (enable) { 157a7e91bd7SHuang Rui tmp = REG_SET_FIELD(tmp, BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL, 158a7e91bd7SHuang Rui DOORBELL_SELFRING_GPA_APER_EN, 1) | 159a7e91bd7SHuang Rui REG_SET_FIELD(tmp, BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL, 160a7e91bd7SHuang Rui DOORBELL_SELFRING_GPA_APER_MODE, 1) | 161a7e91bd7SHuang Rui REG_SET_FIELD(tmp, BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL, 162a7e91bd7SHuang Rui DOORBELL_SELFRING_GPA_APER_SIZE, 0); 163a7e91bd7SHuang Rui 164a7e91bd7SHuang Rui WREG32_SOC15(NBIO, 0, 165a7e91bd7SHuang Rui regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW, 166a7e91bd7SHuang Rui lower_32_bits(adev->doorbell.base)); 167a7e91bd7SHuang Rui WREG32_SOC15(NBIO, 0, 168a7e91bd7SHuang Rui regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH, 169a7e91bd7SHuang Rui upper_32_bits(adev->doorbell.base)); 170a7e91bd7SHuang Rui } 171a7e91bd7SHuang Rui 172a7e91bd7SHuang Rui WREG32_SOC15(NBIO, 0, regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL, 173a7e91bd7SHuang Rui tmp); 174a7e91bd7SHuang Rui } 175a7e91bd7SHuang Rui 176a7e91bd7SHuang Rui 177a7e91bd7SHuang Rui static void nbio_v7_2_ih_doorbell_range(struct amdgpu_device *adev, 178a7e91bd7SHuang Rui bool use_doorbell, int doorbell_index) 179a7e91bd7SHuang Rui { 180a7e91bd7SHuang Rui u32 ih_doorbell_range = RREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regGDC0_BIF_IH_DOORBELL_RANGE)); 181a7e91bd7SHuang Rui 182a7e91bd7SHuang Rui if (use_doorbell) { 183a7e91bd7SHuang Rui ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, 184a7e91bd7SHuang Rui GDC0_BIF_IH_DOORBELL_RANGE, OFFSET, 185a7e91bd7SHuang Rui doorbell_index); 186a7e91bd7SHuang Rui ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, 187a7e91bd7SHuang Rui GDC0_BIF_IH_DOORBELL_RANGE, SIZE, 188a7e91bd7SHuang Rui 2); 189a7e91bd7SHuang Rui } else { 190a7e91bd7SHuang Rui ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, 191a7e91bd7SHuang Rui GDC0_BIF_IH_DOORBELL_RANGE, SIZE, 192a7e91bd7SHuang Rui 0); 193a7e91bd7SHuang Rui } 194a7e91bd7SHuang Rui 195a7e91bd7SHuang Rui WREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regGDC0_BIF_IH_DOORBELL_RANGE), 196a7e91bd7SHuang Rui ih_doorbell_range); 197a7e91bd7SHuang Rui } 198a7e91bd7SHuang Rui 199a7e91bd7SHuang Rui static void nbio_v7_2_ih_control(struct amdgpu_device *adev) 200a7e91bd7SHuang Rui { 201a7e91bd7SHuang Rui u32 interrupt_cntl; 202a7e91bd7SHuang Rui 203a7e91bd7SHuang Rui /* setup interrupt control */ 204a7e91bd7SHuang Rui WREG32_SOC15(NBIO, 0, regBIF_BX0_INTERRUPT_CNTL2, 205a7e91bd7SHuang Rui adev->dummy_page_addr >> 8); 206a7e91bd7SHuang Rui 207a7e91bd7SHuang Rui interrupt_cntl = RREG32_SOC15(NBIO, 0, regBIF_BX0_INTERRUPT_CNTL); 208a7e91bd7SHuang Rui /* 209a7e91bd7SHuang Rui * INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=0 - dummy read disabled with msi, enabled without msi 210a7e91bd7SHuang Rui * INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=1 - dummy read controlled by IH_DUMMY_RD_EN 211a7e91bd7SHuang Rui */ 212a7e91bd7SHuang Rui interrupt_cntl = REG_SET_FIELD(interrupt_cntl, BIF_BX0_INTERRUPT_CNTL, 213a7e91bd7SHuang Rui IH_DUMMY_RD_OVERRIDE, 0); 214a7e91bd7SHuang Rui 215a7e91bd7SHuang Rui /* INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN_MASK=1 if ring is in non-cacheable memory, e.g., vram */ 216a7e91bd7SHuang Rui interrupt_cntl = REG_SET_FIELD(interrupt_cntl, BIF_BX0_INTERRUPT_CNTL, 217a7e91bd7SHuang Rui IH_REQ_NONSNOOP_EN, 0); 218a7e91bd7SHuang Rui 219a7e91bd7SHuang Rui WREG32_SOC15(NBIO, 0, regBIF_BX0_INTERRUPT_CNTL, interrupt_cntl); 220a7e91bd7SHuang Rui } 221a7e91bd7SHuang Rui 222a7e91bd7SHuang Rui static void nbio_v7_2_update_medium_grain_clock_gating(struct amdgpu_device *adev, 223a7e91bd7SHuang Rui bool enable) 224a7e91bd7SHuang Rui { 225a7e91bd7SHuang Rui uint32_t def, data; 226a7e91bd7SHuang Rui 227a7e91bd7SHuang Rui def = data = RREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regCPM_CONTROL)); 228a7e91bd7SHuang Rui if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_MGCG)) { 229a7e91bd7SHuang Rui data |= (CPM_CONTROL__LCLK_DYN_GATE_ENABLE_MASK | 230a7e91bd7SHuang Rui CPM_CONTROL__TXCLK_DYN_GATE_ENABLE_MASK | 231a7e91bd7SHuang Rui CPM_CONTROL__TXCLK_LCNT_GATE_ENABLE_MASK | 232a7e91bd7SHuang Rui CPM_CONTROL__TXCLK_REGS_GATE_ENABLE_MASK | 233a7e91bd7SHuang Rui CPM_CONTROL__TXCLK_PRBS_GATE_ENABLE_MASK | 234a7e91bd7SHuang Rui CPM_CONTROL__REFCLK_REGS_GATE_ENABLE_MASK); 235a7e91bd7SHuang Rui } else { 236a7e91bd7SHuang Rui data &= ~(CPM_CONTROL__LCLK_DYN_GATE_ENABLE_MASK | 237a7e91bd7SHuang Rui CPM_CONTROL__TXCLK_DYN_GATE_ENABLE_MASK | 238a7e91bd7SHuang Rui CPM_CONTROL__TXCLK_LCNT_GATE_ENABLE_MASK | 239a7e91bd7SHuang Rui CPM_CONTROL__TXCLK_REGS_GATE_ENABLE_MASK | 240a7e91bd7SHuang Rui CPM_CONTROL__TXCLK_PRBS_GATE_ENABLE_MASK | 241a7e91bd7SHuang Rui CPM_CONTROL__REFCLK_REGS_GATE_ENABLE_MASK); 242a7e91bd7SHuang Rui } 243a7e91bd7SHuang Rui 244a7e91bd7SHuang Rui if (def != data) 245a7e91bd7SHuang Rui WREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regCPM_CONTROL), data); 246a7e91bd7SHuang Rui } 247a7e91bd7SHuang Rui 248a7e91bd7SHuang Rui static void nbio_v7_2_update_medium_grain_light_sleep(struct amdgpu_device *adev, 249a7e91bd7SHuang Rui bool enable) 250a7e91bd7SHuang Rui { 251a7e91bd7SHuang Rui uint32_t def, data; 252a7e91bd7SHuang Rui 253*011b514fSAaron Liu if (adev->asic_type == CHIP_YELLOW_CARP) { 254a7e91bd7SHuang Rui def = data = RREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regPCIE_CNTL2)); 255*011b514fSAaron Liu if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_LS)) 256*011b514fSAaron Liu data |= PCIE_CNTL2__SLV_MEM_LS_EN_MASK; 257*011b514fSAaron Liu else 258*011b514fSAaron Liu data &= ~PCIE_CNTL2__SLV_MEM_LS_EN_MASK; 259a7e91bd7SHuang Rui 260a7e91bd7SHuang Rui if (def != data) 261a7e91bd7SHuang Rui WREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regPCIE_CNTL2), data); 262*011b514fSAaron Liu 263*011b514fSAaron Liu data = RREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regBIF1_PCIE_TX_POWER_CTRL_1)); 264*011b514fSAaron Liu def = data; 265*011b514fSAaron Liu if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_LS)) 266*011b514fSAaron Liu data |= (BIF1_PCIE_TX_POWER_CTRL_1__MST_MEM_LS_EN_MASK | 267*011b514fSAaron Liu BIF1_PCIE_TX_POWER_CTRL_1__REPLAY_MEM_LS_EN_MASK); 268*011b514fSAaron Liu else 269*011b514fSAaron Liu data &= ~(BIF1_PCIE_TX_POWER_CTRL_1__MST_MEM_LS_EN_MASK | 270*011b514fSAaron Liu BIF1_PCIE_TX_POWER_CTRL_1__REPLAY_MEM_LS_EN_MASK); 271*011b514fSAaron Liu 272*011b514fSAaron Liu if (def != data) 273*011b514fSAaron Liu WREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regBIF1_PCIE_TX_POWER_CTRL_1), 274*011b514fSAaron Liu data); 275*011b514fSAaron Liu } else { 276*011b514fSAaron Liu def = data = RREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regPCIE_CNTL2)); 277*011b514fSAaron Liu if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_LS)) 278*011b514fSAaron Liu data |= (PCIE_CNTL2__SLV_MEM_LS_EN_MASK | 279*011b514fSAaron Liu PCIE_CNTL2__MST_MEM_LS_EN_MASK | 280*011b514fSAaron Liu PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK); 281*011b514fSAaron Liu else 282*011b514fSAaron Liu data &= ~(PCIE_CNTL2__SLV_MEM_LS_EN_MASK | 283*011b514fSAaron Liu PCIE_CNTL2__MST_MEM_LS_EN_MASK | 284*011b514fSAaron Liu PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK); 285*011b514fSAaron Liu 286*011b514fSAaron Liu if (def != data) 287*011b514fSAaron Liu WREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regPCIE_CNTL2), data); 288*011b514fSAaron Liu } 289a7e91bd7SHuang Rui } 290a7e91bd7SHuang Rui 291a7e91bd7SHuang Rui static void nbio_v7_2_get_clockgating_state(struct amdgpu_device *adev, 292a7e91bd7SHuang Rui u32 *flags) 293a7e91bd7SHuang Rui { 294a7e91bd7SHuang Rui int data; 295a7e91bd7SHuang Rui 296a7e91bd7SHuang Rui /* AMD_CG_SUPPORT_BIF_MGCG */ 297a7e91bd7SHuang Rui data = RREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regCPM_CONTROL)); 298a7e91bd7SHuang Rui if (data & CPM_CONTROL__LCLK_DYN_GATE_ENABLE_MASK) 299a7e91bd7SHuang Rui *flags |= AMD_CG_SUPPORT_BIF_MGCG; 300a7e91bd7SHuang Rui 301a7e91bd7SHuang Rui /* AMD_CG_SUPPORT_BIF_LS */ 302a7e91bd7SHuang Rui data = RREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regPCIE_CNTL2)); 303a7e91bd7SHuang Rui if (data & PCIE_CNTL2__SLV_MEM_LS_EN_MASK) 304a7e91bd7SHuang Rui *flags |= AMD_CG_SUPPORT_BIF_LS; 305a7e91bd7SHuang Rui } 306a7e91bd7SHuang Rui 307a7e91bd7SHuang Rui static u32 nbio_v7_2_get_hdp_flush_req_offset(struct amdgpu_device *adev) 308a7e91bd7SHuang Rui { 309a7e91bd7SHuang Rui return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX_PF0_GPU_HDP_FLUSH_REQ); 310a7e91bd7SHuang Rui } 311a7e91bd7SHuang Rui 312a7e91bd7SHuang Rui static u32 nbio_v7_2_get_hdp_flush_done_offset(struct amdgpu_device *adev) 313a7e91bd7SHuang Rui { 314a7e91bd7SHuang Rui return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX_PF0_GPU_HDP_FLUSH_DONE); 315a7e91bd7SHuang Rui } 316a7e91bd7SHuang Rui 317a7e91bd7SHuang Rui static u32 nbio_v7_2_get_pcie_index_offset(struct amdgpu_device *adev) 318a7e91bd7SHuang Rui { 319a7e91bd7SHuang Rui return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX0_PCIE_INDEX2); 320a7e91bd7SHuang Rui } 321a7e91bd7SHuang Rui 322a7e91bd7SHuang Rui static u32 nbio_v7_2_get_pcie_data_offset(struct amdgpu_device *adev) 323a7e91bd7SHuang Rui { 324a7e91bd7SHuang Rui return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX0_PCIE_DATA2); 325a7e91bd7SHuang Rui } 326a7e91bd7SHuang Rui 327a7e91bd7SHuang Rui static u32 nbio_v7_2_get_pcie_port_index_offset(struct amdgpu_device *adev) 328a7e91bd7SHuang Rui { 329a7e91bd7SHuang Rui return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX_PF0_RSMU_INDEX); 330a7e91bd7SHuang Rui } 331a7e91bd7SHuang Rui 332a7e91bd7SHuang Rui static u32 nbio_v7_2_get_pcie_port_data_offset(struct amdgpu_device *adev) 333a7e91bd7SHuang Rui { 334a7e91bd7SHuang Rui return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX_PF0_RSMU_DATA); 335a7e91bd7SHuang Rui } 336a7e91bd7SHuang Rui 337a7e91bd7SHuang Rui const struct nbio_hdp_flush_reg nbio_v7_2_hdp_flush_reg = { 338a7e91bd7SHuang Rui .ref_and_mask_cp0 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP0_MASK, 339a7e91bd7SHuang Rui .ref_and_mask_cp1 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP1_MASK, 340a7e91bd7SHuang Rui .ref_and_mask_cp2 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP2_MASK, 341a7e91bd7SHuang Rui .ref_and_mask_cp3 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP3_MASK, 342a7e91bd7SHuang Rui .ref_and_mask_cp4 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP4_MASK, 343a7e91bd7SHuang Rui .ref_and_mask_cp5 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP5_MASK, 344a7e91bd7SHuang Rui .ref_and_mask_cp6 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP6_MASK, 345a7e91bd7SHuang Rui .ref_and_mask_cp7 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP7_MASK, 346a7e91bd7SHuang Rui .ref_and_mask_cp8 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP8_MASK, 347a7e91bd7SHuang Rui .ref_and_mask_cp9 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP9_MASK, 348a7e91bd7SHuang Rui .ref_and_mask_sdma0 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__SDMA0_MASK, 349a7e91bd7SHuang Rui .ref_and_mask_sdma1 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__SDMA1_MASK, 350a7e91bd7SHuang Rui }; 351a7e91bd7SHuang Rui 352a7e91bd7SHuang Rui static void nbio_v7_2_init_registers(struct amdgpu_device *adev) 353a7e91bd7SHuang Rui { 354a7e91bd7SHuang Rui uint32_t def, data; 355*011b514fSAaron Liu if (adev->asic_type == CHIP_YELLOW_CARP) { 356*011b514fSAaron Liu def = data = RREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regBIF1_PCIE_MST_CTRL_3)); 357*011b514fSAaron Liu data = REG_SET_FIELD(data, BIF1_PCIE_MST_CTRL_3, 358*011b514fSAaron Liu CI_SWUS_MAX_READ_REQUEST_SIZE_MODE, 1); 359*011b514fSAaron Liu data = REG_SET_FIELD(data, BIF1_PCIE_MST_CTRL_3, 360*011b514fSAaron Liu CI_SWUS_MAX_READ_REQUEST_SIZE_PRIV, 1); 361a7e91bd7SHuang Rui 362a7e91bd7SHuang Rui if (def != data) 363*011b514fSAaron Liu WREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regBIF1_PCIE_MST_CTRL_3), data); 364*011b514fSAaron Liu } else { 365*011b514fSAaron Liu def = data = RREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regPCIE_CONFIG_CNTL)); 366*011b514fSAaron Liu data = REG_SET_FIELD(data, PCIE_CONFIG_CNTL, 367*011b514fSAaron Liu CI_SWUS_MAX_READ_REQUEST_SIZE_MODE, 1); 368*011b514fSAaron Liu data = REG_SET_FIELD(data, PCIE_CONFIG_CNTL, 369*011b514fSAaron Liu CI_SWUS_MAX_READ_REQUEST_SIZE_PRIV, 1); 370*011b514fSAaron Liu 371*011b514fSAaron Liu if (def != data) 372*011b514fSAaron Liu WREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regPCIE_CONFIG_CNTL), data); 373*011b514fSAaron Liu } 374a7e91bd7SHuang Rui } 375a7e91bd7SHuang Rui 376a7e91bd7SHuang Rui const struct amdgpu_nbio_funcs nbio_v7_2_funcs = { 377a7e91bd7SHuang Rui .get_hdp_flush_req_offset = nbio_v7_2_get_hdp_flush_req_offset, 378a7e91bd7SHuang Rui .get_hdp_flush_done_offset = nbio_v7_2_get_hdp_flush_done_offset, 379a7e91bd7SHuang Rui .get_pcie_index_offset = nbio_v7_2_get_pcie_index_offset, 380a7e91bd7SHuang Rui .get_pcie_data_offset = nbio_v7_2_get_pcie_data_offset, 381a7e91bd7SHuang Rui .get_pcie_port_index_offset = nbio_v7_2_get_pcie_port_index_offset, 382a7e91bd7SHuang Rui .get_pcie_port_data_offset = nbio_v7_2_get_pcie_port_data_offset, 383a7e91bd7SHuang Rui .get_rev_id = nbio_v7_2_get_rev_id, 384a7e91bd7SHuang Rui .mc_access_enable = nbio_v7_2_mc_access_enable, 385a7e91bd7SHuang Rui .get_memsize = nbio_v7_2_get_memsize, 386a7e91bd7SHuang Rui .sdma_doorbell_range = nbio_v7_2_sdma_doorbell_range, 387a7e91bd7SHuang Rui .vcn_doorbell_range = nbio_v7_2_vcn_doorbell_range, 388a7e91bd7SHuang Rui .enable_doorbell_aperture = nbio_v7_2_enable_doorbell_aperture, 389a7e91bd7SHuang Rui .enable_doorbell_selfring_aperture = nbio_v7_2_enable_doorbell_selfring_aperture, 390a7e91bd7SHuang Rui .ih_doorbell_range = nbio_v7_2_ih_doorbell_range, 391a7e91bd7SHuang Rui .update_medium_grain_clock_gating = nbio_v7_2_update_medium_grain_clock_gating, 392a7e91bd7SHuang Rui .update_medium_grain_light_sleep = nbio_v7_2_update_medium_grain_light_sleep, 393a7e91bd7SHuang Rui .get_clockgating_state = nbio_v7_2_get_clockgating_state, 394a7e91bd7SHuang Rui .ih_control = nbio_v7_2_ih_control, 395a7e91bd7SHuang Rui .init_registers = nbio_v7_2_init_registers, 396a7e91bd7SHuang Rui .remap_hdp_registers = nbio_v7_2_remap_hdp_registers, 397a7e91bd7SHuang Rui }; 398