1954d5d43SChunming Zhou /* 2954d5d43SChunming Zhou * Copyright 2016 Advanced Micro Devices, Inc. 3954d5d43SChunming Zhou * 4954d5d43SChunming Zhou * Permission is hereby granted, free of charge, to any person obtaining a 5954d5d43SChunming Zhou * copy of this software and associated documentation files (the "Software"), 6954d5d43SChunming Zhou * to deal in the Software without restriction, including without limitation 7954d5d43SChunming Zhou * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8954d5d43SChunming Zhou * and/or sell copies of the Software, and to permit persons to whom the 9954d5d43SChunming Zhou * Software is furnished to do so, subject to the following conditions: 10954d5d43SChunming Zhou * 11954d5d43SChunming Zhou * The above copyright notice and this permission notice shall be included in 12954d5d43SChunming Zhou * all copies or substantial portions of the Software. 13954d5d43SChunming Zhou * 14954d5d43SChunming Zhou * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15954d5d43SChunming Zhou * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16954d5d43SChunming Zhou * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17954d5d43SChunming Zhou * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18954d5d43SChunming Zhou * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19954d5d43SChunming Zhou * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20954d5d43SChunming Zhou * OTHER DEALINGS IN THE SOFTWARE. 21954d5d43SChunming Zhou * 22954d5d43SChunming Zhou */ 23954d5d43SChunming Zhou #include "amdgpu.h" 24954d5d43SChunming Zhou #include "amdgpu_atombios.h" 25954d5d43SChunming Zhou #include "nbio_v7_0.h" 26954d5d43SChunming Zhou 2751199920SFeifei Xu #include "nbio/nbio_7_0_default.h" 2851199920SFeifei Xu #include "nbio/nbio_7_0_offset.h" 2951199920SFeifei Xu #include "nbio/nbio_7_0_sh_mask.h" 30fb960bd2SFeifei Xu #include "vega10_enum.h" 31954d5d43SChunming Zhou 32954d5d43SChunming Zhou #define smnNBIF_MGCG_CTRL_LCLK 0x1013a05c 33954d5d43SChunming Zhou 34bf383fb6SAlex Deucher #define smnCPM_CONTROL 0x11180460 35bf383fb6SAlex Deucher #define smnPCIE_CNTL2 0x11180070 36946a4d5bSShaoyun Liu 37bf383fb6SAlex Deucher static u32 nbio_v7_0_get_rev_id(struct amdgpu_device *adev) 38954d5d43SChunming Zhou { 39ba7d5a22STom St Denis u32 tmp = RREG32_SOC15(NBIO, 0, mmRCC_DEV0_EPF0_STRAP0); 40954d5d43SChunming Zhou 41954d5d43SChunming Zhou tmp &= RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0_MASK; 42954d5d43SChunming Zhou tmp >>= RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0__SHIFT; 43954d5d43SChunming Zhou 44954d5d43SChunming Zhou return tmp; 45954d5d43SChunming Zhou } 46954d5d43SChunming Zhou 47bf383fb6SAlex Deucher static void nbio_v7_0_mc_access_enable(struct amdgpu_device *adev, bool enable) 48954d5d43SChunming Zhou { 49954d5d43SChunming Zhou if (enable) 50ba7d5a22STom St Denis WREG32_SOC15(NBIO, 0, mmBIF_FB_EN, 51954d5d43SChunming Zhou BIF_FB_EN__FB_READ_EN_MASK | BIF_FB_EN__FB_WRITE_EN_MASK); 52954d5d43SChunming Zhou else 53ba7d5a22STom St Denis WREG32_SOC15(NBIO, 0, mmBIF_FB_EN, 0); 54954d5d43SChunming Zhou } 55954d5d43SChunming Zhou 5669882565SChristian König static void nbio_v7_0_hdp_flush(struct amdgpu_device *adev, 5769882565SChristian König struct amdgpu_ring *ring) 58954d5d43SChunming Zhou { 5969882565SChristian König if (!ring || !ring->funcs->emit_wreg) 6057ea8c7bSShaoyun Liu WREG32_SOC15_NO_KIQ(NBIO, 0, mmHDP_MEM_COHERENCY_FLUSH_CNTL, 0); 6169882565SChristian König else 6269882565SChristian König amdgpu_ring_emit_wreg(ring, SOC15_REG_OFFSET( 6369882565SChristian König NBIO, 0, mmHDP_MEM_COHERENCY_FLUSH_CNTL), 0); 64954d5d43SChunming Zhou } 65954d5d43SChunming Zhou 66bf383fb6SAlex Deucher static u32 nbio_v7_0_get_memsize(struct amdgpu_device *adev) 67954d5d43SChunming Zhou { 68ba7d5a22STom St Denis return RREG32_SOC15(NBIO, 0, mmRCC_CONFIG_MEMSIZE); 69954d5d43SChunming Zhou } 70954d5d43SChunming Zhou 71bf383fb6SAlex Deucher static void nbio_v7_0_sdma_doorbell_range(struct amdgpu_device *adev, int instance, 72954d5d43SChunming Zhou bool use_doorbell, int doorbell_index) 73954d5d43SChunming Zhou { 74946a4d5bSShaoyun Liu u32 reg = instance == 0 ? SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA0_DOORBELL_RANGE) : 75946a4d5bSShaoyun Liu SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA1_DOORBELL_RANGE); 76946a4d5bSShaoyun Liu 77946a4d5bSShaoyun Liu u32 doorbell_range = RREG32(reg); 78954d5d43SChunming Zhou 79954d5d43SChunming Zhou if (use_doorbell) { 80954d5d43SChunming Zhou doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, OFFSET, doorbell_index); 81954d5d43SChunming Zhou doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, SIZE, 2); 82954d5d43SChunming Zhou } else 83954d5d43SChunming Zhou doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, SIZE, 0); 84954d5d43SChunming Zhou 85946a4d5bSShaoyun Liu WREG32(reg, doorbell_range); 86954d5d43SChunming Zhou } 87954d5d43SChunming Zhou 88bf383fb6SAlex Deucher static void nbio_v7_0_enable_doorbell_aperture(struct amdgpu_device *adev, 89954d5d43SChunming Zhou bool enable) 90954d5d43SChunming Zhou { 91ba7d5a22STom St Denis WREG32_FIELD15(NBIO, 0, RCC_DOORBELL_APER_EN, BIF_DOORBELL_APER_EN, enable ? 1 : 0); 92954d5d43SChunming Zhou } 93954d5d43SChunming Zhou 94bf383fb6SAlex Deucher static void nbio_v7_0_enable_doorbell_selfring_aperture(struct amdgpu_device *adev, 95bf383fb6SAlex Deucher bool enable) 96bf383fb6SAlex Deucher { 97bf383fb6SAlex Deucher 98bf383fb6SAlex Deucher } 99bf383fb6SAlex Deucher 100bf383fb6SAlex Deucher static void nbio_v7_0_ih_doorbell_range(struct amdgpu_device *adev, 101954d5d43SChunming Zhou bool use_doorbell, int doorbell_index) 102954d5d43SChunming Zhou { 103ba7d5a22STom St Denis u32 ih_doorbell_range = RREG32_SOC15(NBIO, 0 , mmBIF_IH_DOORBELL_RANGE); 104954d5d43SChunming Zhou 105954d5d43SChunming Zhou if (use_doorbell) { 106954d5d43SChunming Zhou ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, BIF_IH_DOORBELL_RANGE, OFFSET, doorbell_index); 107954d5d43SChunming Zhou ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, BIF_IH_DOORBELL_RANGE, SIZE, 2); 108954d5d43SChunming Zhou } else 109954d5d43SChunming Zhou ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, BIF_IH_DOORBELL_RANGE, SIZE, 0); 110954d5d43SChunming Zhou 111ba7d5a22STom St Denis WREG32_SOC15(NBIO, 0, mmBIF_IH_DOORBELL_RANGE, ih_doorbell_range); 112954d5d43SChunming Zhou } 113954d5d43SChunming Zhou 114954d5d43SChunming Zhou static uint32_t nbio_7_0_read_syshub_ind_mmr(struct amdgpu_device *adev, uint32_t offset) 115954d5d43SChunming Zhou { 116954d5d43SChunming Zhou uint32_t data; 117954d5d43SChunming Zhou 118ba7d5a22STom St Denis WREG32_SOC15(NBIO, 0, mmSYSHUB_INDEX, offset); 119ba7d5a22STom St Denis data = RREG32_SOC15(NBIO, 0, mmSYSHUB_DATA); 120954d5d43SChunming Zhou 121954d5d43SChunming Zhou return data; 122954d5d43SChunming Zhou } 123954d5d43SChunming Zhou 124954d5d43SChunming Zhou static void nbio_7_0_write_syshub_ind_mmr(struct amdgpu_device *adev, uint32_t offset, 125954d5d43SChunming Zhou uint32_t data) 126954d5d43SChunming Zhou { 127ba7d5a22STom St Denis WREG32_SOC15(NBIO, 0, mmSYSHUB_INDEX, offset); 128ba7d5a22STom St Denis WREG32_SOC15(NBIO, 0, mmSYSHUB_DATA, data); 129954d5d43SChunming Zhou } 130954d5d43SChunming Zhou 131bf383fb6SAlex Deucher static void nbio_v7_0_update_medium_grain_clock_gating(struct amdgpu_device *adev, 132954d5d43SChunming Zhou bool enable) 133954d5d43SChunming Zhou { 134954d5d43SChunming Zhou uint32_t def, data; 135954d5d43SChunming Zhou 136954d5d43SChunming Zhou /* NBIF_MGCG_CTRL_LCLK */ 137954d5d43SChunming Zhou def = data = RREG32_PCIE(smnNBIF_MGCG_CTRL_LCLK); 138954d5d43SChunming Zhou 139954d5d43SChunming Zhou if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_MGCG)) 140954d5d43SChunming Zhou data |= NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_EN_LCLK_MASK; 141954d5d43SChunming Zhou else 142954d5d43SChunming Zhou data &= ~NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_EN_LCLK_MASK; 143954d5d43SChunming Zhou 144954d5d43SChunming Zhou if (def != data) 145954d5d43SChunming Zhou WREG32_PCIE(smnNBIF_MGCG_CTRL_LCLK, data); 146954d5d43SChunming Zhou 147954d5d43SChunming Zhou /* SYSHUB_MGCG_CTRL_SOCCLK */ 148954d5d43SChunming Zhou def = data = nbio_7_0_read_syshub_ind_mmr(adev, ixSYSHUB_MMREG_IND_SYSHUB_MGCG_CTRL_SOCCLK); 149954d5d43SChunming Zhou 150954d5d43SChunming Zhou if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_MGCG)) 151954d5d43SChunming Zhou data |= SYSHUB_MMREG_DIRECT_SYSHUB_MGCG_CTRL_SOCCLK__SYSHUB_MGCG_EN_SOCCLK_MASK; 152954d5d43SChunming Zhou else 153954d5d43SChunming Zhou data &= ~SYSHUB_MMREG_DIRECT_SYSHUB_MGCG_CTRL_SOCCLK__SYSHUB_MGCG_EN_SOCCLK_MASK; 154954d5d43SChunming Zhou 155954d5d43SChunming Zhou if (def != data) 156954d5d43SChunming Zhou nbio_7_0_write_syshub_ind_mmr(adev, ixSYSHUB_MMREG_IND_SYSHUB_MGCG_CTRL_SOCCLK, data); 157954d5d43SChunming Zhou 158954d5d43SChunming Zhou /* SYSHUB_MGCG_CTRL_SHUBCLK */ 159954d5d43SChunming Zhou def = data = nbio_7_0_read_syshub_ind_mmr(adev, ixSYSHUB_MMREG_IND_SYSHUB_MGCG_CTRL_SHUBCLK); 160954d5d43SChunming Zhou 161954d5d43SChunming Zhou if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_MGCG)) 162954d5d43SChunming Zhou data |= SYSHUB_MMREG_DIRECT_SYSHUB_MGCG_CTRL_SHUBCLK__SYSHUB_MGCG_EN_SHUBCLK_MASK; 163954d5d43SChunming Zhou else 164954d5d43SChunming Zhou data &= ~SYSHUB_MMREG_DIRECT_SYSHUB_MGCG_CTRL_SHUBCLK__SYSHUB_MGCG_EN_SHUBCLK_MASK; 165954d5d43SChunming Zhou 166954d5d43SChunming Zhou if (def != data) 167954d5d43SChunming Zhou nbio_7_0_write_syshub_ind_mmr(adev, ixSYSHUB_MMREG_IND_SYSHUB_MGCG_CTRL_SHUBCLK, data); 168954d5d43SChunming Zhou } 169954d5d43SChunming Zhou 170bf383fb6SAlex Deucher static void nbio_v7_0_update_medium_grain_light_sleep(struct amdgpu_device *adev, 171bf383fb6SAlex Deucher bool enable) 172bf383fb6SAlex Deucher { 173bf383fb6SAlex Deucher uint32_t def, data; 174bf383fb6SAlex Deucher 175bf383fb6SAlex Deucher def = data = RREG32_PCIE(smnPCIE_CNTL2); 176bf383fb6SAlex Deucher if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_LS)) { 177bf383fb6SAlex Deucher data |= (PCIE_CNTL2__SLV_MEM_LS_EN_MASK | 178bf383fb6SAlex Deucher PCIE_CNTL2__MST_MEM_LS_EN_MASK | 179bf383fb6SAlex Deucher PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK); 180bf383fb6SAlex Deucher } else { 181bf383fb6SAlex Deucher data &= ~(PCIE_CNTL2__SLV_MEM_LS_EN_MASK | 182bf383fb6SAlex Deucher PCIE_CNTL2__MST_MEM_LS_EN_MASK | 183bf383fb6SAlex Deucher PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK); 184bf383fb6SAlex Deucher } 185bf383fb6SAlex Deucher 186bf383fb6SAlex Deucher if (def != data) 187bf383fb6SAlex Deucher WREG32_PCIE(smnPCIE_CNTL2, data); 188bf383fb6SAlex Deucher } 189bf383fb6SAlex Deucher 190bf383fb6SAlex Deucher static void nbio_v7_0_get_clockgating_state(struct amdgpu_device *adev, 191bf383fb6SAlex Deucher u32 *flags) 192bf383fb6SAlex Deucher { 193bf383fb6SAlex Deucher int data; 194bf383fb6SAlex Deucher 195bf383fb6SAlex Deucher /* AMD_CG_SUPPORT_BIF_MGCG */ 196bf383fb6SAlex Deucher data = RREG32_PCIE(smnCPM_CONTROL); 197bf383fb6SAlex Deucher if (data & CPM_CONTROL__LCLK_DYN_GATE_ENABLE_MASK) 198bf383fb6SAlex Deucher *flags |= AMD_CG_SUPPORT_BIF_MGCG; 199bf383fb6SAlex Deucher 200bf383fb6SAlex Deucher /* AMD_CG_SUPPORT_BIF_LS */ 201bf383fb6SAlex Deucher data = RREG32_PCIE(smnPCIE_CNTL2); 202bf383fb6SAlex Deucher if (data & PCIE_CNTL2__SLV_MEM_LS_EN_MASK) 203bf383fb6SAlex Deucher *flags |= AMD_CG_SUPPORT_BIF_LS; 204bf383fb6SAlex Deucher } 205bf383fb6SAlex Deucher 206bf383fb6SAlex Deucher static void nbio_v7_0_ih_control(struct amdgpu_device *adev) 207954d5d43SChunming Zhou { 208954d5d43SChunming Zhou u32 interrupt_cntl; 209954d5d43SChunming Zhou 210954d5d43SChunming Zhou /* setup interrupt control */ 211ba7d5a22STom St Denis WREG32_SOC15(NBIO, 0, mmINTERRUPT_CNTL2, adev->dummy_page.addr >> 8); 212ba7d5a22STom St Denis interrupt_cntl = RREG32_SOC15(NBIO, 0, mmINTERRUPT_CNTL); 213954d5d43SChunming Zhou /* INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=0 - dummy read disabled with msi, enabled without msi 214954d5d43SChunming Zhou * INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=1 - dummy read controlled by IH_DUMMY_RD_EN 215954d5d43SChunming Zhou */ 216954d5d43SChunming Zhou interrupt_cntl = REG_SET_FIELD(interrupt_cntl, INTERRUPT_CNTL, IH_DUMMY_RD_OVERRIDE, 0); 217954d5d43SChunming Zhou /* INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN_MASK=1 if ring is in non-cacheable memory, e.g., vram */ 218954d5d43SChunming Zhou interrupt_cntl = REG_SET_FIELD(interrupt_cntl, INTERRUPT_CNTL, IH_REQ_NONSNOOP_EN, 0); 219ba7d5a22STom St Denis WREG32_SOC15(NBIO, 0, mmINTERRUPT_CNTL, interrupt_cntl); 220954d5d43SChunming Zhou } 221954d5d43SChunming Zhou 22274e1d67cSAlex Deucher static u32 nbio_v7_0_get_hdp_flush_req_offset(struct amdgpu_device *adev) 223946a4d5bSShaoyun Liu { 224946a4d5bSShaoyun Liu return SOC15_REG_OFFSET(NBIO, 0, mmGPU_HDP_FLUSH_REQ); 225946a4d5bSShaoyun Liu } 226946a4d5bSShaoyun Liu 22774e1d67cSAlex Deucher static u32 nbio_v7_0_get_hdp_flush_done_offset(struct amdgpu_device *adev) 228946a4d5bSShaoyun Liu { 229946a4d5bSShaoyun Liu return SOC15_REG_OFFSET(NBIO, 0, mmGPU_HDP_FLUSH_DONE); 230946a4d5bSShaoyun Liu } 231946a4d5bSShaoyun Liu 23274e1d67cSAlex Deucher static u32 nbio_v7_0_get_pcie_index_offset(struct amdgpu_device *adev) 233946a4d5bSShaoyun Liu { 234946a4d5bSShaoyun Liu return SOC15_REG_OFFSET(NBIO, 0, mmPCIE_INDEX2); 235946a4d5bSShaoyun Liu } 236946a4d5bSShaoyun Liu 23774e1d67cSAlex Deucher static u32 nbio_v7_0_get_pcie_data_offset(struct amdgpu_device *adev) 238946a4d5bSShaoyun Liu { 239946a4d5bSShaoyun Liu return SOC15_REG_OFFSET(NBIO, 0, mmPCIE_DATA2); 240946a4d5bSShaoyun Liu } 241946a4d5bSShaoyun Liu 242c6622f3aSDave Airlie const struct nbio_hdp_flush_reg nbio_v7_0_hdp_flush_reg = { 243c6622f3aSDave Airlie .ref_and_mask_cp0 = GPU_HDP_FLUSH_DONE__CP0_MASK, 244c6622f3aSDave Airlie .ref_and_mask_cp1 = GPU_HDP_FLUSH_DONE__CP1_MASK, 245c6622f3aSDave Airlie .ref_and_mask_cp2 = GPU_HDP_FLUSH_DONE__CP2_MASK, 246c6622f3aSDave Airlie .ref_and_mask_cp3 = GPU_HDP_FLUSH_DONE__CP3_MASK, 247c6622f3aSDave Airlie .ref_and_mask_cp4 = GPU_HDP_FLUSH_DONE__CP4_MASK, 248c6622f3aSDave Airlie .ref_and_mask_cp5 = GPU_HDP_FLUSH_DONE__CP5_MASK, 249c6622f3aSDave Airlie .ref_and_mask_cp6 = GPU_HDP_FLUSH_DONE__CP6_MASK, 250c6622f3aSDave Airlie .ref_and_mask_cp7 = GPU_HDP_FLUSH_DONE__CP7_MASK, 251c6622f3aSDave Airlie .ref_and_mask_cp8 = GPU_HDP_FLUSH_DONE__CP8_MASK, 252c6622f3aSDave Airlie .ref_and_mask_cp9 = GPU_HDP_FLUSH_DONE__CP9_MASK, 253c6622f3aSDave Airlie .ref_and_mask_sdma0 = GPU_HDP_FLUSH_DONE__SDMA0_MASK, 254c6622f3aSDave Airlie .ref_and_mask_sdma1 = GPU_HDP_FLUSH_DONE__SDMA1_MASK, 255c6622f3aSDave Airlie }; 256c6622f3aSDave Airlie 257bf383fb6SAlex Deucher static void nbio_v7_0_detect_hw_virt(struct amdgpu_device *adev) 258bf383fb6SAlex Deucher { 259bf383fb6SAlex Deucher if (is_virtual_machine()) /* passthrough mode exclus sriov mod */ 260bf383fb6SAlex Deucher adev->virt.caps |= AMDGPU_PASSTHROUGH_MODE; 261bf383fb6SAlex Deucher } 262bf383fb6SAlex Deucher 263bf383fb6SAlex Deucher static void nbio_v7_0_init_registers(struct amdgpu_device *adev) 264bf383fb6SAlex Deucher { 265bf383fb6SAlex Deucher 266bf383fb6SAlex Deucher } 267bf383fb6SAlex Deucher 268946a4d5bSShaoyun Liu const struct amdgpu_nbio_funcs nbio_v7_0_funcs = { 269bf383fb6SAlex Deucher .hdp_flush_reg = &nbio_v7_0_hdp_flush_reg, 27074e1d67cSAlex Deucher .get_hdp_flush_req_offset = nbio_v7_0_get_hdp_flush_req_offset, 27174e1d67cSAlex Deucher .get_hdp_flush_done_offset = nbio_v7_0_get_hdp_flush_done_offset, 27274e1d67cSAlex Deucher .get_pcie_index_offset = nbio_v7_0_get_pcie_index_offset, 27374e1d67cSAlex Deucher .get_pcie_data_offset = nbio_v7_0_get_pcie_data_offset, 274bf383fb6SAlex Deucher .get_rev_id = nbio_v7_0_get_rev_id, 275bf383fb6SAlex Deucher .mc_access_enable = nbio_v7_0_mc_access_enable, 276bf383fb6SAlex Deucher .hdp_flush = nbio_v7_0_hdp_flush, 277bf383fb6SAlex Deucher .get_memsize = nbio_v7_0_get_memsize, 278bf383fb6SAlex Deucher .sdma_doorbell_range = nbio_v7_0_sdma_doorbell_range, 279bf383fb6SAlex Deucher .enable_doorbell_aperture = nbio_v7_0_enable_doorbell_aperture, 280bf383fb6SAlex Deucher .enable_doorbell_selfring_aperture = nbio_v7_0_enable_doorbell_selfring_aperture, 281bf383fb6SAlex Deucher .ih_doorbell_range = nbio_v7_0_ih_doorbell_range, 282bf383fb6SAlex Deucher .update_medium_grain_clock_gating = nbio_v7_0_update_medium_grain_clock_gating, 283bf383fb6SAlex Deucher .update_medium_grain_light_sleep = nbio_v7_0_update_medium_grain_light_sleep, 284bf383fb6SAlex Deucher .get_clockgating_state = nbio_v7_0_get_clockgating_state, 285bf383fb6SAlex Deucher .ih_control = nbio_v7_0_ih_control, 286bf383fb6SAlex Deucher .init_registers = nbio_v7_0_init_registers, 287bf383fb6SAlex Deucher .detect_hw_virt = nbio_v7_0_detect_hw_virt, 28835b31f7cSDave Airlie }; 289