1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include "amdgpu.h" 24 #include "amdgpu_atombios.h" 25 #include "nbio_v6_1.h" 26 27 #include "vega10/soc15ip.h" 28 #include "vega10/NBIO/nbio_6_1_default.h" 29 #include "vega10/NBIO/nbio_6_1_offset.h" 30 #include "vega10/NBIO/nbio_6_1_sh_mask.h" 31 #include "vega10/vega10_enum.h" 32 33 #define smnCPM_CONTROL 0x11180460 34 #define smnPCIE_CNTL2 0x11180070 35 #define smnPCIE_CONFIG_CNTL 0x11180044 36 37 u32 nbio_v6_1_get_rev_id(struct amdgpu_device *adev) 38 { 39 u32 tmp = RREG32_SOC15(NBIO, 0, mmRCC_DEV0_EPF0_STRAP0); 40 41 tmp &= RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0_MASK; 42 tmp >>= RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0__SHIFT; 43 44 return tmp; 45 } 46 47 u32 nbio_v6_1_get_atombios_scratch_regs(struct amdgpu_device *adev, 48 uint32_t idx) 49 { 50 return RREG32_SOC15_OFFSET(NBIO, 0, mmBIOS_SCRATCH_0, idx); 51 } 52 53 void nbio_v6_1_set_atombios_scratch_regs(struct amdgpu_device *adev, 54 uint32_t idx, uint32_t val) 55 { 56 WREG32_SOC15_OFFSET(NBIO, 0, mmBIOS_SCRATCH_0, idx, val); 57 } 58 59 void nbio_v6_1_mc_access_enable(struct amdgpu_device *adev, bool enable) 60 { 61 if (enable) 62 WREG32_SOC15(NBIO, 0, mmBIF_FB_EN, 63 BIF_FB_EN__FB_READ_EN_MASK | 64 BIF_FB_EN__FB_WRITE_EN_MASK); 65 else 66 WREG32_SOC15(NBIO, 0, mmBIF_FB_EN, 0); 67 } 68 69 void nbio_v6_1_hdp_flush(struct amdgpu_device *adev) 70 { 71 WREG32_SOC15_NO_KIQ(NBIO, 0, mmBIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_CNTL, 0); 72 } 73 74 u32 nbio_v6_1_get_memsize(struct amdgpu_device *adev) 75 { 76 return RREG32_SOC15(NBIO, 0, mmRCC_PF_0_0_RCC_CONFIG_MEMSIZE); 77 } 78 79 static const u32 nbio_sdma_doorbell_range_reg[] = 80 { 81 SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA0_DOORBELL_RANGE), 82 SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA1_DOORBELL_RANGE) 83 }; 84 85 void nbio_v6_1_sdma_doorbell_range(struct amdgpu_device *adev, int instance, 86 bool use_doorbell, int doorbell_index) 87 { 88 u32 doorbell_range = RREG32(nbio_sdma_doorbell_range_reg[instance]); 89 90 if (use_doorbell) { 91 doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, OFFSET, doorbell_index); 92 doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, SIZE, 2); 93 } else 94 doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, SIZE, 0); 95 96 WREG32(nbio_sdma_doorbell_range_reg[instance], doorbell_range); 97 } 98 99 void nbio_v6_1_enable_doorbell_aperture(struct amdgpu_device *adev, 100 bool enable) 101 { 102 WREG32_FIELD15(NBIO, 0, RCC_PF_0_0_RCC_DOORBELL_APER_EN, BIF_DOORBELL_APER_EN, enable ? 1 : 0); 103 } 104 105 void nbio_v6_1_enable_doorbell_selfring_aperture(struct amdgpu_device *adev, 106 bool enable) 107 { 108 u32 tmp = 0; 109 110 if (enable) { 111 tmp = REG_SET_FIELD(tmp, BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL, DOORBELL_SELFRING_GPA_APER_EN, 1) | 112 REG_SET_FIELD(tmp, BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL, DOORBELL_SELFRING_GPA_APER_MODE, 1) | 113 REG_SET_FIELD(tmp, BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL, DOORBELL_SELFRING_GPA_APER_SIZE, 0); 114 115 WREG32_SOC15(NBIO, 0, mmBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW, 116 lower_32_bits(adev->doorbell.base)); 117 WREG32_SOC15(NBIO, 0, mmBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH, 118 upper_32_bits(adev->doorbell.base)); 119 } 120 121 WREG32_SOC15(NBIO, 0, mmBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL, tmp); 122 } 123 124 125 void nbio_v6_1_ih_doorbell_range(struct amdgpu_device *adev, 126 bool use_doorbell, int doorbell_index) 127 { 128 u32 ih_doorbell_range = RREG32_SOC15(NBIO, 0 , mmBIF_IH_DOORBELL_RANGE); 129 130 if (use_doorbell) { 131 ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, BIF_IH_DOORBELL_RANGE, OFFSET, doorbell_index); 132 ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, BIF_IH_DOORBELL_RANGE, SIZE, 2); 133 } else 134 ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, BIF_IH_DOORBELL_RANGE, SIZE, 0); 135 136 WREG32_SOC15(NBIO, 0, mmBIF_IH_DOORBELL_RANGE, ih_doorbell_range); 137 } 138 139 void nbio_v6_1_ih_control(struct amdgpu_device *adev) 140 { 141 u32 interrupt_cntl; 142 143 /* setup interrupt control */ 144 WREG32_SOC15(NBIO, 0, mmINTERRUPT_CNTL2, adev->dummy_page.addr >> 8); 145 interrupt_cntl = RREG32_SOC15(NBIO, 0, mmINTERRUPT_CNTL); 146 /* INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=0 - dummy read disabled with msi, enabled without msi 147 * INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=1 - dummy read controlled by IH_DUMMY_RD_EN 148 */ 149 interrupt_cntl = REG_SET_FIELD(interrupt_cntl, INTERRUPT_CNTL, IH_DUMMY_RD_OVERRIDE, 0); 150 /* INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN_MASK=1 if ring is in non-cacheable memory, e.g., vram */ 151 interrupt_cntl = REG_SET_FIELD(interrupt_cntl, INTERRUPT_CNTL, IH_REQ_NONSNOOP_EN, 0); 152 WREG32_SOC15(NBIO, 0, mmINTERRUPT_CNTL, interrupt_cntl); 153 } 154 155 void nbio_v6_1_update_medium_grain_clock_gating(struct amdgpu_device *adev, 156 bool enable) 157 { 158 uint32_t def, data; 159 160 def = data = RREG32_PCIE(smnCPM_CONTROL); 161 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_MGCG)) { 162 data |= (CPM_CONTROL__LCLK_DYN_GATE_ENABLE_MASK | 163 CPM_CONTROL__TXCLK_DYN_GATE_ENABLE_MASK | 164 CPM_CONTROL__TXCLK_PERM_GATE_ENABLE_MASK | 165 CPM_CONTROL__TXCLK_LCNT_GATE_ENABLE_MASK | 166 CPM_CONTROL__TXCLK_REGS_GATE_ENABLE_MASK | 167 CPM_CONTROL__TXCLK_PRBS_GATE_ENABLE_MASK | 168 CPM_CONTROL__REFCLK_REGS_GATE_ENABLE_MASK); 169 } else { 170 data &= ~(CPM_CONTROL__LCLK_DYN_GATE_ENABLE_MASK | 171 CPM_CONTROL__TXCLK_DYN_GATE_ENABLE_MASK | 172 CPM_CONTROL__TXCLK_PERM_GATE_ENABLE_MASK | 173 CPM_CONTROL__TXCLK_LCNT_GATE_ENABLE_MASK | 174 CPM_CONTROL__TXCLK_REGS_GATE_ENABLE_MASK | 175 CPM_CONTROL__TXCLK_PRBS_GATE_ENABLE_MASK | 176 CPM_CONTROL__REFCLK_REGS_GATE_ENABLE_MASK); 177 } 178 179 if (def != data) 180 WREG32_PCIE(smnCPM_CONTROL, data); 181 } 182 183 void nbio_v6_1_update_medium_grain_light_sleep(struct amdgpu_device *adev, 184 bool enable) 185 { 186 uint32_t def, data; 187 188 def = data = RREG32_PCIE(smnPCIE_CNTL2); 189 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_LS)) { 190 data |= (PCIE_CNTL2__SLV_MEM_LS_EN_MASK | 191 PCIE_CNTL2__MST_MEM_LS_EN_MASK | 192 PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK); 193 } else { 194 data &= ~(PCIE_CNTL2__SLV_MEM_LS_EN_MASK | 195 PCIE_CNTL2__MST_MEM_LS_EN_MASK | 196 PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK); 197 } 198 199 if (def != data) 200 WREG32_PCIE(smnPCIE_CNTL2, data); 201 } 202 203 void nbio_v6_1_get_clockgating_state(struct amdgpu_device *adev, u32 *flags) 204 { 205 int data; 206 207 /* AMD_CG_SUPPORT_BIF_MGCG */ 208 data = RREG32_PCIE(smnCPM_CONTROL); 209 if (data & CPM_CONTROL__LCLK_DYN_GATE_ENABLE_MASK) 210 *flags |= AMD_CG_SUPPORT_BIF_MGCG; 211 212 /* AMD_CG_SUPPORT_BIF_LS */ 213 data = RREG32_PCIE(smnPCIE_CNTL2); 214 if (data & PCIE_CNTL2__SLV_MEM_LS_EN_MASK) 215 *flags |= AMD_CG_SUPPORT_BIF_LS; 216 } 217 218 const struct nbio_hdp_flush_reg nbio_v6_1_hdp_flush_reg = { 219 .hdp_flush_req_offset = SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_GPU_HDP_FLUSH_REQ), 220 .hdp_flush_done_offset = SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_GPU_HDP_FLUSH_DONE), 221 .ref_and_mask_cp0 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP0_MASK, 222 .ref_and_mask_cp1 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP1_MASK, 223 .ref_and_mask_cp2 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP2_MASK, 224 .ref_and_mask_cp3 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP3_MASK, 225 .ref_and_mask_cp4 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP4_MASK, 226 .ref_and_mask_cp5 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP5_MASK, 227 .ref_and_mask_cp6 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP6_MASK, 228 .ref_and_mask_cp7 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP7_MASK, 229 .ref_and_mask_cp8 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP8_MASK, 230 .ref_and_mask_cp9 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP9_MASK, 231 .ref_and_mask_sdma0 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__SDMA0_MASK, 232 .ref_and_mask_sdma1 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__SDMA1_MASK 233 }; 234 235 const struct nbio_pcie_index_data nbio_v6_1_pcie_index_data = { 236 .index_offset = SOC15_REG_OFFSET(NBIO, 0, mmPCIE_INDEX), 237 .data_offset = SOC15_REG_OFFSET(NBIO, 0, mmPCIE_DATA), 238 }; 239 240 void nbio_v6_1_detect_hw_virt(struct amdgpu_device *adev) 241 { 242 uint32_t reg; 243 244 reg = RREG32_SOC15(NBIO, 0, mmRCC_PF_0_0_RCC_IOV_FUNC_IDENTIFIER); 245 if (reg & 1) 246 adev->virt.caps |= AMDGPU_SRIOV_CAPS_IS_VF; 247 248 if (reg & 0x80000000) 249 adev->virt.caps |= AMDGPU_SRIOV_CAPS_ENABLE_IOV; 250 251 if (!reg) { 252 if (is_virtual_machine()) /* passthrough mode exclus sriov mod */ 253 adev->virt.caps |= AMDGPU_PASSTHROUGH_MODE; 254 } 255 } 256 257 void nbio_v6_1_init_registers(struct amdgpu_device *adev) 258 { 259 uint32_t def, data; 260 261 def = data = RREG32_PCIE(smnPCIE_CONFIG_CNTL); 262 data = REG_SET_FIELD(data, PCIE_CONFIG_CNTL, CI_SWUS_MAX_READ_REQUEST_SIZE_MODE, 1); 263 data = REG_SET_FIELD(data, PCIE_CONFIG_CNTL, CI_SWUS_MAX_READ_REQUEST_SIZE_PRIV, 1); 264 265 if (def != data) 266 WREG32_PCIE(smnPCIE_CONFIG_CNTL, data); 267 } 268