1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include "amdgpu.h" 24 #include "amdgpu_atombios.h" 25 #include "nbio_v6_1.h" 26 27 #include "nbio/nbio_6_1_default.h" 28 #include "nbio/nbio_6_1_offset.h" 29 #include "nbio/nbio_6_1_sh_mask.h" 30 #include "vega10_enum.h" 31 32 #define smnCPM_CONTROL 0x11180460 33 #define smnPCIE_CNTL2 0x11180070 34 #define smnPCIE_CONFIG_CNTL 0x11180044 35 36 static u32 nbio_v6_1_get_rev_id(struct amdgpu_device *adev) 37 { 38 u32 tmp = RREG32_SOC15(NBIO, 0, mmRCC_DEV0_EPF0_STRAP0); 39 40 tmp &= RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0_MASK; 41 tmp >>= RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0__SHIFT; 42 43 return tmp; 44 } 45 46 static void nbio_v6_1_mc_access_enable(struct amdgpu_device *adev, bool enable) 47 { 48 if (enable) 49 WREG32_SOC15(NBIO, 0, mmBIF_FB_EN, 50 BIF_FB_EN__FB_READ_EN_MASK | 51 BIF_FB_EN__FB_WRITE_EN_MASK); 52 else 53 WREG32_SOC15(NBIO, 0, mmBIF_FB_EN, 0); 54 } 55 56 static void nbio_v6_1_hdp_flush(struct amdgpu_device *adev) 57 { 58 WREG32_SOC15_NO_KIQ(NBIO, 0, mmBIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_CNTL, 0); 59 } 60 61 static u32 nbio_v6_1_get_memsize(struct amdgpu_device *adev) 62 { 63 return RREG32_SOC15(NBIO, 0, mmRCC_PF_0_0_RCC_CONFIG_MEMSIZE); 64 } 65 66 static void nbio_v6_1_sdma_doorbell_range(struct amdgpu_device *adev, int instance, 67 bool use_doorbell, int doorbell_index) 68 { 69 u32 reg = instance == 0 ? SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA0_DOORBELL_RANGE) : 70 SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA1_DOORBELL_RANGE); 71 72 u32 doorbell_range = RREG32(reg); 73 74 if (use_doorbell) { 75 doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, OFFSET, doorbell_index); 76 doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, SIZE, 2); 77 } else 78 doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, SIZE, 0); 79 80 WREG32(reg, doorbell_range); 81 82 } 83 84 static void nbio_v6_1_enable_doorbell_aperture(struct amdgpu_device *adev, 85 bool enable) 86 { 87 WREG32_FIELD15(NBIO, 0, RCC_PF_0_0_RCC_DOORBELL_APER_EN, BIF_DOORBELL_APER_EN, enable ? 1 : 0); 88 } 89 90 static void nbio_v6_1_enable_doorbell_selfring_aperture(struct amdgpu_device *adev, 91 bool enable) 92 { 93 u32 tmp = 0; 94 95 if (enable) { 96 tmp = REG_SET_FIELD(tmp, BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL, DOORBELL_SELFRING_GPA_APER_EN, 1) | 97 REG_SET_FIELD(tmp, BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL, DOORBELL_SELFRING_GPA_APER_MODE, 1) | 98 REG_SET_FIELD(tmp, BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL, DOORBELL_SELFRING_GPA_APER_SIZE, 0); 99 100 WREG32_SOC15(NBIO, 0, mmBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW, 101 lower_32_bits(adev->doorbell.base)); 102 WREG32_SOC15(NBIO, 0, mmBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH, 103 upper_32_bits(adev->doorbell.base)); 104 } 105 106 WREG32_SOC15(NBIO, 0, mmBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL, tmp); 107 } 108 109 110 static void nbio_v6_1_ih_doorbell_range(struct amdgpu_device *adev, 111 bool use_doorbell, int doorbell_index) 112 { 113 u32 ih_doorbell_range = RREG32_SOC15(NBIO, 0 , mmBIF_IH_DOORBELL_RANGE); 114 115 if (use_doorbell) { 116 ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, BIF_IH_DOORBELL_RANGE, OFFSET, doorbell_index); 117 ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, BIF_IH_DOORBELL_RANGE, SIZE, 2); 118 } else 119 ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, BIF_IH_DOORBELL_RANGE, SIZE, 0); 120 121 WREG32_SOC15(NBIO, 0, mmBIF_IH_DOORBELL_RANGE, ih_doorbell_range); 122 } 123 124 static void nbio_v6_1_ih_control(struct amdgpu_device *adev) 125 { 126 u32 interrupt_cntl; 127 128 /* setup interrupt control */ 129 WREG32_SOC15(NBIO, 0, mmINTERRUPT_CNTL2, adev->dummy_page.addr >> 8); 130 interrupt_cntl = RREG32_SOC15(NBIO, 0, mmINTERRUPT_CNTL); 131 /* INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=0 - dummy read disabled with msi, enabled without msi 132 * INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=1 - dummy read controlled by IH_DUMMY_RD_EN 133 */ 134 interrupt_cntl = REG_SET_FIELD(interrupt_cntl, INTERRUPT_CNTL, IH_DUMMY_RD_OVERRIDE, 0); 135 /* INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN_MASK=1 if ring is in non-cacheable memory, e.g., vram */ 136 interrupt_cntl = REG_SET_FIELD(interrupt_cntl, INTERRUPT_CNTL, IH_REQ_NONSNOOP_EN, 0); 137 WREG32_SOC15(NBIO, 0, mmINTERRUPT_CNTL, interrupt_cntl); 138 } 139 140 static void nbio_v6_1_update_medium_grain_clock_gating(struct amdgpu_device *adev, 141 bool enable) 142 { 143 uint32_t def, data; 144 145 def = data = RREG32_PCIE(smnCPM_CONTROL); 146 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_MGCG)) { 147 data |= (CPM_CONTROL__LCLK_DYN_GATE_ENABLE_MASK | 148 CPM_CONTROL__TXCLK_DYN_GATE_ENABLE_MASK | 149 CPM_CONTROL__TXCLK_PERM_GATE_ENABLE_MASK | 150 CPM_CONTROL__TXCLK_LCNT_GATE_ENABLE_MASK | 151 CPM_CONTROL__TXCLK_REGS_GATE_ENABLE_MASK | 152 CPM_CONTROL__TXCLK_PRBS_GATE_ENABLE_MASK | 153 CPM_CONTROL__REFCLK_REGS_GATE_ENABLE_MASK); 154 } else { 155 data &= ~(CPM_CONTROL__LCLK_DYN_GATE_ENABLE_MASK | 156 CPM_CONTROL__TXCLK_DYN_GATE_ENABLE_MASK | 157 CPM_CONTROL__TXCLK_PERM_GATE_ENABLE_MASK | 158 CPM_CONTROL__TXCLK_LCNT_GATE_ENABLE_MASK | 159 CPM_CONTROL__TXCLK_REGS_GATE_ENABLE_MASK | 160 CPM_CONTROL__TXCLK_PRBS_GATE_ENABLE_MASK | 161 CPM_CONTROL__REFCLK_REGS_GATE_ENABLE_MASK); 162 } 163 164 if (def != data) 165 WREG32_PCIE(smnCPM_CONTROL, data); 166 } 167 168 static void nbio_v6_1_update_medium_grain_light_sleep(struct amdgpu_device *adev, 169 bool enable) 170 { 171 uint32_t def, data; 172 173 def = data = RREG32_PCIE(smnPCIE_CNTL2); 174 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_LS)) { 175 data |= (PCIE_CNTL2__SLV_MEM_LS_EN_MASK | 176 PCIE_CNTL2__MST_MEM_LS_EN_MASK | 177 PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK); 178 } else { 179 data &= ~(PCIE_CNTL2__SLV_MEM_LS_EN_MASK | 180 PCIE_CNTL2__MST_MEM_LS_EN_MASK | 181 PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK); 182 } 183 184 if (def != data) 185 WREG32_PCIE(smnPCIE_CNTL2, data); 186 } 187 188 static void nbio_v6_1_get_clockgating_state(struct amdgpu_device *adev, 189 u32 *flags) 190 { 191 int data; 192 193 /* AMD_CG_SUPPORT_BIF_MGCG */ 194 data = RREG32_PCIE(smnCPM_CONTROL); 195 if (data & CPM_CONTROL__LCLK_DYN_GATE_ENABLE_MASK) 196 *flags |= AMD_CG_SUPPORT_BIF_MGCG; 197 198 /* AMD_CG_SUPPORT_BIF_LS */ 199 data = RREG32_PCIE(smnPCIE_CNTL2); 200 if (data & PCIE_CNTL2__SLV_MEM_LS_EN_MASK) 201 *flags |= AMD_CG_SUPPORT_BIF_LS; 202 } 203 204 static u32 nbio_v6_1_get_hdp_flush_req_offset(struct amdgpu_device *adev) 205 { 206 return SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_GPU_HDP_FLUSH_REQ); 207 } 208 209 static u32 nbio_v6_1_get_hdp_flush_done_offset(struct amdgpu_device *adev) 210 { 211 return SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_GPU_HDP_FLUSH_DONE); 212 } 213 214 static u32 nbio_v6_1_get_pcie_index_offset(struct amdgpu_device *adev) 215 { 216 return SOC15_REG_OFFSET(NBIO, 0, mmPCIE_INDEX); 217 } 218 219 static u32 nbio_v6_1_get_pcie_data_offset(struct amdgpu_device *adev) 220 { 221 return SOC15_REG_OFFSET(NBIO, 0, mmPCIE_DATA); 222 } 223 224 static const struct nbio_hdp_flush_reg nbio_v6_1_hdp_flush_reg = { 225 .ref_and_mask_cp0 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP0_MASK, 226 .ref_and_mask_cp1 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP1_MASK, 227 .ref_and_mask_cp2 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP2_MASK, 228 .ref_and_mask_cp3 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP3_MASK, 229 .ref_and_mask_cp4 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP4_MASK, 230 .ref_and_mask_cp5 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP5_MASK, 231 .ref_and_mask_cp6 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP6_MASK, 232 .ref_and_mask_cp7 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP7_MASK, 233 .ref_and_mask_cp8 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP8_MASK, 234 .ref_and_mask_cp9 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP9_MASK, 235 .ref_and_mask_sdma0 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__SDMA0_MASK, 236 .ref_and_mask_sdma1 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__SDMA1_MASK 237 }; 238 239 static void nbio_v6_1_detect_hw_virt(struct amdgpu_device *adev) 240 { 241 uint32_t reg; 242 243 reg = RREG32_SOC15(NBIO, 0, mmRCC_PF_0_0_RCC_IOV_FUNC_IDENTIFIER); 244 if (reg & 1) 245 adev->virt.caps |= AMDGPU_SRIOV_CAPS_IS_VF; 246 247 if (reg & 0x80000000) 248 adev->virt.caps |= AMDGPU_SRIOV_CAPS_ENABLE_IOV; 249 250 if (!reg) { 251 if (is_virtual_machine()) /* passthrough mode exclus sriov mod */ 252 adev->virt.caps |= AMDGPU_PASSTHROUGH_MODE; 253 } 254 } 255 256 static void nbio_v6_1_init_registers(struct amdgpu_device *adev) 257 { 258 uint32_t def, data; 259 260 def = data = RREG32_PCIE(smnPCIE_CONFIG_CNTL); 261 data = REG_SET_FIELD(data, PCIE_CONFIG_CNTL, CI_SWUS_MAX_READ_REQUEST_SIZE_MODE, 1); 262 data = REG_SET_FIELD(data, PCIE_CONFIG_CNTL, CI_SWUS_MAX_READ_REQUEST_SIZE_PRIV, 1); 263 264 if (def != data) 265 WREG32_PCIE(smnPCIE_CONFIG_CNTL, data); 266 } 267 268 const struct amdgpu_nbio_funcs nbio_v6_1_funcs = { 269 .hdp_flush_reg = &nbio_v6_1_hdp_flush_reg, 270 .get_hdp_flush_req_offset = nbio_v6_1_get_hdp_flush_req_offset, 271 .get_hdp_flush_done_offset = nbio_v6_1_get_hdp_flush_done_offset, 272 .get_pcie_index_offset = nbio_v6_1_get_pcie_index_offset, 273 .get_pcie_data_offset = nbio_v6_1_get_pcie_data_offset, 274 .get_rev_id = nbio_v6_1_get_rev_id, 275 .mc_access_enable = nbio_v6_1_mc_access_enable, 276 .hdp_flush = nbio_v6_1_hdp_flush, 277 .get_memsize = nbio_v6_1_get_memsize, 278 .sdma_doorbell_range = nbio_v6_1_sdma_doorbell_range, 279 .enable_doorbell_aperture = nbio_v6_1_enable_doorbell_aperture, 280 .enable_doorbell_selfring_aperture = nbio_v6_1_enable_doorbell_selfring_aperture, 281 .ih_doorbell_range = nbio_v6_1_ih_doorbell_range, 282 .update_medium_grain_clock_gating = nbio_v6_1_update_medium_grain_clock_gating, 283 .update_medium_grain_light_sleep = nbio_v6_1_update_medium_grain_light_sleep, 284 .get_clockgating_state = nbio_v6_1_get_clockgating_state, 285 .ih_control = nbio_v6_1_ih_control, 286 .init_registers = nbio_v6_1_init_registers, 287 .detect_hw_virt = nbio_v6_1_detect_hw_virt, 288 }; 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