1*0d09a60eSStanley.Yang /* 2*0d09a60eSStanley.Yang * Copyright 2021 Advanced Micro Devices, Inc. 3*0d09a60eSStanley.Yang * 4*0d09a60eSStanley.Yang * Permission is hereby granted, free of charge, to any person obtaining a 5*0d09a60eSStanley.Yang * copy of this software and associated documentation files (the "Software"), 6*0d09a60eSStanley.Yang * to deal in the Software without restriction, including without limitation 7*0d09a60eSStanley.Yang * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8*0d09a60eSStanley.Yang * and/or sell copies of the Software, and to permit persons to whom the 9*0d09a60eSStanley.Yang * Software is furnished to do so, subject to the following conditions: 10*0d09a60eSStanley.Yang * 11*0d09a60eSStanley.Yang * The above copyright notice and this permission notice shall be included in 12*0d09a60eSStanley.Yang * all copies or substantial portions of the Software. 13*0d09a60eSStanley.Yang * 14*0d09a60eSStanley.Yang * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15*0d09a60eSStanley.Yang * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16*0d09a60eSStanley.Yang * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17*0d09a60eSStanley.Yang * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18*0d09a60eSStanley.Yang * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19*0d09a60eSStanley.Yang * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20*0d09a60eSStanley.Yang * OTHER DEALINGS IN THE SOFTWARE. 21*0d09a60eSStanley.Yang * 22*0d09a60eSStanley.Yang */ 23*0d09a60eSStanley.Yang #include "amdgpu.h" 24*0d09a60eSStanley.Yang #include "amdgpu_atombios.h" 25*0d09a60eSStanley.Yang #include "nbio_v4_3.h" 26*0d09a60eSStanley.Yang 27*0d09a60eSStanley.Yang #include "nbio/nbio_4_3_0_offset.h" 28*0d09a60eSStanley.Yang #include "nbio/nbio_4_3_0_sh_mask.h" 29*0d09a60eSStanley.Yang #include <uapi/linux/kfd_ioctl.h> 30*0d09a60eSStanley.Yang 31*0d09a60eSStanley.Yang static void nbio_v4_3_remap_hdp_registers(struct amdgpu_device *adev) 32*0d09a60eSStanley.Yang { 33*0d09a60eSStanley.Yang WREG32_SOC15(NBIO, 0, regBIF_BX0_REMAP_HDP_MEM_FLUSH_CNTL, 34*0d09a60eSStanley.Yang adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL); 35*0d09a60eSStanley.Yang WREG32_SOC15(NBIO, 0, regBIF_BX0_REMAP_HDP_REG_FLUSH_CNTL, 36*0d09a60eSStanley.Yang adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_REG_FLUSH_CNTL); 37*0d09a60eSStanley.Yang } 38*0d09a60eSStanley.Yang 39*0d09a60eSStanley.Yang static u32 nbio_v4_3_get_rev_id(struct amdgpu_device *adev) 40*0d09a60eSStanley.Yang { 41*0d09a60eSStanley.Yang u32 tmp = RREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_DEV0_EPF0_STRAP0); 42*0d09a60eSStanley.Yang 43*0d09a60eSStanley.Yang tmp &= RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0_MASK; 44*0d09a60eSStanley.Yang tmp >>= RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0__SHIFT; 45*0d09a60eSStanley.Yang 46*0d09a60eSStanley.Yang return tmp; 47*0d09a60eSStanley.Yang } 48*0d09a60eSStanley.Yang 49*0d09a60eSStanley.Yang static void nbio_v4_3_mc_access_enable(struct amdgpu_device *adev, bool enable) 50*0d09a60eSStanley.Yang { 51*0d09a60eSStanley.Yang if (enable) 52*0d09a60eSStanley.Yang WREG32_SOC15(NBIO, 0, regBIF_BX0_BIF_FB_EN, 53*0d09a60eSStanley.Yang BIF_BX0_BIF_FB_EN__FB_READ_EN_MASK | 54*0d09a60eSStanley.Yang BIF_BX0_BIF_FB_EN__FB_WRITE_EN_MASK); 55*0d09a60eSStanley.Yang else 56*0d09a60eSStanley.Yang WREG32_SOC15(NBIO, 0, regBIF_BX0_BIF_FB_EN, 0); 57*0d09a60eSStanley.Yang } 58*0d09a60eSStanley.Yang 59*0d09a60eSStanley.Yang static u32 nbio_v4_3_get_memsize(struct amdgpu_device *adev) 60*0d09a60eSStanley.Yang { 61*0d09a60eSStanley.Yang return RREG32_SOC15(NBIO, 0, regRCC_DEV0_EPF0_RCC_CONFIG_MEMSIZE); 62*0d09a60eSStanley.Yang } 63*0d09a60eSStanley.Yang 64*0d09a60eSStanley.Yang static void nbio_v4_3_sdma_doorbell_range(struct amdgpu_device *adev, int instance, 65*0d09a60eSStanley.Yang bool use_doorbell, int doorbell_index, 66*0d09a60eSStanley.Yang int doorbell_size) 67*0d09a60eSStanley.Yang { 68*0d09a60eSStanley.Yang if (instance == 0) { 69*0d09a60eSStanley.Yang u32 doorbell_range = RREG32_SOC15(NBIO, 0, regS2A_DOORBELL_ENTRY_2_CTRL); 70*0d09a60eSStanley.Yang 71*0d09a60eSStanley.Yang if (use_doorbell) { 72*0d09a60eSStanley.Yang doorbell_range = REG_SET_FIELD(doorbell_range, 73*0d09a60eSStanley.Yang S2A_DOORBELL_ENTRY_2_CTRL, 74*0d09a60eSStanley.Yang S2A_DOORBELL_PORT2_ENABLE, 75*0d09a60eSStanley.Yang 0x1); 76*0d09a60eSStanley.Yang doorbell_range = REG_SET_FIELD(doorbell_range, 77*0d09a60eSStanley.Yang S2A_DOORBELL_ENTRY_2_CTRL, 78*0d09a60eSStanley.Yang S2A_DOORBELL_PORT2_AWID, 79*0d09a60eSStanley.Yang 0xe); 80*0d09a60eSStanley.Yang doorbell_range = REG_SET_FIELD(doorbell_range, 81*0d09a60eSStanley.Yang S2A_DOORBELL_ENTRY_2_CTRL, 82*0d09a60eSStanley.Yang S2A_DOORBELL_PORT2_RANGE_OFFSET, 83*0d09a60eSStanley.Yang doorbell_index); 84*0d09a60eSStanley.Yang doorbell_range = REG_SET_FIELD(doorbell_range, 85*0d09a60eSStanley.Yang S2A_DOORBELL_ENTRY_2_CTRL, 86*0d09a60eSStanley.Yang S2A_DOORBELL_PORT2_RANGE_SIZE, 87*0d09a60eSStanley.Yang doorbell_size); 88*0d09a60eSStanley.Yang doorbell_range = REG_SET_FIELD(doorbell_range, 89*0d09a60eSStanley.Yang S2A_DOORBELL_ENTRY_2_CTRL, 90*0d09a60eSStanley.Yang S2A_DOORBELL_PORT2_AWADDR_31_28_VALUE, 91*0d09a60eSStanley.Yang 0x3); 92*0d09a60eSStanley.Yang } else 93*0d09a60eSStanley.Yang doorbell_range = REG_SET_FIELD(doorbell_range, 94*0d09a60eSStanley.Yang S2A_DOORBELL_ENTRY_2_CTRL, 95*0d09a60eSStanley.Yang S2A_DOORBELL_PORT2_RANGE_SIZE, 96*0d09a60eSStanley.Yang 0); 97*0d09a60eSStanley.Yang 98*0d09a60eSStanley.Yang WREG32_SOC15(NBIO, 0, regS2A_DOORBELL_ENTRY_2_CTRL, doorbell_range); 99*0d09a60eSStanley.Yang } 100*0d09a60eSStanley.Yang } 101*0d09a60eSStanley.Yang 102*0d09a60eSStanley.Yang static void nbio_v4_3_vcn_doorbell_range(struct amdgpu_device *adev, bool use_doorbell, 103*0d09a60eSStanley.Yang int doorbell_index, int instance) 104*0d09a60eSStanley.Yang { 105*0d09a60eSStanley.Yang u32 doorbell_range; 106*0d09a60eSStanley.Yang 107*0d09a60eSStanley.Yang if (instance) 108*0d09a60eSStanley.Yang doorbell_range = RREG32_SOC15(NBIO, 0, regS2A_DOORBELL_ENTRY_5_CTRL); 109*0d09a60eSStanley.Yang else 110*0d09a60eSStanley.Yang doorbell_range = RREG32_SOC15(NBIO, 0, regS2A_DOORBELL_ENTRY_4_CTRL); 111*0d09a60eSStanley.Yang 112*0d09a60eSStanley.Yang if (use_doorbell) { 113*0d09a60eSStanley.Yang doorbell_range = REG_SET_FIELD(doorbell_range, 114*0d09a60eSStanley.Yang S2A_DOORBELL_ENTRY_4_CTRL, 115*0d09a60eSStanley.Yang S2A_DOORBELL_PORT4_ENABLE, 116*0d09a60eSStanley.Yang 0x1); 117*0d09a60eSStanley.Yang doorbell_range = REG_SET_FIELD(doorbell_range, 118*0d09a60eSStanley.Yang S2A_DOORBELL_ENTRY_4_CTRL, 119*0d09a60eSStanley.Yang S2A_DOORBELL_PORT4_AWID, 120*0d09a60eSStanley.Yang instance ? 0x7 : 0x4); 121*0d09a60eSStanley.Yang doorbell_range = REG_SET_FIELD(doorbell_range, 122*0d09a60eSStanley.Yang S2A_DOORBELL_ENTRY_4_CTRL, 123*0d09a60eSStanley.Yang S2A_DOORBELL_PORT4_RANGE_OFFSET, 124*0d09a60eSStanley.Yang doorbell_index); 125*0d09a60eSStanley.Yang doorbell_range = REG_SET_FIELD(doorbell_range, 126*0d09a60eSStanley.Yang S2A_DOORBELL_ENTRY_4_CTRL, 127*0d09a60eSStanley.Yang S2A_DOORBELL_PORT4_RANGE_SIZE, 128*0d09a60eSStanley.Yang 8); 129*0d09a60eSStanley.Yang doorbell_range = REG_SET_FIELD(doorbell_range, 130*0d09a60eSStanley.Yang S2A_DOORBELL_ENTRY_4_CTRL, 131*0d09a60eSStanley.Yang S2A_DOORBELL_PORT4_AWADDR_31_28_VALUE, 132*0d09a60eSStanley.Yang instance ? 0x7 : 0x4); 133*0d09a60eSStanley.Yang } else 134*0d09a60eSStanley.Yang doorbell_range = REG_SET_FIELD(doorbell_range, 135*0d09a60eSStanley.Yang S2A_DOORBELL_ENTRY_4_CTRL, 136*0d09a60eSStanley.Yang S2A_DOORBELL_PORT4_RANGE_SIZE, 137*0d09a60eSStanley.Yang 0); 138*0d09a60eSStanley.Yang 139*0d09a60eSStanley.Yang if (instance) 140*0d09a60eSStanley.Yang WREG32_SOC15(NBIO, 0, regS2A_DOORBELL_ENTRY_5_CTRL, doorbell_range); 141*0d09a60eSStanley.Yang else 142*0d09a60eSStanley.Yang WREG32_SOC15(NBIO, 0, regS2A_DOORBELL_ENTRY_4_CTRL, doorbell_range); 143*0d09a60eSStanley.Yang } 144*0d09a60eSStanley.Yang 145*0d09a60eSStanley.Yang static void nbio_v4_3_gc_doorbell_init(struct amdgpu_device *adev) 146*0d09a60eSStanley.Yang { 147*0d09a60eSStanley.Yang WREG32_SOC15(NBIO, 0, regS2A_DOORBELL_ENTRY_0_CTRL, 0x30000007); 148*0d09a60eSStanley.Yang WREG32_SOC15(NBIO, 0, regS2A_DOORBELL_ENTRY_3_CTRL, 0x3000000d); 149*0d09a60eSStanley.Yang } 150*0d09a60eSStanley.Yang 151*0d09a60eSStanley.Yang static void nbio_v4_3_enable_doorbell_aperture(struct amdgpu_device *adev, 152*0d09a60eSStanley.Yang bool enable) 153*0d09a60eSStanley.Yang { 154*0d09a60eSStanley.Yang WREG32_FIELD15_PREREG(NBIO, 0, RCC_DEV0_EPF0_RCC_DOORBELL_APER_EN, 155*0d09a60eSStanley.Yang BIF_DOORBELL_APER_EN, enable ? 1 : 0); 156*0d09a60eSStanley.Yang } 157*0d09a60eSStanley.Yang 158*0d09a60eSStanley.Yang static void nbio_v4_3_enable_doorbell_selfring_aperture(struct amdgpu_device *adev, 159*0d09a60eSStanley.Yang bool enable) 160*0d09a60eSStanley.Yang { 161*0d09a60eSStanley.Yang u32 tmp = 0; 162*0d09a60eSStanley.Yang 163*0d09a60eSStanley.Yang if (enable) { 164*0d09a60eSStanley.Yang tmp = REG_SET_FIELD(tmp, BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL, 165*0d09a60eSStanley.Yang DOORBELL_SELFRING_GPA_APER_EN, 1) | 166*0d09a60eSStanley.Yang REG_SET_FIELD(tmp, BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL, 167*0d09a60eSStanley.Yang DOORBELL_SELFRING_GPA_APER_MODE, 1) | 168*0d09a60eSStanley.Yang REG_SET_FIELD(tmp, BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL, 169*0d09a60eSStanley.Yang DOORBELL_SELFRING_GPA_APER_SIZE, 0); 170*0d09a60eSStanley.Yang 171*0d09a60eSStanley.Yang WREG32_SOC15(NBIO, 0, regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW, 172*0d09a60eSStanley.Yang lower_32_bits(adev->doorbell.base)); 173*0d09a60eSStanley.Yang WREG32_SOC15(NBIO, 0, regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH, 174*0d09a60eSStanley.Yang upper_32_bits(adev->doorbell.base)); 175*0d09a60eSStanley.Yang } 176*0d09a60eSStanley.Yang 177*0d09a60eSStanley.Yang WREG32_SOC15(NBIO, 0, regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL, 178*0d09a60eSStanley.Yang tmp); 179*0d09a60eSStanley.Yang } 180*0d09a60eSStanley.Yang 181*0d09a60eSStanley.Yang static void nbio_v4_3_ih_doorbell_range(struct amdgpu_device *adev, 182*0d09a60eSStanley.Yang bool use_doorbell, int doorbell_index) 183*0d09a60eSStanley.Yang { 184*0d09a60eSStanley.Yang u32 ih_doorbell_range = RREG32_SOC15(NBIO, 0, regS2A_DOORBELL_ENTRY_1_CTRL); 185*0d09a60eSStanley.Yang 186*0d09a60eSStanley.Yang if (use_doorbell) { 187*0d09a60eSStanley.Yang ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, 188*0d09a60eSStanley.Yang S2A_DOORBELL_ENTRY_1_CTRL, 189*0d09a60eSStanley.Yang S2A_DOORBELL_PORT1_ENABLE, 190*0d09a60eSStanley.Yang 0x1); 191*0d09a60eSStanley.Yang ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, 192*0d09a60eSStanley.Yang S2A_DOORBELL_ENTRY_1_CTRL, 193*0d09a60eSStanley.Yang S2A_DOORBELL_PORT1_AWID, 194*0d09a60eSStanley.Yang 0x0); 195*0d09a60eSStanley.Yang ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, 196*0d09a60eSStanley.Yang S2A_DOORBELL_ENTRY_1_CTRL, 197*0d09a60eSStanley.Yang S2A_DOORBELL_PORT1_RANGE_OFFSET, 198*0d09a60eSStanley.Yang doorbell_index); 199*0d09a60eSStanley.Yang ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, 200*0d09a60eSStanley.Yang S2A_DOORBELL_ENTRY_1_CTRL, 201*0d09a60eSStanley.Yang S2A_DOORBELL_PORT1_RANGE_SIZE, 202*0d09a60eSStanley.Yang 2); 203*0d09a60eSStanley.Yang ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, 204*0d09a60eSStanley.Yang S2A_DOORBELL_ENTRY_1_CTRL, 205*0d09a60eSStanley.Yang S2A_DOORBELL_PORT1_AWADDR_31_28_VALUE, 206*0d09a60eSStanley.Yang 0x0); 207*0d09a60eSStanley.Yang } else 208*0d09a60eSStanley.Yang ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, 209*0d09a60eSStanley.Yang S2A_DOORBELL_ENTRY_1_CTRL, 210*0d09a60eSStanley.Yang S2A_DOORBELL_PORT1_RANGE_SIZE, 211*0d09a60eSStanley.Yang 0); 212*0d09a60eSStanley.Yang 213*0d09a60eSStanley.Yang WREG32_SOC15(NBIO, 0, regS2A_DOORBELL_ENTRY_1_CTRL, ih_doorbell_range); 214*0d09a60eSStanley.Yang } 215*0d09a60eSStanley.Yang 216*0d09a60eSStanley.Yang static void nbio_v4_3_ih_control(struct amdgpu_device *adev) 217*0d09a60eSStanley.Yang { 218*0d09a60eSStanley.Yang u32 interrupt_cntl; 219*0d09a60eSStanley.Yang 220*0d09a60eSStanley.Yang /* setup interrupt control */ 221*0d09a60eSStanley.Yang WREG32_SOC15(NBIO, 0, regBIF_BX0_INTERRUPT_CNTL2, adev->dummy_page_addr >> 8); 222*0d09a60eSStanley.Yang 223*0d09a60eSStanley.Yang interrupt_cntl = RREG32_SOC15(NBIO, 0, regBIF_BX0_INTERRUPT_CNTL); 224*0d09a60eSStanley.Yang /* 225*0d09a60eSStanley.Yang * BIF_BX0_INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=0 - dummy read disabled with msi, enabled without msi 226*0d09a60eSStanley.Yang * BIF_BX0_INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=1 - dummy read controlled by IH_DUMMY_RD_EN 227*0d09a60eSStanley.Yang */ 228*0d09a60eSStanley.Yang interrupt_cntl = REG_SET_FIELD(interrupt_cntl, BIF_BX0_INTERRUPT_CNTL, 229*0d09a60eSStanley.Yang IH_DUMMY_RD_OVERRIDE, 0); 230*0d09a60eSStanley.Yang 231*0d09a60eSStanley.Yang /* BIF_BX0_INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN_MASK=1 if ring is in non-cacheable memory, e.g., vram */ 232*0d09a60eSStanley.Yang interrupt_cntl = REG_SET_FIELD(interrupt_cntl, BIF_BX0_INTERRUPT_CNTL, 233*0d09a60eSStanley.Yang IH_REQ_NONSNOOP_EN, 0); 234*0d09a60eSStanley.Yang 235*0d09a60eSStanley.Yang WREG32_SOC15(NBIO, 0, regBIF_BX0_INTERRUPT_CNTL, interrupt_cntl); 236*0d09a60eSStanley.Yang } 237*0d09a60eSStanley.Yang 238*0d09a60eSStanley.Yang static void nbio_v4_3_update_medium_grain_clock_gating(struct amdgpu_device *adev, 239*0d09a60eSStanley.Yang bool enable) 240*0d09a60eSStanley.Yang { 241*0d09a60eSStanley.Yang uint32_t def, data; 242*0d09a60eSStanley.Yang 243*0d09a60eSStanley.Yang def = data = RREG32_SOC15(NBIO, 0, regCPM_CONTROL); 244*0d09a60eSStanley.Yang if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_MGCG)) { 245*0d09a60eSStanley.Yang data |= (CPM_CONTROL__LCLK_DYN_GATE_ENABLE_MASK | 246*0d09a60eSStanley.Yang CPM_CONTROL__TXCLK_DYN_GATE_ENABLE_MASK | 247*0d09a60eSStanley.Yang CPM_CONTROL__TXCLK_LCNT_GATE_ENABLE_MASK | 248*0d09a60eSStanley.Yang CPM_CONTROL__TXCLK_REGS_GATE_ENABLE_MASK | 249*0d09a60eSStanley.Yang CPM_CONTROL__TXCLK_PRBS_GATE_ENABLE_MASK | 250*0d09a60eSStanley.Yang CPM_CONTROL__REFCLK_REGS_GATE_ENABLE_MASK); 251*0d09a60eSStanley.Yang } else { 252*0d09a60eSStanley.Yang data &= ~(CPM_CONTROL__LCLK_DYN_GATE_ENABLE_MASK | 253*0d09a60eSStanley.Yang CPM_CONTROL__TXCLK_DYN_GATE_ENABLE_MASK | 254*0d09a60eSStanley.Yang CPM_CONTROL__TXCLK_LCNT_GATE_ENABLE_MASK | 255*0d09a60eSStanley.Yang CPM_CONTROL__TXCLK_REGS_GATE_ENABLE_MASK | 256*0d09a60eSStanley.Yang CPM_CONTROL__TXCLK_PRBS_GATE_ENABLE_MASK | 257*0d09a60eSStanley.Yang CPM_CONTROL__REFCLK_REGS_GATE_ENABLE_MASK); 258*0d09a60eSStanley.Yang } 259*0d09a60eSStanley.Yang 260*0d09a60eSStanley.Yang if (def != data) 261*0d09a60eSStanley.Yang WREG32_SOC15(NBIO, 0, regCPM_CONTROL, data); 262*0d09a60eSStanley.Yang } 263*0d09a60eSStanley.Yang 264*0d09a60eSStanley.Yang static void nbio_v4_3_update_medium_grain_light_sleep(struct amdgpu_device *adev, 265*0d09a60eSStanley.Yang bool enable) 266*0d09a60eSStanley.Yang { 267*0d09a60eSStanley.Yang uint32_t def, data; 268*0d09a60eSStanley.Yang 269*0d09a60eSStanley.Yang /* TODO: need update in future */ 270*0d09a60eSStanley.Yang def = data = RREG32_SOC15(NBIO, 0, regPCIE_CNTL2); 271*0d09a60eSStanley.Yang if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_LS)) { 272*0d09a60eSStanley.Yang data |= PCIE_CNTL2__SLV_MEM_LS_EN_MASK; 273*0d09a60eSStanley.Yang } else { 274*0d09a60eSStanley.Yang data &= ~PCIE_CNTL2__SLV_MEM_LS_EN_MASK; 275*0d09a60eSStanley.Yang } 276*0d09a60eSStanley.Yang 277*0d09a60eSStanley.Yang if (def != data) 278*0d09a60eSStanley.Yang WREG32_SOC15(NBIO, 0, regPCIE_CNTL2, data); 279*0d09a60eSStanley.Yang } 280*0d09a60eSStanley.Yang 281*0d09a60eSStanley.Yang static void nbio_v4_3_get_clockgating_state(struct amdgpu_device *adev, 282*0d09a60eSStanley.Yang u64 *flags) 283*0d09a60eSStanley.Yang { 284*0d09a60eSStanley.Yang int data; 285*0d09a60eSStanley.Yang 286*0d09a60eSStanley.Yang /* AMD_CG_SUPPORT_BIF_MGCG */ 287*0d09a60eSStanley.Yang data = RREG32_SOC15(NBIO, 0, regCPM_CONTROL); 288*0d09a60eSStanley.Yang if (data & CPM_CONTROL__LCLK_DYN_GATE_ENABLE_MASK) 289*0d09a60eSStanley.Yang *flags |= AMD_CG_SUPPORT_BIF_MGCG; 290*0d09a60eSStanley.Yang 291*0d09a60eSStanley.Yang /* AMD_CG_SUPPORT_BIF_LS */ 292*0d09a60eSStanley.Yang data = RREG32_SOC15(NBIO, 0, regPCIE_CNTL2); 293*0d09a60eSStanley.Yang if (data & PCIE_CNTL2__SLV_MEM_LS_EN_MASK) 294*0d09a60eSStanley.Yang *flags |= AMD_CG_SUPPORT_BIF_LS; 295*0d09a60eSStanley.Yang } 296*0d09a60eSStanley.Yang 297*0d09a60eSStanley.Yang static u32 nbio_v4_3_get_hdp_flush_req_offset(struct amdgpu_device *adev) 298*0d09a60eSStanley.Yang { 299*0d09a60eSStanley.Yang return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX_PF0_GPU_HDP_FLUSH_REQ); 300*0d09a60eSStanley.Yang } 301*0d09a60eSStanley.Yang 302*0d09a60eSStanley.Yang static u32 nbio_v4_3_get_hdp_flush_done_offset(struct amdgpu_device *adev) 303*0d09a60eSStanley.Yang { 304*0d09a60eSStanley.Yang return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX_PF0_GPU_HDP_FLUSH_DONE); 305*0d09a60eSStanley.Yang } 306*0d09a60eSStanley.Yang 307*0d09a60eSStanley.Yang static u32 nbio_v4_3_get_pcie_index_offset(struct amdgpu_device *adev) 308*0d09a60eSStanley.Yang { 309*0d09a60eSStanley.Yang return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX_PF0_RSMU_INDEX); 310*0d09a60eSStanley.Yang } 311*0d09a60eSStanley.Yang 312*0d09a60eSStanley.Yang static u32 nbio_v4_3_get_pcie_data_offset(struct amdgpu_device *adev) 313*0d09a60eSStanley.Yang { 314*0d09a60eSStanley.Yang return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX_PF0_RSMU_DATA); 315*0d09a60eSStanley.Yang } 316*0d09a60eSStanley.Yang 317*0d09a60eSStanley.Yang const struct nbio_hdp_flush_reg nbio_v4_3_hdp_flush_reg = { 318*0d09a60eSStanley.Yang .ref_and_mask_cp0 = BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP0_MASK, 319*0d09a60eSStanley.Yang .ref_and_mask_cp1 = BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP1_MASK, 320*0d09a60eSStanley.Yang .ref_and_mask_cp2 = BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP2_MASK, 321*0d09a60eSStanley.Yang .ref_and_mask_cp3 = BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP3_MASK, 322*0d09a60eSStanley.Yang .ref_and_mask_cp4 = BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP4_MASK, 323*0d09a60eSStanley.Yang .ref_and_mask_cp5 = BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP5_MASK, 324*0d09a60eSStanley.Yang .ref_and_mask_cp6 = BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP6_MASK, 325*0d09a60eSStanley.Yang .ref_and_mask_cp7 = BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP7_MASK, 326*0d09a60eSStanley.Yang .ref_and_mask_cp8 = BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP8_MASK, 327*0d09a60eSStanley.Yang .ref_and_mask_cp9 = BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP9_MASK, 328*0d09a60eSStanley.Yang .ref_and_mask_sdma0 = BIF_BX_PF_GPU_HDP_FLUSH_DONE__SDMA0_MASK, 329*0d09a60eSStanley.Yang .ref_and_mask_sdma1 = BIF_BX_PF_GPU_HDP_FLUSH_DONE__SDMA1_MASK, 330*0d09a60eSStanley.Yang }; 331*0d09a60eSStanley.Yang 332*0d09a60eSStanley.Yang static void nbio_v4_3_init_registers(struct amdgpu_device *adev) 333*0d09a60eSStanley.Yang { 334*0d09a60eSStanley.Yang return; 335*0d09a60eSStanley.Yang } 336*0d09a60eSStanley.Yang 337*0d09a60eSStanley.Yang static u32 nbio_v4_3_get_rom_offset(struct amdgpu_device *adev) 338*0d09a60eSStanley.Yang { 339*0d09a60eSStanley.Yang u32 data, rom_offset; 340*0d09a60eSStanley.Yang 341*0d09a60eSStanley.Yang data = RREG32_SOC15(NBIO, 0, regREGS_ROM_OFFSET_CTRL); 342*0d09a60eSStanley.Yang rom_offset = REG_GET_FIELD(data, REGS_ROM_OFFSET_CTRL, ROM_OFFSET); 343*0d09a60eSStanley.Yang 344*0d09a60eSStanley.Yang return rom_offset; 345*0d09a60eSStanley.Yang } 346*0d09a60eSStanley.Yang 347*0d09a60eSStanley.Yang const struct amdgpu_nbio_funcs nbio_v4_3_funcs = { 348*0d09a60eSStanley.Yang .get_hdp_flush_req_offset = nbio_v4_3_get_hdp_flush_req_offset, 349*0d09a60eSStanley.Yang .get_hdp_flush_done_offset = nbio_v4_3_get_hdp_flush_done_offset, 350*0d09a60eSStanley.Yang .get_pcie_index_offset = nbio_v4_3_get_pcie_index_offset, 351*0d09a60eSStanley.Yang .get_pcie_data_offset = nbio_v4_3_get_pcie_data_offset, 352*0d09a60eSStanley.Yang .get_rev_id = nbio_v4_3_get_rev_id, 353*0d09a60eSStanley.Yang .mc_access_enable = nbio_v4_3_mc_access_enable, 354*0d09a60eSStanley.Yang .get_memsize = nbio_v4_3_get_memsize, 355*0d09a60eSStanley.Yang .sdma_doorbell_range = nbio_v4_3_sdma_doorbell_range, 356*0d09a60eSStanley.Yang .vcn_doorbell_range = nbio_v4_3_vcn_doorbell_range, 357*0d09a60eSStanley.Yang .gc_doorbell_init = nbio_v4_3_gc_doorbell_init, 358*0d09a60eSStanley.Yang .enable_doorbell_aperture = nbio_v4_3_enable_doorbell_aperture, 359*0d09a60eSStanley.Yang .enable_doorbell_selfring_aperture = nbio_v4_3_enable_doorbell_selfring_aperture, 360*0d09a60eSStanley.Yang .ih_doorbell_range = nbio_v4_3_ih_doorbell_range, 361*0d09a60eSStanley.Yang .update_medium_grain_clock_gating = nbio_v4_3_update_medium_grain_clock_gating, 362*0d09a60eSStanley.Yang .update_medium_grain_light_sleep = nbio_v4_3_update_medium_grain_light_sleep, 363*0d09a60eSStanley.Yang .get_clockgating_state = nbio_v4_3_get_clockgating_state, 364*0d09a60eSStanley.Yang .ih_control = nbio_v4_3_ih_control, 365*0d09a60eSStanley.Yang .init_registers = nbio_v4_3_init_registers, 366*0d09a60eSStanley.Yang .remap_hdp_registers = nbio_v4_3_remap_hdp_registers, 367*0d09a60eSStanley.Yang .get_rom_offset = nbio_v4_3_get_rom_offset, 368*0d09a60eSStanley.Yang }; 369