1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include "amdgpu.h" 24 #include "amdgpu_atombios.h" 25 #include "nbio_v2_3.h" 26 27 #include "nbio/nbio_2_3_default.h" 28 #include "nbio/nbio_2_3_offset.h" 29 #include "nbio/nbio_2_3_sh_mask.h" 30 #include <uapi/linux/kfd_ioctl.h> 31 #include <linux/pci.h> 32 33 #define smnPCIE_CONFIG_CNTL 0x11180044 34 #define smnCPM_CONTROL 0x11180460 35 #define smnPCIE_CNTL2 0x11180070 36 #define smnPCIE_LC_CNTL 0x11140280 37 38 #define mmBIF_SDMA2_DOORBELL_RANGE 0x01d6 39 #define mmBIF_SDMA2_DOORBELL_RANGE_BASE_IDX 2 40 #define mmBIF_SDMA3_DOORBELL_RANGE 0x01d7 41 #define mmBIF_SDMA3_DOORBELL_RANGE_BASE_IDX 2 42 43 #define mmBIF_MMSCH1_DOORBELL_RANGE 0x01d8 44 #define mmBIF_MMSCH1_DOORBELL_RANGE_BASE_IDX 2 45 46 static void nbio_v2_3_remap_hdp_registers(struct amdgpu_device *adev) 47 { 48 WREG32_SOC15(NBIO, 0, mmREMAP_HDP_MEM_FLUSH_CNTL, 49 adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL); 50 WREG32_SOC15(NBIO, 0, mmREMAP_HDP_REG_FLUSH_CNTL, 51 adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_REG_FLUSH_CNTL); 52 } 53 54 static u32 nbio_v2_3_get_rev_id(struct amdgpu_device *adev) 55 { 56 u32 tmp; 57 58 /* 59 * guest vm gets 0xffffffff when reading RCC_DEV0_EPF0_STRAP0, 60 * therefore we force rev_id to 0 (which is the default value) 61 */ 62 if (amdgpu_sriov_vf(adev)) { 63 return 0; 64 } 65 66 tmp = RREG32_SOC15(NBIO, 0, mmRCC_DEV0_EPF0_STRAP0); 67 tmp &= RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0_MASK; 68 tmp >>= RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0__SHIFT; 69 70 return tmp; 71 } 72 73 static void nbio_v2_3_mc_access_enable(struct amdgpu_device *adev, bool enable) 74 { 75 if (enable) 76 WREG32_SOC15(NBIO, 0, mmBIF_FB_EN, 77 BIF_FB_EN__FB_READ_EN_MASK | 78 BIF_FB_EN__FB_WRITE_EN_MASK); 79 else 80 WREG32_SOC15(NBIO, 0, mmBIF_FB_EN, 0); 81 } 82 83 static u32 nbio_v2_3_get_memsize(struct amdgpu_device *adev) 84 { 85 return RREG32_SOC15(NBIO, 0, mmRCC_DEV0_EPF0_RCC_CONFIG_MEMSIZE); 86 } 87 88 static void nbio_v2_3_sdma_doorbell_range(struct amdgpu_device *adev, int instance, 89 bool use_doorbell, int doorbell_index, 90 int doorbell_size) 91 { 92 u32 reg = instance == 0 ? SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA0_DOORBELL_RANGE) : 93 instance == 1 ? SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA1_DOORBELL_RANGE) : 94 instance == 2 ? SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA2_DOORBELL_RANGE) : 95 SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA3_DOORBELL_RANGE); 96 97 u32 doorbell_range = RREG32(reg); 98 99 if (use_doorbell) { 100 doorbell_range = REG_SET_FIELD(doorbell_range, 101 BIF_SDMA0_DOORBELL_RANGE, OFFSET, 102 doorbell_index); 103 doorbell_range = REG_SET_FIELD(doorbell_range, 104 BIF_SDMA0_DOORBELL_RANGE, SIZE, 105 doorbell_size); 106 } else 107 doorbell_range = REG_SET_FIELD(doorbell_range, 108 BIF_SDMA0_DOORBELL_RANGE, SIZE, 109 0); 110 111 WREG32(reg, doorbell_range); 112 } 113 114 static void nbio_v2_3_vcn_doorbell_range(struct amdgpu_device *adev, bool use_doorbell, 115 int doorbell_index, int instance) 116 { 117 u32 reg = instance ? SOC15_REG_OFFSET(NBIO, 0, mmBIF_MMSCH1_DOORBELL_RANGE) : 118 SOC15_REG_OFFSET(NBIO, 0, mmBIF_MMSCH0_DOORBELL_RANGE); 119 120 u32 doorbell_range = RREG32(reg); 121 122 if (use_doorbell) { 123 doorbell_range = REG_SET_FIELD(doorbell_range, 124 BIF_MMSCH0_DOORBELL_RANGE, OFFSET, 125 doorbell_index); 126 doorbell_range = REG_SET_FIELD(doorbell_range, 127 BIF_MMSCH0_DOORBELL_RANGE, SIZE, 8); 128 } else 129 doorbell_range = REG_SET_FIELD(doorbell_range, 130 BIF_MMSCH0_DOORBELL_RANGE, SIZE, 0); 131 132 WREG32(reg, doorbell_range); 133 } 134 135 static void nbio_v2_3_enable_doorbell_aperture(struct amdgpu_device *adev, 136 bool enable) 137 { 138 WREG32_FIELD15(NBIO, 0, RCC_DEV0_EPF0_RCC_DOORBELL_APER_EN, BIF_DOORBELL_APER_EN, 139 enable ? 1 : 0); 140 } 141 142 static void nbio_v2_3_enable_doorbell_selfring_aperture(struct amdgpu_device *adev, 143 bool enable) 144 { 145 u32 tmp = 0; 146 147 if (enable) { 148 tmp = REG_SET_FIELD(tmp, BIF_BX_PF_DOORBELL_SELFRING_GPA_APER_CNTL, 149 DOORBELL_SELFRING_GPA_APER_EN, 1) | 150 REG_SET_FIELD(tmp, BIF_BX_PF_DOORBELL_SELFRING_GPA_APER_CNTL, 151 DOORBELL_SELFRING_GPA_APER_MODE, 1) | 152 REG_SET_FIELD(tmp, BIF_BX_PF_DOORBELL_SELFRING_GPA_APER_CNTL, 153 DOORBELL_SELFRING_GPA_APER_SIZE, 0); 154 155 WREG32_SOC15(NBIO, 0, mmBIF_BX_PF_DOORBELL_SELFRING_GPA_APER_BASE_LOW, 156 lower_32_bits(adev->doorbell.base)); 157 WREG32_SOC15(NBIO, 0, mmBIF_BX_PF_DOORBELL_SELFRING_GPA_APER_BASE_HIGH, 158 upper_32_bits(adev->doorbell.base)); 159 } 160 161 WREG32_SOC15(NBIO, 0, mmBIF_BX_PF_DOORBELL_SELFRING_GPA_APER_CNTL, 162 tmp); 163 } 164 165 166 static void nbio_v2_3_ih_doorbell_range(struct amdgpu_device *adev, 167 bool use_doorbell, int doorbell_index) 168 { 169 u32 ih_doorbell_range = RREG32_SOC15(NBIO, 0, mmBIF_IH_DOORBELL_RANGE); 170 171 if (use_doorbell) { 172 ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, 173 BIF_IH_DOORBELL_RANGE, OFFSET, 174 doorbell_index); 175 ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, 176 BIF_IH_DOORBELL_RANGE, SIZE, 177 2); 178 } else 179 ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, 180 BIF_IH_DOORBELL_RANGE, SIZE, 181 0); 182 183 WREG32_SOC15(NBIO, 0, mmBIF_IH_DOORBELL_RANGE, ih_doorbell_range); 184 } 185 186 static void nbio_v2_3_ih_control(struct amdgpu_device *adev) 187 { 188 u32 interrupt_cntl; 189 190 /* setup interrupt control */ 191 WREG32_SOC15(NBIO, 0, mmINTERRUPT_CNTL2, adev->dummy_page_addr >> 8); 192 193 interrupt_cntl = RREG32_SOC15(NBIO, 0, mmINTERRUPT_CNTL); 194 /* 195 * INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=0 - dummy read disabled with msi, enabled without msi 196 * INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=1 - dummy read controlled by IH_DUMMY_RD_EN 197 */ 198 interrupt_cntl = REG_SET_FIELD(interrupt_cntl, INTERRUPT_CNTL, 199 IH_DUMMY_RD_OVERRIDE, 0); 200 201 /* INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN_MASK=1 if ring is in non-cacheable memory, e.g., vram */ 202 interrupt_cntl = REG_SET_FIELD(interrupt_cntl, INTERRUPT_CNTL, 203 IH_REQ_NONSNOOP_EN, 0); 204 205 WREG32_SOC15(NBIO, 0, mmINTERRUPT_CNTL, interrupt_cntl); 206 } 207 208 static void nbio_v2_3_update_medium_grain_clock_gating(struct amdgpu_device *adev, 209 bool enable) 210 { 211 uint32_t def, data; 212 213 def = data = RREG32_PCIE(smnCPM_CONTROL); 214 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_MGCG)) { 215 data |= (CPM_CONTROL__LCLK_DYN_GATE_ENABLE_MASK | 216 CPM_CONTROL__TXCLK_DYN_GATE_ENABLE_MASK | 217 CPM_CONTROL__TXCLK_LCNT_GATE_ENABLE_MASK | 218 CPM_CONTROL__TXCLK_REGS_GATE_ENABLE_MASK | 219 CPM_CONTROL__TXCLK_PRBS_GATE_ENABLE_MASK | 220 CPM_CONTROL__REFCLK_REGS_GATE_ENABLE_MASK); 221 } else { 222 data &= ~(CPM_CONTROL__LCLK_DYN_GATE_ENABLE_MASK | 223 CPM_CONTROL__TXCLK_DYN_GATE_ENABLE_MASK | 224 CPM_CONTROL__TXCLK_LCNT_GATE_ENABLE_MASK | 225 CPM_CONTROL__TXCLK_REGS_GATE_ENABLE_MASK | 226 CPM_CONTROL__TXCLK_PRBS_GATE_ENABLE_MASK | 227 CPM_CONTROL__REFCLK_REGS_GATE_ENABLE_MASK); 228 } 229 230 if (def != data) 231 WREG32_PCIE(smnCPM_CONTROL, data); 232 } 233 234 static void nbio_v2_3_update_medium_grain_light_sleep(struct amdgpu_device *adev, 235 bool enable) 236 { 237 uint32_t def, data; 238 239 def = data = RREG32_PCIE(smnPCIE_CNTL2); 240 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_LS)) { 241 data |= (PCIE_CNTL2__SLV_MEM_LS_EN_MASK | 242 PCIE_CNTL2__MST_MEM_LS_EN_MASK | 243 PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK); 244 } else { 245 data &= ~(PCIE_CNTL2__SLV_MEM_LS_EN_MASK | 246 PCIE_CNTL2__MST_MEM_LS_EN_MASK | 247 PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK); 248 } 249 250 if (def != data) 251 WREG32_PCIE(smnPCIE_CNTL2, data); 252 } 253 254 static void nbio_v2_3_get_clockgating_state(struct amdgpu_device *adev, 255 u32 *flags) 256 { 257 int data; 258 259 /* AMD_CG_SUPPORT_BIF_MGCG */ 260 data = RREG32_PCIE(smnCPM_CONTROL); 261 if (data & CPM_CONTROL__LCLK_DYN_GATE_ENABLE_MASK) 262 *flags |= AMD_CG_SUPPORT_BIF_MGCG; 263 264 /* AMD_CG_SUPPORT_BIF_LS */ 265 data = RREG32_PCIE(smnPCIE_CNTL2); 266 if (data & PCIE_CNTL2__SLV_MEM_LS_EN_MASK) 267 *flags |= AMD_CG_SUPPORT_BIF_LS; 268 } 269 270 static u32 nbio_v2_3_get_hdp_flush_req_offset(struct amdgpu_device *adev) 271 { 272 return SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF_GPU_HDP_FLUSH_REQ); 273 } 274 275 static u32 nbio_v2_3_get_hdp_flush_done_offset(struct amdgpu_device *adev) 276 { 277 return SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF_GPU_HDP_FLUSH_DONE); 278 } 279 280 static u32 nbio_v2_3_get_pcie_index_offset(struct amdgpu_device *adev) 281 { 282 return SOC15_REG_OFFSET(NBIO, 0, mmPCIE_INDEX2); 283 } 284 285 static u32 nbio_v2_3_get_pcie_data_offset(struct amdgpu_device *adev) 286 { 287 return SOC15_REG_OFFSET(NBIO, 0, mmPCIE_DATA2); 288 } 289 290 const struct nbio_hdp_flush_reg nbio_v2_3_hdp_flush_reg = { 291 .ref_and_mask_cp0 = BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP0_MASK, 292 .ref_and_mask_cp1 = BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP1_MASK, 293 .ref_and_mask_cp2 = BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP2_MASK, 294 .ref_and_mask_cp3 = BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP3_MASK, 295 .ref_and_mask_cp4 = BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP4_MASK, 296 .ref_and_mask_cp5 = BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP5_MASK, 297 .ref_and_mask_cp6 = BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP6_MASK, 298 .ref_and_mask_cp7 = BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP7_MASK, 299 .ref_and_mask_cp8 = BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP8_MASK, 300 .ref_and_mask_cp9 = BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP9_MASK, 301 .ref_and_mask_sdma0 = BIF_BX_PF_GPU_HDP_FLUSH_DONE__SDMA0_MASK, 302 .ref_and_mask_sdma1 = BIF_BX_PF_GPU_HDP_FLUSH_DONE__SDMA1_MASK, 303 }; 304 305 static void nbio_v2_3_init_registers(struct amdgpu_device *adev) 306 { 307 uint32_t def, data; 308 309 def = data = RREG32_PCIE(smnPCIE_CONFIG_CNTL); 310 data = REG_SET_FIELD(data, PCIE_CONFIG_CNTL, CI_SWUS_MAX_READ_REQUEST_SIZE_MODE, 1); 311 data = REG_SET_FIELD(data, PCIE_CONFIG_CNTL, CI_SWUS_MAX_READ_REQUEST_SIZE_PRIV, 1); 312 313 if (def != data) 314 WREG32_PCIE(smnPCIE_CONFIG_CNTL, data); 315 } 316 317 #define NAVI10_PCIE__LC_L0S_INACTIVITY_DEFAULT 0x00000000 // off by default, no gains over L1 318 #define NAVI10_PCIE__LC_L1_INACTIVITY_DEFAULT 0x00000009 // 1=1us, 9=1ms 319 #define NAVI10_PCIE__LC_L1_INACTIVITY_TBT_DEFAULT 0x0000000E // 4ms 320 321 static void nbio_v2_3_enable_aspm(struct amdgpu_device *adev, 322 bool enable) 323 { 324 uint32_t def, data; 325 326 def = data = RREG32_PCIE(smnPCIE_LC_CNTL); 327 328 if (enable) { 329 /* Disable ASPM L0s/L1 first */ 330 data &= ~(PCIE_LC_CNTL__LC_L0S_INACTIVITY_MASK | PCIE_LC_CNTL__LC_L1_INACTIVITY_MASK); 331 332 data |= NAVI10_PCIE__LC_L0S_INACTIVITY_DEFAULT << PCIE_LC_CNTL__LC_L0S_INACTIVITY__SHIFT; 333 334 if (pci_is_thunderbolt_attached(adev->pdev)) 335 data |= NAVI10_PCIE__LC_L1_INACTIVITY_TBT_DEFAULT << PCIE_LC_CNTL__LC_L1_INACTIVITY__SHIFT; 336 else 337 data |= NAVI10_PCIE__LC_L1_INACTIVITY_DEFAULT << PCIE_LC_CNTL__LC_L1_INACTIVITY__SHIFT; 338 339 data &= ~PCIE_LC_CNTL__LC_PMI_TO_L1_DIS_MASK; 340 } else { 341 /* Disbale ASPM L1 */ 342 data &= ~PCIE_LC_CNTL__LC_L1_INACTIVITY_MASK; 343 /* Disable ASPM TxL0s */ 344 data &= ~PCIE_LC_CNTL__LC_L0S_INACTIVITY_MASK; 345 /* Disable ACPI L1 */ 346 data |= PCIE_LC_CNTL__LC_PMI_TO_L1_DIS_MASK; 347 } 348 349 if (def != data) 350 WREG32_PCIE(smnPCIE_LC_CNTL, data); 351 } 352 353 const struct amdgpu_nbio_funcs nbio_v2_3_funcs = { 354 .get_hdp_flush_req_offset = nbio_v2_3_get_hdp_flush_req_offset, 355 .get_hdp_flush_done_offset = nbio_v2_3_get_hdp_flush_done_offset, 356 .get_pcie_index_offset = nbio_v2_3_get_pcie_index_offset, 357 .get_pcie_data_offset = nbio_v2_3_get_pcie_data_offset, 358 .get_rev_id = nbio_v2_3_get_rev_id, 359 .mc_access_enable = nbio_v2_3_mc_access_enable, 360 .get_memsize = nbio_v2_3_get_memsize, 361 .sdma_doorbell_range = nbio_v2_3_sdma_doorbell_range, 362 .vcn_doorbell_range = nbio_v2_3_vcn_doorbell_range, 363 .enable_doorbell_aperture = nbio_v2_3_enable_doorbell_aperture, 364 .enable_doorbell_selfring_aperture = nbio_v2_3_enable_doorbell_selfring_aperture, 365 .ih_doorbell_range = nbio_v2_3_ih_doorbell_range, 366 .update_medium_grain_clock_gating = nbio_v2_3_update_medium_grain_clock_gating, 367 .update_medium_grain_light_sleep = nbio_v2_3_update_medium_grain_light_sleep, 368 .get_clockgating_state = nbio_v2_3_get_clockgating_state, 369 .ih_control = nbio_v2_3_ih_control, 370 .init_registers = nbio_v2_3_init_registers, 371 .remap_hdp_registers = nbio_v2_3_remap_hdp_registers, 372 .enable_aspm = nbio_v2_3_enable_aspm, 373 }; 374