1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include "amdgpu.h" 24 #include "amdgpu_atombios.h" 25 #include "nbio_v2_3.h" 26 27 #include "nbio/nbio_2_3_default.h" 28 #include "nbio/nbio_2_3_offset.h" 29 #include "nbio/nbio_2_3_sh_mask.h" 30 #include <uapi/linux/kfd_ioctl.h> 31 32 #define smnPCIE_CONFIG_CNTL 0x11180044 33 #define smnCPM_CONTROL 0x11180460 34 #define smnPCIE_CNTL2 0x11180070 35 36 37 static void nbio_v2_3_remap_hdp_registers(struct amdgpu_device *adev) 38 { 39 WREG32_SOC15(NBIO, 0, mmREMAP_HDP_MEM_FLUSH_CNTL, 40 adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL); 41 WREG32_SOC15(NBIO, 0, mmREMAP_HDP_REG_FLUSH_CNTL, 42 adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_REG_FLUSH_CNTL); 43 } 44 45 static u32 nbio_v2_3_get_rev_id(struct amdgpu_device *adev) 46 { 47 u32 tmp = RREG32_SOC15(NBIO, 0, mmRCC_DEV0_EPF0_STRAP0); 48 49 tmp &= RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0_MASK; 50 tmp >>= RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0__SHIFT; 51 52 return tmp; 53 } 54 55 static void nbio_v2_3_mc_access_enable(struct amdgpu_device *adev, bool enable) 56 { 57 if (enable) 58 WREG32_SOC15(NBIO, 0, mmBIF_FB_EN, 59 BIF_FB_EN__FB_READ_EN_MASK | 60 BIF_FB_EN__FB_WRITE_EN_MASK); 61 else 62 WREG32_SOC15(NBIO, 0, mmBIF_FB_EN, 0); 63 } 64 65 static void nbio_v2_3_hdp_flush(struct amdgpu_device *adev, 66 struct amdgpu_ring *ring) 67 { 68 if (!ring || !ring->funcs->emit_wreg) 69 WREG32_NO_KIQ((adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2, 0); 70 else 71 amdgpu_ring_emit_wreg(ring, (adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2, 0); 72 } 73 74 static u32 nbio_v2_3_get_memsize(struct amdgpu_device *adev) 75 { 76 return RREG32_SOC15(NBIO, 0, mmRCC_DEV0_EPF0_RCC_CONFIG_MEMSIZE); 77 } 78 79 static void nbio_v2_3_sdma_doorbell_range(struct amdgpu_device *adev, int instance, 80 bool use_doorbell, int doorbell_index, 81 int doorbell_size) 82 { 83 u32 reg = instance == 0 ? SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA0_DOORBELL_RANGE) : 84 SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA1_DOORBELL_RANGE); 85 86 u32 doorbell_range = RREG32(reg); 87 88 if (use_doorbell) { 89 doorbell_range = REG_SET_FIELD(doorbell_range, 90 BIF_SDMA0_DOORBELL_RANGE, OFFSET, 91 doorbell_index); 92 doorbell_range = REG_SET_FIELD(doorbell_range, 93 BIF_SDMA0_DOORBELL_RANGE, SIZE, 94 doorbell_size); 95 } else 96 doorbell_range = REG_SET_FIELD(doorbell_range, 97 BIF_SDMA0_DOORBELL_RANGE, SIZE, 98 0); 99 100 WREG32(reg, doorbell_range); 101 } 102 103 static void nbio_v2_3_vcn_doorbell_range(struct amdgpu_device *adev, bool use_doorbell, 104 int doorbell_index, int instance) 105 { 106 u32 reg = SOC15_REG_OFFSET(NBIO, 0, mmBIF_MMSCH0_DOORBELL_RANGE); 107 108 u32 doorbell_range = RREG32(reg); 109 110 if (use_doorbell) { 111 doorbell_range = REG_SET_FIELD(doorbell_range, 112 BIF_MMSCH0_DOORBELL_RANGE, OFFSET, 113 doorbell_index); 114 doorbell_range = REG_SET_FIELD(doorbell_range, 115 BIF_MMSCH0_DOORBELL_RANGE, SIZE, 8); 116 } else 117 doorbell_range = REG_SET_FIELD(doorbell_range, 118 BIF_MMSCH0_DOORBELL_RANGE, SIZE, 0); 119 120 WREG32(reg, doorbell_range); 121 } 122 123 static void nbio_v2_3_enable_doorbell_aperture(struct amdgpu_device *adev, 124 bool enable) 125 { 126 WREG32_FIELD15(NBIO, 0, RCC_DEV0_EPF0_RCC_DOORBELL_APER_EN, BIF_DOORBELL_APER_EN, 127 enable ? 1 : 0); 128 } 129 130 static void nbio_v2_3_enable_doorbell_selfring_aperture(struct amdgpu_device *adev, 131 bool enable) 132 { 133 u32 tmp = 0; 134 135 if (enable) { 136 tmp = REG_SET_FIELD(tmp, BIF_BX_PF_DOORBELL_SELFRING_GPA_APER_CNTL, 137 DOORBELL_SELFRING_GPA_APER_EN, 1) | 138 REG_SET_FIELD(tmp, BIF_BX_PF_DOORBELL_SELFRING_GPA_APER_CNTL, 139 DOORBELL_SELFRING_GPA_APER_MODE, 1) | 140 REG_SET_FIELD(tmp, BIF_BX_PF_DOORBELL_SELFRING_GPA_APER_CNTL, 141 DOORBELL_SELFRING_GPA_APER_SIZE, 0); 142 143 WREG32_SOC15(NBIO, 0, mmBIF_BX_PF_DOORBELL_SELFRING_GPA_APER_BASE_LOW, 144 lower_32_bits(adev->doorbell.base)); 145 WREG32_SOC15(NBIO, 0, mmBIF_BX_PF_DOORBELL_SELFRING_GPA_APER_BASE_HIGH, 146 upper_32_bits(adev->doorbell.base)); 147 } 148 149 WREG32_SOC15(NBIO, 0, mmBIF_BX_PF_DOORBELL_SELFRING_GPA_APER_CNTL, 150 tmp); 151 } 152 153 154 static void nbio_v2_3_ih_doorbell_range(struct amdgpu_device *adev, 155 bool use_doorbell, int doorbell_index) 156 { 157 u32 ih_doorbell_range = RREG32_SOC15(NBIO, 0, mmBIF_IH_DOORBELL_RANGE); 158 159 if (use_doorbell) { 160 ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, 161 BIF_IH_DOORBELL_RANGE, OFFSET, 162 doorbell_index); 163 ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, 164 BIF_IH_DOORBELL_RANGE, SIZE, 165 2); 166 } else 167 ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, 168 BIF_IH_DOORBELL_RANGE, SIZE, 169 0); 170 171 WREG32_SOC15(NBIO, 0, mmBIF_IH_DOORBELL_RANGE, ih_doorbell_range); 172 } 173 174 static void nbio_v2_3_ih_control(struct amdgpu_device *adev) 175 { 176 u32 interrupt_cntl; 177 178 /* setup interrupt control */ 179 WREG32_SOC15(NBIO, 0, mmINTERRUPT_CNTL2, adev->dummy_page_addr >> 8); 180 181 interrupt_cntl = RREG32_SOC15(NBIO, 0, mmINTERRUPT_CNTL); 182 /* 183 * INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=0 - dummy read disabled with msi, enabled without msi 184 * INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=1 - dummy read controlled by IH_DUMMY_RD_EN 185 */ 186 interrupt_cntl = REG_SET_FIELD(interrupt_cntl, INTERRUPT_CNTL, 187 IH_DUMMY_RD_OVERRIDE, 0); 188 189 /* INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN_MASK=1 if ring is in non-cacheable memory, e.g., vram */ 190 interrupt_cntl = REG_SET_FIELD(interrupt_cntl, INTERRUPT_CNTL, 191 IH_REQ_NONSNOOP_EN, 0); 192 193 WREG32_SOC15(NBIO, 0, mmINTERRUPT_CNTL, interrupt_cntl); 194 } 195 196 static void nbio_v2_3_update_medium_grain_clock_gating(struct amdgpu_device *adev, 197 bool enable) 198 { 199 uint32_t def, data; 200 201 def = data = RREG32_PCIE(smnCPM_CONTROL); 202 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_MGCG)) { 203 data |= (CPM_CONTROL__LCLK_DYN_GATE_ENABLE_MASK | 204 CPM_CONTROL__TXCLK_DYN_GATE_ENABLE_MASK | 205 CPM_CONTROL__TXCLK_LCNT_GATE_ENABLE_MASK | 206 CPM_CONTROL__TXCLK_REGS_GATE_ENABLE_MASK | 207 CPM_CONTROL__TXCLK_PRBS_GATE_ENABLE_MASK | 208 CPM_CONTROL__REFCLK_REGS_GATE_ENABLE_MASK); 209 } else { 210 data &= ~(CPM_CONTROL__LCLK_DYN_GATE_ENABLE_MASK | 211 CPM_CONTROL__TXCLK_DYN_GATE_ENABLE_MASK | 212 CPM_CONTROL__TXCLK_LCNT_GATE_ENABLE_MASK | 213 CPM_CONTROL__TXCLK_REGS_GATE_ENABLE_MASK | 214 CPM_CONTROL__TXCLK_PRBS_GATE_ENABLE_MASK | 215 CPM_CONTROL__REFCLK_REGS_GATE_ENABLE_MASK); 216 } 217 218 if (def != data) 219 WREG32_PCIE(smnCPM_CONTROL, data); 220 } 221 222 static void nbio_v2_3_update_medium_grain_light_sleep(struct amdgpu_device *adev, 223 bool enable) 224 { 225 uint32_t def, data; 226 227 def = data = RREG32_PCIE(smnPCIE_CNTL2); 228 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_LS)) { 229 data |= (PCIE_CNTL2__SLV_MEM_LS_EN_MASK | 230 PCIE_CNTL2__MST_MEM_LS_EN_MASK | 231 PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK); 232 } else { 233 data &= ~(PCIE_CNTL2__SLV_MEM_LS_EN_MASK | 234 PCIE_CNTL2__MST_MEM_LS_EN_MASK | 235 PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK); 236 } 237 238 if (def != data) 239 WREG32_PCIE(smnPCIE_CNTL2, data); 240 } 241 242 static void nbio_v2_3_get_clockgating_state(struct amdgpu_device *adev, 243 u32 *flags) 244 { 245 int data; 246 247 /* AMD_CG_SUPPORT_BIF_MGCG */ 248 data = RREG32_PCIE(smnCPM_CONTROL); 249 if (data & CPM_CONTROL__LCLK_DYN_GATE_ENABLE_MASK) 250 *flags |= AMD_CG_SUPPORT_BIF_MGCG; 251 252 /* AMD_CG_SUPPORT_BIF_LS */ 253 data = RREG32_PCIE(smnPCIE_CNTL2); 254 if (data & PCIE_CNTL2__SLV_MEM_LS_EN_MASK) 255 *flags |= AMD_CG_SUPPORT_BIF_LS; 256 } 257 258 static u32 nbio_v2_3_get_hdp_flush_req_offset(struct amdgpu_device *adev) 259 { 260 return SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF_GPU_HDP_FLUSH_REQ); 261 } 262 263 static u32 nbio_v2_3_get_hdp_flush_done_offset(struct amdgpu_device *adev) 264 { 265 return SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF_GPU_HDP_FLUSH_DONE); 266 } 267 268 static u32 nbio_v2_3_get_pcie_index_offset(struct amdgpu_device *adev) 269 { 270 return SOC15_REG_OFFSET(NBIO, 0, mmPCIE_INDEX2); 271 } 272 273 static u32 nbio_v2_3_get_pcie_data_offset(struct amdgpu_device *adev) 274 { 275 return SOC15_REG_OFFSET(NBIO, 0, mmPCIE_DATA2); 276 } 277 278 const struct nbio_hdp_flush_reg nbio_v2_3_hdp_flush_reg = { 279 .ref_and_mask_cp0 = BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP0_MASK, 280 .ref_and_mask_cp1 = BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP1_MASK, 281 .ref_and_mask_cp2 = BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP2_MASK, 282 .ref_and_mask_cp3 = BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP3_MASK, 283 .ref_and_mask_cp4 = BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP4_MASK, 284 .ref_and_mask_cp5 = BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP5_MASK, 285 .ref_and_mask_cp6 = BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP6_MASK, 286 .ref_and_mask_cp7 = BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP7_MASK, 287 .ref_and_mask_cp8 = BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP8_MASK, 288 .ref_and_mask_cp9 = BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP9_MASK, 289 .ref_and_mask_sdma0 = BIF_BX_PF_GPU_HDP_FLUSH_DONE__SDMA0_MASK, 290 .ref_and_mask_sdma1 = BIF_BX_PF_GPU_HDP_FLUSH_DONE__SDMA1_MASK, 291 }; 292 293 static void nbio_v2_3_init_registers(struct amdgpu_device *adev) 294 { 295 uint32_t def, data; 296 297 def = data = RREG32_PCIE(smnPCIE_CONFIG_CNTL); 298 data = REG_SET_FIELD(data, PCIE_CONFIG_CNTL, CI_SWUS_MAX_READ_REQUEST_SIZE_MODE, 1); 299 data = REG_SET_FIELD(data, PCIE_CONFIG_CNTL, CI_SWUS_MAX_READ_REQUEST_SIZE_PRIV, 1); 300 301 if (def != data) 302 WREG32_PCIE(smnPCIE_CONFIG_CNTL, data); 303 } 304 305 const struct amdgpu_nbio_funcs nbio_v2_3_funcs = { 306 .get_hdp_flush_req_offset = nbio_v2_3_get_hdp_flush_req_offset, 307 .get_hdp_flush_done_offset = nbio_v2_3_get_hdp_flush_done_offset, 308 .get_pcie_index_offset = nbio_v2_3_get_pcie_index_offset, 309 .get_pcie_data_offset = nbio_v2_3_get_pcie_data_offset, 310 .get_rev_id = nbio_v2_3_get_rev_id, 311 .mc_access_enable = nbio_v2_3_mc_access_enable, 312 .hdp_flush = nbio_v2_3_hdp_flush, 313 .get_memsize = nbio_v2_3_get_memsize, 314 .sdma_doorbell_range = nbio_v2_3_sdma_doorbell_range, 315 .vcn_doorbell_range = nbio_v2_3_vcn_doorbell_range, 316 .enable_doorbell_aperture = nbio_v2_3_enable_doorbell_aperture, 317 .enable_doorbell_selfring_aperture = nbio_v2_3_enable_doorbell_selfring_aperture, 318 .ih_doorbell_range = nbio_v2_3_ih_doorbell_range, 319 .update_medium_grain_clock_gating = nbio_v2_3_update_medium_grain_clock_gating, 320 .update_medium_grain_light_sleep = nbio_v2_3_update_medium_grain_light_sleep, 321 .get_clockgating_state = nbio_v2_3_get_clockgating_state, 322 .ih_control = nbio_v2_3_ih_control, 323 .init_registers = nbio_v2_3_init_registers, 324 .remap_hdp_registers = nbio_v2_3_remap_hdp_registers, 325 }; 326