1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include "amdgpu.h" 24 #include "amdgpu_atombios.h" 25 #include "nbio_v2_3.h" 26 27 #include "nbio/nbio_2_3_default.h" 28 #include "nbio/nbio_2_3_offset.h" 29 #include "nbio/nbio_2_3_sh_mask.h" 30 #include <uapi/linux/kfd_ioctl.h> 31 32 #define smnPCIE_CONFIG_CNTL 0x11180044 33 #define smnCPM_CONTROL 0x11180460 34 #define smnPCIE_CNTL2 0x11180070 35 36 #define mmBIF_SDMA2_DOORBELL_RANGE 0x01d6 37 #define mmBIF_SDMA2_DOORBELL_RANGE_BASE_IDX 2 38 #define mmBIF_SDMA3_DOORBELL_RANGE 0x01d7 39 #define mmBIF_SDMA3_DOORBELL_RANGE_BASE_IDX 2 40 41 #define mmBIF_MMSCH1_DOORBELL_RANGE 0x01d8 42 #define mmBIF_MMSCH1_DOORBELL_RANGE_BASE_IDX 2 43 44 static void nbio_v2_3_remap_hdp_registers(struct amdgpu_device *adev) 45 { 46 WREG32_SOC15(NBIO, 0, mmREMAP_HDP_MEM_FLUSH_CNTL, 47 adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL); 48 WREG32_SOC15(NBIO, 0, mmREMAP_HDP_REG_FLUSH_CNTL, 49 adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_REG_FLUSH_CNTL); 50 } 51 52 static u32 nbio_v2_3_get_rev_id(struct amdgpu_device *adev) 53 { 54 u32 tmp = RREG32_SOC15(NBIO, 0, mmRCC_DEV0_EPF0_STRAP0); 55 56 tmp &= RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0_MASK; 57 tmp >>= RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0__SHIFT; 58 59 return tmp; 60 } 61 62 static void nbio_v2_3_mc_access_enable(struct amdgpu_device *adev, bool enable) 63 { 64 if (enable) 65 WREG32_SOC15(NBIO, 0, mmBIF_FB_EN, 66 BIF_FB_EN__FB_READ_EN_MASK | 67 BIF_FB_EN__FB_WRITE_EN_MASK); 68 else 69 WREG32_SOC15(NBIO, 0, mmBIF_FB_EN, 0); 70 } 71 72 static void nbio_v2_3_hdp_flush(struct amdgpu_device *adev, 73 struct amdgpu_ring *ring) 74 { 75 if (!ring || !ring->funcs->emit_wreg) 76 WREG32_NO_KIQ((adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2, 0); 77 else 78 amdgpu_ring_emit_wreg(ring, (adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2, 0); 79 } 80 81 static u32 nbio_v2_3_get_memsize(struct amdgpu_device *adev) 82 { 83 return RREG32_SOC15(NBIO, 0, mmRCC_DEV0_EPF0_RCC_CONFIG_MEMSIZE); 84 } 85 86 static void nbio_v2_3_sdma_doorbell_range(struct amdgpu_device *adev, int instance, 87 bool use_doorbell, int doorbell_index, 88 int doorbell_size) 89 { 90 u32 reg = instance == 0 ? SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA0_DOORBELL_RANGE) : 91 instance == 1 ? SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA1_DOORBELL_RANGE) : 92 instance == 2 ? SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA2_DOORBELL_RANGE) : 93 SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA3_DOORBELL_RANGE); 94 95 u32 doorbell_range = RREG32(reg); 96 97 if (use_doorbell) { 98 doorbell_range = REG_SET_FIELD(doorbell_range, 99 BIF_SDMA0_DOORBELL_RANGE, OFFSET, 100 doorbell_index); 101 doorbell_range = REG_SET_FIELD(doorbell_range, 102 BIF_SDMA0_DOORBELL_RANGE, SIZE, 103 doorbell_size); 104 } else 105 doorbell_range = REG_SET_FIELD(doorbell_range, 106 BIF_SDMA0_DOORBELL_RANGE, SIZE, 107 0); 108 109 WREG32(reg, doorbell_range); 110 } 111 112 static void nbio_v2_3_vcn_doorbell_range(struct amdgpu_device *adev, bool use_doorbell, 113 int doorbell_index, int instance) 114 { 115 u32 reg = instance ? SOC15_REG_OFFSET(NBIO, 0, mmBIF_MMSCH1_DOORBELL_RANGE) : 116 SOC15_REG_OFFSET(NBIO, 0, mmBIF_MMSCH0_DOORBELL_RANGE); 117 118 u32 doorbell_range = RREG32(reg); 119 120 if (use_doorbell) { 121 doorbell_range = REG_SET_FIELD(doorbell_range, 122 BIF_MMSCH0_DOORBELL_RANGE, OFFSET, 123 doorbell_index); 124 doorbell_range = REG_SET_FIELD(doorbell_range, 125 BIF_MMSCH0_DOORBELL_RANGE, SIZE, 8); 126 } else 127 doorbell_range = REG_SET_FIELD(doorbell_range, 128 BIF_MMSCH0_DOORBELL_RANGE, SIZE, 0); 129 130 WREG32(reg, doorbell_range); 131 } 132 133 static void nbio_v2_3_enable_doorbell_aperture(struct amdgpu_device *adev, 134 bool enable) 135 { 136 WREG32_FIELD15(NBIO, 0, RCC_DEV0_EPF0_RCC_DOORBELL_APER_EN, BIF_DOORBELL_APER_EN, 137 enable ? 1 : 0); 138 } 139 140 static void nbio_v2_3_enable_doorbell_selfring_aperture(struct amdgpu_device *adev, 141 bool enable) 142 { 143 u32 tmp = 0; 144 145 if (enable) { 146 tmp = REG_SET_FIELD(tmp, BIF_BX_PF_DOORBELL_SELFRING_GPA_APER_CNTL, 147 DOORBELL_SELFRING_GPA_APER_EN, 1) | 148 REG_SET_FIELD(tmp, BIF_BX_PF_DOORBELL_SELFRING_GPA_APER_CNTL, 149 DOORBELL_SELFRING_GPA_APER_MODE, 1) | 150 REG_SET_FIELD(tmp, BIF_BX_PF_DOORBELL_SELFRING_GPA_APER_CNTL, 151 DOORBELL_SELFRING_GPA_APER_SIZE, 0); 152 153 WREG32_SOC15(NBIO, 0, mmBIF_BX_PF_DOORBELL_SELFRING_GPA_APER_BASE_LOW, 154 lower_32_bits(adev->doorbell.base)); 155 WREG32_SOC15(NBIO, 0, mmBIF_BX_PF_DOORBELL_SELFRING_GPA_APER_BASE_HIGH, 156 upper_32_bits(adev->doorbell.base)); 157 } 158 159 WREG32_SOC15(NBIO, 0, mmBIF_BX_PF_DOORBELL_SELFRING_GPA_APER_CNTL, 160 tmp); 161 } 162 163 164 static void nbio_v2_3_ih_doorbell_range(struct amdgpu_device *adev, 165 bool use_doorbell, int doorbell_index) 166 { 167 u32 ih_doorbell_range = RREG32_SOC15(NBIO, 0, mmBIF_IH_DOORBELL_RANGE); 168 169 if (use_doorbell) { 170 ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, 171 BIF_IH_DOORBELL_RANGE, OFFSET, 172 doorbell_index); 173 ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, 174 BIF_IH_DOORBELL_RANGE, SIZE, 175 2); 176 } else 177 ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, 178 BIF_IH_DOORBELL_RANGE, SIZE, 179 0); 180 181 WREG32_SOC15(NBIO, 0, mmBIF_IH_DOORBELL_RANGE, ih_doorbell_range); 182 } 183 184 static void nbio_v2_3_ih_control(struct amdgpu_device *adev) 185 { 186 u32 interrupt_cntl; 187 188 /* setup interrupt control */ 189 WREG32_SOC15(NBIO, 0, mmINTERRUPT_CNTL2, adev->dummy_page_addr >> 8); 190 191 interrupt_cntl = RREG32_SOC15(NBIO, 0, mmINTERRUPT_CNTL); 192 /* 193 * INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=0 - dummy read disabled with msi, enabled without msi 194 * INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=1 - dummy read controlled by IH_DUMMY_RD_EN 195 */ 196 interrupt_cntl = REG_SET_FIELD(interrupt_cntl, INTERRUPT_CNTL, 197 IH_DUMMY_RD_OVERRIDE, 0); 198 199 /* INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN_MASK=1 if ring is in non-cacheable memory, e.g., vram */ 200 interrupt_cntl = REG_SET_FIELD(interrupt_cntl, INTERRUPT_CNTL, 201 IH_REQ_NONSNOOP_EN, 0); 202 203 WREG32_SOC15(NBIO, 0, mmINTERRUPT_CNTL, interrupt_cntl); 204 } 205 206 static void nbio_v2_3_update_medium_grain_clock_gating(struct amdgpu_device *adev, 207 bool enable) 208 { 209 uint32_t def, data; 210 211 def = data = RREG32_PCIE(smnCPM_CONTROL); 212 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_MGCG)) { 213 data |= (CPM_CONTROL__LCLK_DYN_GATE_ENABLE_MASK | 214 CPM_CONTROL__TXCLK_DYN_GATE_ENABLE_MASK | 215 CPM_CONTROL__TXCLK_LCNT_GATE_ENABLE_MASK | 216 CPM_CONTROL__TXCLK_REGS_GATE_ENABLE_MASK | 217 CPM_CONTROL__TXCLK_PRBS_GATE_ENABLE_MASK | 218 CPM_CONTROL__REFCLK_REGS_GATE_ENABLE_MASK); 219 } else { 220 data &= ~(CPM_CONTROL__LCLK_DYN_GATE_ENABLE_MASK | 221 CPM_CONTROL__TXCLK_DYN_GATE_ENABLE_MASK | 222 CPM_CONTROL__TXCLK_LCNT_GATE_ENABLE_MASK | 223 CPM_CONTROL__TXCLK_REGS_GATE_ENABLE_MASK | 224 CPM_CONTROL__TXCLK_PRBS_GATE_ENABLE_MASK | 225 CPM_CONTROL__REFCLK_REGS_GATE_ENABLE_MASK); 226 } 227 228 if (def != data) 229 WREG32_PCIE(smnCPM_CONTROL, data); 230 } 231 232 static void nbio_v2_3_update_medium_grain_light_sleep(struct amdgpu_device *adev, 233 bool enable) 234 { 235 uint32_t def, data; 236 237 def = data = RREG32_PCIE(smnPCIE_CNTL2); 238 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_LS)) { 239 data |= (PCIE_CNTL2__SLV_MEM_LS_EN_MASK | 240 PCIE_CNTL2__MST_MEM_LS_EN_MASK | 241 PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK); 242 } else { 243 data &= ~(PCIE_CNTL2__SLV_MEM_LS_EN_MASK | 244 PCIE_CNTL2__MST_MEM_LS_EN_MASK | 245 PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK); 246 } 247 248 if (def != data) 249 WREG32_PCIE(smnPCIE_CNTL2, data); 250 } 251 252 static void nbio_v2_3_get_clockgating_state(struct amdgpu_device *adev, 253 u32 *flags) 254 { 255 int data; 256 257 /* AMD_CG_SUPPORT_BIF_MGCG */ 258 data = RREG32_PCIE(smnCPM_CONTROL); 259 if (data & CPM_CONTROL__LCLK_DYN_GATE_ENABLE_MASK) 260 *flags |= AMD_CG_SUPPORT_BIF_MGCG; 261 262 /* AMD_CG_SUPPORT_BIF_LS */ 263 data = RREG32_PCIE(smnPCIE_CNTL2); 264 if (data & PCIE_CNTL2__SLV_MEM_LS_EN_MASK) 265 *flags |= AMD_CG_SUPPORT_BIF_LS; 266 } 267 268 static u32 nbio_v2_3_get_hdp_flush_req_offset(struct amdgpu_device *adev) 269 { 270 return SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF_GPU_HDP_FLUSH_REQ); 271 } 272 273 static u32 nbio_v2_3_get_hdp_flush_done_offset(struct amdgpu_device *adev) 274 { 275 return SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF_GPU_HDP_FLUSH_DONE); 276 } 277 278 static u32 nbio_v2_3_get_pcie_index_offset(struct amdgpu_device *adev) 279 { 280 return SOC15_REG_OFFSET(NBIO, 0, mmPCIE_INDEX2); 281 } 282 283 static u32 nbio_v2_3_get_pcie_data_offset(struct amdgpu_device *adev) 284 { 285 return SOC15_REG_OFFSET(NBIO, 0, mmPCIE_DATA2); 286 } 287 288 const struct nbio_hdp_flush_reg nbio_v2_3_hdp_flush_reg = { 289 .ref_and_mask_cp0 = BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP0_MASK, 290 .ref_and_mask_cp1 = BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP1_MASK, 291 .ref_and_mask_cp2 = BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP2_MASK, 292 .ref_and_mask_cp3 = BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP3_MASK, 293 .ref_and_mask_cp4 = BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP4_MASK, 294 .ref_and_mask_cp5 = BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP5_MASK, 295 .ref_and_mask_cp6 = BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP6_MASK, 296 .ref_and_mask_cp7 = BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP7_MASK, 297 .ref_and_mask_cp8 = BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP8_MASK, 298 .ref_and_mask_cp9 = BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP9_MASK, 299 .ref_and_mask_sdma0 = BIF_BX_PF_GPU_HDP_FLUSH_DONE__SDMA0_MASK, 300 .ref_and_mask_sdma1 = BIF_BX_PF_GPU_HDP_FLUSH_DONE__SDMA1_MASK, 301 }; 302 303 static void nbio_v2_3_init_registers(struct amdgpu_device *adev) 304 { 305 uint32_t def, data; 306 307 def = data = RREG32_PCIE(smnPCIE_CONFIG_CNTL); 308 data = REG_SET_FIELD(data, PCIE_CONFIG_CNTL, CI_SWUS_MAX_READ_REQUEST_SIZE_MODE, 1); 309 data = REG_SET_FIELD(data, PCIE_CONFIG_CNTL, CI_SWUS_MAX_READ_REQUEST_SIZE_PRIV, 1); 310 311 if (def != data) 312 WREG32_PCIE(smnPCIE_CONFIG_CNTL, data); 313 } 314 315 const struct amdgpu_nbio_funcs nbio_v2_3_funcs = { 316 .get_hdp_flush_req_offset = nbio_v2_3_get_hdp_flush_req_offset, 317 .get_hdp_flush_done_offset = nbio_v2_3_get_hdp_flush_done_offset, 318 .get_pcie_index_offset = nbio_v2_3_get_pcie_index_offset, 319 .get_pcie_data_offset = nbio_v2_3_get_pcie_data_offset, 320 .get_rev_id = nbio_v2_3_get_rev_id, 321 .mc_access_enable = nbio_v2_3_mc_access_enable, 322 .hdp_flush = nbio_v2_3_hdp_flush, 323 .get_memsize = nbio_v2_3_get_memsize, 324 .sdma_doorbell_range = nbio_v2_3_sdma_doorbell_range, 325 .vcn_doorbell_range = nbio_v2_3_vcn_doorbell_range, 326 .enable_doorbell_aperture = nbio_v2_3_enable_doorbell_aperture, 327 .enable_doorbell_selfring_aperture = nbio_v2_3_enable_doorbell_selfring_aperture, 328 .ih_doorbell_range = nbio_v2_3_ih_doorbell_range, 329 .update_medium_grain_clock_gating = nbio_v2_3_update_medium_grain_clock_gating, 330 .update_medium_grain_light_sleep = nbio_v2_3_update_medium_grain_light_sleep, 331 .get_clockgating_state = nbio_v2_3_get_clockgating_state, 332 .ih_control = nbio_v2_3_ih_control, 333 .init_registers = nbio_v2_3_init_registers, 334 .remap_hdp_registers = nbio_v2_3_remap_hdp_registers, 335 }; 336