1225cef9dSHawking Zhang /* 2225cef9dSHawking Zhang * Copyright 2019 Advanced Micro Devices, Inc. 3225cef9dSHawking Zhang * 4225cef9dSHawking Zhang * Permission is hereby granted, free of charge, to any person obtaining a 5225cef9dSHawking Zhang * copy of this software and associated documentation files (the "Software"), 6225cef9dSHawking Zhang * to deal in the Software without restriction, including without limitation 7225cef9dSHawking Zhang * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8225cef9dSHawking Zhang * and/or sell copies of the Software, and to permit persons to whom the 9225cef9dSHawking Zhang * Software is furnished to do so, subject to the following conditions: 10225cef9dSHawking Zhang * 11225cef9dSHawking Zhang * The above copyright notice and this permission notice shall be included in 12225cef9dSHawking Zhang * all copies or substantial portions of the Software. 13225cef9dSHawking Zhang * 14225cef9dSHawking Zhang * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15225cef9dSHawking Zhang * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16225cef9dSHawking Zhang * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17225cef9dSHawking Zhang * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18225cef9dSHawking Zhang * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19225cef9dSHawking Zhang * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20225cef9dSHawking Zhang * OTHER DEALINGS IN THE SOFTWARE. 21225cef9dSHawking Zhang * 22225cef9dSHawking Zhang */ 23225cef9dSHawking Zhang #include "amdgpu.h" 24225cef9dSHawking Zhang #include "amdgpu_atombios.h" 25225cef9dSHawking Zhang #include "nbio_v2_3.h" 26225cef9dSHawking Zhang 27225cef9dSHawking Zhang #include "nbio/nbio_2_3_default.h" 28225cef9dSHawking Zhang #include "nbio/nbio_2_3_offset.h" 29225cef9dSHawking Zhang #include "nbio/nbio_2_3_sh_mask.h" 30225cef9dSHawking Zhang 31225cef9dSHawking Zhang #define smnPCIE_CONFIG_CNTL 0x11180044 32225cef9dSHawking Zhang #define smnCPM_CONTROL 0x11180460 33225cef9dSHawking Zhang #define smnPCIE_CNTL2 0x11180070 34225cef9dSHawking Zhang 35225cef9dSHawking Zhang static u32 nbio_v2_3_get_rev_id(struct amdgpu_device *adev) 36225cef9dSHawking Zhang { 37225cef9dSHawking Zhang u32 tmp = RREG32_SOC15(NBIO, 0, mmRCC_DEV0_EPF0_STRAP0); 38225cef9dSHawking Zhang 39225cef9dSHawking Zhang tmp &= RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0_MASK; 40225cef9dSHawking Zhang tmp >>= RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0__SHIFT; 41225cef9dSHawking Zhang 42225cef9dSHawking Zhang return tmp; 43225cef9dSHawking Zhang } 44225cef9dSHawking Zhang 45225cef9dSHawking Zhang static void nbio_v2_3_mc_access_enable(struct amdgpu_device *adev, bool enable) 46225cef9dSHawking Zhang { 47225cef9dSHawking Zhang if (enable) 48225cef9dSHawking Zhang WREG32_SOC15(NBIO, 0, mmBIF_FB_EN, 49225cef9dSHawking Zhang BIF_FB_EN__FB_READ_EN_MASK | 50225cef9dSHawking Zhang BIF_FB_EN__FB_WRITE_EN_MASK); 51225cef9dSHawking Zhang else 52225cef9dSHawking Zhang WREG32_SOC15(NBIO, 0, mmBIF_FB_EN, 0); 53225cef9dSHawking Zhang } 54225cef9dSHawking Zhang 55225cef9dSHawking Zhang static void nbio_v2_3_hdp_flush(struct amdgpu_device *adev, 56225cef9dSHawking Zhang struct amdgpu_ring *ring) 57225cef9dSHawking Zhang { 58225cef9dSHawking Zhang if (!ring || !ring->funcs->emit_wreg) 59225cef9dSHawking Zhang WREG32_SOC15_NO_KIQ(NBIO, 0, mmBIF_BX_PF_HDP_MEM_COHERENCY_FLUSH_CNTL, 0); 60225cef9dSHawking Zhang else 61225cef9dSHawking Zhang amdgpu_ring_emit_wreg(ring, SOC15_REG_OFFSET( 62225cef9dSHawking Zhang NBIO, 0, mmBIF_BX_PF_HDP_MEM_COHERENCY_FLUSH_CNTL), 0); 63225cef9dSHawking Zhang } 64225cef9dSHawking Zhang 65225cef9dSHawking Zhang static u32 nbio_v2_3_get_memsize(struct amdgpu_device *adev) 66225cef9dSHawking Zhang { 67225cef9dSHawking Zhang return RREG32_SOC15(NBIO, 0, mmRCC_DEV0_EPF0_RCC_CONFIG_MEMSIZE); 68225cef9dSHawking Zhang } 69225cef9dSHawking Zhang 70225cef9dSHawking Zhang static void nbio_v2_3_sdma_doorbell_range(struct amdgpu_device *adev, int instance, 71225cef9dSHawking Zhang bool use_doorbell, int doorbell_index, 72225cef9dSHawking Zhang int doorbell_size) 73225cef9dSHawking Zhang { 74225cef9dSHawking Zhang u32 reg = instance == 0 ? SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA0_DOORBELL_RANGE) : 75225cef9dSHawking Zhang SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA1_DOORBELL_RANGE); 76225cef9dSHawking Zhang 77225cef9dSHawking Zhang u32 doorbell_range = RREG32(reg); 78225cef9dSHawking Zhang 79225cef9dSHawking Zhang if (use_doorbell) { 80225cef9dSHawking Zhang doorbell_range = REG_SET_FIELD(doorbell_range, 81225cef9dSHawking Zhang BIF_SDMA0_DOORBELL_RANGE, OFFSET, 82225cef9dSHawking Zhang doorbell_index); 83225cef9dSHawking Zhang doorbell_range = REG_SET_FIELD(doorbell_range, 84225cef9dSHawking Zhang BIF_SDMA0_DOORBELL_RANGE, SIZE, 85225cef9dSHawking Zhang doorbell_size); 86225cef9dSHawking Zhang } else 87225cef9dSHawking Zhang doorbell_range = REG_SET_FIELD(doorbell_range, 88225cef9dSHawking Zhang BIF_SDMA0_DOORBELL_RANGE, SIZE, 89225cef9dSHawking Zhang 0); 90225cef9dSHawking Zhang 91225cef9dSHawking Zhang WREG32(reg, doorbell_range); 92225cef9dSHawking Zhang } 93225cef9dSHawking Zhang 94225cef9dSHawking Zhang static void nbio_v2_3_vcn_doorbell_range(struct amdgpu_device *adev, bool use_doorbell, 95989b6a05SJames Zhu int doorbell_index, int instance) 96225cef9dSHawking Zhang { 97225cef9dSHawking Zhang u32 reg = SOC15_REG_OFFSET(NBIO, 0, mmBIF_MMSCH0_DOORBELL_RANGE); 98225cef9dSHawking Zhang 99225cef9dSHawking Zhang u32 doorbell_range = RREG32(reg); 100225cef9dSHawking Zhang 101225cef9dSHawking Zhang if (use_doorbell) { 102225cef9dSHawking Zhang doorbell_range = REG_SET_FIELD(doorbell_range, 103225cef9dSHawking Zhang BIF_MMSCH0_DOORBELL_RANGE, OFFSET, 104225cef9dSHawking Zhang doorbell_index); 105225cef9dSHawking Zhang doorbell_range = REG_SET_FIELD(doorbell_range, 106225cef9dSHawking Zhang BIF_MMSCH0_DOORBELL_RANGE, SIZE, 8); 107225cef9dSHawking Zhang } else 108225cef9dSHawking Zhang doorbell_range = REG_SET_FIELD(doorbell_range, 109225cef9dSHawking Zhang BIF_MMSCH0_DOORBELL_RANGE, SIZE, 0); 110225cef9dSHawking Zhang 111225cef9dSHawking Zhang WREG32(reg, doorbell_range); 112225cef9dSHawking Zhang } 113225cef9dSHawking Zhang 114225cef9dSHawking Zhang static void nbio_v2_3_enable_doorbell_aperture(struct amdgpu_device *adev, 115225cef9dSHawking Zhang bool enable) 116225cef9dSHawking Zhang { 117225cef9dSHawking Zhang WREG32_FIELD15(NBIO, 0, RCC_DEV0_EPF0_RCC_DOORBELL_APER_EN, BIF_DOORBELL_APER_EN, 118225cef9dSHawking Zhang enable ? 1 : 0); 119225cef9dSHawking Zhang } 120225cef9dSHawking Zhang 121225cef9dSHawking Zhang static void nbio_v2_3_enable_doorbell_selfring_aperture(struct amdgpu_device *adev, 122225cef9dSHawking Zhang bool enable) 123225cef9dSHawking Zhang { 124225cef9dSHawking Zhang u32 tmp = 0; 125225cef9dSHawking Zhang 126225cef9dSHawking Zhang if (enable) { 127225cef9dSHawking Zhang tmp = REG_SET_FIELD(tmp, BIF_BX_PF_DOORBELL_SELFRING_GPA_APER_CNTL, 128225cef9dSHawking Zhang DOORBELL_SELFRING_GPA_APER_EN, 1) | 129225cef9dSHawking Zhang REG_SET_FIELD(tmp, BIF_BX_PF_DOORBELL_SELFRING_GPA_APER_CNTL, 130225cef9dSHawking Zhang DOORBELL_SELFRING_GPA_APER_MODE, 1) | 131225cef9dSHawking Zhang REG_SET_FIELD(tmp, BIF_BX_PF_DOORBELL_SELFRING_GPA_APER_CNTL, 132225cef9dSHawking Zhang DOORBELL_SELFRING_GPA_APER_SIZE, 0); 133225cef9dSHawking Zhang 134225cef9dSHawking Zhang WREG32_SOC15(NBIO, 0, mmBIF_BX_PF_DOORBELL_SELFRING_GPA_APER_BASE_LOW, 135225cef9dSHawking Zhang lower_32_bits(adev->doorbell.base)); 136225cef9dSHawking Zhang WREG32_SOC15(NBIO, 0, mmBIF_BX_PF_DOORBELL_SELFRING_GPA_APER_BASE_HIGH, 137225cef9dSHawking Zhang upper_32_bits(adev->doorbell.base)); 138225cef9dSHawking Zhang } 139225cef9dSHawking Zhang 140225cef9dSHawking Zhang WREG32_SOC15(NBIO, 0, mmBIF_BX_PF_DOORBELL_SELFRING_GPA_APER_CNTL, 141225cef9dSHawking Zhang tmp); 142225cef9dSHawking Zhang } 143225cef9dSHawking Zhang 144225cef9dSHawking Zhang 145225cef9dSHawking Zhang static void nbio_v2_3_ih_doorbell_range(struct amdgpu_device *adev, 146225cef9dSHawking Zhang bool use_doorbell, int doorbell_index) 147225cef9dSHawking Zhang { 148225cef9dSHawking Zhang u32 ih_doorbell_range = RREG32_SOC15(NBIO, 0, mmBIF_IH_DOORBELL_RANGE); 149225cef9dSHawking Zhang 150225cef9dSHawking Zhang if (use_doorbell) { 151225cef9dSHawking Zhang ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, 152225cef9dSHawking Zhang BIF_IH_DOORBELL_RANGE, OFFSET, 153225cef9dSHawking Zhang doorbell_index); 154225cef9dSHawking Zhang ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, 155225cef9dSHawking Zhang BIF_IH_DOORBELL_RANGE, SIZE, 156225cef9dSHawking Zhang 2); 157225cef9dSHawking Zhang } else 158225cef9dSHawking Zhang ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, 159225cef9dSHawking Zhang BIF_IH_DOORBELL_RANGE, SIZE, 160225cef9dSHawking Zhang 0); 161225cef9dSHawking Zhang 162225cef9dSHawking Zhang WREG32_SOC15(NBIO, 0, mmBIF_IH_DOORBELL_RANGE, ih_doorbell_range); 163225cef9dSHawking Zhang } 164225cef9dSHawking Zhang 165225cef9dSHawking Zhang static void nbio_v2_3_ih_control(struct amdgpu_device *adev) 166225cef9dSHawking Zhang { 167225cef9dSHawking Zhang u32 interrupt_cntl; 168225cef9dSHawking Zhang 169225cef9dSHawking Zhang /* setup interrupt control */ 170225cef9dSHawking Zhang WREG32_SOC15(NBIO, 0, mmINTERRUPT_CNTL2, adev->dummy_page_addr >> 8); 171225cef9dSHawking Zhang 172225cef9dSHawking Zhang interrupt_cntl = RREG32_SOC15(NBIO, 0, mmINTERRUPT_CNTL); 173225cef9dSHawking Zhang /* 174225cef9dSHawking Zhang * INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=0 - dummy read disabled with msi, enabled without msi 175225cef9dSHawking Zhang * INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=1 - dummy read controlled by IH_DUMMY_RD_EN 176225cef9dSHawking Zhang */ 177225cef9dSHawking Zhang interrupt_cntl = REG_SET_FIELD(interrupt_cntl, INTERRUPT_CNTL, 178225cef9dSHawking Zhang IH_DUMMY_RD_OVERRIDE, 0); 179225cef9dSHawking Zhang 180225cef9dSHawking Zhang /* INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN_MASK=1 if ring is in non-cacheable memory, e.g., vram */ 181225cef9dSHawking Zhang interrupt_cntl = REG_SET_FIELD(interrupt_cntl, INTERRUPT_CNTL, 182225cef9dSHawking Zhang IH_REQ_NONSNOOP_EN, 0); 183225cef9dSHawking Zhang 184225cef9dSHawking Zhang WREG32_SOC15(NBIO, 0, mmINTERRUPT_CNTL, interrupt_cntl); 185225cef9dSHawking Zhang } 186225cef9dSHawking Zhang 187225cef9dSHawking Zhang static void nbio_v2_3_update_medium_grain_clock_gating(struct amdgpu_device *adev, 188225cef9dSHawking Zhang bool enable) 189225cef9dSHawking Zhang { 190225cef9dSHawking Zhang uint32_t def, data; 191225cef9dSHawking Zhang 192225cef9dSHawking Zhang def = data = RREG32_PCIE(smnCPM_CONTROL); 193225cef9dSHawking Zhang if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_MGCG)) { 194225cef9dSHawking Zhang data |= (CPM_CONTROL__LCLK_DYN_GATE_ENABLE_MASK | 195225cef9dSHawking Zhang CPM_CONTROL__TXCLK_DYN_GATE_ENABLE_MASK | 196225cef9dSHawking Zhang CPM_CONTROL__TXCLK_LCNT_GATE_ENABLE_MASK | 197225cef9dSHawking Zhang CPM_CONTROL__TXCLK_REGS_GATE_ENABLE_MASK | 198225cef9dSHawking Zhang CPM_CONTROL__TXCLK_PRBS_GATE_ENABLE_MASK | 199225cef9dSHawking Zhang CPM_CONTROL__REFCLK_REGS_GATE_ENABLE_MASK); 200225cef9dSHawking Zhang } else { 201225cef9dSHawking Zhang data &= ~(CPM_CONTROL__LCLK_DYN_GATE_ENABLE_MASK | 202225cef9dSHawking Zhang CPM_CONTROL__TXCLK_DYN_GATE_ENABLE_MASK | 203225cef9dSHawking Zhang CPM_CONTROL__TXCLK_LCNT_GATE_ENABLE_MASK | 204225cef9dSHawking Zhang CPM_CONTROL__TXCLK_REGS_GATE_ENABLE_MASK | 205225cef9dSHawking Zhang CPM_CONTROL__TXCLK_PRBS_GATE_ENABLE_MASK | 206225cef9dSHawking Zhang CPM_CONTROL__REFCLK_REGS_GATE_ENABLE_MASK); 207225cef9dSHawking Zhang } 208225cef9dSHawking Zhang 209225cef9dSHawking Zhang if (def != data) 210225cef9dSHawking Zhang WREG32_PCIE(smnCPM_CONTROL, data); 211225cef9dSHawking Zhang } 212225cef9dSHawking Zhang 213225cef9dSHawking Zhang static void nbio_v2_3_update_medium_grain_light_sleep(struct amdgpu_device *adev, 214225cef9dSHawking Zhang bool enable) 215225cef9dSHawking Zhang { 216225cef9dSHawking Zhang uint32_t def, data; 217225cef9dSHawking Zhang 218225cef9dSHawking Zhang def = data = RREG32_PCIE(smnPCIE_CNTL2); 219225cef9dSHawking Zhang if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_LS)) { 220225cef9dSHawking Zhang data |= (PCIE_CNTL2__SLV_MEM_LS_EN_MASK | 221225cef9dSHawking Zhang PCIE_CNTL2__MST_MEM_LS_EN_MASK | 222225cef9dSHawking Zhang PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK); 223225cef9dSHawking Zhang } else { 224225cef9dSHawking Zhang data &= ~(PCIE_CNTL2__SLV_MEM_LS_EN_MASK | 225225cef9dSHawking Zhang PCIE_CNTL2__MST_MEM_LS_EN_MASK | 226225cef9dSHawking Zhang PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK); 227225cef9dSHawking Zhang } 228225cef9dSHawking Zhang 229225cef9dSHawking Zhang if (def != data) 230225cef9dSHawking Zhang WREG32_PCIE(smnPCIE_CNTL2, data); 231225cef9dSHawking Zhang } 232225cef9dSHawking Zhang 233225cef9dSHawking Zhang static void nbio_v2_3_get_clockgating_state(struct amdgpu_device *adev, 234225cef9dSHawking Zhang u32 *flags) 235225cef9dSHawking Zhang { 236225cef9dSHawking Zhang int data; 237225cef9dSHawking Zhang 238225cef9dSHawking Zhang /* AMD_CG_SUPPORT_BIF_MGCG */ 239225cef9dSHawking Zhang data = RREG32_PCIE(smnCPM_CONTROL); 240225cef9dSHawking Zhang if (data & CPM_CONTROL__LCLK_DYN_GATE_ENABLE_MASK) 241225cef9dSHawking Zhang *flags |= AMD_CG_SUPPORT_BIF_MGCG; 242225cef9dSHawking Zhang 243225cef9dSHawking Zhang /* AMD_CG_SUPPORT_BIF_LS */ 244225cef9dSHawking Zhang data = RREG32_PCIE(smnPCIE_CNTL2); 245225cef9dSHawking Zhang if (data & PCIE_CNTL2__SLV_MEM_LS_EN_MASK) 246225cef9dSHawking Zhang *flags |= AMD_CG_SUPPORT_BIF_LS; 247225cef9dSHawking Zhang } 248225cef9dSHawking Zhang 249225cef9dSHawking Zhang static u32 nbio_v2_3_get_hdp_flush_req_offset(struct amdgpu_device *adev) 250225cef9dSHawking Zhang { 251225cef9dSHawking Zhang return SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF_GPU_HDP_FLUSH_REQ); 252225cef9dSHawking Zhang } 253225cef9dSHawking Zhang 254225cef9dSHawking Zhang static u32 nbio_v2_3_get_hdp_flush_done_offset(struct amdgpu_device *adev) 255225cef9dSHawking Zhang { 256225cef9dSHawking Zhang return SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF_GPU_HDP_FLUSH_DONE); 257225cef9dSHawking Zhang } 258225cef9dSHawking Zhang 259225cef9dSHawking Zhang static u32 nbio_v2_3_get_pcie_index_offset(struct amdgpu_device *adev) 260225cef9dSHawking Zhang { 261225cef9dSHawking Zhang return SOC15_REG_OFFSET(NBIO, 0, mmPCIE_INDEX2); 262225cef9dSHawking Zhang } 263225cef9dSHawking Zhang 264225cef9dSHawking Zhang static u32 nbio_v2_3_get_pcie_data_offset(struct amdgpu_device *adev) 265225cef9dSHawking Zhang { 266225cef9dSHawking Zhang return SOC15_REG_OFFSET(NBIO, 0, mmPCIE_DATA2); 267225cef9dSHawking Zhang } 268225cef9dSHawking Zhang 269225cef9dSHawking Zhang const struct nbio_hdp_flush_reg nbio_v2_3_hdp_flush_reg = { 270225cef9dSHawking Zhang .ref_and_mask_cp0 = BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP0_MASK, 271225cef9dSHawking Zhang .ref_and_mask_cp1 = BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP1_MASK, 272225cef9dSHawking Zhang .ref_and_mask_cp2 = BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP2_MASK, 273225cef9dSHawking Zhang .ref_and_mask_cp3 = BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP3_MASK, 274225cef9dSHawking Zhang .ref_and_mask_cp4 = BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP4_MASK, 275225cef9dSHawking Zhang .ref_and_mask_cp5 = BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP5_MASK, 276225cef9dSHawking Zhang .ref_and_mask_cp6 = BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP6_MASK, 277225cef9dSHawking Zhang .ref_and_mask_cp7 = BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP7_MASK, 278225cef9dSHawking Zhang .ref_and_mask_cp8 = BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP8_MASK, 279225cef9dSHawking Zhang .ref_and_mask_cp9 = BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP9_MASK, 280225cef9dSHawking Zhang .ref_and_mask_sdma0 = BIF_BX_PF_GPU_HDP_FLUSH_DONE__SDMA0_MASK, 281225cef9dSHawking Zhang .ref_and_mask_sdma1 = BIF_BX_PF_GPU_HDP_FLUSH_DONE__SDMA1_MASK, 282225cef9dSHawking Zhang }; 283225cef9dSHawking Zhang 284225cef9dSHawking Zhang static void nbio_v2_3_detect_hw_virt(struct amdgpu_device *adev) 285225cef9dSHawking Zhang { 286225cef9dSHawking Zhang uint32_t reg; 287225cef9dSHawking Zhang 288225cef9dSHawking Zhang reg = RREG32_SOC15(NBIO, 0, mmRCC_DEV0_EPF0_RCC_IOV_FUNC_IDENTIFIER); 289225cef9dSHawking Zhang if (reg & 1) 290225cef9dSHawking Zhang adev->virt.caps |= AMDGPU_SRIOV_CAPS_IS_VF; 291225cef9dSHawking Zhang 292225cef9dSHawking Zhang if (reg & 0x80000000) 293225cef9dSHawking Zhang adev->virt.caps |= AMDGPU_SRIOV_CAPS_ENABLE_IOV; 294225cef9dSHawking Zhang 295225cef9dSHawking Zhang if (!reg) { 296225cef9dSHawking Zhang if (is_virtual_machine()) /* passthrough mode exclus sriov mod */ 297225cef9dSHawking Zhang adev->virt.caps |= AMDGPU_PASSTHROUGH_MODE; 298225cef9dSHawking Zhang } 299225cef9dSHawking Zhang } 300225cef9dSHawking Zhang 301225cef9dSHawking Zhang static void nbio_v2_3_init_registers(struct amdgpu_device *adev) 302225cef9dSHawking Zhang { 303225cef9dSHawking Zhang uint32_t def, data; 304225cef9dSHawking Zhang 305225cef9dSHawking Zhang def = data = RREG32_PCIE(smnPCIE_CONFIG_CNTL); 306225cef9dSHawking Zhang data = REG_SET_FIELD(data, PCIE_CONFIG_CNTL, CI_SWUS_MAX_READ_REQUEST_SIZE_MODE, 1); 307225cef9dSHawking Zhang data = REG_SET_FIELD(data, PCIE_CONFIG_CNTL, CI_SWUS_MAX_READ_REQUEST_SIZE_PRIV, 1); 308225cef9dSHawking Zhang 309225cef9dSHawking Zhang if (def != data) 310225cef9dSHawking Zhang WREG32_PCIE(smnPCIE_CONFIG_CNTL, data); 311225cef9dSHawking Zhang } 312225cef9dSHawking Zhang 313225cef9dSHawking Zhang const struct amdgpu_nbio_funcs nbio_v2_3_funcs = { 314225cef9dSHawking Zhang .hdp_flush_reg = &nbio_v2_3_hdp_flush_reg, 315225cef9dSHawking Zhang .get_hdp_flush_req_offset = nbio_v2_3_get_hdp_flush_req_offset, 316225cef9dSHawking Zhang .get_hdp_flush_done_offset = nbio_v2_3_get_hdp_flush_done_offset, 317225cef9dSHawking Zhang .get_pcie_index_offset = nbio_v2_3_get_pcie_index_offset, 318225cef9dSHawking Zhang .get_pcie_data_offset = nbio_v2_3_get_pcie_data_offset, 319225cef9dSHawking Zhang .get_rev_id = nbio_v2_3_get_rev_id, 320225cef9dSHawking Zhang .mc_access_enable = nbio_v2_3_mc_access_enable, 321225cef9dSHawking Zhang .hdp_flush = nbio_v2_3_hdp_flush, 322225cef9dSHawking Zhang .get_memsize = nbio_v2_3_get_memsize, 323225cef9dSHawking Zhang .sdma_doorbell_range = nbio_v2_3_sdma_doorbell_range, 324225cef9dSHawking Zhang .vcn_doorbell_range = nbio_v2_3_vcn_doorbell_range, 325225cef9dSHawking Zhang .enable_doorbell_aperture = nbio_v2_3_enable_doorbell_aperture, 326225cef9dSHawking Zhang .enable_doorbell_selfring_aperture = nbio_v2_3_enable_doorbell_selfring_aperture, 327225cef9dSHawking Zhang .ih_doorbell_range = nbio_v2_3_ih_doorbell_range, 328225cef9dSHawking Zhang .update_medium_grain_clock_gating = nbio_v2_3_update_medium_grain_clock_gating, 329225cef9dSHawking Zhang .update_medium_grain_light_sleep = nbio_v2_3_update_medium_grain_light_sleep, 330225cef9dSHawking Zhang .get_clockgating_state = nbio_v2_3_get_clockgating_state, 331225cef9dSHawking Zhang .ih_control = nbio_v2_3_ih_control, 332225cef9dSHawking Zhang .init_registers = nbio_v2_3_init_registers, 333225cef9dSHawking Zhang .detect_hw_virt = nbio_v2_3_detect_hw_virt, 334225cef9dSHawking Zhang }; 335