1225cef9dSHawking Zhang /* 2225cef9dSHawking Zhang * Copyright 2019 Advanced Micro Devices, Inc. 3225cef9dSHawking Zhang * 4225cef9dSHawking Zhang * Permission is hereby granted, free of charge, to any person obtaining a 5225cef9dSHawking Zhang * copy of this software and associated documentation files (the "Software"), 6225cef9dSHawking Zhang * to deal in the Software without restriction, including without limitation 7225cef9dSHawking Zhang * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8225cef9dSHawking Zhang * and/or sell copies of the Software, and to permit persons to whom the 9225cef9dSHawking Zhang * Software is furnished to do so, subject to the following conditions: 10225cef9dSHawking Zhang * 11225cef9dSHawking Zhang * The above copyright notice and this permission notice shall be included in 12225cef9dSHawking Zhang * all copies or substantial portions of the Software. 13225cef9dSHawking Zhang * 14225cef9dSHawking Zhang * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15225cef9dSHawking Zhang * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16225cef9dSHawking Zhang * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17225cef9dSHawking Zhang * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18225cef9dSHawking Zhang * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19225cef9dSHawking Zhang * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20225cef9dSHawking Zhang * OTHER DEALINGS IN THE SOFTWARE. 21225cef9dSHawking Zhang * 22225cef9dSHawking Zhang */ 23225cef9dSHawking Zhang #include "amdgpu.h" 24225cef9dSHawking Zhang #include "amdgpu_atombios.h" 25225cef9dSHawking Zhang #include "nbio_v2_3.h" 26225cef9dSHawking Zhang 27225cef9dSHawking Zhang #include "nbio/nbio_2_3_default.h" 28225cef9dSHawking Zhang #include "nbio/nbio_2_3_offset.h" 29225cef9dSHawking Zhang #include "nbio/nbio_2_3_sh_mask.h" 30923c087aSYong Zhao #include <uapi/linux/kfd_ioctl.h> 31225cef9dSHawking Zhang 32225cef9dSHawking Zhang #define smnPCIE_CONFIG_CNTL 0x11180044 33225cef9dSHawking Zhang #define smnCPM_CONTROL 0x11180460 34225cef9dSHawking Zhang #define smnPCIE_CNTL2 0x11180070 35225cef9dSHawking Zhang 36923c087aSYong Zhao 37923c087aSYong Zhao static void nbio_v2_3_remap_hdp_registers(struct amdgpu_device *adev) 38923c087aSYong Zhao { 39923c087aSYong Zhao WREG32_SOC15(NBIO, 0, mmREMAP_HDP_MEM_FLUSH_CNTL, 40923c087aSYong Zhao adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL); 41923c087aSYong Zhao WREG32_SOC15(NBIO, 0, mmREMAP_HDP_REG_FLUSH_CNTL, 42923c087aSYong Zhao adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_REG_FLUSH_CNTL); 43923c087aSYong Zhao } 44923c087aSYong Zhao 45225cef9dSHawking Zhang static u32 nbio_v2_3_get_rev_id(struct amdgpu_device *adev) 46225cef9dSHawking Zhang { 47225cef9dSHawking Zhang u32 tmp = RREG32_SOC15(NBIO, 0, mmRCC_DEV0_EPF0_STRAP0); 48225cef9dSHawking Zhang 49225cef9dSHawking Zhang tmp &= RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0_MASK; 50225cef9dSHawking Zhang tmp >>= RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0__SHIFT; 51225cef9dSHawking Zhang 52225cef9dSHawking Zhang return tmp; 53225cef9dSHawking Zhang } 54225cef9dSHawking Zhang 55225cef9dSHawking Zhang static void nbio_v2_3_mc_access_enable(struct amdgpu_device *adev, bool enable) 56225cef9dSHawking Zhang { 57225cef9dSHawking Zhang if (enable) 58225cef9dSHawking Zhang WREG32_SOC15(NBIO, 0, mmBIF_FB_EN, 59225cef9dSHawking Zhang BIF_FB_EN__FB_READ_EN_MASK | 60225cef9dSHawking Zhang BIF_FB_EN__FB_WRITE_EN_MASK); 61225cef9dSHawking Zhang else 62225cef9dSHawking Zhang WREG32_SOC15(NBIO, 0, mmBIF_FB_EN, 0); 63225cef9dSHawking Zhang } 64225cef9dSHawking Zhang 65225cef9dSHawking Zhang static void nbio_v2_3_hdp_flush(struct amdgpu_device *adev, 66225cef9dSHawking Zhang struct amdgpu_ring *ring) 67225cef9dSHawking Zhang { 68225cef9dSHawking Zhang if (!ring || !ring->funcs->emit_wreg) 69923c087aSYong Zhao WREG32_NO_KIQ((adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2, 0); 70225cef9dSHawking Zhang else 71923c087aSYong Zhao amdgpu_ring_emit_wreg(ring, (adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2, 0); 72225cef9dSHawking Zhang } 73225cef9dSHawking Zhang 74225cef9dSHawking Zhang static u32 nbio_v2_3_get_memsize(struct amdgpu_device *adev) 75225cef9dSHawking Zhang { 76225cef9dSHawking Zhang return RREG32_SOC15(NBIO, 0, mmRCC_DEV0_EPF0_RCC_CONFIG_MEMSIZE); 77225cef9dSHawking Zhang } 78225cef9dSHawking Zhang 79225cef9dSHawking Zhang static void nbio_v2_3_sdma_doorbell_range(struct amdgpu_device *adev, int instance, 80225cef9dSHawking Zhang bool use_doorbell, int doorbell_index, 81225cef9dSHawking Zhang int doorbell_size) 82225cef9dSHawking Zhang { 83225cef9dSHawking Zhang u32 reg = instance == 0 ? SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA0_DOORBELL_RANGE) : 84225cef9dSHawking Zhang SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA1_DOORBELL_RANGE); 85225cef9dSHawking Zhang 86225cef9dSHawking Zhang u32 doorbell_range = RREG32(reg); 87225cef9dSHawking Zhang 88225cef9dSHawking Zhang if (use_doorbell) { 89225cef9dSHawking Zhang doorbell_range = REG_SET_FIELD(doorbell_range, 90225cef9dSHawking Zhang BIF_SDMA0_DOORBELL_RANGE, OFFSET, 91225cef9dSHawking Zhang doorbell_index); 92225cef9dSHawking Zhang doorbell_range = REG_SET_FIELD(doorbell_range, 93225cef9dSHawking Zhang BIF_SDMA0_DOORBELL_RANGE, SIZE, 94225cef9dSHawking Zhang doorbell_size); 95225cef9dSHawking Zhang } else 96225cef9dSHawking Zhang doorbell_range = REG_SET_FIELD(doorbell_range, 97225cef9dSHawking Zhang BIF_SDMA0_DOORBELL_RANGE, SIZE, 98225cef9dSHawking Zhang 0); 99225cef9dSHawking Zhang 100225cef9dSHawking Zhang WREG32(reg, doorbell_range); 101225cef9dSHawking Zhang } 102225cef9dSHawking Zhang 103225cef9dSHawking Zhang static void nbio_v2_3_vcn_doorbell_range(struct amdgpu_device *adev, bool use_doorbell, 104989b6a05SJames Zhu int doorbell_index, int instance) 105225cef9dSHawking Zhang { 106225cef9dSHawking Zhang u32 reg = SOC15_REG_OFFSET(NBIO, 0, mmBIF_MMSCH0_DOORBELL_RANGE); 107225cef9dSHawking Zhang 108225cef9dSHawking Zhang u32 doorbell_range = RREG32(reg); 109225cef9dSHawking Zhang 110225cef9dSHawking Zhang if (use_doorbell) { 111225cef9dSHawking Zhang doorbell_range = REG_SET_FIELD(doorbell_range, 112225cef9dSHawking Zhang BIF_MMSCH0_DOORBELL_RANGE, OFFSET, 113225cef9dSHawking Zhang doorbell_index); 114225cef9dSHawking Zhang doorbell_range = REG_SET_FIELD(doorbell_range, 115225cef9dSHawking Zhang BIF_MMSCH0_DOORBELL_RANGE, SIZE, 8); 116225cef9dSHawking Zhang } else 117225cef9dSHawking Zhang doorbell_range = REG_SET_FIELD(doorbell_range, 118225cef9dSHawking Zhang BIF_MMSCH0_DOORBELL_RANGE, SIZE, 0); 119225cef9dSHawking Zhang 120225cef9dSHawking Zhang WREG32(reg, doorbell_range); 121225cef9dSHawking Zhang } 122225cef9dSHawking Zhang 123225cef9dSHawking Zhang static void nbio_v2_3_enable_doorbell_aperture(struct amdgpu_device *adev, 124225cef9dSHawking Zhang bool enable) 125225cef9dSHawking Zhang { 126225cef9dSHawking Zhang WREG32_FIELD15(NBIO, 0, RCC_DEV0_EPF0_RCC_DOORBELL_APER_EN, BIF_DOORBELL_APER_EN, 127225cef9dSHawking Zhang enable ? 1 : 0); 128225cef9dSHawking Zhang } 129225cef9dSHawking Zhang 130225cef9dSHawking Zhang static void nbio_v2_3_enable_doorbell_selfring_aperture(struct amdgpu_device *adev, 131225cef9dSHawking Zhang bool enable) 132225cef9dSHawking Zhang { 133225cef9dSHawking Zhang u32 tmp = 0; 134225cef9dSHawking Zhang 135225cef9dSHawking Zhang if (enable) { 136225cef9dSHawking Zhang tmp = REG_SET_FIELD(tmp, BIF_BX_PF_DOORBELL_SELFRING_GPA_APER_CNTL, 137225cef9dSHawking Zhang DOORBELL_SELFRING_GPA_APER_EN, 1) | 138225cef9dSHawking Zhang REG_SET_FIELD(tmp, BIF_BX_PF_DOORBELL_SELFRING_GPA_APER_CNTL, 139225cef9dSHawking Zhang DOORBELL_SELFRING_GPA_APER_MODE, 1) | 140225cef9dSHawking Zhang REG_SET_FIELD(tmp, BIF_BX_PF_DOORBELL_SELFRING_GPA_APER_CNTL, 141225cef9dSHawking Zhang DOORBELL_SELFRING_GPA_APER_SIZE, 0); 142225cef9dSHawking Zhang 143225cef9dSHawking Zhang WREG32_SOC15(NBIO, 0, mmBIF_BX_PF_DOORBELL_SELFRING_GPA_APER_BASE_LOW, 144225cef9dSHawking Zhang lower_32_bits(adev->doorbell.base)); 145225cef9dSHawking Zhang WREG32_SOC15(NBIO, 0, mmBIF_BX_PF_DOORBELL_SELFRING_GPA_APER_BASE_HIGH, 146225cef9dSHawking Zhang upper_32_bits(adev->doorbell.base)); 147225cef9dSHawking Zhang } 148225cef9dSHawking Zhang 149225cef9dSHawking Zhang WREG32_SOC15(NBIO, 0, mmBIF_BX_PF_DOORBELL_SELFRING_GPA_APER_CNTL, 150225cef9dSHawking Zhang tmp); 151225cef9dSHawking Zhang } 152225cef9dSHawking Zhang 153225cef9dSHawking Zhang 154225cef9dSHawking Zhang static void nbio_v2_3_ih_doorbell_range(struct amdgpu_device *adev, 155225cef9dSHawking Zhang bool use_doorbell, int doorbell_index) 156225cef9dSHawking Zhang { 157225cef9dSHawking Zhang u32 ih_doorbell_range = RREG32_SOC15(NBIO, 0, mmBIF_IH_DOORBELL_RANGE); 158225cef9dSHawking Zhang 159225cef9dSHawking Zhang if (use_doorbell) { 160225cef9dSHawking Zhang ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, 161225cef9dSHawking Zhang BIF_IH_DOORBELL_RANGE, OFFSET, 162225cef9dSHawking Zhang doorbell_index); 163225cef9dSHawking Zhang ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, 164225cef9dSHawking Zhang BIF_IH_DOORBELL_RANGE, SIZE, 165225cef9dSHawking Zhang 2); 166225cef9dSHawking Zhang } else 167225cef9dSHawking Zhang ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, 168225cef9dSHawking Zhang BIF_IH_DOORBELL_RANGE, SIZE, 169225cef9dSHawking Zhang 0); 170225cef9dSHawking Zhang 171225cef9dSHawking Zhang WREG32_SOC15(NBIO, 0, mmBIF_IH_DOORBELL_RANGE, ih_doorbell_range); 172225cef9dSHawking Zhang } 173225cef9dSHawking Zhang 174225cef9dSHawking Zhang static void nbio_v2_3_ih_control(struct amdgpu_device *adev) 175225cef9dSHawking Zhang { 176225cef9dSHawking Zhang u32 interrupt_cntl; 177225cef9dSHawking Zhang 178225cef9dSHawking Zhang /* setup interrupt control */ 179225cef9dSHawking Zhang WREG32_SOC15(NBIO, 0, mmINTERRUPT_CNTL2, adev->dummy_page_addr >> 8); 180225cef9dSHawking Zhang 181225cef9dSHawking Zhang interrupt_cntl = RREG32_SOC15(NBIO, 0, mmINTERRUPT_CNTL); 182225cef9dSHawking Zhang /* 183225cef9dSHawking Zhang * INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=0 - dummy read disabled with msi, enabled without msi 184225cef9dSHawking Zhang * INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=1 - dummy read controlled by IH_DUMMY_RD_EN 185225cef9dSHawking Zhang */ 186225cef9dSHawking Zhang interrupt_cntl = REG_SET_FIELD(interrupt_cntl, INTERRUPT_CNTL, 187225cef9dSHawking Zhang IH_DUMMY_RD_OVERRIDE, 0); 188225cef9dSHawking Zhang 189225cef9dSHawking Zhang /* INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN_MASK=1 if ring is in non-cacheable memory, e.g., vram */ 190225cef9dSHawking Zhang interrupt_cntl = REG_SET_FIELD(interrupt_cntl, INTERRUPT_CNTL, 191225cef9dSHawking Zhang IH_REQ_NONSNOOP_EN, 0); 192225cef9dSHawking Zhang 193225cef9dSHawking Zhang WREG32_SOC15(NBIO, 0, mmINTERRUPT_CNTL, interrupt_cntl); 194225cef9dSHawking Zhang } 195225cef9dSHawking Zhang 196225cef9dSHawking Zhang static void nbio_v2_3_update_medium_grain_clock_gating(struct amdgpu_device *adev, 197225cef9dSHawking Zhang bool enable) 198225cef9dSHawking Zhang { 199225cef9dSHawking Zhang uint32_t def, data; 200225cef9dSHawking Zhang 201225cef9dSHawking Zhang def = data = RREG32_PCIE(smnCPM_CONTROL); 202225cef9dSHawking Zhang if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_MGCG)) { 203225cef9dSHawking Zhang data |= (CPM_CONTROL__LCLK_DYN_GATE_ENABLE_MASK | 204225cef9dSHawking Zhang CPM_CONTROL__TXCLK_DYN_GATE_ENABLE_MASK | 205225cef9dSHawking Zhang CPM_CONTROL__TXCLK_LCNT_GATE_ENABLE_MASK | 206225cef9dSHawking Zhang CPM_CONTROL__TXCLK_REGS_GATE_ENABLE_MASK | 207225cef9dSHawking Zhang CPM_CONTROL__TXCLK_PRBS_GATE_ENABLE_MASK | 208225cef9dSHawking Zhang CPM_CONTROL__REFCLK_REGS_GATE_ENABLE_MASK); 209225cef9dSHawking Zhang } else { 210225cef9dSHawking Zhang data &= ~(CPM_CONTROL__LCLK_DYN_GATE_ENABLE_MASK | 211225cef9dSHawking Zhang CPM_CONTROL__TXCLK_DYN_GATE_ENABLE_MASK | 212225cef9dSHawking Zhang CPM_CONTROL__TXCLK_LCNT_GATE_ENABLE_MASK | 213225cef9dSHawking Zhang CPM_CONTROL__TXCLK_REGS_GATE_ENABLE_MASK | 214225cef9dSHawking Zhang CPM_CONTROL__TXCLK_PRBS_GATE_ENABLE_MASK | 215225cef9dSHawking Zhang CPM_CONTROL__REFCLK_REGS_GATE_ENABLE_MASK); 216225cef9dSHawking Zhang } 217225cef9dSHawking Zhang 218225cef9dSHawking Zhang if (def != data) 219225cef9dSHawking Zhang WREG32_PCIE(smnCPM_CONTROL, data); 220225cef9dSHawking Zhang } 221225cef9dSHawking Zhang 222225cef9dSHawking Zhang static void nbio_v2_3_update_medium_grain_light_sleep(struct amdgpu_device *adev, 223225cef9dSHawking Zhang bool enable) 224225cef9dSHawking Zhang { 225225cef9dSHawking Zhang uint32_t def, data; 226225cef9dSHawking Zhang 227225cef9dSHawking Zhang def = data = RREG32_PCIE(smnPCIE_CNTL2); 228225cef9dSHawking Zhang if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_LS)) { 229225cef9dSHawking Zhang data |= (PCIE_CNTL2__SLV_MEM_LS_EN_MASK | 230225cef9dSHawking Zhang PCIE_CNTL2__MST_MEM_LS_EN_MASK | 231225cef9dSHawking Zhang PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK); 232225cef9dSHawking Zhang } else { 233225cef9dSHawking Zhang data &= ~(PCIE_CNTL2__SLV_MEM_LS_EN_MASK | 234225cef9dSHawking Zhang PCIE_CNTL2__MST_MEM_LS_EN_MASK | 235225cef9dSHawking Zhang PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK); 236225cef9dSHawking Zhang } 237225cef9dSHawking Zhang 238225cef9dSHawking Zhang if (def != data) 239225cef9dSHawking Zhang WREG32_PCIE(smnPCIE_CNTL2, data); 240225cef9dSHawking Zhang } 241225cef9dSHawking Zhang 242225cef9dSHawking Zhang static void nbio_v2_3_get_clockgating_state(struct amdgpu_device *adev, 243225cef9dSHawking Zhang u32 *flags) 244225cef9dSHawking Zhang { 245225cef9dSHawking Zhang int data; 246225cef9dSHawking Zhang 247225cef9dSHawking Zhang /* AMD_CG_SUPPORT_BIF_MGCG */ 248225cef9dSHawking Zhang data = RREG32_PCIE(smnCPM_CONTROL); 249225cef9dSHawking Zhang if (data & CPM_CONTROL__LCLK_DYN_GATE_ENABLE_MASK) 250225cef9dSHawking Zhang *flags |= AMD_CG_SUPPORT_BIF_MGCG; 251225cef9dSHawking Zhang 252225cef9dSHawking Zhang /* AMD_CG_SUPPORT_BIF_LS */ 253225cef9dSHawking Zhang data = RREG32_PCIE(smnPCIE_CNTL2); 254225cef9dSHawking Zhang if (data & PCIE_CNTL2__SLV_MEM_LS_EN_MASK) 255225cef9dSHawking Zhang *flags |= AMD_CG_SUPPORT_BIF_LS; 256225cef9dSHawking Zhang } 257225cef9dSHawking Zhang 258225cef9dSHawking Zhang static u32 nbio_v2_3_get_hdp_flush_req_offset(struct amdgpu_device *adev) 259225cef9dSHawking Zhang { 260225cef9dSHawking Zhang return SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF_GPU_HDP_FLUSH_REQ); 261225cef9dSHawking Zhang } 262225cef9dSHawking Zhang 263225cef9dSHawking Zhang static u32 nbio_v2_3_get_hdp_flush_done_offset(struct amdgpu_device *adev) 264225cef9dSHawking Zhang { 265225cef9dSHawking Zhang return SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF_GPU_HDP_FLUSH_DONE); 266225cef9dSHawking Zhang } 267225cef9dSHawking Zhang 268225cef9dSHawking Zhang static u32 nbio_v2_3_get_pcie_index_offset(struct amdgpu_device *adev) 269225cef9dSHawking Zhang { 270225cef9dSHawking Zhang return SOC15_REG_OFFSET(NBIO, 0, mmPCIE_INDEX2); 271225cef9dSHawking Zhang } 272225cef9dSHawking Zhang 273225cef9dSHawking Zhang static u32 nbio_v2_3_get_pcie_data_offset(struct amdgpu_device *adev) 274225cef9dSHawking Zhang { 275225cef9dSHawking Zhang return SOC15_REG_OFFSET(NBIO, 0, mmPCIE_DATA2); 276225cef9dSHawking Zhang } 277225cef9dSHawking Zhang 278225cef9dSHawking Zhang const struct nbio_hdp_flush_reg nbio_v2_3_hdp_flush_reg = { 279225cef9dSHawking Zhang .ref_and_mask_cp0 = BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP0_MASK, 280225cef9dSHawking Zhang .ref_and_mask_cp1 = BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP1_MASK, 281225cef9dSHawking Zhang .ref_and_mask_cp2 = BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP2_MASK, 282225cef9dSHawking Zhang .ref_and_mask_cp3 = BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP3_MASK, 283225cef9dSHawking Zhang .ref_and_mask_cp4 = BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP4_MASK, 284225cef9dSHawking Zhang .ref_and_mask_cp5 = BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP5_MASK, 285225cef9dSHawking Zhang .ref_and_mask_cp6 = BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP6_MASK, 286225cef9dSHawking Zhang .ref_and_mask_cp7 = BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP7_MASK, 287225cef9dSHawking Zhang .ref_and_mask_cp8 = BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP8_MASK, 288225cef9dSHawking Zhang .ref_and_mask_cp9 = BIF_BX_PF_GPU_HDP_FLUSH_DONE__CP9_MASK, 289225cef9dSHawking Zhang .ref_and_mask_sdma0 = BIF_BX_PF_GPU_HDP_FLUSH_DONE__SDMA0_MASK, 290225cef9dSHawking Zhang .ref_and_mask_sdma1 = BIF_BX_PF_GPU_HDP_FLUSH_DONE__SDMA1_MASK, 291225cef9dSHawking Zhang }; 292225cef9dSHawking Zhang 293225cef9dSHawking Zhang static void nbio_v2_3_detect_hw_virt(struct amdgpu_device *adev) 294225cef9dSHawking Zhang { 295225cef9dSHawking Zhang uint32_t reg; 296225cef9dSHawking Zhang 297225cef9dSHawking Zhang reg = RREG32_SOC15(NBIO, 0, mmRCC_DEV0_EPF0_RCC_IOV_FUNC_IDENTIFIER); 298225cef9dSHawking Zhang if (reg & 1) 299225cef9dSHawking Zhang adev->virt.caps |= AMDGPU_SRIOV_CAPS_IS_VF; 300225cef9dSHawking Zhang 301225cef9dSHawking Zhang if (reg & 0x80000000) 302225cef9dSHawking Zhang adev->virt.caps |= AMDGPU_SRIOV_CAPS_ENABLE_IOV; 303225cef9dSHawking Zhang 304225cef9dSHawking Zhang if (!reg) { 305225cef9dSHawking Zhang if (is_virtual_machine()) /* passthrough mode exclus sriov mod */ 306225cef9dSHawking Zhang adev->virt.caps |= AMDGPU_PASSTHROUGH_MODE; 307225cef9dSHawking Zhang } 308225cef9dSHawking Zhang } 309225cef9dSHawking Zhang 310225cef9dSHawking Zhang static void nbio_v2_3_init_registers(struct amdgpu_device *adev) 311225cef9dSHawking Zhang { 312225cef9dSHawking Zhang uint32_t def, data; 313225cef9dSHawking Zhang 314225cef9dSHawking Zhang def = data = RREG32_PCIE(smnPCIE_CONFIG_CNTL); 315225cef9dSHawking Zhang data = REG_SET_FIELD(data, PCIE_CONFIG_CNTL, CI_SWUS_MAX_READ_REQUEST_SIZE_MODE, 1); 316225cef9dSHawking Zhang data = REG_SET_FIELD(data, PCIE_CONFIG_CNTL, CI_SWUS_MAX_READ_REQUEST_SIZE_PRIV, 1); 317225cef9dSHawking Zhang 318225cef9dSHawking Zhang if (def != data) 319225cef9dSHawking Zhang WREG32_PCIE(smnPCIE_CONFIG_CNTL, data); 320225cef9dSHawking Zhang } 321225cef9dSHawking Zhang 322225cef9dSHawking Zhang const struct amdgpu_nbio_funcs nbio_v2_3_funcs = { 323225cef9dSHawking Zhang .get_hdp_flush_req_offset = nbio_v2_3_get_hdp_flush_req_offset, 324225cef9dSHawking Zhang .get_hdp_flush_done_offset = nbio_v2_3_get_hdp_flush_done_offset, 325225cef9dSHawking Zhang .get_pcie_index_offset = nbio_v2_3_get_pcie_index_offset, 326225cef9dSHawking Zhang .get_pcie_data_offset = nbio_v2_3_get_pcie_data_offset, 327225cef9dSHawking Zhang .get_rev_id = nbio_v2_3_get_rev_id, 328225cef9dSHawking Zhang .mc_access_enable = nbio_v2_3_mc_access_enable, 329225cef9dSHawking Zhang .hdp_flush = nbio_v2_3_hdp_flush, 330225cef9dSHawking Zhang .get_memsize = nbio_v2_3_get_memsize, 331225cef9dSHawking Zhang .sdma_doorbell_range = nbio_v2_3_sdma_doorbell_range, 332225cef9dSHawking Zhang .vcn_doorbell_range = nbio_v2_3_vcn_doorbell_range, 333225cef9dSHawking Zhang .enable_doorbell_aperture = nbio_v2_3_enable_doorbell_aperture, 334225cef9dSHawking Zhang .enable_doorbell_selfring_aperture = nbio_v2_3_enable_doorbell_selfring_aperture, 335225cef9dSHawking Zhang .ih_doorbell_range = nbio_v2_3_ih_doorbell_range, 336225cef9dSHawking Zhang .update_medium_grain_clock_gating = nbio_v2_3_update_medium_grain_clock_gating, 337225cef9dSHawking Zhang .update_medium_grain_light_sleep = nbio_v2_3_update_medium_grain_light_sleep, 338225cef9dSHawking Zhang .get_clockgating_state = nbio_v2_3_get_clockgating_state, 339225cef9dSHawking Zhang .ih_control = nbio_v2_3_ih_control, 340225cef9dSHawking Zhang .init_registers = nbio_v2_3_init_registers, 341225cef9dSHawking Zhang .detect_hw_virt = nbio_v2_3_detect_hw_virt, 342923c087aSYong Zhao .remap_hdp_registers = nbio_v2_3_remap_hdp_registers, 343225cef9dSHawking Zhang }; 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