1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/pci.h> 25 26 #include "amdgpu.h" 27 #include "amdgpu_ih.h" 28 29 #include "oss/osssys_5_0_0_offset.h" 30 #include "oss/osssys_5_0_0_sh_mask.h" 31 32 #include "soc15_common.h" 33 #include "navi10_ih.h" 34 35 #define MAX_REARM_RETRY 10 36 37 #define mmIH_CHICKEN_Sienna_Cichlid 0x018d 38 #define mmIH_CHICKEN_Sienna_Cichlid_BASE_IDX 0 39 40 static void navi10_ih_set_interrupt_funcs(struct amdgpu_device *adev); 41 42 /** 43 * navi10_ih_init_register_offset - Initialize register offset for ih rings 44 * 45 * @adev: amdgpu_device pointer 46 * 47 * Initialize register offset ih rings (NAVI10). 48 */ 49 static void navi10_ih_init_register_offset(struct amdgpu_device *adev) 50 { 51 struct amdgpu_ih_regs *ih_regs; 52 53 if (adev->irq.ih.ring_size) { 54 ih_regs = &adev->irq.ih.ih_regs; 55 ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE); 56 ih_regs->ih_rb_base_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_HI); 57 ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL); 58 ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR); 59 ih_regs->ih_rb_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR); 60 ih_regs->ih_doorbell_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_DOORBELL_RPTR); 61 ih_regs->ih_rb_wptr_addr_lo = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_ADDR_LO); 62 ih_regs->ih_rb_wptr_addr_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_ADDR_HI); 63 ih_regs->psp_reg_id = PSP_REG_IH_RB_CNTL; 64 } 65 66 if (adev->irq.ih1.ring_size) { 67 ih_regs = &adev->irq.ih1.ih_regs; 68 ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_RING1); 69 ih_regs->ih_rb_base_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_HI_RING1); 70 ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL_RING1); 71 ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_RING1); 72 ih_regs->ih_rb_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR_RING1); 73 ih_regs->ih_doorbell_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_DOORBELL_RPTR_RING1); 74 ih_regs->psp_reg_id = PSP_REG_IH_RB_CNTL_RING1; 75 } 76 77 if (adev->irq.ih2.ring_size) { 78 ih_regs = &adev->irq.ih2.ih_regs; 79 ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_RING2); 80 ih_regs->ih_rb_base_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_HI_RING2); 81 ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL_RING2); 82 ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_RING2); 83 ih_regs->ih_rb_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR_RING2); 84 ih_regs->ih_doorbell_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_DOORBELL_RPTR_RING2); 85 ih_regs->psp_reg_id = PSP_REG_IH_RB_CNTL_RING2; 86 } 87 } 88 89 /** 90 * force_update_wptr_for_self_int - Force update the wptr for self interrupt 91 * 92 * @adev: amdgpu_device pointer 93 * @threshold: threshold to trigger the wptr reporting 94 * @timeout: timeout to trigger the wptr reporting 95 * @enabled: Enable/disable timeout flush mechanism 96 * 97 * threshold input range: 0 ~ 15, default 0, 98 * real_threshold = 2^threshold 99 * timeout input range: 0 ~ 20, default 8, 100 * real_timeout = (2^timeout) * 1024 / (socclk_freq) 101 * 102 * Force update wptr for self interrupt ( >= SIENNA_CICHLID). 103 */ 104 static void 105 force_update_wptr_for_self_int(struct amdgpu_device *adev, 106 u32 threshold, u32 timeout, bool enabled) 107 { 108 u32 ih_cntl, ih_rb_cntl; 109 110 if (adev->asic_type < CHIP_SIENNA_CICHLID) 111 return; 112 113 ih_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_CNTL2); 114 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1); 115 116 ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL2, 117 SELF_IV_FORCE_WPTR_UPDATE_TIMEOUT, timeout); 118 ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL2, 119 SELF_IV_FORCE_WPTR_UPDATE_ENABLE, enabled); 120 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING1, 121 RB_USED_INT_THRESHOLD, threshold); 122 123 WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1, ih_rb_cntl); 124 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2); 125 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING2, 126 RB_USED_INT_THRESHOLD, threshold); 127 WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2, ih_rb_cntl); 128 WREG32_SOC15(OSSSYS, 0, mmIH_CNTL2, ih_cntl); 129 } 130 131 /** 132 * navi10_ih_toggle_ring_interrupts - toggle the interrupt ring buffer 133 * 134 * @adev: amdgpu_device pointer 135 * @ih: amdgpu_ih_ring pointet 136 * @enable: true - enable the interrupts, false - disable the interrupts 137 * 138 * Toggle the interrupt ring buffer (NAVI10) 139 */ 140 static int navi10_ih_toggle_ring_interrupts(struct amdgpu_device *adev, 141 struct amdgpu_ih_ring *ih, 142 bool enable) 143 { 144 struct amdgpu_ih_regs *ih_regs; 145 uint32_t tmp; 146 147 ih_regs = &ih->ih_regs; 148 149 tmp = RREG32(ih_regs->ih_rb_cntl); 150 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RB_ENABLE, (enable ? 1 : 0)); 151 /* enable_intr field is only valid in ring0 */ 152 if (ih == &adev->irq.ih) 153 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, ENABLE_INTR, (enable ? 1 : 0)); 154 if (amdgpu_sriov_vf(adev) && adev->asic_type < CHIP_NAVI10) { 155 if (psp_reg_program(&adev->psp, ih_regs->psp_reg_id, tmp)) { 156 dev_err(adev->dev, "PSP program IH_RB_CNTL failed!\n"); 157 return -ETIMEDOUT; 158 } 159 } else { 160 WREG32(ih_regs->ih_rb_cntl, tmp); 161 } 162 163 if (enable) { 164 ih->enabled = true; 165 } else { 166 /* set rptr, wptr to 0 */ 167 WREG32(ih_regs->ih_rb_rptr, 0); 168 WREG32(ih_regs->ih_rb_wptr, 0); 169 ih->enabled = false; 170 ih->rptr = 0; 171 } 172 173 return 0; 174 } 175 176 /** 177 * navi10_ih_toggle_interrupts - Toggle all the available interrupt ring buffers 178 * 179 * @adev: amdgpu_device pointer 180 * @enable: enable or disable interrupt ring buffers 181 * 182 * Toggle all the available interrupt ring buffers (NAVI10). 183 */ 184 static int navi10_ih_toggle_interrupts(struct amdgpu_device *adev, bool enable) 185 { 186 struct amdgpu_ih_ring *ih[] = {&adev->irq.ih, &adev->irq.ih1, &adev->irq.ih2}; 187 int i; 188 int r; 189 190 for (i = 0; i < ARRAY_SIZE(ih); i++) { 191 if (ih[i]->ring_size) { 192 r = navi10_ih_toggle_ring_interrupts(adev, ih[i], enable); 193 if (r) 194 return r; 195 } 196 } 197 198 return 0; 199 } 200 201 static uint32_t navi10_ih_rb_cntl(struct amdgpu_ih_ring *ih, uint32_t ih_rb_cntl) 202 { 203 int rb_bufsz = order_base_2(ih->ring_size / 4); 204 205 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, 206 MC_SPACE, ih->use_bus_addr ? 1 : 4); 207 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, 208 WPTR_OVERFLOW_CLEAR, 1); 209 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, 210 WPTR_OVERFLOW_ENABLE, 1); 211 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_SIZE, rb_bufsz); 212 /* Ring Buffer write pointer writeback. If enabled, IH_RB_WPTR register 213 * value is written to memory 214 */ 215 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, 216 WPTR_WRITEBACK_ENABLE, 1); 217 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_SNOOP, 1); 218 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_RO, 0); 219 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_VMID, 0); 220 221 return ih_rb_cntl; 222 } 223 224 static uint32_t navi10_ih_doorbell_rptr(struct amdgpu_ih_ring *ih) 225 { 226 u32 ih_doorbell_rtpr = 0; 227 228 if (ih->use_doorbell) { 229 ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr, 230 IH_DOORBELL_RPTR, OFFSET, 231 ih->doorbell_index); 232 ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr, 233 IH_DOORBELL_RPTR, 234 ENABLE, 1); 235 } else { 236 ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr, 237 IH_DOORBELL_RPTR, 238 ENABLE, 0); 239 } 240 return ih_doorbell_rtpr; 241 } 242 243 /** 244 * navi10_ih_enable_ring - enable an ih ring buffer 245 * 246 * @adev: amdgpu_device pointer 247 * @ih: amdgpu_ih_ring pointer 248 * 249 * Enable an ih ring buffer (NAVI10) 250 */ 251 static int navi10_ih_enable_ring(struct amdgpu_device *adev, 252 struct amdgpu_ih_ring *ih) 253 { 254 struct amdgpu_ih_regs *ih_regs; 255 uint32_t tmp; 256 257 ih_regs = &ih->ih_regs; 258 259 /* Ring Buffer base. [39:8] of 40-bit address of the beginning of the ring buffer*/ 260 WREG32(ih_regs->ih_rb_base, ih->gpu_addr >> 8); 261 WREG32(ih_regs->ih_rb_base_hi, (ih->gpu_addr >> 40) & 0xff); 262 263 tmp = RREG32(ih_regs->ih_rb_cntl); 264 tmp = navi10_ih_rb_cntl(ih, tmp); 265 if (ih == &adev->irq.ih) 266 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RPTR_REARM, !!adev->irq.msi_enabled); 267 if (ih == &adev->irq.ih1) { 268 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_ENABLE, 0); 269 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RB_FULL_DRAIN_ENABLE, 1); 270 } 271 if (amdgpu_sriov_vf(adev) && adev->asic_type < CHIP_NAVI10) { 272 if (psp_reg_program(&adev->psp, ih_regs->psp_reg_id, tmp)) { 273 dev_err(adev->dev, "PSP program IH_RB_CNTL failed!\n"); 274 return -ETIMEDOUT; 275 } 276 } else { 277 WREG32(ih_regs->ih_rb_cntl, tmp); 278 } 279 280 if (ih == &adev->irq.ih) { 281 /* set the ih ring 0 writeback address whether it's enabled or not */ 282 WREG32(ih_regs->ih_rb_wptr_addr_lo, lower_32_bits(ih->wptr_addr)); 283 WREG32(ih_regs->ih_rb_wptr_addr_hi, upper_32_bits(ih->wptr_addr) & 0xFFFF); 284 } 285 286 /* set rptr, wptr to 0 */ 287 WREG32(ih_regs->ih_rb_wptr, 0); 288 WREG32(ih_regs->ih_rb_rptr, 0); 289 290 WREG32(ih_regs->ih_doorbell_rptr, navi10_ih_doorbell_rptr(ih)); 291 292 return 0; 293 } 294 295 static void navi10_ih_reroute_ih(struct amdgpu_device *adev) 296 { 297 uint32_t tmp; 298 299 /* Reroute to IH ring 1 for VMC */ 300 WREG32_SOC15(OSSSYS, 0, mmIH_CLIENT_CFG_INDEX, 0x12); 301 tmp = RREG32_SOC15(OSSSYS, 0, mmIH_CLIENT_CFG_DATA); 302 tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, CLIENT_TYPE, 1); 303 tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, RING_ID, 1); 304 WREG32_SOC15(OSSSYS, 0, mmIH_CLIENT_CFG_DATA, tmp); 305 306 /* Reroute IH ring 1 for UMC */ 307 WREG32_SOC15(OSSSYS, 0, mmIH_CLIENT_CFG_INDEX, 0x1B); 308 tmp = RREG32_SOC15(OSSSYS, 0, mmIH_CLIENT_CFG_DATA); 309 tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, RING_ID, 1); 310 WREG32_SOC15(OSSSYS, 0, mmIH_CLIENT_CFG_DATA, tmp); 311 } 312 313 /** 314 * navi10_ih_irq_init - init and enable the interrupt ring 315 * 316 * @adev: amdgpu_device pointer 317 * 318 * Allocate a ring buffer for the interrupt controller, 319 * enable the RLC, disable interrupts, enable the IH 320 * ring buffer and enable it (NAVI). 321 * Called at device load and reume. 322 * Returns 0 for success, errors for failure. 323 */ 324 static int navi10_ih_irq_init(struct amdgpu_device *adev) 325 { 326 struct amdgpu_ih_ring *ih[] = {&adev->irq.ih, &adev->irq.ih1, &adev->irq.ih2}; 327 u32 ih_chicken; 328 u32 tmp; 329 int ret; 330 int i; 331 332 /* disable irqs */ 333 ret = navi10_ih_toggle_interrupts(adev, false); 334 if (ret) 335 return ret; 336 337 adev->nbio.funcs->ih_control(adev); 338 339 if (unlikely(adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT)) { 340 if (ih[0]->use_bus_addr) { 341 switch (adev->asic_type) { 342 case CHIP_SIENNA_CICHLID: 343 case CHIP_NAVY_FLOUNDER: 344 case CHIP_VANGOGH: 345 case CHIP_DIMGREY_CAVEFISH: 346 ih_chicken = RREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN_Sienna_Cichlid); 347 ih_chicken = REG_SET_FIELD(ih_chicken, 348 IH_CHICKEN, MC_SPACE_GPA_ENABLE, 1); 349 WREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN_Sienna_Cichlid, ih_chicken); 350 break; 351 default: 352 ih_chicken = RREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN); 353 ih_chicken = REG_SET_FIELD(ih_chicken, 354 IH_CHICKEN, MC_SPACE_GPA_ENABLE, 1); 355 WREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN, ih_chicken); 356 break; 357 } 358 } 359 } 360 361 for (i = 0; i < ARRAY_SIZE(ih); i++) { 362 if (ih[i]->ring_size) { 363 ret = navi10_ih_enable_ring(adev, ih[i]); 364 if (ret) 365 return ret; 366 } 367 } 368 369 /* update doorbell range for ih ring 0*/ 370 adev->nbio.funcs->ih_doorbell_range(adev, ih[0]->use_doorbell, 371 ih[0]->doorbell_index); 372 373 tmp = RREG32_SOC15(OSSSYS, 0, mmIH_STORM_CLIENT_LIST_CNTL); 374 tmp = REG_SET_FIELD(tmp, IH_STORM_CLIENT_LIST_CNTL, 375 CLIENT18_IS_STORM_CLIENT, 1); 376 WREG32_SOC15(OSSSYS, 0, mmIH_STORM_CLIENT_LIST_CNTL, tmp); 377 378 tmp = RREG32_SOC15(OSSSYS, 0, mmIH_INT_FLOOD_CNTL); 379 tmp = REG_SET_FIELD(tmp, IH_INT_FLOOD_CNTL, FLOOD_CNTL_ENABLE, 1); 380 WREG32_SOC15(OSSSYS, 0, mmIH_INT_FLOOD_CNTL, tmp); 381 382 pci_set_master(adev->pdev); 383 384 /* enable interrupts */ 385 ret = navi10_ih_toggle_interrupts(adev, true); 386 if (ret) 387 return ret; 388 /* enable wptr force update for self int */ 389 force_update_wptr_for_self_int(adev, 0, 8, true); 390 391 return 0; 392 } 393 394 /** 395 * navi10_ih_irq_disable - disable interrupts 396 * 397 * @adev: amdgpu_device pointer 398 * 399 * Disable interrupts on the hw (NAVI10). 400 */ 401 static void navi10_ih_irq_disable(struct amdgpu_device *adev) 402 { 403 force_update_wptr_for_self_int(adev, 0, 8, false); 404 navi10_ih_toggle_interrupts(adev, false); 405 406 /* Wait and acknowledge irq */ 407 mdelay(1); 408 } 409 410 /** 411 * navi10_ih_get_wptr - get the IH ring buffer wptr 412 * 413 * @adev: amdgpu_device pointer 414 * @ih: IH ring buffer to fetch wptr 415 * 416 * Get the IH ring buffer wptr from either the register 417 * or the writeback memory buffer (NAVI10). Also check for 418 * ring buffer overflow and deal with it. 419 * Returns the value of the wptr. 420 */ 421 static u32 navi10_ih_get_wptr(struct amdgpu_device *adev, 422 struct amdgpu_ih_ring *ih) 423 { 424 u32 wptr, reg, tmp; 425 426 wptr = le32_to_cpu(*ih->wptr_cpu); 427 428 if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) 429 goto out; 430 431 if (ih == &adev->irq.ih) 432 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR); 433 else if (ih == &adev->irq.ih1) 434 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_RING1); 435 else if (ih == &adev->irq.ih2) 436 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_RING2); 437 else 438 BUG(); 439 440 wptr = RREG32_NO_KIQ(reg); 441 if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) 442 goto out; 443 wptr = REG_SET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW, 0); 444 445 /* When a ring buffer overflow happen start parsing interrupt 446 * from the last not overwritten vector (wptr + 32). Hopefully 447 * this should allow us to catch up. 448 */ 449 tmp = (wptr + 32) & ih->ptr_mask; 450 dev_warn(adev->dev, "IH ring buffer overflow " 451 "(0x%08X, 0x%08X, 0x%08X)\n", 452 wptr, ih->rptr, tmp); 453 ih->rptr = tmp; 454 455 if (ih == &adev->irq.ih) 456 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL); 457 else if (ih == &adev->irq.ih1) 458 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL_RING1); 459 else if (ih == &adev->irq.ih2) 460 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL_RING2); 461 else 462 BUG(); 463 464 tmp = RREG32_NO_KIQ(reg); 465 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1); 466 WREG32_NO_KIQ(reg, tmp); 467 out: 468 return (wptr & ih->ptr_mask); 469 } 470 471 /** 472 * navi10_ih_decode_iv - decode an interrupt vector 473 * 474 * @adev: amdgpu_device pointer 475 * @ih: IH ring buffer to decode 476 * @entry: IV entry to place decoded information into 477 * 478 * Decodes the interrupt vector at the current rptr 479 * position and also advance the position. 480 */ 481 static void navi10_ih_decode_iv(struct amdgpu_device *adev, 482 struct amdgpu_ih_ring *ih, 483 struct amdgpu_iv_entry *entry) 484 { 485 /* wptr/rptr are in bytes! */ 486 u32 ring_index = ih->rptr >> 2; 487 uint32_t dw[8]; 488 489 dw[0] = le32_to_cpu(ih->ring[ring_index + 0]); 490 dw[1] = le32_to_cpu(ih->ring[ring_index + 1]); 491 dw[2] = le32_to_cpu(ih->ring[ring_index + 2]); 492 dw[3] = le32_to_cpu(ih->ring[ring_index + 3]); 493 dw[4] = le32_to_cpu(ih->ring[ring_index + 4]); 494 dw[5] = le32_to_cpu(ih->ring[ring_index + 5]); 495 dw[6] = le32_to_cpu(ih->ring[ring_index + 6]); 496 dw[7] = le32_to_cpu(ih->ring[ring_index + 7]); 497 498 entry->client_id = dw[0] & 0xff; 499 entry->src_id = (dw[0] >> 8) & 0xff; 500 entry->ring_id = (dw[0] >> 16) & 0xff; 501 entry->vmid = (dw[0] >> 24) & 0xf; 502 entry->vmid_src = (dw[0] >> 31); 503 entry->timestamp = dw[1] | ((u64)(dw[2] & 0xffff) << 32); 504 entry->timestamp_src = dw[2] >> 31; 505 entry->pasid = dw[3] & 0xffff; 506 entry->pasid_src = dw[3] >> 31; 507 entry->src_data[0] = dw[4]; 508 entry->src_data[1] = dw[5]; 509 entry->src_data[2] = dw[6]; 510 entry->src_data[3] = dw[7]; 511 512 /* wptr/rptr are in bytes! */ 513 ih->rptr += 32; 514 } 515 516 /** 517 * navi10_ih_irq_rearm - rearm IRQ if lost 518 * 519 * @adev: amdgpu_device pointer 520 * @ih: IH ring to match 521 * 522 */ 523 static void navi10_ih_irq_rearm(struct amdgpu_device *adev, 524 struct amdgpu_ih_ring *ih) 525 { 526 uint32_t reg_rptr = 0; 527 uint32_t v = 0; 528 uint32_t i = 0; 529 530 if (ih == &adev->irq.ih) 531 reg_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR); 532 else if (ih == &adev->irq.ih1) 533 reg_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR_RING1); 534 else if (ih == &adev->irq.ih2) 535 reg_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR_RING2); 536 else 537 return; 538 539 /* Rearm IRQ / re-write doorbell if doorbell write is lost */ 540 for (i = 0; i < MAX_REARM_RETRY; i++) { 541 v = RREG32_NO_KIQ(reg_rptr); 542 if ((v < ih->ring_size) && (v != ih->rptr)) 543 WDOORBELL32(ih->doorbell_index, ih->rptr); 544 else 545 break; 546 } 547 } 548 549 /** 550 * navi10_ih_set_rptr - set the IH ring buffer rptr 551 * 552 * @adev: amdgpu_device pointer 553 * 554 * @ih: IH ring buffer to set rptr 555 * Set the IH ring buffer rptr. 556 */ 557 static void navi10_ih_set_rptr(struct amdgpu_device *adev, 558 struct amdgpu_ih_ring *ih) 559 { 560 if (ih->use_doorbell) { 561 /* XXX check if swapping is necessary on BE */ 562 *ih->rptr_cpu = ih->rptr; 563 WDOORBELL32(ih->doorbell_index, ih->rptr); 564 565 if (amdgpu_sriov_vf(adev)) 566 navi10_ih_irq_rearm(adev, ih); 567 } else if (ih == &adev->irq.ih) { 568 WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR, ih->rptr); 569 } else if (ih == &adev->irq.ih1) { 570 WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR_RING1, ih->rptr); 571 } else if (ih == &adev->irq.ih2) { 572 WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR_RING2, ih->rptr); 573 } 574 } 575 576 /** 577 * navi10_ih_self_irq - dispatch work for ring 1 and 2 578 * 579 * @adev: amdgpu_device pointer 580 * @source: irq source 581 * @entry: IV with WPTR update 582 * 583 * Update the WPTR from the IV and schedule work to handle the entries. 584 */ 585 static int navi10_ih_self_irq(struct amdgpu_device *adev, 586 struct amdgpu_irq_src *source, 587 struct amdgpu_iv_entry *entry) 588 { 589 uint32_t wptr = cpu_to_le32(entry->src_data[0]); 590 591 switch (entry->ring_id) { 592 case 1: 593 *adev->irq.ih1.wptr_cpu = wptr; 594 schedule_work(&adev->irq.ih1_work); 595 break; 596 case 2: 597 *adev->irq.ih2.wptr_cpu = wptr; 598 schedule_work(&adev->irq.ih2_work); 599 break; 600 default: break; 601 } 602 return 0; 603 } 604 605 static const struct amdgpu_irq_src_funcs navi10_ih_self_irq_funcs = { 606 .process = navi10_ih_self_irq, 607 }; 608 609 static void navi10_ih_set_self_irq_funcs(struct amdgpu_device *adev) 610 { 611 adev->irq.self_irq.num_types = 0; 612 adev->irq.self_irq.funcs = &navi10_ih_self_irq_funcs; 613 } 614 615 static int navi10_ih_early_init(void *handle) 616 { 617 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 618 619 navi10_ih_set_interrupt_funcs(adev); 620 navi10_ih_set_self_irq_funcs(adev); 621 return 0; 622 } 623 624 static int navi10_ih_sw_init(void *handle) 625 { 626 int r; 627 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 628 bool use_bus_addr; 629 630 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_IH, 0, 631 &adev->irq.self_irq); 632 633 if (r) 634 return r; 635 636 /* use gpu virtual address for ih ring 637 * until ih_checken is programmed to allow 638 * use bus address for ih ring by psp bl */ 639 if ((adev->flags & AMD_IS_APU) || 640 (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) 641 use_bus_addr = false; 642 else 643 use_bus_addr = true; 644 r = amdgpu_ih_ring_init(adev, &adev->irq.ih, 256 * 1024, use_bus_addr); 645 if (r) 646 return r; 647 648 adev->irq.ih.use_doorbell = true; 649 adev->irq.ih.doorbell_index = adev->doorbell_index.ih << 1; 650 651 adev->irq.ih1.ring_size = 0; 652 adev->irq.ih2.ring_size = 0; 653 654 if (adev->asic_type < CHIP_NAVI10) { 655 r = amdgpu_ih_ring_init(adev, &adev->irq.ih1, PAGE_SIZE, true); 656 if (r) 657 return r; 658 659 adev->irq.ih1.use_doorbell = true; 660 adev->irq.ih1.doorbell_index = 661 (adev->doorbell_index.ih + 1) << 1; 662 663 r = amdgpu_ih_ring_init(adev, &adev->irq.ih2, PAGE_SIZE, true); 664 if (r) 665 return r; 666 667 adev->irq.ih2.use_doorbell = true; 668 adev->irq.ih2.doorbell_index = 669 (adev->doorbell_index.ih + 2) << 1; 670 } 671 672 /* initialize ih control registers offset */ 673 navi10_ih_init_register_offset(adev); 674 675 r = amdgpu_ih_ring_init(adev, &adev->irq.ih_soft, PAGE_SIZE, true); 676 if (r) 677 return r; 678 679 r = amdgpu_irq_init(adev); 680 681 return r; 682 } 683 684 static int navi10_ih_sw_fini(void *handle) 685 { 686 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 687 688 amdgpu_irq_fini(adev); 689 amdgpu_ih_ring_fini(adev, &adev->irq.ih2); 690 amdgpu_ih_ring_fini(adev, &adev->irq.ih1); 691 amdgpu_ih_ring_fini(adev, &adev->irq.ih); 692 693 return 0; 694 } 695 696 static int navi10_ih_hw_init(void *handle) 697 { 698 int r; 699 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 700 701 r = navi10_ih_irq_init(adev); 702 if (r) 703 return r; 704 705 return 0; 706 } 707 708 static int navi10_ih_hw_fini(void *handle) 709 { 710 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 711 712 navi10_ih_irq_disable(adev); 713 714 return 0; 715 } 716 717 static int navi10_ih_suspend(void *handle) 718 { 719 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 720 721 return navi10_ih_hw_fini(adev); 722 } 723 724 static int navi10_ih_resume(void *handle) 725 { 726 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 727 728 return navi10_ih_hw_init(adev); 729 } 730 731 static bool navi10_ih_is_idle(void *handle) 732 { 733 /* todo */ 734 return true; 735 } 736 737 static int navi10_ih_wait_for_idle(void *handle) 738 { 739 /* todo */ 740 return -ETIMEDOUT; 741 } 742 743 static int navi10_ih_soft_reset(void *handle) 744 { 745 /* todo */ 746 return 0; 747 } 748 749 static void navi10_ih_update_clockgating_state(struct amdgpu_device *adev, 750 bool enable) 751 { 752 uint32_t data, def, field_val; 753 754 if (adev->cg_flags & AMD_CG_SUPPORT_IH_CG) { 755 def = data = RREG32_SOC15(OSSSYS, 0, mmIH_CLK_CTRL); 756 field_val = enable ? 0 : 1; 757 data = REG_SET_FIELD(data, IH_CLK_CTRL, 758 DBUS_MUX_CLK_SOFT_OVERRIDE, field_val); 759 data = REG_SET_FIELD(data, IH_CLK_CTRL, 760 OSSSYS_SHARE_CLK_SOFT_OVERRIDE, field_val); 761 data = REG_SET_FIELD(data, IH_CLK_CTRL, 762 LIMIT_SMN_CLK_SOFT_OVERRIDE, field_val); 763 data = REG_SET_FIELD(data, IH_CLK_CTRL, 764 DYN_CLK_SOFT_OVERRIDE, field_val); 765 data = REG_SET_FIELD(data, IH_CLK_CTRL, 766 REG_CLK_SOFT_OVERRIDE, field_val); 767 if (def != data) 768 WREG32_SOC15(OSSSYS, 0, mmIH_CLK_CTRL, data); 769 } 770 771 return; 772 } 773 774 static int navi10_ih_set_clockgating_state(void *handle, 775 enum amd_clockgating_state state) 776 { 777 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 778 779 navi10_ih_update_clockgating_state(adev, 780 state == AMD_CG_STATE_GATE); 781 return 0; 782 } 783 784 static int navi10_ih_set_powergating_state(void *handle, 785 enum amd_powergating_state state) 786 { 787 return 0; 788 } 789 790 static void navi10_ih_get_clockgating_state(void *handle, u32 *flags) 791 { 792 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 793 794 if (!RREG32_SOC15(OSSSYS, 0, mmIH_CLK_CTRL)) 795 *flags |= AMD_CG_SUPPORT_IH_CG; 796 797 return; 798 } 799 800 static const struct amd_ip_funcs navi10_ih_ip_funcs = { 801 .name = "navi10_ih", 802 .early_init = navi10_ih_early_init, 803 .late_init = NULL, 804 .sw_init = navi10_ih_sw_init, 805 .sw_fini = navi10_ih_sw_fini, 806 .hw_init = navi10_ih_hw_init, 807 .hw_fini = navi10_ih_hw_fini, 808 .suspend = navi10_ih_suspend, 809 .resume = navi10_ih_resume, 810 .is_idle = navi10_ih_is_idle, 811 .wait_for_idle = navi10_ih_wait_for_idle, 812 .soft_reset = navi10_ih_soft_reset, 813 .set_clockgating_state = navi10_ih_set_clockgating_state, 814 .set_powergating_state = navi10_ih_set_powergating_state, 815 .get_clockgating_state = navi10_ih_get_clockgating_state, 816 }; 817 818 static const struct amdgpu_ih_funcs navi10_ih_funcs = { 819 .get_wptr = navi10_ih_get_wptr, 820 .decode_iv = navi10_ih_decode_iv, 821 .set_rptr = navi10_ih_set_rptr 822 }; 823 824 static void navi10_ih_set_interrupt_funcs(struct amdgpu_device *adev) 825 { 826 if (adev->irq.ih_funcs == NULL) 827 adev->irq.ih_funcs = &navi10_ih_funcs; 828 } 829 830 const struct amdgpu_ip_block_version navi10_ih_ip_block = 831 { 832 .type = AMD_IP_BLOCK_TYPE_IH, 833 .major = 5, 834 .minor = 0, 835 .rev = 0, 836 .funcs = &navi10_ih_ip_funcs, 837 }; 838