1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/pci.h> 25 26 #include "amdgpu.h" 27 #include "amdgpu_ih.h" 28 29 #include "oss/osssys_5_0_0_offset.h" 30 #include "oss/osssys_5_0_0_sh_mask.h" 31 32 #include "soc15_common.h" 33 #include "navi10_ih.h" 34 35 #define MAX_REARM_RETRY 10 36 37 #define mmIH_CHICKEN_Sienna_Cichlid 0x018d 38 #define mmIH_CHICKEN_Sienna_Cichlid_BASE_IDX 0 39 40 static void navi10_ih_set_interrupt_funcs(struct amdgpu_device *adev); 41 42 /** 43 * navi10_ih_init_register_offset - Initialize register offset for ih rings 44 * 45 * @adev: amdgpu_device pointer 46 * 47 * Initialize register offset ih rings (NAVI10). 48 */ 49 static void navi10_ih_init_register_offset(struct amdgpu_device *adev) 50 { 51 struct amdgpu_ih_regs *ih_regs; 52 53 if (adev->irq.ih.ring_size) { 54 ih_regs = &adev->irq.ih.ih_regs; 55 ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE); 56 ih_regs->ih_rb_base_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_HI); 57 ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL); 58 ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR); 59 ih_regs->ih_rb_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR); 60 ih_regs->ih_doorbell_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_DOORBELL_RPTR); 61 ih_regs->ih_rb_wptr_addr_lo = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_ADDR_LO); 62 ih_regs->ih_rb_wptr_addr_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_ADDR_HI); 63 ih_regs->psp_reg_id = PSP_REG_IH_RB_CNTL; 64 } 65 66 if (adev->irq.ih1.ring_size) { 67 ih_regs = &adev->irq.ih1.ih_regs; 68 ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_RING1); 69 ih_regs->ih_rb_base_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_HI_RING1); 70 ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL_RING1); 71 ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_RING1); 72 ih_regs->ih_rb_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR_RING1); 73 ih_regs->ih_doorbell_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_DOORBELL_RPTR_RING1); 74 ih_regs->psp_reg_id = PSP_REG_IH_RB_CNTL_RING1; 75 } 76 77 if (adev->irq.ih2.ring_size) { 78 ih_regs = &adev->irq.ih2.ih_regs; 79 ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_RING2); 80 ih_regs->ih_rb_base_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_HI_RING2); 81 ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL_RING2); 82 ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_RING2); 83 ih_regs->ih_rb_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR_RING2); 84 ih_regs->ih_doorbell_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_DOORBELL_RPTR_RING2); 85 ih_regs->psp_reg_id = PSP_REG_IH_RB_CNTL_RING2; 86 } 87 } 88 89 /** 90 * force_update_wptr_for_self_int - Force update the wptr for self interrupt 91 * 92 * @adev: amdgpu_device pointer 93 * @threshold: threshold to trigger the wptr reporting 94 * @timeout: timeout to trigger the wptr reporting 95 * @enabled: Enable/disable timeout flush mechanism 96 * 97 * threshold input range: 0 ~ 15, default 0, 98 * real_threshold = 2^threshold 99 * timeout input range: 0 ~ 20, default 8, 100 * real_timeout = (2^timeout) * 1024 / (socclk_freq) 101 * 102 * Force update wptr for self interrupt ( >= SIENNA_CICHLID). 103 */ 104 static void 105 force_update_wptr_for_self_int(struct amdgpu_device *adev, 106 u32 threshold, u32 timeout, bool enabled) 107 { 108 u32 ih_cntl, ih_rb_cntl; 109 110 if (adev->asic_type < CHIP_SIENNA_CICHLID) 111 return; 112 113 ih_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_CNTL2); 114 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1); 115 116 ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL2, 117 SELF_IV_FORCE_WPTR_UPDATE_TIMEOUT, timeout); 118 ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL2, 119 SELF_IV_FORCE_WPTR_UPDATE_ENABLE, enabled); 120 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING1, 121 RB_USED_INT_THRESHOLD, threshold); 122 123 WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1, ih_rb_cntl); 124 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2); 125 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING2, 126 RB_USED_INT_THRESHOLD, threshold); 127 WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2, ih_rb_cntl); 128 WREG32_SOC15(OSSSYS, 0, mmIH_CNTL2, ih_cntl); 129 } 130 131 /** 132 * navi10_ih_toggle_ring_interrupts - toggle the interrupt ring buffer 133 * 134 * @adev: amdgpu_device pointer 135 * @ih: amdgpu_ih_ring pointet 136 * @enable: true - enable the interrupts, false - disable the interrupts 137 * 138 * Toggle the interrupt ring buffer (NAVI10) 139 */ 140 static int navi10_ih_toggle_ring_interrupts(struct amdgpu_device *adev, 141 struct amdgpu_ih_ring *ih, 142 bool enable) 143 { 144 struct amdgpu_ih_regs *ih_regs; 145 uint32_t tmp; 146 147 ih_regs = &ih->ih_regs; 148 149 tmp = RREG32(ih_regs->ih_rb_cntl); 150 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RB_ENABLE, (enable ? 1 : 0)); 151 /* enable_intr field is only valid in ring0 */ 152 if (ih == &adev->irq.ih) 153 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, ENABLE_INTR, (enable ? 1 : 0)); 154 155 if (amdgpu_sriov_vf(adev) && amdgpu_sriov_reg_indirect_ih(adev)) { 156 if (psp_reg_program(&adev->psp, ih_regs->psp_reg_id, tmp)) { 157 DRM_ERROR("PSP program IH_RB_CNTL failed!\n"); 158 return -ETIMEDOUT; 159 } 160 } else { 161 WREG32(ih_regs->ih_rb_cntl, tmp); 162 } 163 164 if (enable) { 165 ih->enabled = true; 166 } else { 167 /* set rptr, wptr to 0 */ 168 WREG32(ih_regs->ih_rb_rptr, 0); 169 WREG32(ih_regs->ih_rb_wptr, 0); 170 ih->enabled = false; 171 ih->rptr = 0; 172 } 173 174 return 0; 175 } 176 177 /** 178 * navi10_ih_toggle_interrupts - Toggle all the available interrupt ring buffers 179 * 180 * @adev: amdgpu_device pointer 181 * @enable: enable or disable interrupt ring buffers 182 * 183 * Toggle all the available interrupt ring buffers (NAVI10). 184 */ 185 static int navi10_ih_toggle_interrupts(struct amdgpu_device *adev, bool enable) 186 { 187 struct amdgpu_ih_ring *ih[] = {&adev->irq.ih, &adev->irq.ih1, &adev->irq.ih2}; 188 int i; 189 int r; 190 191 for (i = 0; i < ARRAY_SIZE(ih); i++) { 192 if (ih[i]->ring_size) { 193 r = navi10_ih_toggle_ring_interrupts(adev, ih[i], enable); 194 if (r) 195 return r; 196 } 197 } 198 199 return 0; 200 } 201 202 static uint32_t navi10_ih_rb_cntl(struct amdgpu_ih_ring *ih, uint32_t ih_rb_cntl) 203 { 204 int rb_bufsz = order_base_2(ih->ring_size / 4); 205 206 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, 207 MC_SPACE, ih->use_bus_addr ? 1 : 4); 208 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, 209 WPTR_OVERFLOW_CLEAR, 1); 210 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, 211 WPTR_OVERFLOW_ENABLE, 1); 212 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_SIZE, rb_bufsz); 213 /* Ring Buffer write pointer writeback. If enabled, IH_RB_WPTR register 214 * value is written to memory 215 */ 216 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, 217 WPTR_WRITEBACK_ENABLE, 1); 218 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_SNOOP, 1); 219 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_RO, 0); 220 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_VMID, 0); 221 222 return ih_rb_cntl; 223 } 224 225 static uint32_t navi10_ih_doorbell_rptr(struct amdgpu_ih_ring *ih) 226 { 227 u32 ih_doorbell_rtpr = 0; 228 229 if (ih->use_doorbell) { 230 ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr, 231 IH_DOORBELL_RPTR, OFFSET, 232 ih->doorbell_index); 233 ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr, 234 IH_DOORBELL_RPTR, 235 ENABLE, 1); 236 } else { 237 ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr, 238 IH_DOORBELL_RPTR, 239 ENABLE, 0); 240 } 241 return ih_doorbell_rtpr; 242 } 243 244 /** 245 * navi10_ih_enable_ring - enable an ih ring buffer 246 * 247 * @adev: amdgpu_device pointer 248 * @ih: amdgpu_ih_ring pointer 249 * 250 * Enable an ih ring buffer (NAVI10) 251 */ 252 static int navi10_ih_enable_ring(struct amdgpu_device *adev, 253 struct amdgpu_ih_ring *ih) 254 { 255 struct amdgpu_ih_regs *ih_regs; 256 uint32_t tmp; 257 258 ih_regs = &ih->ih_regs; 259 260 /* Ring Buffer base. [39:8] of 40-bit address of the beginning of the ring buffer*/ 261 WREG32(ih_regs->ih_rb_base, ih->gpu_addr >> 8); 262 WREG32(ih_regs->ih_rb_base_hi, (ih->gpu_addr >> 40) & 0xff); 263 264 tmp = RREG32(ih_regs->ih_rb_cntl); 265 tmp = navi10_ih_rb_cntl(ih, tmp); 266 if (ih == &adev->irq.ih) 267 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RPTR_REARM, !!adev->irq.msi_enabled); 268 if (ih == &adev->irq.ih1) { 269 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_ENABLE, 0); 270 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RB_FULL_DRAIN_ENABLE, 1); 271 } 272 273 if (amdgpu_sriov_vf(adev) && amdgpu_sriov_reg_indirect_ih(adev)) { 274 if (psp_reg_program(&adev->psp, ih_regs->psp_reg_id, tmp)) { 275 DRM_ERROR("PSP program IH_RB_CNTL failed!\n"); 276 return -ETIMEDOUT; 277 } 278 } else { 279 WREG32(ih_regs->ih_rb_cntl, tmp); 280 } 281 282 if (ih == &adev->irq.ih) { 283 /* set the ih ring 0 writeback address whether it's enabled or not */ 284 WREG32(ih_regs->ih_rb_wptr_addr_lo, lower_32_bits(ih->wptr_addr)); 285 WREG32(ih_regs->ih_rb_wptr_addr_hi, upper_32_bits(ih->wptr_addr) & 0xFFFF); 286 } 287 288 /* set rptr, wptr to 0 */ 289 WREG32(ih_regs->ih_rb_wptr, 0); 290 WREG32(ih_regs->ih_rb_rptr, 0); 291 292 WREG32(ih_regs->ih_doorbell_rptr, navi10_ih_doorbell_rptr(ih)); 293 294 return 0; 295 } 296 297 /** 298 * navi10_ih_irq_init - init and enable the interrupt ring 299 * 300 * @adev: amdgpu_device pointer 301 * 302 * Allocate a ring buffer for the interrupt controller, 303 * enable the RLC, disable interrupts, enable the IH 304 * ring buffer and enable it (NAVI). 305 * Called at device load and reume. 306 * Returns 0 for success, errors for failure. 307 */ 308 static int navi10_ih_irq_init(struct amdgpu_device *adev) 309 { 310 struct amdgpu_ih_ring *ih[] = {&adev->irq.ih, &adev->irq.ih1, &adev->irq.ih2}; 311 u32 ih_chicken; 312 u32 tmp; 313 int ret; 314 int i; 315 316 /* disable irqs */ 317 ret = navi10_ih_toggle_interrupts(adev, false); 318 if (ret) 319 return ret; 320 321 adev->nbio.funcs->ih_control(adev); 322 323 if (unlikely(adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT)) { 324 if (ih[0]->use_bus_addr) { 325 switch (adev->asic_type) { 326 case CHIP_SIENNA_CICHLID: 327 case CHIP_NAVY_FLOUNDER: 328 case CHIP_VANGOGH: 329 case CHIP_DIMGREY_CAVEFISH: 330 case CHIP_BEIGE_GOBY: 331 case CHIP_YELLOW_CARP: 332 ih_chicken = RREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN_Sienna_Cichlid); 333 ih_chicken = REG_SET_FIELD(ih_chicken, 334 IH_CHICKEN, MC_SPACE_GPA_ENABLE, 1); 335 WREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN_Sienna_Cichlid, ih_chicken); 336 break; 337 default: 338 ih_chicken = RREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN); 339 ih_chicken = REG_SET_FIELD(ih_chicken, 340 IH_CHICKEN, MC_SPACE_GPA_ENABLE, 1); 341 WREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN, ih_chicken); 342 break; 343 } 344 } 345 } 346 347 for (i = 0; i < ARRAY_SIZE(ih); i++) { 348 if (ih[i]->ring_size) { 349 ret = navi10_ih_enable_ring(adev, ih[i]); 350 if (ret) 351 return ret; 352 } 353 } 354 355 /* update doorbell range for ih ring 0*/ 356 adev->nbio.funcs->ih_doorbell_range(adev, ih[0]->use_doorbell, 357 ih[0]->doorbell_index); 358 359 tmp = RREG32_SOC15(OSSSYS, 0, mmIH_STORM_CLIENT_LIST_CNTL); 360 tmp = REG_SET_FIELD(tmp, IH_STORM_CLIENT_LIST_CNTL, 361 CLIENT18_IS_STORM_CLIENT, 1); 362 WREG32_SOC15(OSSSYS, 0, mmIH_STORM_CLIENT_LIST_CNTL, tmp); 363 364 tmp = RREG32_SOC15(OSSSYS, 0, mmIH_INT_FLOOD_CNTL); 365 tmp = REG_SET_FIELD(tmp, IH_INT_FLOOD_CNTL, FLOOD_CNTL_ENABLE, 1); 366 WREG32_SOC15(OSSSYS, 0, mmIH_INT_FLOOD_CNTL, tmp); 367 368 pci_set_master(adev->pdev); 369 370 /* enable interrupts */ 371 ret = navi10_ih_toggle_interrupts(adev, true); 372 if (ret) 373 return ret; 374 /* enable wptr force update for self int */ 375 force_update_wptr_for_self_int(adev, 0, 8, true); 376 377 if (adev->irq.ih_soft.ring_size) 378 adev->irq.ih_soft.enabled = true; 379 380 return 0; 381 } 382 383 /** 384 * navi10_ih_irq_disable - disable interrupts 385 * 386 * @adev: amdgpu_device pointer 387 * 388 * Disable interrupts on the hw (NAVI10). 389 */ 390 static void navi10_ih_irq_disable(struct amdgpu_device *adev) 391 { 392 force_update_wptr_for_self_int(adev, 0, 8, false); 393 navi10_ih_toggle_interrupts(adev, false); 394 395 /* Wait and acknowledge irq */ 396 mdelay(1); 397 } 398 399 /** 400 * navi10_ih_get_wptr - get the IH ring buffer wptr 401 * 402 * @adev: amdgpu_device pointer 403 * @ih: IH ring buffer to fetch wptr 404 * 405 * Get the IH ring buffer wptr from either the register 406 * or the writeback memory buffer (NAVI10). Also check for 407 * ring buffer overflow and deal with it. 408 * Returns the value of the wptr. 409 */ 410 static u32 navi10_ih_get_wptr(struct amdgpu_device *adev, 411 struct amdgpu_ih_ring *ih) 412 { 413 u32 wptr, tmp; 414 struct amdgpu_ih_regs *ih_regs; 415 416 wptr = le32_to_cpu(*ih->wptr_cpu); 417 ih_regs = &ih->ih_regs; 418 419 if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) 420 goto out; 421 422 wptr = RREG32_NO_KIQ(ih_regs->ih_rb_wptr); 423 if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) 424 goto out; 425 wptr = REG_SET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW, 0); 426 427 /* When a ring buffer overflow happen start parsing interrupt 428 * from the last not overwritten vector (wptr + 32). Hopefully 429 * this should allow us to catch up. 430 */ 431 tmp = (wptr + 32) & ih->ptr_mask; 432 dev_warn(adev->dev, "IH ring buffer overflow " 433 "(0x%08X, 0x%08X, 0x%08X)\n", 434 wptr, ih->rptr, tmp); 435 ih->rptr = tmp; 436 437 tmp = RREG32_NO_KIQ(ih_regs->ih_rb_cntl); 438 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1); 439 WREG32_NO_KIQ(ih_regs->ih_rb_cntl, tmp); 440 out: 441 return (wptr & ih->ptr_mask); 442 } 443 444 /** 445 * navi10_ih_irq_rearm - rearm IRQ if lost 446 * 447 * @adev: amdgpu_device pointer 448 * @ih: IH ring to match 449 * 450 */ 451 static void navi10_ih_irq_rearm(struct amdgpu_device *adev, 452 struct amdgpu_ih_ring *ih) 453 { 454 uint32_t v = 0; 455 uint32_t i = 0; 456 struct amdgpu_ih_regs *ih_regs; 457 458 ih_regs = &ih->ih_regs; 459 460 /* Rearm IRQ / re-write doorbell if doorbell write is lost */ 461 for (i = 0; i < MAX_REARM_RETRY; i++) { 462 v = RREG32_NO_KIQ(ih_regs->ih_rb_rptr); 463 if ((v < ih->ring_size) && (v != ih->rptr)) 464 WDOORBELL32(ih->doorbell_index, ih->rptr); 465 else 466 break; 467 } 468 } 469 470 /** 471 * navi10_ih_set_rptr - set the IH ring buffer rptr 472 * 473 * @adev: amdgpu_device pointer 474 * 475 * @ih: IH ring buffer to set rptr 476 * Set the IH ring buffer rptr. 477 */ 478 static void navi10_ih_set_rptr(struct amdgpu_device *adev, 479 struct amdgpu_ih_ring *ih) 480 { 481 struct amdgpu_ih_regs *ih_regs; 482 483 if (ih->use_doorbell) { 484 /* XXX check if swapping is necessary on BE */ 485 *ih->rptr_cpu = ih->rptr; 486 WDOORBELL32(ih->doorbell_index, ih->rptr); 487 488 if (amdgpu_sriov_vf(adev)) 489 navi10_ih_irq_rearm(adev, ih); 490 } else { 491 ih_regs = &ih->ih_regs; 492 WREG32(ih_regs->ih_rb_rptr, ih->rptr); 493 } 494 } 495 496 /** 497 * navi10_ih_self_irq - dispatch work for ring 1 and 2 498 * 499 * @adev: amdgpu_device pointer 500 * @source: irq source 501 * @entry: IV with WPTR update 502 * 503 * Update the WPTR from the IV and schedule work to handle the entries. 504 */ 505 static int navi10_ih_self_irq(struct amdgpu_device *adev, 506 struct amdgpu_irq_src *source, 507 struct amdgpu_iv_entry *entry) 508 { 509 uint32_t wptr = cpu_to_le32(entry->src_data[0]); 510 511 switch (entry->ring_id) { 512 case 1: 513 *adev->irq.ih1.wptr_cpu = wptr; 514 schedule_work(&adev->irq.ih1_work); 515 break; 516 case 2: 517 *adev->irq.ih2.wptr_cpu = wptr; 518 schedule_work(&adev->irq.ih2_work); 519 break; 520 default: break; 521 } 522 return 0; 523 } 524 525 static const struct amdgpu_irq_src_funcs navi10_ih_self_irq_funcs = { 526 .process = navi10_ih_self_irq, 527 }; 528 529 static void navi10_ih_set_self_irq_funcs(struct amdgpu_device *adev) 530 { 531 adev->irq.self_irq.num_types = 0; 532 adev->irq.self_irq.funcs = &navi10_ih_self_irq_funcs; 533 } 534 535 static int navi10_ih_early_init(void *handle) 536 { 537 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 538 539 navi10_ih_set_interrupt_funcs(adev); 540 navi10_ih_set_self_irq_funcs(adev); 541 return 0; 542 } 543 544 static int navi10_ih_sw_init(void *handle) 545 { 546 int r; 547 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 548 bool use_bus_addr; 549 550 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_IH, 0, 551 &adev->irq.self_irq); 552 553 if (r) 554 return r; 555 556 /* use gpu virtual address for ih ring 557 * until ih_checken is programmed to allow 558 * use bus address for ih ring by psp bl */ 559 if ((adev->flags & AMD_IS_APU) || 560 (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) 561 use_bus_addr = false; 562 else 563 use_bus_addr = true; 564 r = amdgpu_ih_ring_init(adev, &adev->irq.ih, 256 * 1024, use_bus_addr); 565 if (r) 566 return r; 567 568 adev->irq.ih.use_doorbell = true; 569 adev->irq.ih.doorbell_index = adev->doorbell_index.ih << 1; 570 571 adev->irq.ih1.ring_size = 0; 572 adev->irq.ih2.ring_size = 0; 573 574 /* initialize ih control registers offset */ 575 navi10_ih_init_register_offset(adev); 576 577 r = amdgpu_ih_ring_init(adev, &adev->irq.ih_soft, PAGE_SIZE, true); 578 if (r) 579 return r; 580 581 r = amdgpu_irq_init(adev); 582 583 return r; 584 } 585 586 static int navi10_ih_sw_fini(void *handle) 587 { 588 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 589 590 amdgpu_irq_fini_sw(adev); 591 592 return 0; 593 } 594 595 static int navi10_ih_hw_init(void *handle) 596 { 597 int r; 598 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 599 600 r = navi10_ih_irq_init(adev); 601 if (r) 602 return r; 603 604 return 0; 605 } 606 607 static int navi10_ih_hw_fini(void *handle) 608 { 609 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 610 611 navi10_ih_irq_disable(adev); 612 613 return 0; 614 } 615 616 static int navi10_ih_suspend(void *handle) 617 { 618 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 619 620 return navi10_ih_hw_fini(adev); 621 } 622 623 static int navi10_ih_resume(void *handle) 624 { 625 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 626 627 return navi10_ih_hw_init(adev); 628 } 629 630 static bool navi10_ih_is_idle(void *handle) 631 { 632 /* todo */ 633 return true; 634 } 635 636 static int navi10_ih_wait_for_idle(void *handle) 637 { 638 /* todo */ 639 return -ETIMEDOUT; 640 } 641 642 static int navi10_ih_soft_reset(void *handle) 643 { 644 /* todo */ 645 return 0; 646 } 647 648 static void navi10_ih_update_clockgating_state(struct amdgpu_device *adev, 649 bool enable) 650 { 651 uint32_t data, def, field_val; 652 653 if (adev->cg_flags & AMD_CG_SUPPORT_IH_CG) { 654 def = data = RREG32_SOC15(OSSSYS, 0, mmIH_CLK_CTRL); 655 field_val = enable ? 0 : 1; 656 data = REG_SET_FIELD(data, IH_CLK_CTRL, 657 DBUS_MUX_CLK_SOFT_OVERRIDE, field_val); 658 data = REG_SET_FIELD(data, IH_CLK_CTRL, 659 OSSSYS_SHARE_CLK_SOFT_OVERRIDE, field_val); 660 data = REG_SET_FIELD(data, IH_CLK_CTRL, 661 LIMIT_SMN_CLK_SOFT_OVERRIDE, field_val); 662 data = REG_SET_FIELD(data, IH_CLK_CTRL, 663 DYN_CLK_SOFT_OVERRIDE, field_val); 664 data = REG_SET_FIELD(data, IH_CLK_CTRL, 665 REG_CLK_SOFT_OVERRIDE, field_val); 666 if (def != data) 667 WREG32_SOC15(OSSSYS, 0, mmIH_CLK_CTRL, data); 668 } 669 670 return; 671 } 672 673 static int navi10_ih_set_clockgating_state(void *handle, 674 enum amd_clockgating_state state) 675 { 676 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 677 678 navi10_ih_update_clockgating_state(adev, 679 state == AMD_CG_STATE_GATE); 680 return 0; 681 } 682 683 static int navi10_ih_set_powergating_state(void *handle, 684 enum amd_powergating_state state) 685 { 686 return 0; 687 } 688 689 static void navi10_ih_get_clockgating_state(void *handle, u32 *flags) 690 { 691 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 692 693 if (!RREG32_SOC15(OSSSYS, 0, mmIH_CLK_CTRL)) 694 *flags |= AMD_CG_SUPPORT_IH_CG; 695 696 return; 697 } 698 699 static const struct amd_ip_funcs navi10_ih_ip_funcs = { 700 .name = "navi10_ih", 701 .early_init = navi10_ih_early_init, 702 .late_init = NULL, 703 .sw_init = navi10_ih_sw_init, 704 .sw_fini = navi10_ih_sw_fini, 705 .hw_init = navi10_ih_hw_init, 706 .hw_fini = navi10_ih_hw_fini, 707 .suspend = navi10_ih_suspend, 708 .resume = navi10_ih_resume, 709 .is_idle = navi10_ih_is_idle, 710 .wait_for_idle = navi10_ih_wait_for_idle, 711 .soft_reset = navi10_ih_soft_reset, 712 .set_clockgating_state = navi10_ih_set_clockgating_state, 713 .set_powergating_state = navi10_ih_set_powergating_state, 714 .get_clockgating_state = navi10_ih_get_clockgating_state, 715 }; 716 717 static const struct amdgpu_ih_funcs navi10_ih_funcs = { 718 .get_wptr = navi10_ih_get_wptr, 719 .decode_iv = amdgpu_ih_decode_iv_helper, 720 .set_rptr = navi10_ih_set_rptr 721 }; 722 723 static void navi10_ih_set_interrupt_funcs(struct amdgpu_device *adev) 724 { 725 if (adev->irq.ih_funcs == NULL) 726 adev->irq.ih_funcs = &navi10_ih_funcs; 727 } 728 729 const struct amdgpu_ip_block_version navi10_ih_ip_block = 730 { 731 .type = AMD_IP_BLOCK_TYPE_IH, 732 .major = 5, 733 .minor = 0, 734 .rev = 0, 735 .funcs = &navi10_ih_ip_funcs, 736 }; 737