1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/pci.h> 25 26 #include "amdgpu.h" 27 #include "amdgpu_ih.h" 28 29 #include "oss/osssys_5_0_0_offset.h" 30 #include "oss/osssys_5_0_0_sh_mask.h" 31 32 #include "soc15_common.h" 33 #include "navi10_ih.h" 34 35 #define MAX_REARM_RETRY 10 36 37 #define mmIH_CHICKEN_Sienna_Cichlid 0x018d 38 #define mmIH_CHICKEN_Sienna_Cichlid_BASE_IDX 0 39 40 static void navi10_ih_set_interrupt_funcs(struct amdgpu_device *adev); 41 42 /** 43 * navi10_ih_init_register_offset - Initialize register offset for ih rings 44 * 45 * @adev: amdgpu_device pointer 46 * 47 * Initialize register offset ih rings (NAVI10). 48 */ 49 static void navi10_ih_init_register_offset(struct amdgpu_device *adev) 50 { 51 struct amdgpu_ih_regs *ih_regs; 52 53 if (adev->irq.ih.ring_size) { 54 ih_regs = &adev->irq.ih.ih_regs; 55 ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE); 56 ih_regs->ih_rb_base_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_HI); 57 ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL); 58 ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR); 59 ih_regs->ih_rb_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR); 60 ih_regs->ih_doorbell_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_DOORBELL_RPTR); 61 ih_regs->ih_rb_wptr_addr_lo = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_ADDR_LO); 62 ih_regs->ih_rb_wptr_addr_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_ADDR_HI); 63 ih_regs->psp_reg_id = PSP_REG_IH_RB_CNTL; 64 } 65 66 if (adev->irq.ih1.ring_size) { 67 ih_regs = &adev->irq.ih1.ih_regs; 68 ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_RING1); 69 ih_regs->ih_rb_base_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_HI_RING1); 70 ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL_RING1); 71 ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_RING1); 72 ih_regs->ih_rb_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR_RING1); 73 ih_regs->ih_doorbell_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_DOORBELL_RPTR_RING1); 74 ih_regs->psp_reg_id = PSP_REG_IH_RB_CNTL_RING1; 75 } 76 77 if (adev->irq.ih2.ring_size) { 78 ih_regs = &adev->irq.ih2.ih_regs; 79 ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_RING2); 80 ih_regs->ih_rb_base_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_HI_RING2); 81 ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL_RING2); 82 ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_RING2); 83 ih_regs->ih_rb_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR_RING2); 84 ih_regs->ih_doorbell_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_DOORBELL_RPTR_RING2); 85 ih_regs->psp_reg_id = PSP_REG_IH_RB_CNTL_RING2; 86 } 87 } 88 89 /** 90 * force_update_wptr_for_self_int - Force update the wptr for self interrupt 91 * 92 * @adev: amdgpu_device pointer 93 * @threshold: threshold to trigger the wptr reporting 94 * @timeout: timeout to trigger the wptr reporting 95 * @enabled: Enable/disable timeout flush mechanism 96 * 97 * threshold input range: 0 ~ 15, default 0, 98 * real_threshold = 2^threshold 99 * timeout input range: 0 ~ 20, default 8, 100 * real_timeout = (2^timeout) * 1024 / (socclk_freq) 101 * 102 * Force update wptr for self interrupt ( >= SIENNA_CICHLID). 103 */ 104 static void 105 force_update_wptr_for_self_int(struct amdgpu_device *adev, 106 u32 threshold, u32 timeout, bool enabled) 107 { 108 u32 ih_cntl, ih_rb_cntl; 109 110 if (adev->asic_type < CHIP_SIENNA_CICHLID) 111 return; 112 113 ih_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_CNTL2); 114 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1); 115 116 ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL2, 117 SELF_IV_FORCE_WPTR_UPDATE_TIMEOUT, timeout); 118 ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL2, 119 SELF_IV_FORCE_WPTR_UPDATE_ENABLE, enabled); 120 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING1, 121 RB_USED_INT_THRESHOLD, threshold); 122 123 WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1, ih_rb_cntl); 124 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2); 125 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING2, 126 RB_USED_INT_THRESHOLD, threshold); 127 WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2, ih_rb_cntl); 128 WREG32_SOC15(OSSSYS, 0, mmIH_CNTL2, ih_cntl); 129 } 130 131 /** 132 * navi10_ih_toggle_ring_interrupts - toggle the interrupt ring buffer 133 * 134 * @adev: amdgpu_device pointer 135 * @ih: amdgpu_ih_ring pointet 136 * @enable: true - enable the interrupts, false - disable the interrupts 137 * 138 * Toggle the interrupt ring buffer (NAVI10) 139 */ 140 static int navi10_ih_toggle_ring_interrupts(struct amdgpu_device *adev, 141 struct amdgpu_ih_ring *ih, 142 bool enable) 143 { 144 struct amdgpu_ih_regs *ih_regs; 145 uint32_t tmp; 146 147 ih_regs = &ih->ih_regs; 148 149 tmp = RREG32(ih_regs->ih_rb_cntl); 150 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RB_ENABLE, (enable ? 1 : 0)); 151 /* enable_intr field is only valid in ring0 */ 152 if (ih == &adev->irq.ih) 153 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, ENABLE_INTR, (enable ? 1 : 0)); 154 WREG32(ih_regs->ih_rb_cntl, tmp); 155 156 if (enable) { 157 ih->enabled = true; 158 } else { 159 /* set rptr, wptr to 0 */ 160 WREG32(ih_regs->ih_rb_rptr, 0); 161 WREG32(ih_regs->ih_rb_wptr, 0); 162 ih->enabled = false; 163 ih->rptr = 0; 164 } 165 166 return 0; 167 } 168 169 /** 170 * navi10_ih_toggle_interrupts - Toggle all the available interrupt ring buffers 171 * 172 * @adev: amdgpu_device pointer 173 * @enable: enable or disable interrupt ring buffers 174 * 175 * Toggle all the available interrupt ring buffers (NAVI10). 176 */ 177 static int navi10_ih_toggle_interrupts(struct amdgpu_device *adev, bool enable) 178 { 179 struct amdgpu_ih_ring *ih[] = {&adev->irq.ih, &adev->irq.ih1, &adev->irq.ih2}; 180 int i; 181 int r; 182 183 for (i = 0; i < ARRAY_SIZE(ih); i++) { 184 if (ih[i]->ring_size) { 185 r = navi10_ih_toggle_ring_interrupts(adev, ih[i], enable); 186 if (r) 187 return r; 188 } 189 } 190 191 return 0; 192 } 193 194 static uint32_t navi10_ih_rb_cntl(struct amdgpu_ih_ring *ih, uint32_t ih_rb_cntl) 195 { 196 int rb_bufsz = order_base_2(ih->ring_size / 4); 197 198 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, 199 MC_SPACE, ih->use_bus_addr ? 1 : 4); 200 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, 201 WPTR_OVERFLOW_CLEAR, 1); 202 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, 203 WPTR_OVERFLOW_ENABLE, 1); 204 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_SIZE, rb_bufsz); 205 /* Ring Buffer write pointer writeback. If enabled, IH_RB_WPTR register 206 * value is written to memory 207 */ 208 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, 209 WPTR_WRITEBACK_ENABLE, 1); 210 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_SNOOP, 1); 211 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_RO, 0); 212 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_VMID, 0); 213 214 return ih_rb_cntl; 215 } 216 217 static uint32_t navi10_ih_doorbell_rptr(struct amdgpu_ih_ring *ih) 218 { 219 u32 ih_doorbell_rtpr = 0; 220 221 if (ih->use_doorbell) { 222 ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr, 223 IH_DOORBELL_RPTR, OFFSET, 224 ih->doorbell_index); 225 ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr, 226 IH_DOORBELL_RPTR, 227 ENABLE, 1); 228 } else { 229 ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr, 230 IH_DOORBELL_RPTR, 231 ENABLE, 0); 232 } 233 return ih_doorbell_rtpr; 234 } 235 236 /** 237 * navi10_ih_enable_ring - enable an ih ring buffer 238 * 239 * @adev: amdgpu_device pointer 240 * @ih: amdgpu_ih_ring pointer 241 * 242 * Enable an ih ring buffer (NAVI10) 243 */ 244 static int navi10_ih_enable_ring(struct amdgpu_device *adev, 245 struct amdgpu_ih_ring *ih) 246 { 247 struct amdgpu_ih_regs *ih_regs; 248 uint32_t tmp; 249 250 ih_regs = &ih->ih_regs; 251 252 /* Ring Buffer base. [39:8] of 40-bit address of the beginning of the ring buffer*/ 253 WREG32(ih_regs->ih_rb_base, ih->gpu_addr >> 8); 254 WREG32(ih_regs->ih_rb_base_hi, (ih->gpu_addr >> 40) & 0xff); 255 256 tmp = RREG32(ih_regs->ih_rb_cntl); 257 tmp = navi10_ih_rb_cntl(ih, tmp); 258 if (ih == &adev->irq.ih) 259 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RPTR_REARM, !!adev->irq.msi_enabled); 260 if (ih == &adev->irq.ih1) { 261 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_ENABLE, 0); 262 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RB_FULL_DRAIN_ENABLE, 1); 263 } 264 WREG32(ih_regs->ih_rb_cntl, tmp); 265 266 if (ih == &adev->irq.ih) { 267 /* set the ih ring 0 writeback address whether it's enabled or not */ 268 WREG32(ih_regs->ih_rb_wptr_addr_lo, lower_32_bits(ih->wptr_addr)); 269 WREG32(ih_regs->ih_rb_wptr_addr_hi, upper_32_bits(ih->wptr_addr) & 0xFFFF); 270 } 271 272 /* set rptr, wptr to 0 */ 273 WREG32(ih_regs->ih_rb_wptr, 0); 274 WREG32(ih_regs->ih_rb_rptr, 0); 275 276 WREG32(ih_regs->ih_doorbell_rptr, navi10_ih_doorbell_rptr(ih)); 277 278 return 0; 279 } 280 281 /** 282 * navi10_ih_irq_init - init and enable the interrupt ring 283 * 284 * @adev: amdgpu_device pointer 285 * 286 * Allocate a ring buffer for the interrupt controller, 287 * enable the RLC, disable interrupts, enable the IH 288 * ring buffer and enable it (NAVI). 289 * Called at device load and reume. 290 * Returns 0 for success, errors for failure. 291 */ 292 static int navi10_ih_irq_init(struct amdgpu_device *adev) 293 { 294 struct amdgpu_ih_ring *ih[] = {&adev->irq.ih, &adev->irq.ih1, &adev->irq.ih2}; 295 u32 ih_chicken; 296 u32 tmp; 297 int ret; 298 int i; 299 300 /* disable irqs */ 301 ret = navi10_ih_toggle_interrupts(adev, false); 302 if (ret) 303 return ret; 304 305 adev->nbio.funcs->ih_control(adev); 306 307 if (unlikely(adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT)) { 308 if (ih[0]->use_bus_addr) { 309 switch (adev->asic_type) { 310 case CHIP_SIENNA_CICHLID: 311 case CHIP_NAVY_FLOUNDER: 312 case CHIP_VANGOGH: 313 case CHIP_DIMGREY_CAVEFISH: 314 case CHIP_BEIGE_GOBY: 315 ih_chicken = RREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN_Sienna_Cichlid); 316 ih_chicken = REG_SET_FIELD(ih_chicken, 317 IH_CHICKEN, MC_SPACE_GPA_ENABLE, 1); 318 WREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN_Sienna_Cichlid, ih_chicken); 319 break; 320 default: 321 ih_chicken = RREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN); 322 ih_chicken = REG_SET_FIELD(ih_chicken, 323 IH_CHICKEN, MC_SPACE_GPA_ENABLE, 1); 324 WREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN, ih_chicken); 325 break; 326 } 327 } 328 } 329 330 for (i = 0; i < ARRAY_SIZE(ih); i++) { 331 if (ih[i]->ring_size) { 332 ret = navi10_ih_enable_ring(adev, ih[i]); 333 if (ret) 334 return ret; 335 } 336 } 337 338 /* update doorbell range for ih ring 0*/ 339 adev->nbio.funcs->ih_doorbell_range(adev, ih[0]->use_doorbell, 340 ih[0]->doorbell_index); 341 342 tmp = RREG32_SOC15(OSSSYS, 0, mmIH_STORM_CLIENT_LIST_CNTL); 343 tmp = REG_SET_FIELD(tmp, IH_STORM_CLIENT_LIST_CNTL, 344 CLIENT18_IS_STORM_CLIENT, 1); 345 WREG32_SOC15(OSSSYS, 0, mmIH_STORM_CLIENT_LIST_CNTL, tmp); 346 347 tmp = RREG32_SOC15(OSSSYS, 0, mmIH_INT_FLOOD_CNTL); 348 tmp = REG_SET_FIELD(tmp, IH_INT_FLOOD_CNTL, FLOOD_CNTL_ENABLE, 1); 349 WREG32_SOC15(OSSSYS, 0, mmIH_INT_FLOOD_CNTL, tmp); 350 351 pci_set_master(adev->pdev); 352 353 /* enable interrupts */ 354 ret = navi10_ih_toggle_interrupts(adev, true); 355 if (ret) 356 return ret; 357 /* enable wptr force update for self int */ 358 force_update_wptr_for_self_int(adev, 0, 8, true); 359 360 if (adev->irq.ih_soft.ring_size) 361 adev->irq.ih_soft.enabled = true; 362 363 return 0; 364 } 365 366 /** 367 * navi10_ih_irq_disable - disable interrupts 368 * 369 * @adev: amdgpu_device pointer 370 * 371 * Disable interrupts on the hw (NAVI10). 372 */ 373 static void navi10_ih_irq_disable(struct amdgpu_device *adev) 374 { 375 force_update_wptr_for_self_int(adev, 0, 8, false); 376 navi10_ih_toggle_interrupts(adev, false); 377 378 /* Wait and acknowledge irq */ 379 mdelay(1); 380 } 381 382 /** 383 * navi10_ih_get_wptr - get the IH ring buffer wptr 384 * 385 * @adev: amdgpu_device pointer 386 * @ih: IH ring buffer to fetch wptr 387 * 388 * Get the IH ring buffer wptr from either the register 389 * or the writeback memory buffer (NAVI10). Also check for 390 * ring buffer overflow and deal with it. 391 * Returns the value of the wptr. 392 */ 393 static u32 navi10_ih_get_wptr(struct amdgpu_device *adev, 394 struct amdgpu_ih_ring *ih) 395 { 396 u32 wptr, tmp; 397 struct amdgpu_ih_regs *ih_regs; 398 399 wptr = le32_to_cpu(*ih->wptr_cpu); 400 ih_regs = &ih->ih_regs; 401 402 if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) 403 goto out; 404 405 wptr = RREG32_NO_KIQ(ih_regs->ih_rb_wptr); 406 if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) 407 goto out; 408 wptr = REG_SET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW, 0); 409 410 /* When a ring buffer overflow happen start parsing interrupt 411 * from the last not overwritten vector (wptr + 32). Hopefully 412 * this should allow us to catch up. 413 */ 414 tmp = (wptr + 32) & ih->ptr_mask; 415 dev_warn(adev->dev, "IH ring buffer overflow " 416 "(0x%08X, 0x%08X, 0x%08X)\n", 417 wptr, ih->rptr, tmp); 418 ih->rptr = tmp; 419 420 tmp = RREG32_NO_KIQ(ih_regs->ih_rb_cntl); 421 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1); 422 WREG32_NO_KIQ(ih_regs->ih_rb_cntl, tmp); 423 out: 424 return (wptr & ih->ptr_mask); 425 } 426 427 /** 428 * navi10_ih_irq_rearm - rearm IRQ if lost 429 * 430 * @adev: amdgpu_device pointer 431 * @ih: IH ring to match 432 * 433 */ 434 static void navi10_ih_irq_rearm(struct amdgpu_device *adev, 435 struct amdgpu_ih_ring *ih) 436 { 437 uint32_t v = 0; 438 uint32_t i = 0; 439 struct amdgpu_ih_regs *ih_regs; 440 441 ih_regs = &ih->ih_regs; 442 443 /* Rearm IRQ / re-write doorbell if doorbell write is lost */ 444 for (i = 0; i < MAX_REARM_RETRY; i++) { 445 v = RREG32_NO_KIQ(ih_regs->ih_rb_rptr); 446 if ((v < ih->ring_size) && (v != ih->rptr)) 447 WDOORBELL32(ih->doorbell_index, ih->rptr); 448 else 449 break; 450 } 451 } 452 453 /** 454 * navi10_ih_set_rptr - set the IH ring buffer rptr 455 * 456 * @adev: amdgpu_device pointer 457 * 458 * @ih: IH ring buffer to set rptr 459 * Set the IH ring buffer rptr. 460 */ 461 static void navi10_ih_set_rptr(struct amdgpu_device *adev, 462 struct amdgpu_ih_ring *ih) 463 { 464 struct amdgpu_ih_regs *ih_regs; 465 466 if (ih->use_doorbell) { 467 /* XXX check if swapping is necessary on BE */ 468 *ih->rptr_cpu = ih->rptr; 469 WDOORBELL32(ih->doorbell_index, ih->rptr); 470 471 if (amdgpu_sriov_vf(adev)) 472 navi10_ih_irq_rearm(adev, ih); 473 } else { 474 ih_regs = &ih->ih_regs; 475 WREG32(ih_regs->ih_rb_rptr, ih->rptr); 476 } 477 } 478 479 /** 480 * navi10_ih_self_irq - dispatch work for ring 1 and 2 481 * 482 * @adev: amdgpu_device pointer 483 * @source: irq source 484 * @entry: IV with WPTR update 485 * 486 * Update the WPTR from the IV and schedule work to handle the entries. 487 */ 488 static int navi10_ih_self_irq(struct amdgpu_device *adev, 489 struct amdgpu_irq_src *source, 490 struct amdgpu_iv_entry *entry) 491 { 492 uint32_t wptr = cpu_to_le32(entry->src_data[0]); 493 494 switch (entry->ring_id) { 495 case 1: 496 *adev->irq.ih1.wptr_cpu = wptr; 497 schedule_work(&adev->irq.ih1_work); 498 break; 499 case 2: 500 *adev->irq.ih2.wptr_cpu = wptr; 501 schedule_work(&adev->irq.ih2_work); 502 break; 503 default: break; 504 } 505 return 0; 506 } 507 508 static const struct amdgpu_irq_src_funcs navi10_ih_self_irq_funcs = { 509 .process = navi10_ih_self_irq, 510 }; 511 512 static void navi10_ih_set_self_irq_funcs(struct amdgpu_device *adev) 513 { 514 adev->irq.self_irq.num_types = 0; 515 adev->irq.self_irq.funcs = &navi10_ih_self_irq_funcs; 516 } 517 518 static int navi10_ih_early_init(void *handle) 519 { 520 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 521 522 navi10_ih_set_interrupt_funcs(adev); 523 navi10_ih_set_self_irq_funcs(adev); 524 return 0; 525 } 526 527 static int navi10_ih_sw_init(void *handle) 528 { 529 int r; 530 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 531 bool use_bus_addr; 532 533 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_IH, 0, 534 &adev->irq.self_irq); 535 536 if (r) 537 return r; 538 539 /* use gpu virtual address for ih ring 540 * until ih_checken is programmed to allow 541 * use bus address for ih ring by psp bl */ 542 if ((adev->flags & AMD_IS_APU) || 543 (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) 544 use_bus_addr = false; 545 else 546 use_bus_addr = true; 547 r = amdgpu_ih_ring_init(adev, &adev->irq.ih, 256 * 1024, use_bus_addr); 548 if (r) 549 return r; 550 551 adev->irq.ih.use_doorbell = true; 552 adev->irq.ih.doorbell_index = adev->doorbell_index.ih << 1; 553 554 adev->irq.ih1.ring_size = 0; 555 adev->irq.ih2.ring_size = 0; 556 557 /* initialize ih control registers offset */ 558 navi10_ih_init_register_offset(adev); 559 560 r = amdgpu_ih_ring_init(adev, &adev->irq.ih_soft, PAGE_SIZE, true); 561 if (r) 562 return r; 563 564 r = amdgpu_irq_init(adev); 565 566 return r; 567 } 568 569 static int navi10_ih_sw_fini(void *handle) 570 { 571 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 572 573 amdgpu_irq_fini(adev); 574 amdgpu_ih_ring_fini(adev, &adev->irq.ih_soft); 575 amdgpu_ih_ring_fini(adev, &adev->irq.ih2); 576 amdgpu_ih_ring_fini(adev, &adev->irq.ih1); 577 amdgpu_ih_ring_fini(adev, &adev->irq.ih); 578 579 return 0; 580 } 581 582 static int navi10_ih_hw_init(void *handle) 583 { 584 int r; 585 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 586 587 r = navi10_ih_irq_init(adev); 588 if (r) 589 return r; 590 591 return 0; 592 } 593 594 static int navi10_ih_hw_fini(void *handle) 595 { 596 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 597 598 navi10_ih_irq_disable(adev); 599 600 return 0; 601 } 602 603 static int navi10_ih_suspend(void *handle) 604 { 605 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 606 607 return navi10_ih_hw_fini(adev); 608 } 609 610 static int navi10_ih_resume(void *handle) 611 { 612 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 613 614 return navi10_ih_hw_init(adev); 615 } 616 617 static bool navi10_ih_is_idle(void *handle) 618 { 619 /* todo */ 620 return true; 621 } 622 623 static int navi10_ih_wait_for_idle(void *handle) 624 { 625 /* todo */ 626 return -ETIMEDOUT; 627 } 628 629 static int navi10_ih_soft_reset(void *handle) 630 { 631 /* todo */ 632 return 0; 633 } 634 635 static void navi10_ih_update_clockgating_state(struct amdgpu_device *adev, 636 bool enable) 637 { 638 uint32_t data, def, field_val; 639 640 if (adev->cg_flags & AMD_CG_SUPPORT_IH_CG) { 641 def = data = RREG32_SOC15(OSSSYS, 0, mmIH_CLK_CTRL); 642 field_val = enable ? 0 : 1; 643 data = REG_SET_FIELD(data, IH_CLK_CTRL, 644 DBUS_MUX_CLK_SOFT_OVERRIDE, field_val); 645 data = REG_SET_FIELD(data, IH_CLK_CTRL, 646 OSSSYS_SHARE_CLK_SOFT_OVERRIDE, field_val); 647 data = REG_SET_FIELD(data, IH_CLK_CTRL, 648 LIMIT_SMN_CLK_SOFT_OVERRIDE, field_val); 649 data = REG_SET_FIELD(data, IH_CLK_CTRL, 650 DYN_CLK_SOFT_OVERRIDE, field_val); 651 data = REG_SET_FIELD(data, IH_CLK_CTRL, 652 REG_CLK_SOFT_OVERRIDE, field_val); 653 if (def != data) 654 WREG32_SOC15(OSSSYS, 0, mmIH_CLK_CTRL, data); 655 } 656 657 return; 658 } 659 660 static int navi10_ih_set_clockgating_state(void *handle, 661 enum amd_clockgating_state state) 662 { 663 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 664 665 navi10_ih_update_clockgating_state(adev, 666 state == AMD_CG_STATE_GATE); 667 return 0; 668 } 669 670 static int navi10_ih_set_powergating_state(void *handle, 671 enum amd_powergating_state state) 672 { 673 return 0; 674 } 675 676 static void navi10_ih_get_clockgating_state(void *handle, u32 *flags) 677 { 678 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 679 680 if (!RREG32_SOC15(OSSSYS, 0, mmIH_CLK_CTRL)) 681 *flags |= AMD_CG_SUPPORT_IH_CG; 682 683 return; 684 } 685 686 static const struct amd_ip_funcs navi10_ih_ip_funcs = { 687 .name = "navi10_ih", 688 .early_init = navi10_ih_early_init, 689 .late_init = NULL, 690 .sw_init = navi10_ih_sw_init, 691 .sw_fini = navi10_ih_sw_fini, 692 .hw_init = navi10_ih_hw_init, 693 .hw_fini = navi10_ih_hw_fini, 694 .suspend = navi10_ih_suspend, 695 .resume = navi10_ih_resume, 696 .is_idle = navi10_ih_is_idle, 697 .wait_for_idle = navi10_ih_wait_for_idle, 698 .soft_reset = navi10_ih_soft_reset, 699 .set_clockgating_state = navi10_ih_set_clockgating_state, 700 .set_powergating_state = navi10_ih_set_powergating_state, 701 .get_clockgating_state = navi10_ih_get_clockgating_state, 702 }; 703 704 static const struct amdgpu_ih_funcs navi10_ih_funcs = { 705 .get_wptr = navi10_ih_get_wptr, 706 .decode_iv = amdgpu_ih_decode_iv_helper, 707 .set_rptr = navi10_ih_set_rptr 708 }; 709 710 static void navi10_ih_set_interrupt_funcs(struct amdgpu_device *adev) 711 { 712 if (adev->irq.ih_funcs == NULL) 713 adev->irq.ih_funcs = &navi10_ih_funcs; 714 } 715 716 const struct amdgpu_ip_block_version navi10_ih_ip_block = 717 { 718 .type = AMD_IP_BLOCK_TYPE_IH, 719 .major = 5, 720 .minor = 0, 721 .rev = 0, 722 .funcs = &navi10_ih_ip_funcs, 723 }; 724