1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/pci.h> 25 26 #include "amdgpu.h" 27 #include "amdgpu_ih.h" 28 29 #include "oss/osssys_5_0_0_offset.h" 30 #include "oss/osssys_5_0_0_sh_mask.h" 31 32 #include "soc15_common.h" 33 #include "navi10_ih.h" 34 35 #define MAX_REARM_RETRY 10 36 37 #define mmIH_CHICKEN_Sienna_Cichlid 0x018d 38 #define mmIH_CHICKEN_Sienna_Cichlid_BASE_IDX 0 39 40 static void navi10_ih_set_interrupt_funcs(struct amdgpu_device *adev); 41 42 /** 43 * force_update_wptr_for_self_int - Force update the wptr for self interrupt 44 * 45 * @adev: amdgpu_device pointer 46 * @threshold: threshold to trigger the wptr reporting 47 * @timeout: timeout to trigger the wptr reporting 48 * @enabled: Enable/disable timeout flush mechanism 49 * 50 * threshold input range: 0 ~ 15, default 0, 51 * real_threshold = 2^threshold 52 * timeout input range: 0 ~ 20, default 8, 53 * real_timeout = (2^timeout) * 1024 / (socclk_freq) 54 * 55 * Force update wptr for self interrupt ( >= SIENNA_CICHLID). 56 */ 57 static void 58 force_update_wptr_for_self_int(struct amdgpu_device *adev, 59 u32 threshold, u32 timeout, bool enabled) 60 { 61 u32 ih_cntl, ih_rb_cntl; 62 63 if (adev->asic_type < CHIP_SIENNA_CICHLID) 64 return; 65 66 ih_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_CNTL2); 67 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1); 68 69 ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL2, 70 SELF_IV_FORCE_WPTR_UPDATE_TIMEOUT, timeout); 71 ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL2, 72 SELF_IV_FORCE_WPTR_UPDATE_ENABLE, enabled); 73 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING1, 74 RB_USED_INT_THRESHOLD, threshold); 75 76 WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1, ih_rb_cntl); 77 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2); 78 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING2, 79 RB_USED_INT_THRESHOLD, threshold); 80 WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2, ih_rb_cntl); 81 WREG32_SOC15(OSSSYS, 0, mmIH_CNTL2, ih_cntl); 82 } 83 84 /** 85 * navi10_ih_enable_interrupts - Enable the interrupt ring buffer 86 * 87 * @adev: amdgpu_device pointer 88 * 89 * Enable the interrupt ring buffer (NAVI10). 90 */ 91 static void navi10_ih_enable_interrupts(struct amdgpu_device *adev) 92 { 93 u32 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL); 94 95 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 1); 96 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, ENABLE_INTR, 1); 97 if (amdgpu_sriov_vf(adev) && adev->asic_type < CHIP_NAVI10) { 98 if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL, ih_rb_cntl)) { 99 DRM_ERROR("PSP program IH_RB_CNTL failed!\n"); 100 return; 101 } 102 } else { 103 WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL, ih_rb_cntl); 104 } 105 106 adev->irq.ih.enabled = true; 107 108 if (adev->irq.ih1.ring_size) { 109 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1); 110 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING1, 111 RB_ENABLE, 1); 112 if (amdgpu_sriov_vf(adev) && adev->asic_type < CHIP_NAVI10) { 113 if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL_RING1, 114 ih_rb_cntl)) { 115 DRM_ERROR("program IH_RB_CNTL_RING1 failed!\n"); 116 return; 117 } 118 } else { 119 WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1, ih_rb_cntl); 120 } 121 adev->irq.ih1.enabled = true; 122 } 123 124 if (adev->irq.ih2.ring_size) { 125 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2); 126 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING2, 127 RB_ENABLE, 1); 128 if (amdgpu_sriov_vf(adev) && adev->asic_type < CHIP_NAVI10) { 129 if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL_RING2, 130 ih_rb_cntl)) { 131 DRM_ERROR("program IH_RB_CNTL_RING2 failed!\n"); 132 return; 133 } 134 } else { 135 WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2, ih_rb_cntl); 136 } 137 adev->irq.ih2.enabled = true; 138 } 139 } 140 141 /** 142 * navi10_ih_disable_interrupts - Disable the interrupt ring buffer 143 * 144 * @adev: amdgpu_device pointer 145 * 146 * Disable the interrupt ring buffer (NAVI10). 147 */ 148 static void navi10_ih_disable_interrupts(struct amdgpu_device *adev) 149 { 150 u32 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL); 151 152 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 0); 153 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, ENABLE_INTR, 0); 154 if (amdgpu_sriov_vf(adev) && adev->asic_type < CHIP_NAVI10) { 155 if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL, ih_rb_cntl)) { 156 DRM_ERROR("PSP program IH_RB_CNTL failed!\n"); 157 return; 158 } 159 } else { 160 WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL, ih_rb_cntl); 161 } 162 163 /* set rptr, wptr to 0 */ 164 WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR, 0); 165 WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR, 0); 166 adev->irq.ih.enabled = false; 167 adev->irq.ih.rptr = 0; 168 169 if (adev->irq.ih1.ring_size) { 170 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1); 171 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING1, 172 RB_ENABLE, 0); 173 if (amdgpu_sriov_vf(adev) && adev->asic_type < CHIP_NAVI10) { 174 if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL_RING1, 175 ih_rb_cntl)) { 176 DRM_ERROR("program IH_RB_CNTL_RING1 failed!\n"); 177 return; 178 } 179 } else { 180 WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1, ih_rb_cntl); 181 } 182 /* set rptr, wptr to 0 */ 183 WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR_RING1, 0); 184 WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_RING1, 0); 185 adev->irq.ih1.enabled = false; 186 adev->irq.ih1.rptr = 0; 187 } 188 189 if (adev->irq.ih2.ring_size) { 190 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2); 191 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING2, 192 RB_ENABLE, 0); 193 if (amdgpu_sriov_vf(adev) && adev->asic_type < CHIP_NAVI10) { 194 if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL_RING2, 195 ih_rb_cntl)) { 196 DRM_ERROR("program IH_RB_CNTL_RING2 failed!\n"); 197 return; 198 } 199 } else { 200 WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2, ih_rb_cntl); 201 } 202 /* set rptr, wptr to 0 */ 203 WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR_RING2, 0); 204 WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_RING2, 0); 205 adev->irq.ih2.enabled = false; 206 adev->irq.ih2.rptr = 0; 207 } 208 209 } 210 211 static uint32_t navi10_ih_rb_cntl(struct amdgpu_ih_ring *ih, uint32_t ih_rb_cntl) 212 { 213 int rb_bufsz = order_base_2(ih->ring_size / 4); 214 215 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, 216 MC_SPACE, ih->use_bus_addr ? 1 : 4); 217 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, 218 WPTR_OVERFLOW_CLEAR, 1); 219 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, 220 WPTR_OVERFLOW_ENABLE, 1); 221 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_SIZE, rb_bufsz); 222 /* Ring Buffer write pointer writeback. If enabled, IH_RB_WPTR register 223 * value is written to memory 224 */ 225 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, 226 WPTR_WRITEBACK_ENABLE, 1); 227 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_SNOOP, 1); 228 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_RO, 0); 229 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_VMID, 0); 230 231 return ih_rb_cntl; 232 } 233 234 static uint32_t navi10_ih_doorbell_rptr(struct amdgpu_ih_ring *ih) 235 { 236 u32 ih_doorbell_rtpr = 0; 237 238 if (ih->use_doorbell) { 239 ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr, 240 IH_DOORBELL_RPTR, OFFSET, 241 ih->doorbell_index); 242 ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr, 243 IH_DOORBELL_RPTR, 244 ENABLE, 1); 245 } else { 246 ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr, 247 IH_DOORBELL_RPTR, 248 ENABLE, 0); 249 } 250 return ih_doorbell_rtpr; 251 } 252 253 static void navi10_ih_reroute_ih(struct amdgpu_device *adev) 254 { 255 uint32_t tmp; 256 257 /* Reroute to IH ring 1 for VMC */ 258 WREG32_SOC15(OSSSYS, 0, mmIH_CLIENT_CFG_INDEX, 0x12); 259 tmp = RREG32_SOC15(OSSSYS, 0, mmIH_CLIENT_CFG_DATA); 260 tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, CLIENT_TYPE, 1); 261 tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, RING_ID, 1); 262 WREG32_SOC15(OSSSYS, 0, mmIH_CLIENT_CFG_DATA, tmp); 263 264 /* Reroute IH ring 1 for UMC */ 265 WREG32_SOC15(OSSSYS, 0, mmIH_CLIENT_CFG_INDEX, 0x1B); 266 tmp = RREG32_SOC15(OSSSYS, 0, mmIH_CLIENT_CFG_DATA); 267 tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, RING_ID, 1); 268 WREG32_SOC15(OSSSYS, 0, mmIH_CLIENT_CFG_DATA, tmp); 269 } 270 271 /** 272 * navi10_ih_irq_init - init and enable the interrupt ring 273 * 274 * @adev: amdgpu_device pointer 275 * 276 * Allocate a ring buffer for the interrupt controller, 277 * enable the RLC, disable interrupts, enable the IH 278 * ring buffer and enable it (NAVI). 279 * Called at device load and reume. 280 * Returns 0 for success, errors for failure. 281 */ 282 static int navi10_ih_irq_init(struct amdgpu_device *adev) 283 { 284 struct amdgpu_ih_ring *ih = &adev->irq.ih; 285 u32 ih_rb_cntl, ih_chicken; 286 u32 tmp; 287 288 /* disable irqs */ 289 navi10_ih_disable_interrupts(adev); 290 291 adev->nbio.funcs->ih_control(adev); 292 293 /* Ring Buffer base. [39:8] of 40-bit address of the beginning of the ring buffer*/ 294 WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE, ih->gpu_addr >> 8); 295 WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE_HI, (ih->gpu_addr >> 40) & 0xff); 296 297 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL); 298 ih_rb_cntl = navi10_ih_rb_cntl(ih, ih_rb_cntl); 299 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RPTR_REARM, 300 !!adev->irq.msi_enabled); 301 if (amdgpu_sriov_vf(adev) && adev->asic_type < CHIP_NAVI10) { 302 if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL, ih_rb_cntl)) { 303 DRM_ERROR("PSP program IH_RB_CNTL failed!\n"); 304 return -ETIMEDOUT; 305 } 306 } else { 307 WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL, ih_rb_cntl); 308 } 309 if (adev->irq.ih1.ring_size) 310 navi10_ih_reroute_ih(adev); 311 312 if (unlikely(adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT)) { 313 if (ih->use_bus_addr) { 314 switch (adev->asic_type) { 315 case CHIP_SIENNA_CICHLID: 316 case CHIP_NAVY_FLOUNDER: 317 case CHIP_VANGOGH: 318 case CHIP_DIMGREY_CAVEFISH: 319 ih_chicken = RREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN_Sienna_Cichlid); 320 ih_chicken = REG_SET_FIELD(ih_chicken, 321 IH_CHICKEN, MC_SPACE_GPA_ENABLE, 1); 322 WREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN_Sienna_Cichlid, ih_chicken); 323 break; 324 default: 325 ih_chicken = RREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN); 326 ih_chicken = REG_SET_FIELD(ih_chicken, 327 IH_CHICKEN, MC_SPACE_GPA_ENABLE, 1); 328 WREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN, ih_chicken); 329 break; 330 } 331 } 332 } 333 334 /* set the writeback address whether it's enabled or not */ 335 WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_ADDR_LO, 336 lower_32_bits(ih->wptr_addr)); 337 WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_ADDR_HI, 338 upper_32_bits(ih->wptr_addr) & 0xFFFF); 339 340 /* set rptr, wptr to 0 */ 341 WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR, 0); 342 WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR, 0); 343 344 WREG32_SOC15(OSSSYS, 0, mmIH_DOORBELL_RPTR, 345 navi10_ih_doorbell_rptr(ih)); 346 347 adev->nbio.funcs->ih_doorbell_range(adev, ih->use_doorbell, 348 ih->doorbell_index); 349 350 ih = &adev->irq.ih1; 351 if (ih->ring_size) { 352 WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE_RING1, ih->gpu_addr >> 8); 353 WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE_HI_RING1, 354 (ih->gpu_addr >> 40) & 0xff); 355 356 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1); 357 ih_rb_cntl = navi10_ih_rb_cntl(ih, ih_rb_cntl); 358 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, 359 WPTR_OVERFLOW_ENABLE, 0); 360 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, 361 RB_FULL_DRAIN_ENABLE, 1); 362 if (amdgpu_sriov_vf(adev) && adev->asic_type < CHIP_NAVI10) { 363 if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL_RING1, 364 ih_rb_cntl)) { 365 DRM_ERROR("program IH_RB_CNTL_RING1 failed!\n"); 366 return -ETIMEDOUT; 367 } 368 } else { 369 WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1, ih_rb_cntl); 370 } 371 /* set rptr, wptr to 0 */ 372 WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_RING1, 0); 373 WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR_RING1, 0); 374 375 WREG32_SOC15(OSSSYS, 0, mmIH_DOORBELL_RPTR_RING1, 376 navi10_ih_doorbell_rptr(ih)); 377 } 378 379 ih = &adev->irq.ih2; 380 if (ih->ring_size) { 381 WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE_RING2, ih->gpu_addr >> 8); 382 WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE_HI_RING2, 383 (ih->gpu_addr >> 40) & 0xff); 384 385 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2); 386 ih_rb_cntl = navi10_ih_rb_cntl(ih, ih_rb_cntl); 387 388 if (amdgpu_sriov_vf(adev) && adev->asic_type < CHIP_NAVI10) { 389 if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL_RING2, 390 ih_rb_cntl)) { 391 DRM_ERROR("program IH_RB_CNTL_RING2 failed!\n"); 392 return -ETIMEDOUT; 393 } 394 } else { 395 WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2, ih_rb_cntl); 396 } 397 /* set rptr, wptr to 0 */ 398 WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_RING2, 0); 399 WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR_RING2, 0); 400 401 WREG32_SOC15(OSSSYS, 0, mmIH_DOORBELL_RPTR_RING2, 402 navi10_ih_doorbell_rptr(ih)); 403 } 404 405 406 tmp = RREG32_SOC15(OSSSYS, 0, mmIH_STORM_CLIENT_LIST_CNTL); 407 tmp = REG_SET_FIELD(tmp, IH_STORM_CLIENT_LIST_CNTL, 408 CLIENT18_IS_STORM_CLIENT, 1); 409 WREG32_SOC15(OSSSYS, 0, mmIH_STORM_CLIENT_LIST_CNTL, tmp); 410 411 tmp = RREG32_SOC15(OSSSYS, 0, mmIH_INT_FLOOD_CNTL); 412 tmp = REG_SET_FIELD(tmp, IH_INT_FLOOD_CNTL, FLOOD_CNTL_ENABLE, 1); 413 WREG32_SOC15(OSSSYS, 0, mmIH_INT_FLOOD_CNTL, tmp); 414 415 pci_set_master(adev->pdev); 416 417 /* enable interrupts */ 418 navi10_ih_enable_interrupts(adev); 419 /* enable wptr force update for self int */ 420 force_update_wptr_for_self_int(adev, 0, 8, true); 421 422 return 0; 423 } 424 425 /** 426 * navi10_ih_irq_disable - disable interrupts 427 * 428 * @adev: amdgpu_device pointer 429 * 430 * Disable interrupts on the hw (NAVI10). 431 */ 432 static void navi10_ih_irq_disable(struct amdgpu_device *adev) 433 { 434 force_update_wptr_for_self_int(adev, 0, 8, false); 435 navi10_ih_disable_interrupts(adev); 436 437 /* Wait and acknowledge irq */ 438 mdelay(1); 439 } 440 441 /** 442 * navi10_ih_get_wptr - get the IH ring buffer wptr 443 * 444 * @adev: amdgpu_device pointer 445 * 446 * Get the IH ring buffer wptr from either the register 447 * or the writeback memory buffer (NAVI10). Also check for 448 * ring buffer overflow and deal with it. 449 * Returns the value of the wptr. 450 */ 451 static u32 navi10_ih_get_wptr(struct amdgpu_device *adev, 452 struct amdgpu_ih_ring *ih) 453 { 454 u32 wptr, reg, tmp; 455 456 wptr = le32_to_cpu(*ih->wptr_cpu); 457 458 if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) 459 goto out; 460 461 if (ih == &adev->irq.ih) 462 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR); 463 else if (ih == &adev->irq.ih1) 464 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_RING1); 465 else if (ih == &adev->irq.ih2) 466 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_RING2); 467 else 468 BUG(); 469 470 wptr = RREG32_NO_KIQ(reg); 471 if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) 472 goto out; 473 wptr = REG_SET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW, 0); 474 475 /* When a ring buffer overflow happen start parsing interrupt 476 * from the last not overwritten vector (wptr + 32). Hopefully 477 * this should allow us to catch up. 478 */ 479 tmp = (wptr + 32) & ih->ptr_mask; 480 dev_warn(adev->dev, "IH ring buffer overflow " 481 "(0x%08X, 0x%08X, 0x%08X)\n", 482 wptr, ih->rptr, tmp); 483 ih->rptr = tmp; 484 485 if (ih == &adev->irq.ih) 486 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL); 487 else if (ih == &adev->irq.ih1) 488 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL_RING1); 489 else if (ih == &adev->irq.ih2) 490 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL_RING2); 491 else 492 BUG(); 493 494 tmp = RREG32_NO_KIQ(reg); 495 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1); 496 WREG32_NO_KIQ(reg, tmp); 497 out: 498 return (wptr & ih->ptr_mask); 499 } 500 501 /** 502 * navi10_ih_decode_iv - decode an interrupt vector 503 * 504 * @adev: amdgpu_device pointer 505 * 506 * Decodes the interrupt vector at the current rptr 507 * position and also advance the position. 508 */ 509 static void navi10_ih_decode_iv(struct amdgpu_device *adev, 510 struct amdgpu_ih_ring *ih, 511 struct amdgpu_iv_entry *entry) 512 { 513 /* wptr/rptr are in bytes! */ 514 u32 ring_index = ih->rptr >> 2; 515 uint32_t dw[8]; 516 517 dw[0] = le32_to_cpu(ih->ring[ring_index + 0]); 518 dw[1] = le32_to_cpu(ih->ring[ring_index + 1]); 519 dw[2] = le32_to_cpu(ih->ring[ring_index + 2]); 520 dw[3] = le32_to_cpu(ih->ring[ring_index + 3]); 521 dw[4] = le32_to_cpu(ih->ring[ring_index + 4]); 522 dw[5] = le32_to_cpu(ih->ring[ring_index + 5]); 523 dw[6] = le32_to_cpu(ih->ring[ring_index + 6]); 524 dw[7] = le32_to_cpu(ih->ring[ring_index + 7]); 525 526 entry->client_id = dw[0] & 0xff; 527 entry->src_id = (dw[0] >> 8) & 0xff; 528 entry->ring_id = (dw[0] >> 16) & 0xff; 529 entry->vmid = (dw[0] >> 24) & 0xf; 530 entry->vmid_src = (dw[0] >> 31); 531 entry->timestamp = dw[1] | ((u64)(dw[2] & 0xffff) << 32); 532 entry->timestamp_src = dw[2] >> 31; 533 entry->pasid = dw[3] & 0xffff; 534 entry->pasid_src = dw[3] >> 31; 535 entry->src_data[0] = dw[4]; 536 entry->src_data[1] = dw[5]; 537 entry->src_data[2] = dw[6]; 538 entry->src_data[3] = dw[7]; 539 540 /* wptr/rptr are in bytes! */ 541 ih->rptr += 32; 542 } 543 544 /** 545 * navi10_ih_irq_rearm - rearm IRQ if lost 546 * 547 * @adev: amdgpu_device pointer 548 * 549 */ 550 static void navi10_ih_irq_rearm(struct amdgpu_device *adev, 551 struct amdgpu_ih_ring *ih) 552 { 553 uint32_t reg_rptr = 0; 554 uint32_t v = 0; 555 uint32_t i = 0; 556 557 if (ih == &adev->irq.ih) 558 reg_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR); 559 else if (ih == &adev->irq.ih1) 560 reg_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR_RING1); 561 else if (ih == &adev->irq.ih2) 562 reg_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR_RING2); 563 else 564 return; 565 566 /* Rearm IRQ / re-write doorbell if doorbell write is lost */ 567 for (i = 0; i < MAX_REARM_RETRY; i++) { 568 v = RREG32_NO_KIQ(reg_rptr); 569 if ((v < ih->ring_size) && (v != ih->rptr)) 570 WDOORBELL32(ih->doorbell_index, ih->rptr); 571 else 572 break; 573 } 574 } 575 576 /** 577 * navi10_ih_set_rptr - set the IH ring buffer rptr 578 * 579 * @adev: amdgpu_device pointer 580 * 581 * Set the IH ring buffer rptr. 582 */ 583 static void navi10_ih_set_rptr(struct amdgpu_device *adev, 584 struct amdgpu_ih_ring *ih) 585 { 586 if (ih->use_doorbell) { 587 /* XXX check if swapping is necessary on BE */ 588 *ih->rptr_cpu = ih->rptr; 589 WDOORBELL32(ih->doorbell_index, ih->rptr); 590 591 if (amdgpu_sriov_vf(adev)) 592 navi10_ih_irq_rearm(adev, ih); 593 } else if (ih == &adev->irq.ih) { 594 WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR, ih->rptr); 595 } else if (ih == &adev->irq.ih1) { 596 WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR_RING1, ih->rptr); 597 } else if (ih == &adev->irq.ih2) { 598 WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR_RING2, ih->rptr); 599 } 600 } 601 602 /** 603 * navi10_ih_self_irq - dispatch work for ring 1 and 2 604 * 605 * @adev: amdgpu_device pointer 606 * @source: irq source 607 * @entry: IV with WPTR update 608 * 609 * Update the WPTR from the IV and schedule work to handle the entries. 610 */ 611 static int navi10_ih_self_irq(struct amdgpu_device *adev, 612 struct amdgpu_irq_src *source, 613 struct amdgpu_iv_entry *entry) 614 { 615 uint32_t wptr = cpu_to_le32(entry->src_data[0]); 616 617 switch (entry->ring_id) { 618 case 1: 619 *adev->irq.ih1.wptr_cpu = wptr; 620 schedule_work(&adev->irq.ih1_work); 621 break; 622 case 2: 623 *adev->irq.ih2.wptr_cpu = wptr; 624 schedule_work(&adev->irq.ih2_work); 625 break; 626 default: break; 627 } 628 return 0; 629 } 630 631 static const struct amdgpu_irq_src_funcs navi10_ih_self_irq_funcs = { 632 .process = navi10_ih_self_irq, 633 }; 634 635 static void navi10_ih_set_self_irq_funcs(struct amdgpu_device *adev) 636 { 637 adev->irq.self_irq.num_types = 0; 638 adev->irq.self_irq.funcs = &navi10_ih_self_irq_funcs; 639 } 640 641 static int navi10_ih_early_init(void *handle) 642 { 643 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 644 645 navi10_ih_set_interrupt_funcs(adev); 646 navi10_ih_set_self_irq_funcs(adev); 647 return 0; 648 } 649 650 static int navi10_ih_sw_init(void *handle) 651 { 652 int r; 653 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 654 bool use_bus_addr; 655 656 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_IH, 0, 657 &adev->irq.self_irq); 658 659 if (r) 660 return r; 661 662 /* use gpu virtual address for ih ring 663 * until ih_checken is programmed to allow 664 * use bus address for ih ring by psp bl */ 665 if ((adev->flags & AMD_IS_APU) || 666 (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) 667 use_bus_addr = false; 668 else 669 use_bus_addr = true; 670 r = amdgpu_ih_ring_init(adev, &adev->irq.ih, 256 * 1024, use_bus_addr); 671 if (r) 672 return r; 673 674 adev->irq.ih.use_doorbell = true; 675 adev->irq.ih.doorbell_index = adev->doorbell_index.ih << 1; 676 677 adev->irq.ih1.ring_size = 0; 678 adev->irq.ih2.ring_size = 0; 679 680 if (adev->asic_type < CHIP_NAVI10) { 681 r = amdgpu_ih_ring_init(adev, &adev->irq.ih1, PAGE_SIZE, true); 682 if (r) 683 return r; 684 685 adev->irq.ih1.use_doorbell = true; 686 adev->irq.ih1.doorbell_index = 687 (adev->doorbell_index.ih + 1) << 1; 688 689 r = amdgpu_ih_ring_init(adev, &adev->irq.ih2, PAGE_SIZE, true); 690 if (r) 691 return r; 692 693 adev->irq.ih2.use_doorbell = true; 694 adev->irq.ih2.doorbell_index = 695 (adev->doorbell_index.ih + 2) << 1; 696 } 697 698 r = amdgpu_irq_init(adev); 699 700 return r; 701 } 702 703 static int navi10_ih_sw_fini(void *handle) 704 { 705 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 706 707 amdgpu_irq_fini(adev); 708 amdgpu_ih_ring_fini(adev, &adev->irq.ih2); 709 amdgpu_ih_ring_fini(adev, &adev->irq.ih1); 710 amdgpu_ih_ring_fini(adev, &adev->irq.ih); 711 712 return 0; 713 } 714 715 static int navi10_ih_hw_init(void *handle) 716 { 717 int r; 718 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 719 720 r = navi10_ih_irq_init(adev); 721 if (r) 722 return r; 723 724 return 0; 725 } 726 727 static int navi10_ih_hw_fini(void *handle) 728 { 729 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 730 731 navi10_ih_irq_disable(adev); 732 733 return 0; 734 } 735 736 static int navi10_ih_suspend(void *handle) 737 { 738 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 739 740 return navi10_ih_hw_fini(adev); 741 } 742 743 static int navi10_ih_resume(void *handle) 744 { 745 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 746 747 return navi10_ih_hw_init(adev); 748 } 749 750 static bool navi10_ih_is_idle(void *handle) 751 { 752 /* todo */ 753 return true; 754 } 755 756 static int navi10_ih_wait_for_idle(void *handle) 757 { 758 /* todo */ 759 return -ETIMEDOUT; 760 } 761 762 static int navi10_ih_soft_reset(void *handle) 763 { 764 /* todo */ 765 return 0; 766 } 767 768 static void navi10_ih_update_clockgating_state(struct amdgpu_device *adev, 769 bool enable) 770 { 771 uint32_t data, def, field_val; 772 773 if (adev->cg_flags & AMD_CG_SUPPORT_IH_CG) { 774 def = data = RREG32_SOC15(OSSSYS, 0, mmIH_CLK_CTRL); 775 field_val = enable ? 0 : 1; 776 data = REG_SET_FIELD(data, IH_CLK_CTRL, 777 DBUS_MUX_CLK_SOFT_OVERRIDE, field_val); 778 data = REG_SET_FIELD(data, IH_CLK_CTRL, 779 OSSSYS_SHARE_CLK_SOFT_OVERRIDE, field_val); 780 data = REG_SET_FIELD(data, IH_CLK_CTRL, 781 LIMIT_SMN_CLK_SOFT_OVERRIDE, field_val); 782 data = REG_SET_FIELD(data, IH_CLK_CTRL, 783 DYN_CLK_SOFT_OVERRIDE, field_val); 784 data = REG_SET_FIELD(data, IH_CLK_CTRL, 785 REG_CLK_SOFT_OVERRIDE, field_val); 786 if (def != data) 787 WREG32_SOC15(OSSSYS, 0, mmIH_CLK_CTRL, data); 788 } 789 790 return; 791 } 792 793 static int navi10_ih_set_clockgating_state(void *handle, 794 enum amd_clockgating_state state) 795 { 796 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 797 798 navi10_ih_update_clockgating_state(adev, 799 state == AMD_CG_STATE_GATE); 800 return 0; 801 } 802 803 static int navi10_ih_set_powergating_state(void *handle, 804 enum amd_powergating_state state) 805 { 806 return 0; 807 } 808 809 static void navi10_ih_get_clockgating_state(void *handle, u32 *flags) 810 { 811 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 812 813 if (!RREG32_SOC15(OSSSYS, 0, mmIH_CLK_CTRL)) 814 *flags |= AMD_CG_SUPPORT_IH_CG; 815 816 return; 817 } 818 819 static const struct amd_ip_funcs navi10_ih_ip_funcs = { 820 .name = "navi10_ih", 821 .early_init = navi10_ih_early_init, 822 .late_init = NULL, 823 .sw_init = navi10_ih_sw_init, 824 .sw_fini = navi10_ih_sw_fini, 825 .hw_init = navi10_ih_hw_init, 826 .hw_fini = navi10_ih_hw_fini, 827 .suspend = navi10_ih_suspend, 828 .resume = navi10_ih_resume, 829 .is_idle = navi10_ih_is_idle, 830 .wait_for_idle = navi10_ih_wait_for_idle, 831 .soft_reset = navi10_ih_soft_reset, 832 .set_clockgating_state = navi10_ih_set_clockgating_state, 833 .set_powergating_state = navi10_ih_set_powergating_state, 834 .get_clockgating_state = navi10_ih_get_clockgating_state, 835 }; 836 837 static const struct amdgpu_ih_funcs navi10_ih_funcs = { 838 .get_wptr = navi10_ih_get_wptr, 839 .decode_iv = navi10_ih_decode_iv, 840 .set_rptr = navi10_ih_set_rptr 841 }; 842 843 static void navi10_ih_set_interrupt_funcs(struct amdgpu_device *adev) 844 { 845 if (adev->irq.ih_funcs == NULL) 846 adev->irq.ih_funcs = &navi10_ih_funcs; 847 } 848 849 const struct amdgpu_ip_block_version navi10_ih_ip_block = 850 { 851 .type = AMD_IP_BLOCK_TYPE_IH, 852 .major = 5, 853 .minor = 0, 854 .rev = 0, 855 .funcs = &navi10_ih_ip_funcs, 856 }; 857