1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/pci.h> 25 26 #include "amdgpu.h" 27 #include "amdgpu_ih.h" 28 29 #include "oss/osssys_5_0_0_offset.h" 30 #include "oss/osssys_5_0_0_sh_mask.h" 31 32 #include "soc15_common.h" 33 #include "navi10_ih.h" 34 35 #define MAX_REARM_RETRY 10 36 37 #define mmIH_CHICKEN_Sienna_Cichlid 0x018d 38 #define mmIH_CHICKEN_Sienna_Cichlid_BASE_IDX 0 39 40 static void navi10_ih_set_interrupt_funcs(struct amdgpu_device *adev); 41 42 /** 43 * navi10_ih_init_register_offset - Initialize register offset for ih rings 44 * 45 * @adev: amdgpu_device pointer 46 * 47 * Initialize register offset ih rings (NAVI10). 48 */ 49 static void navi10_ih_init_register_offset(struct amdgpu_device *adev) 50 { 51 struct amdgpu_ih_regs *ih_regs; 52 53 if (adev->irq.ih.ring_size) { 54 ih_regs = &adev->irq.ih.ih_regs; 55 ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE); 56 ih_regs->ih_rb_base_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_HI); 57 ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL); 58 ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR); 59 ih_regs->ih_rb_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR); 60 ih_regs->ih_doorbell_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_DOORBELL_RPTR); 61 ih_regs->ih_rb_wptr_addr_lo = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_ADDR_LO); 62 ih_regs->ih_rb_wptr_addr_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_ADDR_HI); 63 ih_regs->psp_reg_id = PSP_REG_IH_RB_CNTL; 64 } 65 66 if (adev->irq.ih1.ring_size) { 67 ih_regs = &adev->irq.ih1.ih_regs; 68 ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_RING1); 69 ih_regs->ih_rb_base_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_HI_RING1); 70 ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL_RING1); 71 ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_RING1); 72 ih_regs->ih_rb_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR_RING1); 73 ih_regs->ih_doorbell_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_DOORBELL_RPTR_RING1); 74 ih_regs->psp_reg_id = PSP_REG_IH_RB_CNTL_RING1; 75 } 76 77 if (adev->irq.ih2.ring_size) { 78 ih_regs = &adev->irq.ih2.ih_regs; 79 ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_RING2); 80 ih_regs->ih_rb_base_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_HI_RING2); 81 ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL_RING2); 82 ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_RING2); 83 ih_regs->ih_rb_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR_RING2); 84 ih_regs->ih_doorbell_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_DOORBELL_RPTR_RING2); 85 ih_regs->psp_reg_id = PSP_REG_IH_RB_CNTL_RING2; 86 } 87 } 88 89 /** 90 * force_update_wptr_for_self_int - Force update the wptr for self interrupt 91 * 92 * @adev: amdgpu_device pointer 93 * @threshold: threshold to trigger the wptr reporting 94 * @timeout: timeout to trigger the wptr reporting 95 * @enabled: Enable/disable timeout flush mechanism 96 * 97 * threshold input range: 0 ~ 15, default 0, 98 * real_threshold = 2^threshold 99 * timeout input range: 0 ~ 20, default 8, 100 * real_timeout = (2^timeout) * 1024 / (socclk_freq) 101 * 102 * Force update wptr for self interrupt ( >= SIENNA_CICHLID). 103 */ 104 static void 105 force_update_wptr_for_self_int(struct amdgpu_device *adev, 106 u32 threshold, u32 timeout, bool enabled) 107 { 108 u32 ih_cntl, ih_rb_cntl; 109 110 if (adev->asic_type < CHIP_SIENNA_CICHLID) 111 return; 112 113 ih_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_CNTL2); 114 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1); 115 116 ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL2, 117 SELF_IV_FORCE_WPTR_UPDATE_TIMEOUT, timeout); 118 ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL2, 119 SELF_IV_FORCE_WPTR_UPDATE_ENABLE, enabled); 120 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING1, 121 RB_USED_INT_THRESHOLD, threshold); 122 123 WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1, ih_rb_cntl); 124 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2); 125 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING2, 126 RB_USED_INT_THRESHOLD, threshold); 127 WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2, ih_rb_cntl); 128 WREG32_SOC15(OSSSYS, 0, mmIH_CNTL2, ih_cntl); 129 } 130 131 /** 132 * navi10_ih_toggle_ring_interrupts - toggle the interrupt ring buffer 133 * 134 * @adev: amdgpu_device pointer 135 * @ih: amdgpu_ih_ring pointet 136 * @enable: true - enable the interrupts, false - disable the interrupts 137 * 138 * Toggle the interrupt ring buffer (NAVI10) 139 */ 140 static int navi10_ih_toggle_ring_interrupts(struct amdgpu_device *adev, 141 struct amdgpu_ih_ring *ih, 142 bool enable) 143 { 144 struct amdgpu_ih_regs *ih_regs; 145 uint32_t tmp; 146 147 ih_regs = &ih->ih_regs; 148 149 tmp = RREG32(ih_regs->ih_rb_cntl); 150 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RB_ENABLE, (enable ? 1 : 0)); 151 /* enable_intr field is only valid in ring0 */ 152 if (ih == &adev->irq.ih) 153 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, ENABLE_INTR, (enable ? 1 : 0)); 154 WREG32(ih_regs->ih_rb_cntl, tmp); 155 156 if (enable) { 157 ih->enabled = true; 158 } else { 159 /* set rptr, wptr to 0 */ 160 WREG32(ih_regs->ih_rb_rptr, 0); 161 WREG32(ih_regs->ih_rb_wptr, 0); 162 ih->enabled = false; 163 ih->rptr = 0; 164 } 165 166 return 0; 167 } 168 169 /** 170 * navi10_ih_toggle_interrupts - Toggle all the available interrupt ring buffers 171 * 172 * @adev: amdgpu_device pointer 173 * @enable: enable or disable interrupt ring buffers 174 * 175 * Toggle all the available interrupt ring buffers (NAVI10). 176 */ 177 static int navi10_ih_toggle_interrupts(struct amdgpu_device *adev, bool enable) 178 { 179 struct amdgpu_ih_ring *ih[] = {&adev->irq.ih, &adev->irq.ih1, &adev->irq.ih2}; 180 int i; 181 int r; 182 183 for (i = 0; i < ARRAY_SIZE(ih); i++) { 184 if (ih[i]->ring_size) { 185 r = navi10_ih_toggle_ring_interrupts(adev, ih[i], enable); 186 if (r) 187 return r; 188 } 189 } 190 191 return 0; 192 } 193 194 static uint32_t navi10_ih_rb_cntl(struct amdgpu_ih_ring *ih, uint32_t ih_rb_cntl) 195 { 196 int rb_bufsz = order_base_2(ih->ring_size / 4); 197 198 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, 199 MC_SPACE, ih->use_bus_addr ? 1 : 4); 200 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, 201 WPTR_OVERFLOW_CLEAR, 1); 202 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, 203 WPTR_OVERFLOW_ENABLE, 1); 204 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_SIZE, rb_bufsz); 205 /* Ring Buffer write pointer writeback. If enabled, IH_RB_WPTR register 206 * value is written to memory 207 */ 208 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, 209 WPTR_WRITEBACK_ENABLE, 1); 210 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_SNOOP, 1); 211 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_RO, 0); 212 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_VMID, 0); 213 214 return ih_rb_cntl; 215 } 216 217 static uint32_t navi10_ih_doorbell_rptr(struct amdgpu_ih_ring *ih) 218 { 219 u32 ih_doorbell_rtpr = 0; 220 221 if (ih->use_doorbell) { 222 ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr, 223 IH_DOORBELL_RPTR, OFFSET, 224 ih->doorbell_index); 225 ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr, 226 IH_DOORBELL_RPTR, 227 ENABLE, 1); 228 } else { 229 ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr, 230 IH_DOORBELL_RPTR, 231 ENABLE, 0); 232 } 233 return ih_doorbell_rtpr; 234 } 235 236 /** 237 * navi10_ih_enable_ring - enable an ih ring buffer 238 * 239 * @adev: amdgpu_device pointer 240 * @ih: amdgpu_ih_ring pointer 241 * 242 * Enable an ih ring buffer (NAVI10) 243 */ 244 static int navi10_ih_enable_ring(struct amdgpu_device *adev, 245 struct amdgpu_ih_ring *ih) 246 { 247 struct amdgpu_ih_regs *ih_regs; 248 uint32_t tmp; 249 250 ih_regs = &ih->ih_regs; 251 252 /* Ring Buffer base. [39:8] of 40-bit address of the beginning of the ring buffer*/ 253 WREG32(ih_regs->ih_rb_base, ih->gpu_addr >> 8); 254 WREG32(ih_regs->ih_rb_base_hi, (ih->gpu_addr >> 40) & 0xff); 255 256 tmp = RREG32(ih_regs->ih_rb_cntl); 257 tmp = navi10_ih_rb_cntl(ih, tmp); 258 if (ih == &adev->irq.ih) 259 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RPTR_REARM, !!adev->irq.msi_enabled); 260 if (ih == &adev->irq.ih1) { 261 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_ENABLE, 0); 262 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RB_FULL_DRAIN_ENABLE, 1); 263 } 264 WREG32(ih_regs->ih_rb_cntl, tmp); 265 266 if (ih == &adev->irq.ih) { 267 /* set the ih ring 0 writeback address whether it's enabled or not */ 268 WREG32(ih_regs->ih_rb_wptr_addr_lo, lower_32_bits(ih->wptr_addr)); 269 WREG32(ih_regs->ih_rb_wptr_addr_hi, upper_32_bits(ih->wptr_addr) & 0xFFFF); 270 } 271 272 /* set rptr, wptr to 0 */ 273 WREG32(ih_regs->ih_rb_wptr, 0); 274 WREG32(ih_regs->ih_rb_rptr, 0); 275 276 WREG32(ih_regs->ih_doorbell_rptr, navi10_ih_doorbell_rptr(ih)); 277 278 return 0; 279 } 280 281 /** 282 * navi10_ih_irq_init - init and enable the interrupt ring 283 * 284 * @adev: amdgpu_device pointer 285 * 286 * Allocate a ring buffer for the interrupt controller, 287 * enable the RLC, disable interrupts, enable the IH 288 * ring buffer and enable it (NAVI). 289 * Called at device load and reume. 290 * Returns 0 for success, errors for failure. 291 */ 292 static int navi10_ih_irq_init(struct amdgpu_device *adev) 293 { 294 struct amdgpu_ih_ring *ih[] = {&adev->irq.ih, &adev->irq.ih1, &adev->irq.ih2}; 295 u32 ih_chicken; 296 u32 tmp; 297 int ret; 298 int i; 299 300 /* disable irqs */ 301 ret = navi10_ih_toggle_interrupts(adev, false); 302 if (ret) 303 return ret; 304 305 adev->nbio.funcs->ih_control(adev); 306 307 if (unlikely(adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT)) { 308 if (ih[0]->use_bus_addr) { 309 switch (adev->asic_type) { 310 case CHIP_SIENNA_CICHLID: 311 case CHIP_NAVY_FLOUNDER: 312 case CHIP_VANGOGH: 313 case CHIP_DIMGREY_CAVEFISH: 314 ih_chicken = RREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN_Sienna_Cichlid); 315 ih_chicken = REG_SET_FIELD(ih_chicken, 316 IH_CHICKEN, MC_SPACE_GPA_ENABLE, 1); 317 WREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN_Sienna_Cichlid, ih_chicken); 318 break; 319 default: 320 ih_chicken = RREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN); 321 ih_chicken = REG_SET_FIELD(ih_chicken, 322 IH_CHICKEN, MC_SPACE_GPA_ENABLE, 1); 323 WREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN, ih_chicken); 324 break; 325 } 326 } 327 } 328 329 for (i = 0; i < ARRAY_SIZE(ih); i++) { 330 if (ih[i]->ring_size) { 331 ret = navi10_ih_enable_ring(adev, ih[i]); 332 if (ret) 333 return ret; 334 } 335 } 336 337 /* update doorbell range for ih ring 0*/ 338 adev->nbio.funcs->ih_doorbell_range(adev, ih[0]->use_doorbell, 339 ih[0]->doorbell_index); 340 341 tmp = RREG32_SOC15(OSSSYS, 0, mmIH_STORM_CLIENT_LIST_CNTL); 342 tmp = REG_SET_FIELD(tmp, IH_STORM_CLIENT_LIST_CNTL, 343 CLIENT18_IS_STORM_CLIENT, 1); 344 WREG32_SOC15(OSSSYS, 0, mmIH_STORM_CLIENT_LIST_CNTL, tmp); 345 346 tmp = RREG32_SOC15(OSSSYS, 0, mmIH_INT_FLOOD_CNTL); 347 tmp = REG_SET_FIELD(tmp, IH_INT_FLOOD_CNTL, FLOOD_CNTL_ENABLE, 1); 348 WREG32_SOC15(OSSSYS, 0, mmIH_INT_FLOOD_CNTL, tmp); 349 350 pci_set_master(adev->pdev); 351 352 /* enable interrupts */ 353 ret = navi10_ih_toggle_interrupts(adev, true); 354 if (ret) 355 return ret; 356 /* enable wptr force update for self int */ 357 force_update_wptr_for_self_int(adev, 0, 8, true); 358 359 if (adev->irq.ih_soft.ring_size) 360 adev->irq.ih_soft.enabled = true; 361 362 return 0; 363 } 364 365 /** 366 * navi10_ih_irq_disable - disable interrupts 367 * 368 * @adev: amdgpu_device pointer 369 * 370 * Disable interrupts on the hw (NAVI10). 371 */ 372 static void navi10_ih_irq_disable(struct amdgpu_device *adev) 373 { 374 force_update_wptr_for_self_int(adev, 0, 8, false); 375 navi10_ih_toggle_interrupts(adev, false); 376 377 /* Wait and acknowledge irq */ 378 mdelay(1); 379 } 380 381 /** 382 * navi10_ih_get_wptr - get the IH ring buffer wptr 383 * 384 * @adev: amdgpu_device pointer 385 * @ih: IH ring buffer to fetch wptr 386 * 387 * Get the IH ring buffer wptr from either the register 388 * or the writeback memory buffer (NAVI10). Also check for 389 * ring buffer overflow and deal with it. 390 * Returns the value of the wptr. 391 */ 392 static u32 navi10_ih_get_wptr(struct amdgpu_device *adev, 393 struct amdgpu_ih_ring *ih) 394 { 395 u32 wptr, tmp; 396 struct amdgpu_ih_regs *ih_regs; 397 398 wptr = le32_to_cpu(*ih->wptr_cpu); 399 ih_regs = &ih->ih_regs; 400 401 if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) 402 goto out; 403 404 wptr = RREG32_NO_KIQ(ih_regs->ih_rb_wptr); 405 if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) 406 goto out; 407 wptr = REG_SET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW, 0); 408 409 /* When a ring buffer overflow happen start parsing interrupt 410 * from the last not overwritten vector (wptr + 32). Hopefully 411 * this should allow us to catch up. 412 */ 413 tmp = (wptr + 32) & ih->ptr_mask; 414 dev_warn(adev->dev, "IH ring buffer overflow " 415 "(0x%08X, 0x%08X, 0x%08X)\n", 416 wptr, ih->rptr, tmp); 417 ih->rptr = tmp; 418 419 tmp = RREG32_NO_KIQ(ih_regs->ih_rb_cntl); 420 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1); 421 WREG32_NO_KIQ(ih_regs->ih_rb_cntl, tmp); 422 out: 423 return (wptr & ih->ptr_mask); 424 } 425 426 /** 427 * navi10_ih_irq_rearm - rearm IRQ if lost 428 * 429 * @adev: amdgpu_device pointer 430 * @ih: IH ring to match 431 * 432 */ 433 static void navi10_ih_irq_rearm(struct amdgpu_device *adev, 434 struct amdgpu_ih_ring *ih) 435 { 436 uint32_t v = 0; 437 uint32_t i = 0; 438 struct amdgpu_ih_regs *ih_regs; 439 440 ih_regs = &ih->ih_regs; 441 442 /* Rearm IRQ / re-write doorbell if doorbell write is lost */ 443 for (i = 0; i < MAX_REARM_RETRY; i++) { 444 v = RREG32_NO_KIQ(ih_regs->ih_rb_rptr); 445 if ((v < ih->ring_size) && (v != ih->rptr)) 446 WDOORBELL32(ih->doorbell_index, ih->rptr); 447 else 448 break; 449 } 450 } 451 452 /** 453 * navi10_ih_set_rptr - set the IH ring buffer rptr 454 * 455 * @adev: amdgpu_device pointer 456 * 457 * @ih: IH ring buffer to set rptr 458 * Set the IH ring buffer rptr. 459 */ 460 static void navi10_ih_set_rptr(struct amdgpu_device *adev, 461 struct amdgpu_ih_ring *ih) 462 { 463 struct amdgpu_ih_regs *ih_regs; 464 465 if (ih->use_doorbell) { 466 /* XXX check if swapping is necessary on BE */ 467 *ih->rptr_cpu = ih->rptr; 468 WDOORBELL32(ih->doorbell_index, ih->rptr); 469 470 if (amdgpu_sriov_vf(adev)) 471 navi10_ih_irq_rearm(adev, ih); 472 } else { 473 ih_regs = &ih->ih_regs; 474 WREG32(ih_regs->ih_rb_rptr, ih->rptr); 475 } 476 } 477 478 /** 479 * navi10_ih_self_irq - dispatch work for ring 1 and 2 480 * 481 * @adev: amdgpu_device pointer 482 * @source: irq source 483 * @entry: IV with WPTR update 484 * 485 * Update the WPTR from the IV and schedule work to handle the entries. 486 */ 487 static int navi10_ih_self_irq(struct amdgpu_device *adev, 488 struct amdgpu_irq_src *source, 489 struct amdgpu_iv_entry *entry) 490 { 491 uint32_t wptr = cpu_to_le32(entry->src_data[0]); 492 493 switch (entry->ring_id) { 494 case 1: 495 *adev->irq.ih1.wptr_cpu = wptr; 496 schedule_work(&adev->irq.ih1_work); 497 break; 498 case 2: 499 *adev->irq.ih2.wptr_cpu = wptr; 500 schedule_work(&adev->irq.ih2_work); 501 break; 502 default: break; 503 } 504 return 0; 505 } 506 507 static const struct amdgpu_irq_src_funcs navi10_ih_self_irq_funcs = { 508 .process = navi10_ih_self_irq, 509 }; 510 511 static void navi10_ih_set_self_irq_funcs(struct amdgpu_device *adev) 512 { 513 adev->irq.self_irq.num_types = 0; 514 adev->irq.self_irq.funcs = &navi10_ih_self_irq_funcs; 515 } 516 517 static int navi10_ih_early_init(void *handle) 518 { 519 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 520 521 navi10_ih_set_interrupt_funcs(adev); 522 navi10_ih_set_self_irq_funcs(adev); 523 return 0; 524 } 525 526 static int navi10_ih_sw_init(void *handle) 527 { 528 int r; 529 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 530 bool use_bus_addr; 531 532 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_IH, 0, 533 &adev->irq.self_irq); 534 535 if (r) 536 return r; 537 538 /* use gpu virtual address for ih ring 539 * until ih_checken is programmed to allow 540 * use bus address for ih ring by psp bl */ 541 if ((adev->flags & AMD_IS_APU) || 542 (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) 543 use_bus_addr = false; 544 else 545 use_bus_addr = true; 546 r = amdgpu_ih_ring_init(adev, &adev->irq.ih, 256 * 1024, use_bus_addr); 547 if (r) 548 return r; 549 550 adev->irq.ih.use_doorbell = true; 551 adev->irq.ih.doorbell_index = adev->doorbell_index.ih << 1; 552 553 adev->irq.ih1.ring_size = 0; 554 adev->irq.ih2.ring_size = 0; 555 556 /* initialize ih control registers offset */ 557 navi10_ih_init_register_offset(adev); 558 559 r = amdgpu_ih_ring_init(adev, &adev->irq.ih_soft, PAGE_SIZE, true); 560 if (r) 561 return r; 562 563 r = amdgpu_irq_init(adev); 564 565 return r; 566 } 567 568 static int navi10_ih_sw_fini(void *handle) 569 { 570 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 571 572 amdgpu_irq_fini_sw(adev); 573 amdgpu_ih_ring_fini(adev, &adev->irq.ih_soft); 574 amdgpu_ih_ring_fini(adev, &adev->irq.ih2); 575 amdgpu_ih_ring_fini(adev, &adev->irq.ih1); 576 amdgpu_ih_ring_fini(adev, &adev->irq.ih); 577 578 return 0; 579 } 580 581 static int navi10_ih_hw_init(void *handle) 582 { 583 int r; 584 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 585 586 r = navi10_ih_irq_init(adev); 587 if (r) 588 return r; 589 590 return 0; 591 } 592 593 static int navi10_ih_hw_fini(void *handle) 594 { 595 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 596 597 navi10_ih_irq_disable(adev); 598 599 return 0; 600 } 601 602 static int navi10_ih_suspend(void *handle) 603 { 604 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 605 606 return navi10_ih_hw_fini(adev); 607 } 608 609 static int navi10_ih_resume(void *handle) 610 { 611 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 612 613 return navi10_ih_hw_init(adev); 614 } 615 616 static bool navi10_ih_is_idle(void *handle) 617 { 618 /* todo */ 619 return true; 620 } 621 622 static int navi10_ih_wait_for_idle(void *handle) 623 { 624 /* todo */ 625 return -ETIMEDOUT; 626 } 627 628 static int navi10_ih_soft_reset(void *handle) 629 { 630 /* todo */ 631 return 0; 632 } 633 634 static void navi10_ih_update_clockgating_state(struct amdgpu_device *adev, 635 bool enable) 636 { 637 uint32_t data, def, field_val; 638 639 if (adev->cg_flags & AMD_CG_SUPPORT_IH_CG) { 640 def = data = RREG32_SOC15(OSSSYS, 0, mmIH_CLK_CTRL); 641 field_val = enable ? 0 : 1; 642 data = REG_SET_FIELD(data, IH_CLK_CTRL, 643 DBUS_MUX_CLK_SOFT_OVERRIDE, field_val); 644 data = REG_SET_FIELD(data, IH_CLK_CTRL, 645 OSSSYS_SHARE_CLK_SOFT_OVERRIDE, field_val); 646 data = REG_SET_FIELD(data, IH_CLK_CTRL, 647 LIMIT_SMN_CLK_SOFT_OVERRIDE, field_val); 648 data = REG_SET_FIELD(data, IH_CLK_CTRL, 649 DYN_CLK_SOFT_OVERRIDE, field_val); 650 data = REG_SET_FIELD(data, IH_CLK_CTRL, 651 REG_CLK_SOFT_OVERRIDE, field_val); 652 if (def != data) 653 WREG32_SOC15(OSSSYS, 0, mmIH_CLK_CTRL, data); 654 } 655 656 return; 657 } 658 659 static int navi10_ih_set_clockgating_state(void *handle, 660 enum amd_clockgating_state state) 661 { 662 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 663 664 navi10_ih_update_clockgating_state(adev, 665 state == AMD_CG_STATE_GATE); 666 return 0; 667 } 668 669 static int navi10_ih_set_powergating_state(void *handle, 670 enum amd_powergating_state state) 671 { 672 return 0; 673 } 674 675 static void navi10_ih_get_clockgating_state(void *handle, u32 *flags) 676 { 677 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 678 679 if (!RREG32_SOC15(OSSSYS, 0, mmIH_CLK_CTRL)) 680 *flags |= AMD_CG_SUPPORT_IH_CG; 681 682 return; 683 } 684 685 static const struct amd_ip_funcs navi10_ih_ip_funcs = { 686 .name = "navi10_ih", 687 .early_init = navi10_ih_early_init, 688 .late_init = NULL, 689 .sw_init = navi10_ih_sw_init, 690 .sw_fini = navi10_ih_sw_fini, 691 .hw_init = navi10_ih_hw_init, 692 .hw_fini = navi10_ih_hw_fini, 693 .suspend = navi10_ih_suspend, 694 .resume = navi10_ih_resume, 695 .is_idle = navi10_ih_is_idle, 696 .wait_for_idle = navi10_ih_wait_for_idle, 697 .soft_reset = navi10_ih_soft_reset, 698 .set_clockgating_state = navi10_ih_set_clockgating_state, 699 .set_powergating_state = navi10_ih_set_powergating_state, 700 .get_clockgating_state = navi10_ih_get_clockgating_state, 701 }; 702 703 static const struct amdgpu_ih_funcs navi10_ih_funcs = { 704 .get_wptr = navi10_ih_get_wptr, 705 .decode_iv = amdgpu_ih_decode_iv_helper, 706 .set_rptr = navi10_ih_set_rptr 707 }; 708 709 static void navi10_ih_set_interrupt_funcs(struct amdgpu_device *adev) 710 { 711 if (adev->irq.ih_funcs == NULL) 712 adev->irq.ih_funcs = &navi10_ih_funcs; 713 } 714 715 const struct amdgpu_ip_block_version navi10_ih_ip_block = 716 { 717 .type = AMD_IP_BLOCK_TYPE_IH, 718 .major = 5, 719 .minor = 0, 720 .rev = 0, 721 .funcs = &navi10_ih_ip_funcs, 722 }; 723