1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/pci.h> 25 26 #include "amdgpu.h" 27 #include "amdgpu_ih.h" 28 29 #include "oss/osssys_5_0_0_offset.h" 30 #include "oss/osssys_5_0_0_sh_mask.h" 31 32 #include "soc15_common.h" 33 #include "navi10_ih.h" 34 35 #define MAX_REARM_RETRY 10 36 37 #define mmIH_CHICKEN_Sienna_Cichlid 0x018d 38 #define mmIH_CHICKEN_Sienna_Cichlid_BASE_IDX 0 39 40 static void navi10_ih_set_interrupt_funcs(struct amdgpu_device *adev); 41 42 /** 43 * navi10_ih_init_register_offset - Initialize register offset for ih rings 44 * 45 * @adev: amdgpu_device pointer 46 * 47 * Initialize register offset ih rings (NAVI10). 48 */ 49 static void navi10_ih_init_register_offset(struct amdgpu_device *adev) 50 { 51 struct amdgpu_ih_regs *ih_regs; 52 53 if (adev->irq.ih.ring_size) { 54 ih_regs = &adev->irq.ih.ih_regs; 55 ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE); 56 ih_regs->ih_rb_base_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_HI); 57 ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL); 58 ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR); 59 ih_regs->ih_rb_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR); 60 ih_regs->ih_doorbell_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_DOORBELL_RPTR); 61 ih_regs->ih_rb_wptr_addr_lo = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_ADDR_LO); 62 ih_regs->ih_rb_wptr_addr_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_ADDR_HI); 63 ih_regs->psp_reg_id = PSP_REG_IH_RB_CNTL; 64 } 65 66 if (adev->irq.ih1.ring_size) { 67 ih_regs = &adev->irq.ih1.ih_regs; 68 ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_RING1); 69 ih_regs->ih_rb_base_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_HI_RING1); 70 ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL_RING1); 71 ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_RING1); 72 ih_regs->ih_rb_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR_RING1); 73 ih_regs->ih_doorbell_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_DOORBELL_RPTR_RING1); 74 ih_regs->psp_reg_id = PSP_REG_IH_RB_CNTL_RING1; 75 } 76 77 if (adev->irq.ih2.ring_size) { 78 ih_regs = &adev->irq.ih2.ih_regs; 79 ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_RING2); 80 ih_regs->ih_rb_base_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_HI_RING2); 81 ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL_RING2); 82 ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_RING2); 83 ih_regs->ih_rb_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR_RING2); 84 ih_regs->ih_doorbell_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_DOORBELL_RPTR_RING2); 85 ih_regs->psp_reg_id = PSP_REG_IH_RB_CNTL_RING2; 86 } 87 } 88 89 /** 90 * force_update_wptr_for_self_int - Force update the wptr for self interrupt 91 * 92 * @adev: amdgpu_device pointer 93 * @threshold: threshold to trigger the wptr reporting 94 * @timeout: timeout to trigger the wptr reporting 95 * @enabled: Enable/disable timeout flush mechanism 96 * 97 * threshold input range: 0 ~ 15, default 0, 98 * real_threshold = 2^threshold 99 * timeout input range: 0 ~ 20, default 8, 100 * real_timeout = (2^timeout) * 1024 / (socclk_freq) 101 * 102 * Force update wptr for self interrupt ( >= SIENNA_CICHLID). 103 */ 104 static void 105 force_update_wptr_for_self_int(struct amdgpu_device *adev, 106 u32 threshold, u32 timeout, bool enabled) 107 { 108 u32 ih_cntl, ih_rb_cntl; 109 110 if (adev->asic_type < CHIP_SIENNA_CICHLID) 111 return; 112 113 ih_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_CNTL2); 114 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1); 115 116 ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL2, 117 SELF_IV_FORCE_WPTR_UPDATE_TIMEOUT, timeout); 118 ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL2, 119 SELF_IV_FORCE_WPTR_UPDATE_ENABLE, enabled); 120 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING1, 121 RB_USED_INT_THRESHOLD, threshold); 122 123 WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1, ih_rb_cntl); 124 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2); 125 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING2, 126 RB_USED_INT_THRESHOLD, threshold); 127 WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2, ih_rb_cntl); 128 WREG32_SOC15(OSSSYS, 0, mmIH_CNTL2, ih_cntl); 129 } 130 131 /** 132 * navi10_ih_toggle_ring_interrupts - toggle the interrupt ring buffer 133 * 134 * @adev: amdgpu_device pointer 135 * @ih: amdgpu_ih_ring pointet 136 * @enable: true - enable the interrupts, false - disable the interrupts 137 * 138 * Toggle the interrupt ring buffer (NAVI10) 139 */ 140 static int navi10_ih_toggle_ring_interrupts(struct amdgpu_device *adev, 141 struct amdgpu_ih_ring *ih, 142 bool enable) 143 { 144 struct amdgpu_ih_regs *ih_regs; 145 uint32_t tmp; 146 147 ih_regs = &ih->ih_regs; 148 149 tmp = RREG32(ih_regs->ih_rb_cntl); 150 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RB_ENABLE, (enable ? 1 : 0)); 151 /* enable_intr field is only valid in ring0 */ 152 if (ih == &adev->irq.ih) 153 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, ENABLE_INTR, (enable ? 1 : 0)); 154 if (amdgpu_sriov_vf(adev) && adev->asic_type < CHIP_NAVI10) { 155 if (psp_reg_program(&adev->psp, ih_regs->psp_reg_id, tmp)) { 156 dev_err(adev->dev, "PSP program IH_RB_CNTL failed!\n"); 157 return -ETIMEDOUT; 158 } 159 } else { 160 WREG32(ih_regs->ih_rb_cntl, tmp); 161 } 162 163 if (enable) { 164 ih->enabled = true; 165 } else { 166 /* set rptr, wptr to 0 */ 167 WREG32(ih_regs->ih_rb_rptr, 0); 168 WREG32(ih_regs->ih_rb_wptr, 0); 169 ih->enabled = false; 170 ih->rptr = 0; 171 } 172 173 return 0; 174 } 175 176 /** 177 * navi10_ih_toggle_interrupts - Toggle all the available interrupt ring buffers 178 * 179 * @adev: amdgpu_device pointer 180 * @enable: enable or disable interrupt ring buffers 181 * 182 * Toggle all the available interrupt ring buffers (NAVI10). 183 */ 184 static int navi10_ih_toggle_interrupts(struct amdgpu_device *adev, bool enable) 185 { 186 struct amdgpu_ih_ring *ih[] = {&adev->irq.ih, &adev->irq.ih1, &adev->irq.ih2}; 187 int i; 188 int r; 189 190 for (i = 0; i < ARRAY_SIZE(ih); i++) { 191 if (ih[i]->ring_size) { 192 r = navi10_ih_toggle_ring_interrupts(adev, ih[i], enable); 193 if (r) 194 return r; 195 } 196 } 197 198 return 0; 199 } 200 201 static uint32_t navi10_ih_rb_cntl(struct amdgpu_ih_ring *ih, uint32_t ih_rb_cntl) 202 { 203 int rb_bufsz = order_base_2(ih->ring_size / 4); 204 205 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, 206 MC_SPACE, ih->use_bus_addr ? 1 : 4); 207 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, 208 WPTR_OVERFLOW_CLEAR, 1); 209 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, 210 WPTR_OVERFLOW_ENABLE, 1); 211 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_SIZE, rb_bufsz); 212 /* Ring Buffer write pointer writeback. If enabled, IH_RB_WPTR register 213 * value is written to memory 214 */ 215 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, 216 WPTR_WRITEBACK_ENABLE, 1); 217 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_SNOOP, 1); 218 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_RO, 0); 219 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_VMID, 0); 220 221 return ih_rb_cntl; 222 } 223 224 static uint32_t navi10_ih_doorbell_rptr(struct amdgpu_ih_ring *ih) 225 { 226 u32 ih_doorbell_rtpr = 0; 227 228 if (ih->use_doorbell) { 229 ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr, 230 IH_DOORBELL_RPTR, OFFSET, 231 ih->doorbell_index); 232 ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr, 233 IH_DOORBELL_RPTR, 234 ENABLE, 1); 235 } else { 236 ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr, 237 IH_DOORBELL_RPTR, 238 ENABLE, 0); 239 } 240 return ih_doorbell_rtpr; 241 } 242 243 /** 244 * navi10_ih_enable_ring - enable an ih ring buffer 245 * 246 * @adev: amdgpu_device pointer 247 * @ih: amdgpu_ih_ring pointer 248 * 249 * Enable an ih ring buffer (NAVI10) 250 */ 251 static int navi10_ih_enable_ring(struct amdgpu_device *adev, 252 struct amdgpu_ih_ring *ih) 253 { 254 struct amdgpu_ih_regs *ih_regs; 255 uint32_t tmp; 256 257 ih_regs = &ih->ih_regs; 258 259 /* Ring Buffer base. [39:8] of 40-bit address of the beginning of the ring buffer*/ 260 WREG32(ih_regs->ih_rb_base, ih->gpu_addr >> 8); 261 WREG32(ih_regs->ih_rb_base_hi, (ih->gpu_addr >> 40) & 0xff); 262 263 tmp = RREG32(ih_regs->ih_rb_cntl); 264 tmp = navi10_ih_rb_cntl(ih, tmp); 265 if (ih == &adev->irq.ih) 266 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RPTR_REARM, !!adev->irq.msi_enabled); 267 if (ih == &adev->irq.ih1) { 268 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_ENABLE, 0); 269 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RB_FULL_DRAIN_ENABLE, 1); 270 } 271 if (amdgpu_sriov_vf(adev) && adev->asic_type < CHIP_NAVI10) { 272 if (psp_reg_program(&adev->psp, ih_regs->psp_reg_id, tmp)) { 273 dev_err(adev->dev, "PSP program IH_RB_CNTL failed!\n"); 274 return -ETIMEDOUT; 275 } 276 } else { 277 WREG32(ih_regs->ih_rb_cntl, tmp); 278 } 279 280 if (ih == &adev->irq.ih) { 281 /* set the ih ring 0 writeback address whether it's enabled or not */ 282 WREG32(ih_regs->ih_rb_wptr_addr_lo, lower_32_bits(ih->wptr_addr)); 283 WREG32(ih_regs->ih_rb_wptr_addr_hi, upper_32_bits(ih->wptr_addr) & 0xFFFF); 284 } 285 286 /* set rptr, wptr to 0 */ 287 WREG32(ih_regs->ih_rb_wptr, 0); 288 WREG32(ih_regs->ih_rb_rptr, 0); 289 290 WREG32(ih_regs->ih_doorbell_rptr, navi10_ih_doorbell_rptr(ih)); 291 292 return 0; 293 } 294 295 static void navi10_ih_reroute_ih(struct amdgpu_device *adev) 296 { 297 uint32_t tmp; 298 299 /* Reroute to IH ring 1 for VMC */ 300 WREG32_SOC15(OSSSYS, 0, mmIH_CLIENT_CFG_INDEX, 0x12); 301 tmp = RREG32_SOC15(OSSSYS, 0, mmIH_CLIENT_CFG_DATA); 302 tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, CLIENT_TYPE, 1); 303 tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, RING_ID, 1); 304 WREG32_SOC15(OSSSYS, 0, mmIH_CLIENT_CFG_DATA, tmp); 305 306 /* Reroute IH ring 1 for UMC */ 307 WREG32_SOC15(OSSSYS, 0, mmIH_CLIENT_CFG_INDEX, 0x1B); 308 tmp = RREG32_SOC15(OSSSYS, 0, mmIH_CLIENT_CFG_DATA); 309 tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, RING_ID, 1); 310 WREG32_SOC15(OSSSYS, 0, mmIH_CLIENT_CFG_DATA, tmp); 311 } 312 313 /** 314 * navi10_ih_irq_init - init and enable the interrupt ring 315 * 316 * @adev: amdgpu_device pointer 317 * 318 * Allocate a ring buffer for the interrupt controller, 319 * enable the RLC, disable interrupts, enable the IH 320 * ring buffer and enable it (NAVI). 321 * Called at device load and reume. 322 * Returns 0 for success, errors for failure. 323 */ 324 static int navi10_ih_irq_init(struct amdgpu_device *adev) 325 { 326 struct amdgpu_ih_ring *ih = &adev->irq.ih; 327 u32 ih_rb_cntl, ih_chicken; 328 u32 tmp; 329 int ret; 330 331 /* disable irqs */ 332 ret = navi10_ih_toggle_interrupts(adev, false); 333 if (ret) 334 return ret; 335 336 adev->nbio.funcs->ih_control(adev); 337 338 /* Ring Buffer base. [39:8] of 40-bit address of the beginning of the ring buffer*/ 339 WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE, ih->gpu_addr >> 8); 340 WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE_HI, (ih->gpu_addr >> 40) & 0xff); 341 342 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL); 343 ih_rb_cntl = navi10_ih_rb_cntl(ih, ih_rb_cntl); 344 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RPTR_REARM, 345 !!adev->irq.msi_enabled); 346 if (amdgpu_sriov_vf(adev) && adev->asic_type < CHIP_NAVI10) { 347 if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL, ih_rb_cntl)) { 348 DRM_ERROR("PSP program IH_RB_CNTL failed!\n"); 349 return -ETIMEDOUT; 350 } 351 } else { 352 WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL, ih_rb_cntl); 353 } 354 if (adev->irq.ih1.ring_size) 355 navi10_ih_reroute_ih(adev); 356 357 if (unlikely(adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT)) { 358 if (ih->use_bus_addr) { 359 switch (adev->asic_type) { 360 case CHIP_SIENNA_CICHLID: 361 case CHIP_NAVY_FLOUNDER: 362 case CHIP_VANGOGH: 363 case CHIP_DIMGREY_CAVEFISH: 364 ih_chicken = RREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN_Sienna_Cichlid); 365 ih_chicken = REG_SET_FIELD(ih_chicken, 366 IH_CHICKEN, MC_SPACE_GPA_ENABLE, 1); 367 WREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN_Sienna_Cichlid, ih_chicken); 368 break; 369 default: 370 ih_chicken = RREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN); 371 ih_chicken = REG_SET_FIELD(ih_chicken, 372 IH_CHICKEN, MC_SPACE_GPA_ENABLE, 1); 373 WREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN, ih_chicken); 374 break; 375 } 376 } 377 } 378 379 /* set the writeback address whether it's enabled or not */ 380 WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_ADDR_LO, 381 lower_32_bits(ih->wptr_addr)); 382 WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_ADDR_HI, 383 upper_32_bits(ih->wptr_addr) & 0xFFFF); 384 385 /* set rptr, wptr to 0 */ 386 WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR, 0); 387 WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR, 0); 388 389 WREG32_SOC15(OSSSYS, 0, mmIH_DOORBELL_RPTR, 390 navi10_ih_doorbell_rptr(ih)); 391 392 adev->nbio.funcs->ih_doorbell_range(adev, ih->use_doorbell, 393 ih->doorbell_index); 394 395 ih = &adev->irq.ih1; 396 if (ih->ring_size) { 397 WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE_RING1, ih->gpu_addr >> 8); 398 WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE_HI_RING1, 399 (ih->gpu_addr >> 40) & 0xff); 400 401 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1); 402 ih_rb_cntl = navi10_ih_rb_cntl(ih, ih_rb_cntl); 403 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, 404 WPTR_OVERFLOW_ENABLE, 0); 405 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, 406 RB_FULL_DRAIN_ENABLE, 1); 407 if (amdgpu_sriov_vf(adev) && adev->asic_type < CHIP_NAVI10) { 408 if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL_RING1, 409 ih_rb_cntl)) { 410 DRM_ERROR("program IH_RB_CNTL_RING1 failed!\n"); 411 return -ETIMEDOUT; 412 } 413 } else { 414 WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1, ih_rb_cntl); 415 } 416 /* set rptr, wptr to 0 */ 417 WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_RING1, 0); 418 WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR_RING1, 0); 419 420 WREG32_SOC15(OSSSYS, 0, mmIH_DOORBELL_RPTR_RING1, 421 navi10_ih_doorbell_rptr(ih)); 422 } 423 424 ih = &adev->irq.ih2; 425 if (ih->ring_size) { 426 WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE_RING2, ih->gpu_addr >> 8); 427 WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE_HI_RING2, 428 (ih->gpu_addr >> 40) & 0xff); 429 430 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2); 431 ih_rb_cntl = navi10_ih_rb_cntl(ih, ih_rb_cntl); 432 433 if (amdgpu_sriov_vf(adev) && adev->asic_type < CHIP_NAVI10) { 434 if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL_RING2, 435 ih_rb_cntl)) { 436 DRM_ERROR("program IH_RB_CNTL_RING2 failed!\n"); 437 return -ETIMEDOUT; 438 } 439 } else { 440 WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2, ih_rb_cntl); 441 } 442 /* set rptr, wptr to 0 */ 443 WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_RING2, 0); 444 WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR_RING2, 0); 445 446 WREG32_SOC15(OSSSYS, 0, mmIH_DOORBELL_RPTR_RING2, 447 navi10_ih_doorbell_rptr(ih)); 448 } 449 450 451 tmp = RREG32_SOC15(OSSSYS, 0, mmIH_STORM_CLIENT_LIST_CNTL); 452 tmp = REG_SET_FIELD(tmp, IH_STORM_CLIENT_LIST_CNTL, 453 CLIENT18_IS_STORM_CLIENT, 1); 454 WREG32_SOC15(OSSSYS, 0, mmIH_STORM_CLIENT_LIST_CNTL, tmp); 455 456 tmp = RREG32_SOC15(OSSSYS, 0, mmIH_INT_FLOOD_CNTL); 457 tmp = REG_SET_FIELD(tmp, IH_INT_FLOOD_CNTL, FLOOD_CNTL_ENABLE, 1); 458 WREG32_SOC15(OSSSYS, 0, mmIH_INT_FLOOD_CNTL, tmp); 459 460 pci_set_master(adev->pdev); 461 462 /* enable interrupts */ 463 ret = navi10_ih_toggle_interrupts(adev, true); 464 if (ret) 465 return ret; 466 /* enable wptr force update for self int */ 467 force_update_wptr_for_self_int(adev, 0, 8, true); 468 469 return 0; 470 } 471 472 /** 473 * navi10_ih_irq_disable - disable interrupts 474 * 475 * @adev: amdgpu_device pointer 476 * 477 * Disable interrupts on the hw (NAVI10). 478 */ 479 static void navi10_ih_irq_disable(struct amdgpu_device *adev) 480 { 481 force_update_wptr_for_self_int(adev, 0, 8, false); 482 navi10_ih_toggle_interrupts(adev, false); 483 484 /* Wait and acknowledge irq */ 485 mdelay(1); 486 } 487 488 /** 489 * navi10_ih_get_wptr - get the IH ring buffer wptr 490 * 491 * @adev: amdgpu_device pointer 492 * @ih: IH ring buffer to fetch wptr 493 * 494 * Get the IH ring buffer wptr from either the register 495 * or the writeback memory buffer (NAVI10). Also check for 496 * ring buffer overflow and deal with it. 497 * Returns the value of the wptr. 498 */ 499 static u32 navi10_ih_get_wptr(struct amdgpu_device *adev, 500 struct amdgpu_ih_ring *ih) 501 { 502 u32 wptr, reg, tmp; 503 504 wptr = le32_to_cpu(*ih->wptr_cpu); 505 506 if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) 507 goto out; 508 509 if (ih == &adev->irq.ih) 510 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR); 511 else if (ih == &adev->irq.ih1) 512 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_RING1); 513 else if (ih == &adev->irq.ih2) 514 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_RING2); 515 else 516 BUG(); 517 518 wptr = RREG32_NO_KIQ(reg); 519 if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) 520 goto out; 521 wptr = REG_SET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW, 0); 522 523 /* When a ring buffer overflow happen start parsing interrupt 524 * from the last not overwritten vector (wptr + 32). Hopefully 525 * this should allow us to catch up. 526 */ 527 tmp = (wptr + 32) & ih->ptr_mask; 528 dev_warn(adev->dev, "IH ring buffer overflow " 529 "(0x%08X, 0x%08X, 0x%08X)\n", 530 wptr, ih->rptr, tmp); 531 ih->rptr = tmp; 532 533 if (ih == &adev->irq.ih) 534 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL); 535 else if (ih == &adev->irq.ih1) 536 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL_RING1); 537 else if (ih == &adev->irq.ih2) 538 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL_RING2); 539 else 540 BUG(); 541 542 tmp = RREG32_NO_KIQ(reg); 543 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1); 544 WREG32_NO_KIQ(reg, tmp); 545 out: 546 return (wptr & ih->ptr_mask); 547 } 548 549 /** 550 * navi10_ih_decode_iv - decode an interrupt vector 551 * 552 * @adev: amdgpu_device pointer 553 * @ih: IH ring buffer to decode 554 * @entry: IV entry to place decoded information into 555 * 556 * Decodes the interrupt vector at the current rptr 557 * position and also advance the position. 558 */ 559 static void navi10_ih_decode_iv(struct amdgpu_device *adev, 560 struct amdgpu_ih_ring *ih, 561 struct amdgpu_iv_entry *entry) 562 { 563 /* wptr/rptr are in bytes! */ 564 u32 ring_index = ih->rptr >> 2; 565 uint32_t dw[8]; 566 567 dw[0] = le32_to_cpu(ih->ring[ring_index + 0]); 568 dw[1] = le32_to_cpu(ih->ring[ring_index + 1]); 569 dw[2] = le32_to_cpu(ih->ring[ring_index + 2]); 570 dw[3] = le32_to_cpu(ih->ring[ring_index + 3]); 571 dw[4] = le32_to_cpu(ih->ring[ring_index + 4]); 572 dw[5] = le32_to_cpu(ih->ring[ring_index + 5]); 573 dw[6] = le32_to_cpu(ih->ring[ring_index + 6]); 574 dw[7] = le32_to_cpu(ih->ring[ring_index + 7]); 575 576 entry->client_id = dw[0] & 0xff; 577 entry->src_id = (dw[0] >> 8) & 0xff; 578 entry->ring_id = (dw[0] >> 16) & 0xff; 579 entry->vmid = (dw[0] >> 24) & 0xf; 580 entry->vmid_src = (dw[0] >> 31); 581 entry->timestamp = dw[1] | ((u64)(dw[2] & 0xffff) << 32); 582 entry->timestamp_src = dw[2] >> 31; 583 entry->pasid = dw[3] & 0xffff; 584 entry->pasid_src = dw[3] >> 31; 585 entry->src_data[0] = dw[4]; 586 entry->src_data[1] = dw[5]; 587 entry->src_data[2] = dw[6]; 588 entry->src_data[3] = dw[7]; 589 590 /* wptr/rptr are in bytes! */ 591 ih->rptr += 32; 592 } 593 594 /** 595 * navi10_ih_irq_rearm - rearm IRQ if lost 596 * 597 * @adev: amdgpu_device pointer 598 * @ih: IH ring to match 599 * 600 */ 601 static void navi10_ih_irq_rearm(struct amdgpu_device *adev, 602 struct amdgpu_ih_ring *ih) 603 { 604 uint32_t reg_rptr = 0; 605 uint32_t v = 0; 606 uint32_t i = 0; 607 608 if (ih == &adev->irq.ih) 609 reg_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR); 610 else if (ih == &adev->irq.ih1) 611 reg_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR_RING1); 612 else if (ih == &adev->irq.ih2) 613 reg_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR_RING2); 614 else 615 return; 616 617 /* Rearm IRQ / re-write doorbell if doorbell write is lost */ 618 for (i = 0; i < MAX_REARM_RETRY; i++) { 619 v = RREG32_NO_KIQ(reg_rptr); 620 if ((v < ih->ring_size) && (v != ih->rptr)) 621 WDOORBELL32(ih->doorbell_index, ih->rptr); 622 else 623 break; 624 } 625 } 626 627 /** 628 * navi10_ih_set_rptr - set the IH ring buffer rptr 629 * 630 * @adev: amdgpu_device pointer 631 * 632 * @ih: IH ring buffer to set rptr 633 * Set the IH ring buffer rptr. 634 */ 635 static void navi10_ih_set_rptr(struct amdgpu_device *adev, 636 struct amdgpu_ih_ring *ih) 637 { 638 if (ih->use_doorbell) { 639 /* XXX check if swapping is necessary on BE */ 640 *ih->rptr_cpu = ih->rptr; 641 WDOORBELL32(ih->doorbell_index, ih->rptr); 642 643 if (amdgpu_sriov_vf(adev)) 644 navi10_ih_irq_rearm(adev, ih); 645 } else if (ih == &adev->irq.ih) { 646 WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR, ih->rptr); 647 } else if (ih == &adev->irq.ih1) { 648 WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR_RING1, ih->rptr); 649 } else if (ih == &adev->irq.ih2) { 650 WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR_RING2, ih->rptr); 651 } 652 } 653 654 /** 655 * navi10_ih_self_irq - dispatch work for ring 1 and 2 656 * 657 * @adev: amdgpu_device pointer 658 * @source: irq source 659 * @entry: IV with WPTR update 660 * 661 * Update the WPTR from the IV and schedule work to handle the entries. 662 */ 663 static int navi10_ih_self_irq(struct amdgpu_device *adev, 664 struct amdgpu_irq_src *source, 665 struct amdgpu_iv_entry *entry) 666 { 667 uint32_t wptr = cpu_to_le32(entry->src_data[0]); 668 669 switch (entry->ring_id) { 670 case 1: 671 *adev->irq.ih1.wptr_cpu = wptr; 672 schedule_work(&adev->irq.ih1_work); 673 break; 674 case 2: 675 *adev->irq.ih2.wptr_cpu = wptr; 676 schedule_work(&adev->irq.ih2_work); 677 break; 678 default: break; 679 } 680 return 0; 681 } 682 683 static const struct amdgpu_irq_src_funcs navi10_ih_self_irq_funcs = { 684 .process = navi10_ih_self_irq, 685 }; 686 687 static void navi10_ih_set_self_irq_funcs(struct amdgpu_device *adev) 688 { 689 adev->irq.self_irq.num_types = 0; 690 adev->irq.self_irq.funcs = &navi10_ih_self_irq_funcs; 691 } 692 693 static int navi10_ih_early_init(void *handle) 694 { 695 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 696 697 navi10_ih_set_interrupt_funcs(adev); 698 navi10_ih_set_self_irq_funcs(adev); 699 return 0; 700 } 701 702 static int navi10_ih_sw_init(void *handle) 703 { 704 int r; 705 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 706 bool use_bus_addr; 707 708 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_IH, 0, 709 &adev->irq.self_irq); 710 711 if (r) 712 return r; 713 714 /* use gpu virtual address for ih ring 715 * until ih_checken is programmed to allow 716 * use bus address for ih ring by psp bl */ 717 if ((adev->flags & AMD_IS_APU) || 718 (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) 719 use_bus_addr = false; 720 else 721 use_bus_addr = true; 722 r = amdgpu_ih_ring_init(adev, &adev->irq.ih, 256 * 1024, use_bus_addr); 723 if (r) 724 return r; 725 726 adev->irq.ih.use_doorbell = true; 727 adev->irq.ih.doorbell_index = adev->doorbell_index.ih << 1; 728 729 adev->irq.ih1.ring_size = 0; 730 adev->irq.ih2.ring_size = 0; 731 732 if (adev->asic_type < CHIP_NAVI10) { 733 r = amdgpu_ih_ring_init(adev, &adev->irq.ih1, PAGE_SIZE, true); 734 if (r) 735 return r; 736 737 adev->irq.ih1.use_doorbell = true; 738 adev->irq.ih1.doorbell_index = 739 (adev->doorbell_index.ih + 1) << 1; 740 741 r = amdgpu_ih_ring_init(adev, &adev->irq.ih2, PAGE_SIZE, true); 742 if (r) 743 return r; 744 745 adev->irq.ih2.use_doorbell = true; 746 adev->irq.ih2.doorbell_index = 747 (adev->doorbell_index.ih + 2) << 1; 748 } 749 750 /* initialize ih control registers offset */ 751 navi10_ih_init_register_offset(adev); 752 753 r = amdgpu_ih_ring_init(adev, &adev->irq.ih_soft, PAGE_SIZE, true); 754 if (r) 755 return r; 756 757 r = amdgpu_irq_init(adev); 758 759 return r; 760 } 761 762 static int navi10_ih_sw_fini(void *handle) 763 { 764 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 765 766 amdgpu_irq_fini(adev); 767 amdgpu_ih_ring_fini(adev, &adev->irq.ih2); 768 amdgpu_ih_ring_fini(adev, &adev->irq.ih1); 769 amdgpu_ih_ring_fini(adev, &adev->irq.ih); 770 771 return 0; 772 } 773 774 static int navi10_ih_hw_init(void *handle) 775 { 776 int r; 777 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 778 779 r = navi10_ih_irq_init(adev); 780 if (r) 781 return r; 782 783 return 0; 784 } 785 786 static int navi10_ih_hw_fini(void *handle) 787 { 788 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 789 790 navi10_ih_irq_disable(adev); 791 792 return 0; 793 } 794 795 static int navi10_ih_suspend(void *handle) 796 { 797 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 798 799 return navi10_ih_hw_fini(adev); 800 } 801 802 static int navi10_ih_resume(void *handle) 803 { 804 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 805 806 return navi10_ih_hw_init(adev); 807 } 808 809 static bool navi10_ih_is_idle(void *handle) 810 { 811 /* todo */ 812 return true; 813 } 814 815 static int navi10_ih_wait_for_idle(void *handle) 816 { 817 /* todo */ 818 return -ETIMEDOUT; 819 } 820 821 static int navi10_ih_soft_reset(void *handle) 822 { 823 /* todo */ 824 return 0; 825 } 826 827 static void navi10_ih_update_clockgating_state(struct amdgpu_device *adev, 828 bool enable) 829 { 830 uint32_t data, def, field_val; 831 832 if (adev->cg_flags & AMD_CG_SUPPORT_IH_CG) { 833 def = data = RREG32_SOC15(OSSSYS, 0, mmIH_CLK_CTRL); 834 field_val = enable ? 0 : 1; 835 data = REG_SET_FIELD(data, IH_CLK_CTRL, 836 DBUS_MUX_CLK_SOFT_OVERRIDE, field_val); 837 data = REG_SET_FIELD(data, IH_CLK_CTRL, 838 OSSSYS_SHARE_CLK_SOFT_OVERRIDE, field_val); 839 data = REG_SET_FIELD(data, IH_CLK_CTRL, 840 LIMIT_SMN_CLK_SOFT_OVERRIDE, field_val); 841 data = REG_SET_FIELD(data, IH_CLK_CTRL, 842 DYN_CLK_SOFT_OVERRIDE, field_val); 843 data = REG_SET_FIELD(data, IH_CLK_CTRL, 844 REG_CLK_SOFT_OVERRIDE, field_val); 845 if (def != data) 846 WREG32_SOC15(OSSSYS, 0, mmIH_CLK_CTRL, data); 847 } 848 849 return; 850 } 851 852 static int navi10_ih_set_clockgating_state(void *handle, 853 enum amd_clockgating_state state) 854 { 855 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 856 857 navi10_ih_update_clockgating_state(adev, 858 state == AMD_CG_STATE_GATE); 859 return 0; 860 } 861 862 static int navi10_ih_set_powergating_state(void *handle, 863 enum amd_powergating_state state) 864 { 865 return 0; 866 } 867 868 static void navi10_ih_get_clockgating_state(void *handle, u32 *flags) 869 { 870 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 871 872 if (!RREG32_SOC15(OSSSYS, 0, mmIH_CLK_CTRL)) 873 *flags |= AMD_CG_SUPPORT_IH_CG; 874 875 return; 876 } 877 878 static const struct amd_ip_funcs navi10_ih_ip_funcs = { 879 .name = "navi10_ih", 880 .early_init = navi10_ih_early_init, 881 .late_init = NULL, 882 .sw_init = navi10_ih_sw_init, 883 .sw_fini = navi10_ih_sw_fini, 884 .hw_init = navi10_ih_hw_init, 885 .hw_fini = navi10_ih_hw_fini, 886 .suspend = navi10_ih_suspend, 887 .resume = navi10_ih_resume, 888 .is_idle = navi10_ih_is_idle, 889 .wait_for_idle = navi10_ih_wait_for_idle, 890 .soft_reset = navi10_ih_soft_reset, 891 .set_clockgating_state = navi10_ih_set_clockgating_state, 892 .set_powergating_state = navi10_ih_set_powergating_state, 893 .get_clockgating_state = navi10_ih_get_clockgating_state, 894 }; 895 896 static const struct amdgpu_ih_funcs navi10_ih_funcs = { 897 .get_wptr = navi10_ih_get_wptr, 898 .decode_iv = navi10_ih_decode_iv, 899 .set_rptr = navi10_ih_set_rptr 900 }; 901 902 static void navi10_ih_set_interrupt_funcs(struct amdgpu_device *adev) 903 { 904 if (adev->irq.ih_funcs == NULL) 905 adev->irq.ih_funcs = &navi10_ih_funcs; 906 } 907 908 const struct amdgpu_ip_block_version navi10_ih_ip_block = 909 { 910 .type = AMD_IP_BLOCK_TYPE_IH, 911 .major = 5, 912 .minor = 0, 913 .rev = 0, 914 .funcs = &navi10_ih_ip_funcs, 915 }; 916