1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/pci.h> 25 26 #include "amdgpu.h" 27 #include "amdgpu_ih.h" 28 29 #include "oss/osssys_5_0_0_offset.h" 30 #include "oss/osssys_5_0_0_sh_mask.h" 31 32 #include "soc15_common.h" 33 #include "navi10_ih.h" 34 35 #define MAX_REARM_RETRY 10 36 37 #define mmIH_CHICKEN_Sienna_Cichlid 0x018d 38 #define mmIH_CHICKEN_Sienna_Cichlid_BASE_IDX 0 39 40 static void navi10_ih_set_interrupt_funcs(struct amdgpu_device *adev); 41 42 /** 43 * navi10_ih_init_register_offset - Initialize register offset for ih rings 44 * 45 * @adev: amdgpu_device pointer 46 * 47 * Initialize register offset ih rings (NAVI10). 48 */ 49 static void navi10_ih_init_register_offset(struct amdgpu_device *adev) 50 { 51 struct amdgpu_ih_regs *ih_regs; 52 53 if (adev->irq.ih.ring_size) { 54 ih_regs = &adev->irq.ih.ih_regs; 55 ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE); 56 ih_regs->ih_rb_base_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_HI); 57 ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL); 58 ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR); 59 ih_regs->ih_rb_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR); 60 ih_regs->ih_doorbell_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_DOORBELL_RPTR); 61 ih_regs->ih_rb_wptr_addr_lo = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_ADDR_LO); 62 ih_regs->ih_rb_wptr_addr_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_ADDR_HI); 63 ih_regs->psp_reg_id = PSP_REG_IH_RB_CNTL; 64 } 65 66 if (adev->irq.ih1.ring_size) { 67 ih_regs = &adev->irq.ih1.ih_regs; 68 ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_RING1); 69 ih_regs->ih_rb_base_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_HI_RING1); 70 ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL_RING1); 71 ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_RING1); 72 ih_regs->ih_rb_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR_RING1); 73 ih_regs->ih_doorbell_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_DOORBELL_RPTR_RING1); 74 ih_regs->psp_reg_id = PSP_REG_IH_RB_CNTL_RING1; 75 } 76 77 if (adev->irq.ih2.ring_size) { 78 ih_regs = &adev->irq.ih2.ih_regs; 79 ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_RING2); 80 ih_regs->ih_rb_base_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_HI_RING2); 81 ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL_RING2); 82 ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_RING2); 83 ih_regs->ih_rb_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR_RING2); 84 ih_regs->ih_doorbell_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_DOORBELL_RPTR_RING2); 85 ih_regs->psp_reg_id = PSP_REG_IH_RB_CNTL_RING2; 86 } 87 } 88 89 /** 90 * force_update_wptr_for_self_int - Force update the wptr for self interrupt 91 * 92 * @adev: amdgpu_device pointer 93 * @threshold: threshold to trigger the wptr reporting 94 * @timeout: timeout to trigger the wptr reporting 95 * @enabled: Enable/disable timeout flush mechanism 96 * 97 * threshold input range: 0 ~ 15, default 0, 98 * real_threshold = 2^threshold 99 * timeout input range: 0 ~ 20, default 8, 100 * real_timeout = (2^timeout) * 1024 / (socclk_freq) 101 * 102 * Force update wptr for self interrupt ( >= SIENNA_CICHLID). 103 */ 104 static void 105 force_update_wptr_for_self_int(struct amdgpu_device *adev, 106 u32 threshold, u32 timeout, bool enabled) 107 { 108 u32 ih_cntl, ih_rb_cntl; 109 110 if (adev->asic_type < CHIP_SIENNA_CICHLID) 111 return; 112 113 ih_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_CNTL2); 114 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1); 115 116 ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL2, 117 SELF_IV_FORCE_WPTR_UPDATE_TIMEOUT, timeout); 118 ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL2, 119 SELF_IV_FORCE_WPTR_UPDATE_ENABLE, enabled); 120 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING1, 121 RB_USED_INT_THRESHOLD, threshold); 122 123 WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1, ih_rb_cntl); 124 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2); 125 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING2, 126 RB_USED_INT_THRESHOLD, threshold); 127 WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2, ih_rb_cntl); 128 WREG32_SOC15(OSSSYS, 0, mmIH_CNTL2, ih_cntl); 129 } 130 131 /** 132 * navi10_ih_toggle_ring_interrupts - toggle the interrupt ring buffer 133 * 134 * @adev: amdgpu_device pointer 135 * @ih: amdgpu_ih_ring pointet 136 * @enable: true - enable the interrupts, false - disable the interrupts 137 * 138 * Toggle the interrupt ring buffer (NAVI10) 139 */ 140 static int navi10_ih_toggle_ring_interrupts(struct amdgpu_device *adev, 141 struct amdgpu_ih_ring *ih, 142 bool enable) 143 { 144 struct amdgpu_ih_regs *ih_regs; 145 uint32_t tmp; 146 147 ih_regs = &ih->ih_regs; 148 149 tmp = RREG32(ih_regs->ih_rb_cntl); 150 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RB_ENABLE, (enable ? 1 : 0)); 151 /* enable_intr field is only valid in ring0 */ 152 if (ih == &adev->irq.ih) 153 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, ENABLE_INTR, (enable ? 1 : 0)); 154 if (amdgpu_sriov_vf(adev)) { 155 if (psp_reg_program(&adev->psp, ih_regs->psp_reg_id, tmp)) { 156 dev_err(adev->dev, "PSP program IH_RB_CNTL failed!\n"); 157 return -ETIMEDOUT; 158 } 159 } else { 160 WREG32(ih_regs->ih_rb_cntl, tmp); 161 } 162 163 if (enable) { 164 ih->enabled = true; 165 } else { 166 /* set rptr, wptr to 0 */ 167 WREG32(ih_regs->ih_rb_rptr, 0); 168 WREG32(ih_regs->ih_rb_wptr, 0); 169 ih->enabled = false; 170 ih->rptr = 0; 171 } 172 173 return 0; 174 } 175 176 /** 177 * navi10_ih_toggle_interrupts - Toggle all the available interrupt ring buffers 178 * 179 * @adev: amdgpu_device pointer 180 * @enable: enable or disable interrupt ring buffers 181 * 182 * Toggle all the available interrupt ring buffers (NAVI10). 183 */ 184 static int navi10_ih_toggle_interrupts(struct amdgpu_device *adev, bool enable) 185 { 186 struct amdgpu_ih_ring *ih[] = {&adev->irq.ih, &adev->irq.ih1, &adev->irq.ih2}; 187 int i; 188 int r; 189 190 for (i = 0; i < ARRAY_SIZE(ih); i++) { 191 if (ih[i]->ring_size) { 192 r = navi10_ih_toggle_ring_interrupts(adev, ih[i], enable); 193 if (r) 194 return r; 195 } 196 } 197 198 return 0; 199 } 200 201 static uint32_t navi10_ih_rb_cntl(struct amdgpu_ih_ring *ih, uint32_t ih_rb_cntl) 202 { 203 int rb_bufsz = order_base_2(ih->ring_size / 4); 204 205 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, 206 MC_SPACE, ih->use_bus_addr ? 1 : 4); 207 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, 208 WPTR_OVERFLOW_CLEAR, 1); 209 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, 210 WPTR_OVERFLOW_ENABLE, 1); 211 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_SIZE, rb_bufsz); 212 /* Ring Buffer write pointer writeback. If enabled, IH_RB_WPTR register 213 * value is written to memory 214 */ 215 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, 216 WPTR_WRITEBACK_ENABLE, 1); 217 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_SNOOP, 1); 218 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_RO, 0); 219 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_VMID, 0); 220 221 return ih_rb_cntl; 222 } 223 224 static uint32_t navi10_ih_doorbell_rptr(struct amdgpu_ih_ring *ih) 225 { 226 u32 ih_doorbell_rtpr = 0; 227 228 if (ih->use_doorbell) { 229 ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr, 230 IH_DOORBELL_RPTR, OFFSET, 231 ih->doorbell_index); 232 ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr, 233 IH_DOORBELL_RPTR, 234 ENABLE, 1); 235 } else { 236 ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr, 237 IH_DOORBELL_RPTR, 238 ENABLE, 0); 239 } 240 return ih_doorbell_rtpr; 241 } 242 243 /** 244 * navi10_ih_enable_ring - enable an ih ring buffer 245 * 246 * @adev: amdgpu_device pointer 247 * @ih: amdgpu_ih_ring pointer 248 * 249 * Enable an ih ring buffer (NAVI10) 250 */ 251 static int navi10_ih_enable_ring(struct amdgpu_device *adev, 252 struct amdgpu_ih_ring *ih) 253 { 254 struct amdgpu_ih_regs *ih_regs; 255 uint32_t tmp; 256 257 ih_regs = &ih->ih_regs; 258 259 /* Ring Buffer base. [39:8] of 40-bit address of the beginning of the ring buffer*/ 260 WREG32(ih_regs->ih_rb_base, ih->gpu_addr >> 8); 261 WREG32(ih_regs->ih_rb_base_hi, (ih->gpu_addr >> 40) & 0xff); 262 263 tmp = RREG32(ih_regs->ih_rb_cntl); 264 tmp = navi10_ih_rb_cntl(ih, tmp); 265 if (ih == &adev->irq.ih) 266 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RPTR_REARM, !!adev->irq.msi_enabled); 267 if (ih == &adev->irq.ih1) { 268 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_ENABLE, 0); 269 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RB_FULL_DRAIN_ENABLE, 1); 270 } 271 if (amdgpu_sriov_vf(adev)) { 272 if (psp_reg_program(&adev->psp, ih_regs->psp_reg_id, tmp)) { 273 dev_err(adev->dev, "PSP program IH_RB_CNTL failed!\n"); 274 return -ETIMEDOUT; 275 } 276 } else { 277 WREG32(ih_regs->ih_rb_cntl, tmp); 278 } 279 280 if (ih == &adev->irq.ih) { 281 /* set the ih ring 0 writeback address whether it's enabled or not */ 282 WREG32(ih_regs->ih_rb_wptr_addr_lo, lower_32_bits(ih->wptr_addr)); 283 WREG32(ih_regs->ih_rb_wptr_addr_hi, upper_32_bits(ih->wptr_addr) & 0xFFFF); 284 } 285 286 /* set rptr, wptr to 0 */ 287 WREG32(ih_regs->ih_rb_wptr, 0); 288 WREG32(ih_regs->ih_rb_rptr, 0); 289 290 WREG32(ih_regs->ih_doorbell_rptr, navi10_ih_doorbell_rptr(ih)); 291 292 return 0; 293 } 294 295 /** 296 * navi10_ih_irq_init - init and enable the interrupt ring 297 * 298 * @adev: amdgpu_device pointer 299 * 300 * Allocate a ring buffer for the interrupt controller, 301 * enable the RLC, disable interrupts, enable the IH 302 * ring buffer and enable it (NAVI). 303 * Called at device load and reume. 304 * Returns 0 for success, errors for failure. 305 */ 306 static int navi10_ih_irq_init(struct amdgpu_device *adev) 307 { 308 struct amdgpu_ih_ring *ih[] = {&adev->irq.ih, &adev->irq.ih1, &adev->irq.ih2}; 309 u32 ih_chicken; 310 u32 tmp; 311 int ret; 312 int i; 313 314 /* disable irqs */ 315 ret = navi10_ih_toggle_interrupts(adev, false); 316 if (ret) 317 return ret; 318 319 adev->nbio.funcs->ih_control(adev); 320 321 if (unlikely(adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT)) { 322 if (ih[0]->use_bus_addr) { 323 switch (adev->asic_type) { 324 case CHIP_SIENNA_CICHLID: 325 case CHIP_NAVY_FLOUNDER: 326 case CHIP_VANGOGH: 327 case CHIP_DIMGREY_CAVEFISH: 328 ih_chicken = RREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN_Sienna_Cichlid); 329 ih_chicken = REG_SET_FIELD(ih_chicken, 330 IH_CHICKEN, MC_SPACE_GPA_ENABLE, 1); 331 WREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN_Sienna_Cichlid, ih_chicken); 332 break; 333 default: 334 ih_chicken = RREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN); 335 ih_chicken = REG_SET_FIELD(ih_chicken, 336 IH_CHICKEN, MC_SPACE_GPA_ENABLE, 1); 337 WREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN, ih_chicken); 338 break; 339 } 340 } 341 } 342 343 for (i = 0; i < ARRAY_SIZE(ih); i++) { 344 if (ih[i]->ring_size) { 345 ret = navi10_ih_enable_ring(adev, ih[i]); 346 if (ret) 347 return ret; 348 } 349 } 350 351 /* update doorbell range for ih ring 0*/ 352 adev->nbio.funcs->ih_doorbell_range(adev, ih[0]->use_doorbell, 353 ih[0]->doorbell_index); 354 355 tmp = RREG32_SOC15(OSSSYS, 0, mmIH_STORM_CLIENT_LIST_CNTL); 356 tmp = REG_SET_FIELD(tmp, IH_STORM_CLIENT_LIST_CNTL, 357 CLIENT18_IS_STORM_CLIENT, 1); 358 WREG32_SOC15(OSSSYS, 0, mmIH_STORM_CLIENT_LIST_CNTL, tmp); 359 360 tmp = RREG32_SOC15(OSSSYS, 0, mmIH_INT_FLOOD_CNTL); 361 tmp = REG_SET_FIELD(tmp, IH_INT_FLOOD_CNTL, FLOOD_CNTL_ENABLE, 1); 362 WREG32_SOC15(OSSSYS, 0, mmIH_INT_FLOOD_CNTL, tmp); 363 364 pci_set_master(adev->pdev); 365 366 /* enable interrupts */ 367 ret = navi10_ih_toggle_interrupts(adev, true); 368 if (ret) 369 return ret; 370 /* enable wptr force update for self int */ 371 force_update_wptr_for_self_int(adev, 0, 8, true); 372 373 return 0; 374 } 375 376 /** 377 * navi10_ih_irq_disable - disable interrupts 378 * 379 * @adev: amdgpu_device pointer 380 * 381 * Disable interrupts on the hw (NAVI10). 382 */ 383 static void navi10_ih_irq_disable(struct amdgpu_device *adev) 384 { 385 force_update_wptr_for_self_int(adev, 0, 8, false); 386 navi10_ih_toggle_interrupts(adev, false); 387 388 /* Wait and acknowledge irq */ 389 mdelay(1); 390 } 391 392 /** 393 * navi10_ih_get_wptr - get the IH ring buffer wptr 394 * 395 * @adev: amdgpu_device pointer 396 * @ih: IH ring buffer to fetch wptr 397 * 398 * Get the IH ring buffer wptr from either the register 399 * or the writeback memory buffer (NAVI10). Also check for 400 * ring buffer overflow and deal with it. 401 * Returns the value of the wptr. 402 */ 403 static u32 navi10_ih_get_wptr(struct amdgpu_device *adev, 404 struct amdgpu_ih_ring *ih) 405 { 406 u32 wptr, tmp; 407 struct amdgpu_ih_regs *ih_regs; 408 409 wptr = le32_to_cpu(*ih->wptr_cpu); 410 ih_regs = &ih->ih_regs; 411 412 if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) 413 goto out; 414 415 wptr = RREG32_NO_KIQ(ih_regs->ih_rb_wptr); 416 if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) 417 goto out; 418 wptr = REG_SET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW, 0); 419 420 /* When a ring buffer overflow happen start parsing interrupt 421 * from the last not overwritten vector (wptr + 32). Hopefully 422 * this should allow us to catch up. 423 */ 424 tmp = (wptr + 32) & ih->ptr_mask; 425 dev_warn(adev->dev, "IH ring buffer overflow " 426 "(0x%08X, 0x%08X, 0x%08X)\n", 427 wptr, ih->rptr, tmp); 428 ih->rptr = tmp; 429 430 tmp = RREG32_NO_KIQ(ih_regs->ih_rb_cntl); 431 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1); 432 WREG32_NO_KIQ(ih_regs->ih_rb_cntl, tmp); 433 out: 434 return (wptr & ih->ptr_mask); 435 } 436 437 /** 438 * navi10_ih_irq_rearm - rearm IRQ if lost 439 * 440 * @adev: amdgpu_device pointer 441 * @ih: IH ring to match 442 * 443 */ 444 static void navi10_ih_irq_rearm(struct amdgpu_device *adev, 445 struct amdgpu_ih_ring *ih) 446 { 447 uint32_t v = 0; 448 uint32_t i = 0; 449 struct amdgpu_ih_regs *ih_regs; 450 451 ih_regs = &ih->ih_regs; 452 453 /* Rearm IRQ / re-write doorbell if doorbell write is lost */ 454 for (i = 0; i < MAX_REARM_RETRY; i++) { 455 v = RREG32_NO_KIQ(ih_regs->ih_rb_rptr); 456 if ((v < ih->ring_size) && (v != ih->rptr)) 457 WDOORBELL32(ih->doorbell_index, ih->rptr); 458 else 459 break; 460 } 461 } 462 463 /** 464 * navi10_ih_set_rptr - set the IH ring buffer rptr 465 * 466 * @adev: amdgpu_device pointer 467 * 468 * @ih: IH ring buffer to set rptr 469 * Set the IH ring buffer rptr. 470 */ 471 static void navi10_ih_set_rptr(struct amdgpu_device *adev, 472 struct amdgpu_ih_ring *ih) 473 { 474 struct amdgpu_ih_regs *ih_regs; 475 476 if (ih->use_doorbell) { 477 /* XXX check if swapping is necessary on BE */ 478 *ih->rptr_cpu = ih->rptr; 479 WDOORBELL32(ih->doorbell_index, ih->rptr); 480 481 if (amdgpu_sriov_vf(adev)) 482 navi10_ih_irq_rearm(adev, ih); 483 } else { 484 ih_regs = &ih->ih_regs; 485 WREG32(ih_regs->ih_rb_rptr, ih->rptr); 486 } 487 } 488 489 /** 490 * navi10_ih_self_irq - dispatch work for ring 1 and 2 491 * 492 * @adev: amdgpu_device pointer 493 * @source: irq source 494 * @entry: IV with WPTR update 495 * 496 * Update the WPTR from the IV and schedule work to handle the entries. 497 */ 498 static int navi10_ih_self_irq(struct amdgpu_device *adev, 499 struct amdgpu_irq_src *source, 500 struct amdgpu_iv_entry *entry) 501 { 502 uint32_t wptr = cpu_to_le32(entry->src_data[0]); 503 504 switch (entry->ring_id) { 505 case 1: 506 *adev->irq.ih1.wptr_cpu = wptr; 507 schedule_work(&adev->irq.ih1_work); 508 break; 509 case 2: 510 *adev->irq.ih2.wptr_cpu = wptr; 511 schedule_work(&adev->irq.ih2_work); 512 break; 513 default: break; 514 } 515 return 0; 516 } 517 518 static const struct amdgpu_irq_src_funcs navi10_ih_self_irq_funcs = { 519 .process = navi10_ih_self_irq, 520 }; 521 522 static void navi10_ih_set_self_irq_funcs(struct amdgpu_device *adev) 523 { 524 adev->irq.self_irq.num_types = 0; 525 adev->irq.self_irq.funcs = &navi10_ih_self_irq_funcs; 526 } 527 528 static int navi10_ih_early_init(void *handle) 529 { 530 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 531 532 navi10_ih_set_interrupt_funcs(adev); 533 navi10_ih_set_self_irq_funcs(adev); 534 return 0; 535 } 536 537 static int navi10_ih_sw_init(void *handle) 538 { 539 int r; 540 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 541 bool use_bus_addr; 542 543 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_IH, 0, 544 &adev->irq.self_irq); 545 546 if (r) 547 return r; 548 549 /* use gpu virtual address for ih ring 550 * until ih_checken is programmed to allow 551 * use bus address for ih ring by psp bl */ 552 if ((adev->flags & AMD_IS_APU) || 553 (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) 554 use_bus_addr = false; 555 else 556 use_bus_addr = true; 557 r = amdgpu_ih_ring_init(adev, &adev->irq.ih, 256 * 1024, use_bus_addr); 558 if (r) 559 return r; 560 561 adev->irq.ih.use_doorbell = true; 562 adev->irq.ih.doorbell_index = adev->doorbell_index.ih << 1; 563 564 adev->irq.ih1.ring_size = 0; 565 adev->irq.ih2.ring_size = 0; 566 567 /* initialize ih control registers offset */ 568 navi10_ih_init_register_offset(adev); 569 570 r = amdgpu_ih_ring_init(adev, &adev->irq.ih_soft, PAGE_SIZE, true); 571 if (r) 572 return r; 573 574 r = amdgpu_irq_init(adev); 575 576 return r; 577 } 578 579 static int navi10_ih_sw_fini(void *handle) 580 { 581 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 582 583 amdgpu_irq_fini(adev); 584 amdgpu_ih_ring_fini(adev, &adev->irq.ih2); 585 amdgpu_ih_ring_fini(adev, &adev->irq.ih1); 586 amdgpu_ih_ring_fini(adev, &adev->irq.ih); 587 588 return 0; 589 } 590 591 static int navi10_ih_hw_init(void *handle) 592 { 593 int r; 594 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 595 596 r = navi10_ih_irq_init(adev); 597 if (r) 598 return r; 599 600 return 0; 601 } 602 603 static int navi10_ih_hw_fini(void *handle) 604 { 605 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 606 607 navi10_ih_irq_disable(adev); 608 609 return 0; 610 } 611 612 static int navi10_ih_suspend(void *handle) 613 { 614 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 615 616 return navi10_ih_hw_fini(adev); 617 } 618 619 static int navi10_ih_resume(void *handle) 620 { 621 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 622 623 return navi10_ih_hw_init(adev); 624 } 625 626 static bool navi10_ih_is_idle(void *handle) 627 { 628 /* todo */ 629 return true; 630 } 631 632 static int navi10_ih_wait_for_idle(void *handle) 633 { 634 /* todo */ 635 return -ETIMEDOUT; 636 } 637 638 static int navi10_ih_soft_reset(void *handle) 639 { 640 /* todo */ 641 return 0; 642 } 643 644 static void navi10_ih_update_clockgating_state(struct amdgpu_device *adev, 645 bool enable) 646 { 647 uint32_t data, def, field_val; 648 649 if (adev->cg_flags & AMD_CG_SUPPORT_IH_CG) { 650 def = data = RREG32_SOC15(OSSSYS, 0, mmIH_CLK_CTRL); 651 field_val = enable ? 0 : 1; 652 data = REG_SET_FIELD(data, IH_CLK_CTRL, 653 DBUS_MUX_CLK_SOFT_OVERRIDE, field_val); 654 data = REG_SET_FIELD(data, IH_CLK_CTRL, 655 OSSSYS_SHARE_CLK_SOFT_OVERRIDE, field_val); 656 data = REG_SET_FIELD(data, IH_CLK_CTRL, 657 LIMIT_SMN_CLK_SOFT_OVERRIDE, field_val); 658 data = REG_SET_FIELD(data, IH_CLK_CTRL, 659 DYN_CLK_SOFT_OVERRIDE, field_val); 660 data = REG_SET_FIELD(data, IH_CLK_CTRL, 661 REG_CLK_SOFT_OVERRIDE, field_val); 662 if (def != data) 663 WREG32_SOC15(OSSSYS, 0, mmIH_CLK_CTRL, data); 664 } 665 666 return; 667 } 668 669 static int navi10_ih_set_clockgating_state(void *handle, 670 enum amd_clockgating_state state) 671 { 672 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 673 674 navi10_ih_update_clockgating_state(adev, 675 state == AMD_CG_STATE_GATE); 676 return 0; 677 } 678 679 static int navi10_ih_set_powergating_state(void *handle, 680 enum amd_powergating_state state) 681 { 682 return 0; 683 } 684 685 static void navi10_ih_get_clockgating_state(void *handle, u32 *flags) 686 { 687 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 688 689 if (!RREG32_SOC15(OSSSYS, 0, mmIH_CLK_CTRL)) 690 *flags |= AMD_CG_SUPPORT_IH_CG; 691 692 return; 693 } 694 695 static const struct amd_ip_funcs navi10_ih_ip_funcs = { 696 .name = "navi10_ih", 697 .early_init = navi10_ih_early_init, 698 .late_init = NULL, 699 .sw_init = navi10_ih_sw_init, 700 .sw_fini = navi10_ih_sw_fini, 701 .hw_init = navi10_ih_hw_init, 702 .hw_fini = navi10_ih_hw_fini, 703 .suspend = navi10_ih_suspend, 704 .resume = navi10_ih_resume, 705 .is_idle = navi10_ih_is_idle, 706 .wait_for_idle = navi10_ih_wait_for_idle, 707 .soft_reset = navi10_ih_soft_reset, 708 .set_clockgating_state = navi10_ih_set_clockgating_state, 709 .set_powergating_state = navi10_ih_set_powergating_state, 710 .get_clockgating_state = navi10_ih_get_clockgating_state, 711 }; 712 713 static const struct amdgpu_ih_funcs navi10_ih_funcs = { 714 .get_wptr = navi10_ih_get_wptr, 715 .decode_iv = amdgpu_ih_decode_iv_helper, 716 .set_rptr = navi10_ih_set_rptr 717 }; 718 719 static void navi10_ih_set_interrupt_funcs(struct amdgpu_device *adev) 720 { 721 if (adev->irq.ih_funcs == NULL) 722 adev->irq.ih_funcs = &navi10_ih_funcs; 723 } 724 725 const struct amdgpu_ip_block_version navi10_ih_ip_block = 726 { 727 .type = AMD_IP_BLOCK_TYPE_IH, 728 .major = 5, 729 .minor = 0, 730 .rev = 0, 731 .funcs = &navi10_ih_ip_funcs, 732 }; 733