1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/pci.h> 25 26 #include "amdgpu.h" 27 #include "amdgpu_ih.h" 28 29 #include "oss/osssys_5_0_0_offset.h" 30 #include "oss/osssys_5_0_0_sh_mask.h" 31 32 #include "soc15_common.h" 33 #include "navi10_ih.h" 34 35 #define MAX_REARM_RETRY 10 36 37 #define mmIH_CHICKEN_Sienna_Cichlid 0x018d 38 #define mmIH_CHICKEN_Sienna_Cichlid_BASE_IDX 0 39 40 static void navi10_ih_set_interrupt_funcs(struct amdgpu_device *adev); 41 42 /** 43 * navi10_ih_init_register_offset - Initialize register offset for ih rings 44 * 45 * @adev: amdgpu_device pointer 46 * 47 * Initialize register offset ih rings (NAVI10). 48 */ 49 static void navi10_ih_init_register_offset(struct amdgpu_device *adev) 50 { 51 struct amdgpu_ih_regs *ih_regs; 52 53 if (adev->irq.ih.ring_size) { 54 ih_regs = &adev->irq.ih.ih_regs; 55 ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE); 56 ih_regs->ih_rb_base_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_HI); 57 ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL); 58 ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR); 59 ih_regs->ih_rb_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR); 60 ih_regs->ih_doorbell_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_DOORBELL_RPTR); 61 ih_regs->ih_rb_wptr_addr_lo = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_ADDR_LO); 62 ih_regs->ih_rb_wptr_addr_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_ADDR_HI); 63 ih_regs->psp_reg_id = PSP_REG_IH_RB_CNTL; 64 } 65 66 if (adev->irq.ih1.ring_size) { 67 ih_regs = &adev->irq.ih1.ih_regs; 68 ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_RING1); 69 ih_regs->ih_rb_base_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_HI_RING1); 70 ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL_RING1); 71 ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_RING1); 72 ih_regs->ih_rb_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR_RING1); 73 ih_regs->ih_doorbell_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_DOORBELL_RPTR_RING1); 74 ih_regs->psp_reg_id = PSP_REG_IH_RB_CNTL_RING1; 75 } 76 77 if (adev->irq.ih2.ring_size) { 78 ih_regs = &adev->irq.ih2.ih_regs; 79 ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_RING2); 80 ih_regs->ih_rb_base_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_HI_RING2); 81 ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL_RING2); 82 ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_RING2); 83 ih_regs->ih_rb_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR_RING2); 84 ih_regs->ih_doorbell_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_DOORBELL_RPTR_RING2); 85 ih_regs->psp_reg_id = PSP_REG_IH_RB_CNTL_RING2; 86 } 87 } 88 89 /** 90 * force_update_wptr_for_self_int - Force update the wptr for self interrupt 91 * 92 * @adev: amdgpu_device pointer 93 * @threshold: threshold to trigger the wptr reporting 94 * @timeout: timeout to trigger the wptr reporting 95 * @enabled: Enable/disable timeout flush mechanism 96 * 97 * threshold input range: 0 ~ 15, default 0, 98 * real_threshold = 2^threshold 99 * timeout input range: 0 ~ 20, default 8, 100 * real_timeout = (2^timeout) * 1024 / (socclk_freq) 101 * 102 * Force update wptr for self interrupt ( >= SIENNA_CICHLID). 103 */ 104 static void 105 force_update_wptr_for_self_int(struct amdgpu_device *adev, 106 u32 threshold, u32 timeout, bool enabled) 107 { 108 u32 ih_cntl, ih_rb_cntl; 109 110 if (adev->asic_type < CHIP_SIENNA_CICHLID) 111 return; 112 113 ih_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_CNTL2); 114 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1); 115 116 ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL2, 117 SELF_IV_FORCE_WPTR_UPDATE_TIMEOUT, timeout); 118 ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL2, 119 SELF_IV_FORCE_WPTR_UPDATE_ENABLE, enabled); 120 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING1, 121 RB_USED_INT_THRESHOLD, threshold); 122 123 WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1, ih_rb_cntl); 124 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2); 125 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING2, 126 RB_USED_INT_THRESHOLD, threshold); 127 WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2, ih_rb_cntl); 128 WREG32_SOC15(OSSSYS, 0, mmIH_CNTL2, ih_cntl); 129 } 130 131 /** 132 * navi10_ih_enable_interrupts - Enable the interrupt ring buffer 133 * 134 * @adev: amdgpu_device pointer 135 * 136 * Enable the interrupt ring buffer (NAVI10). 137 */ 138 static void navi10_ih_enable_interrupts(struct amdgpu_device *adev) 139 { 140 u32 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL); 141 142 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 1); 143 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, ENABLE_INTR, 1); 144 if (amdgpu_sriov_vf(adev) && adev->asic_type < CHIP_NAVI10) { 145 if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL, ih_rb_cntl)) { 146 DRM_ERROR("PSP program IH_RB_CNTL failed!\n"); 147 return; 148 } 149 } else { 150 WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL, ih_rb_cntl); 151 } 152 153 adev->irq.ih.enabled = true; 154 155 if (adev->irq.ih1.ring_size) { 156 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1); 157 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING1, 158 RB_ENABLE, 1); 159 if (amdgpu_sriov_vf(adev) && adev->asic_type < CHIP_NAVI10) { 160 if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL_RING1, 161 ih_rb_cntl)) { 162 DRM_ERROR("program IH_RB_CNTL_RING1 failed!\n"); 163 return; 164 } 165 } else { 166 WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1, ih_rb_cntl); 167 } 168 adev->irq.ih1.enabled = true; 169 } 170 171 if (adev->irq.ih2.ring_size) { 172 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2); 173 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING2, 174 RB_ENABLE, 1); 175 if (amdgpu_sriov_vf(adev) && adev->asic_type < CHIP_NAVI10) { 176 if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL_RING2, 177 ih_rb_cntl)) { 178 DRM_ERROR("program IH_RB_CNTL_RING2 failed!\n"); 179 return; 180 } 181 } else { 182 WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2, ih_rb_cntl); 183 } 184 adev->irq.ih2.enabled = true; 185 } 186 187 if (adev->irq.ih_soft.ring_size) 188 adev->irq.ih_soft.enabled = true; 189 } 190 191 /** 192 * navi10_ih_disable_interrupts - Disable the interrupt ring buffer 193 * 194 * @adev: amdgpu_device pointer 195 * 196 * Disable the interrupt ring buffer (NAVI10). 197 */ 198 static void navi10_ih_disable_interrupts(struct amdgpu_device *adev) 199 { 200 u32 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL); 201 202 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 0); 203 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, ENABLE_INTR, 0); 204 if (amdgpu_sriov_vf(adev) && adev->asic_type < CHIP_NAVI10) { 205 if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL, ih_rb_cntl)) { 206 DRM_ERROR("PSP program IH_RB_CNTL failed!\n"); 207 return; 208 } 209 } else { 210 WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL, ih_rb_cntl); 211 } 212 213 /* set rptr, wptr to 0 */ 214 WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR, 0); 215 WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR, 0); 216 adev->irq.ih.enabled = false; 217 adev->irq.ih.rptr = 0; 218 219 if (adev->irq.ih1.ring_size) { 220 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1); 221 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING1, 222 RB_ENABLE, 0); 223 if (amdgpu_sriov_vf(adev) && adev->asic_type < CHIP_NAVI10) { 224 if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL_RING1, 225 ih_rb_cntl)) { 226 DRM_ERROR("program IH_RB_CNTL_RING1 failed!\n"); 227 return; 228 } 229 } else { 230 WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1, ih_rb_cntl); 231 } 232 /* set rptr, wptr to 0 */ 233 WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR_RING1, 0); 234 WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_RING1, 0); 235 adev->irq.ih1.enabled = false; 236 adev->irq.ih1.rptr = 0; 237 } 238 239 if (adev->irq.ih2.ring_size) { 240 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2); 241 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING2, 242 RB_ENABLE, 0); 243 if (amdgpu_sriov_vf(adev) && adev->asic_type < CHIP_NAVI10) { 244 if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL_RING2, 245 ih_rb_cntl)) { 246 DRM_ERROR("program IH_RB_CNTL_RING2 failed!\n"); 247 return; 248 } 249 } else { 250 WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2, ih_rb_cntl); 251 } 252 /* set rptr, wptr to 0 */ 253 WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR_RING2, 0); 254 WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_RING2, 0); 255 adev->irq.ih2.enabled = false; 256 adev->irq.ih2.rptr = 0; 257 } 258 259 } 260 261 static uint32_t navi10_ih_rb_cntl(struct amdgpu_ih_ring *ih, uint32_t ih_rb_cntl) 262 { 263 int rb_bufsz = order_base_2(ih->ring_size / 4); 264 265 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, 266 MC_SPACE, ih->use_bus_addr ? 1 : 4); 267 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, 268 WPTR_OVERFLOW_CLEAR, 1); 269 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, 270 WPTR_OVERFLOW_ENABLE, 1); 271 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_SIZE, rb_bufsz); 272 /* Ring Buffer write pointer writeback. If enabled, IH_RB_WPTR register 273 * value is written to memory 274 */ 275 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, 276 WPTR_WRITEBACK_ENABLE, 1); 277 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_SNOOP, 1); 278 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_RO, 0); 279 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_VMID, 0); 280 281 return ih_rb_cntl; 282 } 283 284 static uint32_t navi10_ih_doorbell_rptr(struct amdgpu_ih_ring *ih) 285 { 286 u32 ih_doorbell_rtpr = 0; 287 288 if (ih->use_doorbell) { 289 ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr, 290 IH_DOORBELL_RPTR, OFFSET, 291 ih->doorbell_index); 292 ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr, 293 IH_DOORBELL_RPTR, 294 ENABLE, 1); 295 } else { 296 ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr, 297 IH_DOORBELL_RPTR, 298 ENABLE, 0); 299 } 300 return ih_doorbell_rtpr; 301 } 302 303 static void navi10_ih_reroute_ih(struct amdgpu_device *adev) 304 { 305 uint32_t tmp; 306 307 /* Reroute to IH ring 1 for VMC */ 308 WREG32_SOC15(OSSSYS, 0, mmIH_CLIENT_CFG_INDEX, 0x12); 309 tmp = RREG32_SOC15(OSSSYS, 0, mmIH_CLIENT_CFG_DATA); 310 tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, CLIENT_TYPE, 1); 311 tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, RING_ID, 1); 312 WREG32_SOC15(OSSSYS, 0, mmIH_CLIENT_CFG_DATA, tmp); 313 314 /* Reroute IH ring 1 for UMC */ 315 WREG32_SOC15(OSSSYS, 0, mmIH_CLIENT_CFG_INDEX, 0x1B); 316 tmp = RREG32_SOC15(OSSSYS, 0, mmIH_CLIENT_CFG_DATA); 317 tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, RING_ID, 1); 318 WREG32_SOC15(OSSSYS, 0, mmIH_CLIENT_CFG_DATA, tmp); 319 } 320 321 /** 322 * navi10_ih_irq_init - init and enable the interrupt ring 323 * 324 * @adev: amdgpu_device pointer 325 * 326 * Allocate a ring buffer for the interrupt controller, 327 * enable the RLC, disable interrupts, enable the IH 328 * ring buffer and enable it (NAVI). 329 * Called at device load and reume. 330 * Returns 0 for success, errors for failure. 331 */ 332 static int navi10_ih_irq_init(struct amdgpu_device *adev) 333 { 334 struct amdgpu_ih_ring *ih = &adev->irq.ih; 335 u32 ih_rb_cntl, ih_chicken; 336 u32 tmp; 337 338 /* disable irqs */ 339 navi10_ih_disable_interrupts(adev); 340 341 adev->nbio.funcs->ih_control(adev); 342 343 /* Ring Buffer base. [39:8] of 40-bit address of the beginning of the ring buffer*/ 344 WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE, ih->gpu_addr >> 8); 345 WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE_HI, (ih->gpu_addr >> 40) & 0xff); 346 347 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL); 348 ih_rb_cntl = navi10_ih_rb_cntl(ih, ih_rb_cntl); 349 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RPTR_REARM, 350 !!adev->irq.msi_enabled); 351 if (amdgpu_sriov_vf(adev) && adev->asic_type < CHIP_NAVI10) { 352 if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL, ih_rb_cntl)) { 353 DRM_ERROR("PSP program IH_RB_CNTL failed!\n"); 354 return -ETIMEDOUT; 355 } 356 } else { 357 WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL, ih_rb_cntl); 358 } 359 if (adev->irq.ih1.ring_size) 360 navi10_ih_reroute_ih(adev); 361 362 if (unlikely(adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT)) { 363 if (ih->use_bus_addr) { 364 switch (adev->asic_type) { 365 case CHIP_SIENNA_CICHLID: 366 case CHIP_NAVY_FLOUNDER: 367 case CHIP_VANGOGH: 368 case CHIP_DIMGREY_CAVEFISH: 369 ih_chicken = RREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN_Sienna_Cichlid); 370 ih_chicken = REG_SET_FIELD(ih_chicken, 371 IH_CHICKEN, MC_SPACE_GPA_ENABLE, 1); 372 WREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN_Sienna_Cichlid, ih_chicken); 373 break; 374 default: 375 ih_chicken = RREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN); 376 ih_chicken = REG_SET_FIELD(ih_chicken, 377 IH_CHICKEN, MC_SPACE_GPA_ENABLE, 1); 378 WREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN, ih_chicken); 379 break; 380 } 381 } 382 } 383 384 /* set the writeback address whether it's enabled or not */ 385 WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_ADDR_LO, 386 lower_32_bits(ih->wptr_addr)); 387 WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_ADDR_HI, 388 upper_32_bits(ih->wptr_addr) & 0xFFFF); 389 390 /* set rptr, wptr to 0 */ 391 WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR, 0); 392 WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR, 0); 393 394 WREG32_SOC15(OSSSYS, 0, mmIH_DOORBELL_RPTR, 395 navi10_ih_doorbell_rptr(ih)); 396 397 adev->nbio.funcs->ih_doorbell_range(adev, ih->use_doorbell, 398 ih->doorbell_index); 399 400 ih = &adev->irq.ih1; 401 if (ih->ring_size) { 402 WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE_RING1, ih->gpu_addr >> 8); 403 WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE_HI_RING1, 404 (ih->gpu_addr >> 40) & 0xff); 405 406 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1); 407 ih_rb_cntl = navi10_ih_rb_cntl(ih, ih_rb_cntl); 408 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, 409 WPTR_OVERFLOW_ENABLE, 0); 410 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, 411 RB_FULL_DRAIN_ENABLE, 1); 412 if (amdgpu_sriov_vf(adev) && adev->asic_type < CHIP_NAVI10) { 413 if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL_RING1, 414 ih_rb_cntl)) { 415 DRM_ERROR("program IH_RB_CNTL_RING1 failed!\n"); 416 return -ETIMEDOUT; 417 } 418 } else { 419 WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1, ih_rb_cntl); 420 } 421 /* set rptr, wptr to 0 */ 422 WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_RING1, 0); 423 WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR_RING1, 0); 424 425 WREG32_SOC15(OSSSYS, 0, mmIH_DOORBELL_RPTR_RING1, 426 navi10_ih_doorbell_rptr(ih)); 427 } 428 429 ih = &adev->irq.ih2; 430 if (ih->ring_size) { 431 WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE_RING2, ih->gpu_addr >> 8); 432 WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE_HI_RING2, 433 (ih->gpu_addr >> 40) & 0xff); 434 435 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2); 436 ih_rb_cntl = navi10_ih_rb_cntl(ih, ih_rb_cntl); 437 438 if (amdgpu_sriov_vf(adev) && adev->asic_type < CHIP_NAVI10) { 439 if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL_RING2, 440 ih_rb_cntl)) { 441 DRM_ERROR("program IH_RB_CNTL_RING2 failed!\n"); 442 return -ETIMEDOUT; 443 } 444 } else { 445 WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2, ih_rb_cntl); 446 } 447 /* set rptr, wptr to 0 */ 448 WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_RING2, 0); 449 WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR_RING2, 0); 450 451 WREG32_SOC15(OSSSYS, 0, mmIH_DOORBELL_RPTR_RING2, 452 navi10_ih_doorbell_rptr(ih)); 453 } 454 455 456 tmp = RREG32_SOC15(OSSSYS, 0, mmIH_STORM_CLIENT_LIST_CNTL); 457 tmp = REG_SET_FIELD(tmp, IH_STORM_CLIENT_LIST_CNTL, 458 CLIENT18_IS_STORM_CLIENT, 1); 459 WREG32_SOC15(OSSSYS, 0, mmIH_STORM_CLIENT_LIST_CNTL, tmp); 460 461 tmp = RREG32_SOC15(OSSSYS, 0, mmIH_INT_FLOOD_CNTL); 462 tmp = REG_SET_FIELD(tmp, IH_INT_FLOOD_CNTL, FLOOD_CNTL_ENABLE, 1); 463 WREG32_SOC15(OSSSYS, 0, mmIH_INT_FLOOD_CNTL, tmp); 464 465 pci_set_master(adev->pdev); 466 467 /* enable interrupts */ 468 navi10_ih_enable_interrupts(adev); 469 /* enable wptr force update for self int */ 470 force_update_wptr_for_self_int(adev, 0, 8, true); 471 472 return 0; 473 } 474 475 /** 476 * navi10_ih_irq_disable - disable interrupts 477 * 478 * @adev: amdgpu_device pointer 479 * 480 * Disable interrupts on the hw (NAVI10). 481 */ 482 static void navi10_ih_irq_disable(struct amdgpu_device *adev) 483 { 484 force_update_wptr_for_self_int(adev, 0, 8, false); 485 navi10_ih_disable_interrupts(adev); 486 487 /* Wait and acknowledge irq */ 488 mdelay(1); 489 } 490 491 /** 492 * navi10_ih_get_wptr - get the IH ring buffer wptr 493 * 494 * @adev: amdgpu_device pointer 495 * @ih: IH ring buffer to fetch wptr 496 * 497 * Get the IH ring buffer wptr from either the register 498 * or the writeback memory buffer (NAVI10). Also check for 499 * ring buffer overflow and deal with it. 500 * Returns the value of the wptr. 501 */ 502 static u32 navi10_ih_get_wptr(struct amdgpu_device *adev, 503 struct amdgpu_ih_ring *ih) 504 { 505 u32 wptr, reg, tmp; 506 507 wptr = le32_to_cpu(*ih->wptr_cpu); 508 509 if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) 510 goto out; 511 512 if (ih == &adev->irq.ih) 513 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR); 514 else if (ih == &adev->irq.ih1) 515 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_RING1); 516 else if (ih == &adev->irq.ih2) 517 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_RING2); 518 else 519 BUG(); 520 521 wptr = RREG32_NO_KIQ(reg); 522 if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) 523 goto out; 524 wptr = REG_SET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW, 0); 525 526 /* When a ring buffer overflow happen start parsing interrupt 527 * from the last not overwritten vector (wptr + 32). Hopefully 528 * this should allow us to catch up. 529 */ 530 tmp = (wptr + 32) & ih->ptr_mask; 531 dev_warn(adev->dev, "IH ring buffer overflow " 532 "(0x%08X, 0x%08X, 0x%08X)\n", 533 wptr, ih->rptr, tmp); 534 ih->rptr = tmp; 535 536 if (ih == &adev->irq.ih) 537 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL); 538 else if (ih == &adev->irq.ih1) 539 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL_RING1); 540 else if (ih == &adev->irq.ih2) 541 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL_RING2); 542 else 543 BUG(); 544 545 tmp = RREG32_NO_KIQ(reg); 546 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1); 547 WREG32_NO_KIQ(reg, tmp); 548 out: 549 return (wptr & ih->ptr_mask); 550 } 551 552 /** 553 * navi10_ih_decode_iv - decode an interrupt vector 554 * 555 * @adev: amdgpu_device pointer 556 * @ih: IH ring buffer to decode 557 * @entry: IV entry to place decoded information into 558 * 559 * Decodes the interrupt vector at the current rptr 560 * position and also advance the position. 561 */ 562 static void navi10_ih_decode_iv(struct amdgpu_device *adev, 563 struct amdgpu_ih_ring *ih, 564 struct amdgpu_iv_entry *entry) 565 { 566 /* wptr/rptr are in bytes! */ 567 u32 ring_index = ih->rptr >> 2; 568 uint32_t dw[8]; 569 570 dw[0] = le32_to_cpu(ih->ring[ring_index + 0]); 571 dw[1] = le32_to_cpu(ih->ring[ring_index + 1]); 572 dw[2] = le32_to_cpu(ih->ring[ring_index + 2]); 573 dw[3] = le32_to_cpu(ih->ring[ring_index + 3]); 574 dw[4] = le32_to_cpu(ih->ring[ring_index + 4]); 575 dw[5] = le32_to_cpu(ih->ring[ring_index + 5]); 576 dw[6] = le32_to_cpu(ih->ring[ring_index + 6]); 577 dw[7] = le32_to_cpu(ih->ring[ring_index + 7]); 578 579 entry->client_id = dw[0] & 0xff; 580 entry->src_id = (dw[0] >> 8) & 0xff; 581 entry->ring_id = (dw[0] >> 16) & 0xff; 582 entry->vmid = (dw[0] >> 24) & 0xf; 583 entry->vmid_src = (dw[0] >> 31); 584 entry->timestamp = dw[1] | ((u64)(dw[2] & 0xffff) << 32); 585 entry->timestamp_src = dw[2] >> 31; 586 entry->pasid = dw[3] & 0xffff; 587 entry->pasid_src = dw[3] >> 31; 588 entry->src_data[0] = dw[4]; 589 entry->src_data[1] = dw[5]; 590 entry->src_data[2] = dw[6]; 591 entry->src_data[3] = dw[7]; 592 593 /* wptr/rptr are in bytes! */ 594 ih->rptr += 32; 595 } 596 597 /** 598 * navi10_ih_irq_rearm - rearm IRQ if lost 599 * 600 * @adev: amdgpu_device pointer 601 * @ih: IH ring to match 602 * 603 */ 604 static void navi10_ih_irq_rearm(struct amdgpu_device *adev, 605 struct amdgpu_ih_ring *ih) 606 { 607 uint32_t reg_rptr = 0; 608 uint32_t v = 0; 609 uint32_t i = 0; 610 611 if (ih == &adev->irq.ih) 612 reg_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR); 613 else if (ih == &adev->irq.ih1) 614 reg_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR_RING1); 615 else if (ih == &adev->irq.ih2) 616 reg_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR_RING2); 617 else 618 return; 619 620 /* Rearm IRQ / re-write doorbell if doorbell write is lost */ 621 for (i = 0; i < MAX_REARM_RETRY; i++) { 622 v = RREG32_NO_KIQ(reg_rptr); 623 if ((v < ih->ring_size) && (v != ih->rptr)) 624 WDOORBELL32(ih->doorbell_index, ih->rptr); 625 else 626 break; 627 } 628 } 629 630 /** 631 * navi10_ih_set_rptr - set the IH ring buffer rptr 632 * 633 * @adev: amdgpu_device pointer 634 * 635 * @ih: IH ring buffer to set rptr 636 * Set the IH ring buffer rptr. 637 */ 638 static void navi10_ih_set_rptr(struct amdgpu_device *adev, 639 struct amdgpu_ih_ring *ih) 640 { 641 if (ih->use_doorbell) { 642 /* XXX check if swapping is necessary on BE */ 643 *ih->rptr_cpu = ih->rptr; 644 WDOORBELL32(ih->doorbell_index, ih->rptr); 645 646 if (amdgpu_sriov_vf(adev)) 647 navi10_ih_irq_rearm(adev, ih); 648 } else if (ih == &adev->irq.ih) { 649 WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR, ih->rptr); 650 } else if (ih == &adev->irq.ih1) { 651 WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR_RING1, ih->rptr); 652 } else if (ih == &adev->irq.ih2) { 653 WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR_RING2, ih->rptr); 654 } 655 } 656 657 /** 658 * navi10_ih_self_irq - dispatch work for ring 1 and 2 659 * 660 * @adev: amdgpu_device pointer 661 * @source: irq source 662 * @entry: IV with WPTR update 663 * 664 * Update the WPTR from the IV and schedule work to handle the entries. 665 */ 666 static int navi10_ih_self_irq(struct amdgpu_device *adev, 667 struct amdgpu_irq_src *source, 668 struct amdgpu_iv_entry *entry) 669 { 670 uint32_t wptr = cpu_to_le32(entry->src_data[0]); 671 672 switch (entry->ring_id) { 673 case 1: 674 *adev->irq.ih1.wptr_cpu = wptr; 675 schedule_work(&adev->irq.ih1_work); 676 break; 677 case 2: 678 *adev->irq.ih2.wptr_cpu = wptr; 679 schedule_work(&adev->irq.ih2_work); 680 break; 681 default: break; 682 } 683 return 0; 684 } 685 686 static const struct amdgpu_irq_src_funcs navi10_ih_self_irq_funcs = { 687 .process = navi10_ih_self_irq, 688 }; 689 690 static void navi10_ih_set_self_irq_funcs(struct amdgpu_device *adev) 691 { 692 adev->irq.self_irq.num_types = 0; 693 adev->irq.self_irq.funcs = &navi10_ih_self_irq_funcs; 694 } 695 696 static int navi10_ih_early_init(void *handle) 697 { 698 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 699 700 navi10_ih_set_interrupt_funcs(adev); 701 navi10_ih_set_self_irq_funcs(adev); 702 return 0; 703 } 704 705 static int navi10_ih_sw_init(void *handle) 706 { 707 int r; 708 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 709 bool use_bus_addr; 710 711 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_IH, 0, 712 &adev->irq.self_irq); 713 714 if (r) 715 return r; 716 717 /* use gpu virtual address for ih ring 718 * until ih_checken is programmed to allow 719 * use bus address for ih ring by psp bl */ 720 if ((adev->flags & AMD_IS_APU) || 721 (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) 722 use_bus_addr = false; 723 else 724 use_bus_addr = true; 725 r = amdgpu_ih_ring_init(adev, &adev->irq.ih, 256 * 1024, use_bus_addr); 726 if (r) 727 return r; 728 729 adev->irq.ih.use_doorbell = true; 730 adev->irq.ih.doorbell_index = adev->doorbell_index.ih << 1; 731 732 adev->irq.ih1.ring_size = 0; 733 adev->irq.ih2.ring_size = 0; 734 735 if (adev->asic_type < CHIP_NAVI10) { 736 r = amdgpu_ih_ring_init(adev, &adev->irq.ih1, PAGE_SIZE, true); 737 if (r) 738 return r; 739 740 adev->irq.ih1.use_doorbell = true; 741 adev->irq.ih1.doorbell_index = 742 (adev->doorbell_index.ih + 1) << 1; 743 744 r = amdgpu_ih_ring_init(adev, &adev->irq.ih2, PAGE_SIZE, true); 745 if (r) 746 return r; 747 748 adev->irq.ih2.use_doorbell = true; 749 adev->irq.ih2.doorbell_index = 750 (adev->doorbell_index.ih + 2) << 1; 751 } 752 753 r = amdgpu_ih_ring_init(adev, &adev->irq.ih_soft, PAGE_SIZE, true); 754 if (r) 755 return r; 756 757 r = amdgpu_irq_init(adev); 758 759 return r; 760 } 761 762 static int navi10_ih_sw_fini(void *handle) 763 { 764 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 765 766 amdgpu_irq_fini(adev); 767 amdgpu_ih_ring_fini(adev, &adev->irq.ih2); 768 amdgpu_ih_ring_fini(adev, &adev->irq.ih1); 769 amdgpu_ih_ring_fini(adev, &adev->irq.ih); 770 771 return 0; 772 } 773 774 static int navi10_ih_hw_init(void *handle) 775 { 776 int r; 777 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 778 779 r = navi10_ih_irq_init(adev); 780 if (r) 781 return r; 782 783 return 0; 784 } 785 786 static int navi10_ih_hw_fini(void *handle) 787 { 788 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 789 790 navi10_ih_irq_disable(adev); 791 792 return 0; 793 } 794 795 static int navi10_ih_suspend(void *handle) 796 { 797 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 798 799 return navi10_ih_hw_fini(adev); 800 } 801 802 static int navi10_ih_resume(void *handle) 803 { 804 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 805 806 return navi10_ih_hw_init(adev); 807 } 808 809 static bool navi10_ih_is_idle(void *handle) 810 { 811 /* todo */ 812 return true; 813 } 814 815 static int navi10_ih_wait_for_idle(void *handle) 816 { 817 /* todo */ 818 return -ETIMEDOUT; 819 } 820 821 static int navi10_ih_soft_reset(void *handle) 822 { 823 /* todo */ 824 return 0; 825 } 826 827 static void navi10_ih_update_clockgating_state(struct amdgpu_device *adev, 828 bool enable) 829 { 830 uint32_t data, def, field_val; 831 832 if (adev->cg_flags & AMD_CG_SUPPORT_IH_CG) { 833 def = data = RREG32_SOC15(OSSSYS, 0, mmIH_CLK_CTRL); 834 field_val = enable ? 0 : 1; 835 data = REG_SET_FIELD(data, IH_CLK_CTRL, 836 DBUS_MUX_CLK_SOFT_OVERRIDE, field_val); 837 data = REG_SET_FIELD(data, IH_CLK_CTRL, 838 OSSSYS_SHARE_CLK_SOFT_OVERRIDE, field_val); 839 data = REG_SET_FIELD(data, IH_CLK_CTRL, 840 LIMIT_SMN_CLK_SOFT_OVERRIDE, field_val); 841 data = REG_SET_FIELD(data, IH_CLK_CTRL, 842 DYN_CLK_SOFT_OVERRIDE, field_val); 843 data = REG_SET_FIELD(data, IH_CLK_CTRL, 844 REG_CLK_SOFT_OVERRIDE, field_val); 845 if (def != data) 846 WREG32_SOC15(OSSSYS, 0, mmIH_CLK_CTRL, data); 847 } 848 849 return; 850 } 851 852 static int navi10_ih_set_clockgating_state(void *handle, 853 enum amd_clockgating_state state) 854 { 855 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 856 857 navi10_ih_update_clockgating_state(adev, 858 state == AMD_CG_STATE_GATE); 859 return 0; 860 } 861 862 static int navi10_ih_set_powergating_state(void *handle, 863 enum amd_powergating_state state) 864 { 865 return 0; 866 } 867 868 static void navi10_ih_get_clockgating_state(void *handle, u32 *flags) 869 { 870 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 871 872 if (!RREG32_SOC15(OSSSYS, 0, mmIH_CLK_CTRL)) 873 *flags |= AMD_CG_SUPPORT_IH_CG; 874 875 return; 876 } 877 878 static const struct amd_ip_funcs navi10_ih_ip_funcs = { 879 .name = "navi10_ih", 880 .early_init = navi10_ih_early_init, 881 .late_init = NULL, 882 .sw_init = navi10_ih_sw_init, 883 .sw_fini = navi10_ih_sw_fini, 884 .hw_init = navi10_ih_hw_init, 885 .hw_fini = navi10_ih_hw_fini, 886 .suspend = navi10_ih_suspend, 887 .resume = navi10_ih_resume, 888 .is_idle = navi10_ih_is_idle, 889 .wait_for_idle = navi10_ih_wait_for_idle, 890 .soft_reset = navi10_ih_soft_reset, 891 .set_clockgating_state = navi10_ih_set_clockgating_state, 892 .set_powergating_state = navi10_ih_set_powergating_state, 893 .get_clockgating_state = navi10_ih_get_clockgating_state, 894 }; 895 896 static const struct amdgpu_ih_funcs navi10_ih_funcs = { 897 .get_wptr = navi10_ih_get_wptr, 898 .decode_iv = navi10_ih_decode_iv, 899 .set_rptr = navi10_ih_set_rptr 900 }; 901 902 static void navi10_ih_set_interrupt_funcs(struct amdgpu_device *adev) 903 { 904 if (adev->irq.ih_funcs == NULL) 905 adev->irq.ih_funcs = &navi10_ih_funcs; 906 } 907 908 const struct amdgpu_ip_block_version navi10_ih_ip_block = 909 { 910 .type = AMD_IP_BLOCK_TYPE_IH, 911 .major = 5, 912 .minor = 0, 913 .rev = 0, 914 .funcs = &navi10_ih_ip_funcs, 915 }; 916