1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/pci.h> 25 26 #include "amdgpu.h" 27 #include "amdgpu_ih.h" 28 29 #include "oss/osssys_5_0_0_offset.h" 30 #include "oss/osssys_5_0_0_sh_mask.h" 31 32 #include "soc15_common.h" 33 #include "navi10_ih.h" 34 35 #define MAX_REARM_RETRY 10 36 37 #define mmIH_CHICKEN_Sienna_Cichlid 0x018d 38 #define mmIH_CHICKEN_Sienna_Cichlid_BASE_IDX 0 39 40 static void navi10_ih_set_interrupt_funcs(struct amdgpu_device *adev); 41 42 /** 43 * navi10_ih_init_register_offset - Initialize register offset for ih rings 44 * 45 * @adev: amdgpu_device pointer 46 * 47 * Initialize register offset ih rings (NAVI10). 48 */ 49 static void navi10_ih_init_register_offset(struct amdgpu_device *adev) 50 { 51 struct amdgpu_ih_regs *ih_regs; 52 53 if (adev->irq.ih.ring_size) { 54 ih_regs = &adev->irq.ih.ih_regs; 55 ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE); 56 ih_regs->ih_rb_base_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_HI); 57 ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL); 58 ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR); 59 ih_regs->ih_rb_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR); 60 ih_regs->ih_doorbell_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_DOORBELL_RPTR); 61 ih_regs->ih_rb_wptr_addr_lo = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_ADDR_LO); 62 ih_regs->ih_rb_wptr_addr_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_ADDR_HI); 63 ih_regs->psp_reg_id = PSP_REG_IH_RB_CNTL; 64 } 65 66 if (adev->irq.ih1.ring_size) { 67 ih_regs = &adev->irq.ih1.ih_regs; 68 ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_RING1); 69 ih_regs->ih_rb_base_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_HI_RING1); 70 ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL_RING1); 71 ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_RING1); 72 ih_regs->ih_rb_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR_RING1); 73 ih_regs->ih_doorbell_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_DOORBELL_RPTR_RING1); 74 ih_regs->psp_reg_id = PSP_REG_IH_RB_CNTL_RING1; 75 } 76 77 if (adev->irq.ih2.ring_size) { 78 ih_regs = &adev->irq.ih2.ih_regs; 79 ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_RING2); 80 ih_regs->ih_rb_base_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_HI_RING2); 81 ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL_RING2); 82 ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_RING2); 83 ih_regs->ih_rb_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR_RING2); 84 ih_regs->ih_doorbell_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_DOORBELL_RPTR_RING2); 85 ih_regs->psp_reg_id = PSP_REG_IH_RB_CNTL_RING2; 86 } 87 } 88 89 /** 90 * force_update_wptr_for_self_int - Force update the wptr for self interrupt 91 * 92 * @adev: amdgpu_device pointer 93 * @threshold: threshold to trigger the wptr reporting 94 * @timeout: timeout to trigger the wptr reporting 95 * @enabled: Enable/disable timeout flush mechanism 96 * 97 * threshold input range: 0 ~ 15, default 0, 98 * real_threshold = 2^threshold 99 * timeout input range: 0 ~ 20, default 8, 100 * real_timeout = (2^timeout) * 1024 / (socclk_freq) 101 * 102 * Force update wptr for self interrupt ( >= SIENNA_CICHLID). 103 */ 104 static void 105 force_update_wptr_for_self_int(struct amdgpu_device *adev, 106 u32 threshold, u32 timeout, bool enabled) 107 { 108 u32 ih_cntl, ih_rb_cntl; 109 110 if (adev->asic_type < CHIP_SIENNA_CICHLID) 111 return; 112 113 ih_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_CNTL2); 114 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1); 115 116 ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL2, 117 SELF_IV_FORCE_WPTR_UPDATE_TIMEOUT, timeout); 118 ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL2, 119 SELF_IV_FORCE_WPTR_UPDATE_ENABLE, enabled); 120 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING1, 121 RB_USED_INT_THRESHOLD, threshold); 122 123 WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1, ih_rb_cntl); 124 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2); 125 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING2, 126 RB_USED_INT_THRESHOLD, threshold); 127 WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2, ih_rb_cntl); 128 WREG32_SOC15(OSSSYS, 0, mmIH_CNTL2, ih_cntl); 129 } 130 131 /** 132 * navi10_ih_toggle_ring_interrupts - toggle the interrupt ring buffer 133 * 134 * @adev: amdgpu_device pointer 135 * @ih: amdgpu_ih_ring pointet 136 * @enable: true - enable the interrupts, false - disable the interrupts 137 * 138 * Toggle the interrupt ring buffer (NAVI10) 139 */ 140 static int navi10_ih_toggle_ring_interrupts(struct amdgpu_device *adev, 141 struct amdgpu_ih_ring *ih, 142 bool enable) 143 { 144 struct amdgpu_ih_regs *ih_regs; 145 uint32_t tmp; 146 147 ih_regs = &ih->ih_regs; 148 149 tmp = RREG32(ih_regs->ih_rb_cntl); 150 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RB_ENABLE, (enable ? 1 : 0)); 151 /* enable_intr field is only valid in ring0 */ 152 if (ih == &adev->irq.ih) 153 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, ENABLE_INTR, (enable ? 1 : 0)); 154 if (amdgpu_sriov_vf(adev) && adev->asic_type < CHIP_NAVI10) { 155 if (psp_reg_program(&adev->psp, ih_regs->psp_reg_id, tmp)) { 156 dev_err(adev->dev, "PSP program IH_RB_CNTL failed!\n"); 157 return -ETIMEDOUT; 158 } 159 } else { 160 WREG32(ih_regs->ih_rb_cntl, tmp); 161 } 162 163 if (enable) { 164 ih->enabled = true; 165 } else { 166 /* set rptr, wptr to 0 */ 167 WREG32(ih_regs->ih_rb_rptr, 0); 168 WREG32(ih_regs->ih_rb_wptr, 0); 169 ih->enabled = false; 170 ih->rptr = 0; 171 } 172 173 return 0; 174 } 175 176 /** 177 * navi10_ih_toggle_interrupts - Toggle all the available interrupt ring buffers 178 * 179 * @adev: amdgpu_device pointer 180 * @enable: enable or disable interrupt ring buffers 181 * 182 * Toggle all the available interrupt ring buffers (NAVI10). 183 */ 184 static int navi10_ih_toggle_interrupts(struct amdgpu_device *adev, bool enable) 185 { 186 struct amdgpu_ih_ring *ih[] = {&adev->irq.ih, &adev->irq.ih1, &adev->irq.ih2}; 187 int i; 188 int r; 189 190 for (i = 0; i < ARRAY_SIZE(ih); i++) { 191 if (ih[i]->ring_size) { 192 r = navi10_ih_toggle_ring_interrupts(adev, ih[i], enable); 193 if (r) 194 return r; 195 } 196 } 197 198 return 0; 199 } 200 201 static uint32_t navi10_ih_rb_cntl(struct amdgpu_ih_ring *ih, uint32_t ih_rb_cntl) 202 { 203 int rb_bufsz = order_base_2(ih->ring_size / 4); 204 205 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, 206 MC_SPACE, ih->use_bus_addr ? 1 : 4); 207 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, 208 WPTR_OVERFLOW_CLEAR, 1); 209 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, 210 WPTR_OVERFLOW_ENABLE, 1); 211 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_SIZE, rb_bufsz); 212 /* Ring Buffer write pointer writeback. If enabled, IH_RB_WPTR register 213 * value is written to memory 214 */ 215 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, 216 WPTR_WRITEBACK_ENABLE, 1); 217 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_SNOOP, 1); 218 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_RO, 0); 219 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_VMID, 0); 220 221 return ih_rb_cntl; 222 } 223 224 static uint32_t navi10_ih_doorbell_rptr(struct amdgpu_ih_ring *ih) 225 { 226 u32 ih_doorbell_rtpr = 0; 227 228 if (ih->use_doorbell) { 229 ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr, 230 IH_DOORBELL_RPTR, OFFSET, 231 ih->doorbell_index); 232 ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr, 233 IH_DOORBELL_RPTR, 234 ENABLE, 1); 235 } else { 236 ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr, 237 IH_DOORBELL_RPTR, 238 ENABLE, 0); 239 } 240 return ih_doorbell_rtpr; 241 } 242 243 /** 244 * navi10_ih_enable_ring - enable an ih ring buffer 245 * 246 * @adev: amdgpu_device pointer 247 * @ih: amdgpu_ih_ring pointer 248 * 249 * Enable an ih ring buffer (NAVI10) 250 */ 251 static int navi10_ih_enable_ring(struct amdgpu_device *adev, 252 struct amdgpu_ih_ring *ih) 253 { 254 struct amdgpu_ih_regs *ih_regs; 255 uint32_t tmp; 256 257 ih_regs = &ih->ih_regs; 258 259 /* Ring Buffer base. [39:8] of 40-bit address of the beginning of the ring buffer*/ 260 WREG32(ih_regs->ih_rb_base, ih->gpu_addr >> 8); 261 WREG32(ih_regs->ih_rb_base_hi, (ih->gpu_addr >> 40) & 0xff); 262 263 tmp = RREG32(ih_regs->ih_rb_cntl); 264 tmp = navi10_ih_rb_cntl(ih, tmp); 265 if (ih == &adev->irq.ih) 266 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RPTR_REARM, !!adev->irq.msi_enabled); 267 if (ih == &adev->irq.ih1) { 268 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_ENABLE, 0); 269 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RB_FULL_DRAIN_ENABLE, 1); 270 } 271 if (amdgpu_sriov_vf(adev) && adev->asic_type < CHIP_NAVI10) { 272 if (psp_reg_program(&adev->psp, ih_regs->psp_reg_id, tmp)) { 273 dev_err(adev->dev, "PSP program IH_RB_CNTL failed!\n"); 274 return -ETIMEDOUT; 275 } 276 } else { 277 WREG32(ih_regs->ih_rb_cntl, tmp); 278 } 279 280 if (ih == &adev->irq.ih) { 281 /* set the ih ring 0 writeback address whether it's enabled or not */ 282 WREG32(ih_regs->ih_rb_wptr_addr_lo, lower_32_bits(ih->wptr_addr)); 283 WREG32(ih_regs->ih_rb_wptr_addr_hi, upper_32_bits(ih->wptr_addr) & 0xFFFF); 284 } 285 286 /* set rptr, wptr to 0 */ 287 WREG32(ih_regs->ih_rb_wptr, 0); 288 WREG32(ih_regs->ih_rb_rptr, 0); 289 290 WREG32(ih_regs->ih_doorbell_rptr, navi10_ih_doorbell_rptr(ih)); 291 292 return 0; 293 } 294 295 static void navi10_ih_reroute_ih(struct amdgpu_device *adev) 296 { 297 uint32_t tmp; 298 299 /* Reroute to IH ring 1 for VMC */ 300 WREG32_SOC15(OSSSYS, 0, mmIH_CLIENT_CFG_INDEX, 0x12); 301 tmp = RREG32_SOC15(OSSSYS, 0, mmIH_CLIENT_CFG_DATA); 302 tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, CLIENT_TYPE, 1); 303 tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, RING_ID, 1); 304 WREG32_SOC15(OSSSYS, 0, mmIH_CLIENT_CFG_DATA, tmp); 305 306 /* Reroute IH ring 1 for UMC */ 307 WREG32_SOC15(OSSSYS, 0, mmIH_CLIENT_CFG_INDEX, 0x1B); 308 tmp = RREG32_SOC15(OSSSYS, 0, mmIH_CLIENT_CFG_DATA); 309 tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, RING_ID, 1); 310 WREG32_SOC15(OSSSYS, 0, mmIH_CLIENT_CFG_DATA, tmp); 311 } 312 313 /** 314 * navi10_ih_irq_init - init and enable the interrupt ring 315 * 316 * @adev: amdgpu_device pointer 317 * 318 * Allocate a ring buffer for the interrupt controller, 319 * enable the RLC, disable interrupts, enable the IH 320 * ring buffer and enable it (NAVI). 321 * Called at device load and reume. 322 * Returns 0 for success, errors for failure. 323 */ 324 static int navi10_ih_irq_init(struct amdgpu_device *adev) 325 { 326 struct amdgpu_ih_ring *ih[] = {&adev->irq.ih, &adev->irq.ih1, &adev->irq.ih2}; 327 u32 ih_chicken; 328 u32 tmp; 329 int ret; 330 int i; 331 332 /* disable irqs */ 333 ret = navi10_ih_toggle_interrupts(adev, false); 334 if (ret) 335 return ret; 336 337 adev->nbio.funcs->ih_control(adev); 338 339 if (unlikely(adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT)) { 340 if (ih[0]->use_bus_addr) { 341 switch (adev->asic_type) { 342 case CHIP_SIENNA_CICHLID: 343 case CHIP_NAVY_FLOUNDER: 344 case CHIP_VANGOGH: 345 case CHIP_DIMGREY_CAVEFISH: 346 ih_chicken = RREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN_Sienna_Cichlid); 347 ih_chicken = REG_SET_FIELD(ih_chicken, 348 IH_CHICKEN, MC_SPACE_GPA_ENABLE, 1); 349 WREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN_Sienna_Cichlid, ih_chicken); 350 break; 351 default: 352 ih_chicken = RREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN); 353 ih_chicken = REG_SET_FIELD(ih_chicken, 354 IH_CHICKEN, MC_SPACE_GPA_ENABLE, 1); 355 WREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN, ih_chicken); 356 break; 357 } 358 } 359 } 360 361 for (i = 0; i < ARRAY_SIZE(ih); i++) { 362 if (ih[i]->ring_size) { 363 ret = navi10_ih_enable_ring(adev, ih[i]); 364 if (ret) 365 return ret; 366 } 367 } 368 369 /* update doorbell range for ih ring 0*/ 370 adev->nbio.funcs->ih_doorbell_range(adev, ih[0]->use_doorbell, 371 ih[0]->doorbell_index); 372 373 tmp = RREG32_SOC15(OSSSYS, 0, mmIH_STORM_CLIENT_LIST_CNTL); 374 tmp = REG_SET_FIELD(tmp, IH_STORM_CLIENT_LIST_CNTL, 375 CLIENT18_IS_STORM_CLIENT, 1); 376 WREG32_SOC15(OSSSYS, 0, mmIH_STORM_CLIENT_LIST_CNTL, tmp); 377 378 tmp = RREG32_SOC15(OSSSYS, 0, mmIH_INT_FLOOD_CNTL); 379 tmp = REG_SET_FIELD(tmp, IH_INT_FLOOD_CNTL, FLOOD_CNTL_ENABLE, 1); 380 WREG32_SOC15(OSSSYS, 0, mmIH_INT_FLOOD_CNTL, tmp); 381 382 pci_set_master(adev->pdev); 383 384 /* enable interrupts */ 385 ret = navi10_ih_toggle_interrupts(adev, true); 386 if (ret) 387 return ret; 388 /* enable wptr force update for self int */ 389 force_update_wptr_for_self_int(adev, 0, 8, true); 390 391 return 0; 392 } 393 394 /** 395 * navi10_ih_irq_disable - disable interrupts 396 * 397 * @adev: amdgpu_device pointer 398 * 399 * Disable interrupts on the hw (NAVI10). 400 */ 401 static void navi10_ih_irq_disable(struct amdgpu_device *adev) 402 { 403 force_update_wptr_for_self_int(adev, 0, 8, false); 404 navi10_ih_toggle_interrupts(adev, false); 405 406 /* Wait and acknowledge irq */ 407 mdelay(1); 408 } 409 410 /** 411 * navi10_ih_get_wptr - get the IH ring buffer wptr 412 * 413 * @adev: amdgpu_device pointer 414 * @ih: IH ring buffer to fetch wptr 415 * 416 * Get the IH ring buffer wptr from either the register 417 * or the writeback memory buffer (NAVI10). Also check for 418 * ring buffer overflow and deal with it. 419 * Returns the value of the wptr. 420 */ 421 static u32 navi10_ih_get_wptr(struct amdgpu_device *adev, 422 struct amdgpu_ih_ring *ih) 423 { 424 u32 wptr, tmp; 425 struct amdgpu_ih_regs *ih_regs; 426 427 wptr = le32_to_cpu(*ih->wptr_cpu); 428 ih_regs = &ih->ih_regs; 429 430 if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) 431 goto out; 432 433 wptr = RREG32_NO_KIQ(ih_regs->ih_rb_wptr); 434 if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) 435 goto out; 436 wptr = REG_SET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW, 0); 437 438 /* When a ring buffer overflow happen start parsing interrupt 439 * from the last not overwritten vector (wptr + 32). Hopefully 440 * this should allow us to catch up. 441 */ 442 tmp = (wptr + 32) & ih->ptr_mask; 443 dev_warn(adev->dev, "IH ring buffer overflow " 444 "(0x%08X, 0x%08X, 0x%08X)\n", 445 wptr, ih->rptr, tmp); 446 ih->rptr = tmp; 447 448 tmp = RREG32_NO_KIQ(ih_regs->ih_rb_cntl); 449 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1); 450 WREG32_NO_KIQ(ih_regs->ih_rb_cntl, tmp); 451 out: 452 return (wptr & ih->ptr_mask); 453 } 454 455 /** 456 * navi10_ih_decode_iv - decode an interrupt vector 457 * 458 * @adev: amdgpu_device pointer 459 * @ih: IH ring buffer to decode 460 * @entry: IV entry to place decoded information into 461 * 462 * Decodes the interrupt vector at the current rptr 463 * position and also advance the position. 464 */ 465 static void navi10_ih_decode_iv(struct amdgpu_device *adev, 466 struct amdgpu_ih_ring *ih, 467 struct amdgpu_iv_entry *entry) 468 { 469 /* wptr/rptr are in bytes! */ 470 u32 ring_index = ih->rptr >> 2; 471 uint32_t dw[8]; 472 473 dw[0] = le32_to_cpu(ih->ring[ring_index + 0]); 474 dw[1] = le32_to_cpu(ih->ring[ring_index + 1]); 475 dw[2] = le32_to_cpu(ih->ring[ring_index + 2]); 476 dw[3] = le32_to_cpu(ih->ring[ring_index + 3]); 477 dw[4] = le32_to_cpu(ih->ring[ring_index + 4]); 478 dw[5] = le32_to_cpu(ih->ring[ring_index + 5]); 479 dw[6] = le32_to_cpu(ih->ring[ring_index + 6]); 480 dw[7] = le32_to_cpu(ih->ring[ring_index + 7]); 481 482 entry->client_id = dw[0] & 0xff; 483 entry->src_id = (dw[0] >> 8) & 0xff; 484 entry->ring_id = (dw[0] >> 16) & 0xff; 485 entry->vmid = (dw[0] >> 24) & 0xf; 486 entry->vmid_src = (dw[0] >> 31); 487 entry->timestamp = dw[1] | ((u64)(dw[2] & 0xffff) << 32); 488 entry->timestamp_src = dw[2] >> 31; 489 entry->pasid = dw[3] & 0xffff; 490 entry->pasid_src = dw[3] >> 31; 491 entry->src_data[0] = dw[4]; 492 entry->src_data[1] = dw[5]; 493 entry->src_data[2] = dw[6]; 494 entry->src_data[3] = dw[7]; 495 496 /* wptr/rptr are in bytes! */ 497 ih->rptr += 32; 498 } 499 500 /** 501 * navi10_ih_irq_rearm - rearm IRQ if lost 502 * 503 * @adev: amdgpu_device pointer 504 * @ih: IH ring to match 505 * 506 */ 507 static void navi10_ih_irq_rearm(struct amdgpu_device *adev, 508 struct amdgpu_ih_ring *ih) 509 { 510 uint32_t v = 0; 511 uint32_t i = 0; 512 struct amdgpu_ih_regs *ih_regs; 513 514 ih_regs = &ih->ih_regs; 515 516 /* Rearm IRQ / re-write doorbell if doorbell write is lost */ 517 for (i = 0; i < MAX_REARM_RETRY; i++) { 518 v = RREG32_NO_KIQ(ih_regs->ih_rb_rptr); 519 if ((v < ih->ring_size) && (v != ih->rptr)) 520 WDOORBELL32(ih->doorbell_index, ih->rptr); 521 else 522 break; 523 } 524 } 525 526 /** 527 * navi10_ih_set_rptr - set the IH ring buffer rptr 528 * 529 * @adev: amdgpu_device pointer 530 * 531 * @ih: IH ring buffer to set rptr 532 * Set the IH ring buffer rptr. 533 */ 534 static void navi10_ih_set_rptr(struct amdgpu_device *adev, 535 struct amdgpu_ih_ring *ih) 536 { 537 struct amdgpu_ih_regs *ih_regs; 538 539 if (ih->use_doorbell) { 540 /* XXX check if swapping is necessary on BE */ 541 *ih->rptr_cpu = ih->rptr; 542 WDOORBELL32(ih->doorbell_index, ih->rptr); 543 544 if (amdgpu_sriov_vf(adev)) 545 navi10_ih_irq_rearm(adev, ih); 546 } else { 547 ih_regs = &ih->ih_regs; 548 WREG32(ih_regs->ih_rb_rptr, ih->rptr); 549 } 550 } 551 552 /** 553 * navi10_ih_self_irq - dispatch work for ring 1 and 2 554 * 555 * @adev: amdgpu_device pointer 556 * @source: irq source 557 * @entry: IV with WPTR update 558 * 559 * Update the WPTR from the IV and schedule work to handle the entries. 560 */ 561 static int navi10_ih_self_irq(struct amdgpu_device *adev, 562 struct amdgpu_irq_src *source, 563 struct amdgpu_iv_entry *entry) 564 { 565 uint32_t wptr = cpu_to_le32(entry->src_data[0]); 566 567 switch (entry->ring_id) { 568 case 1: 569 *adev->irq.ih1.wptr_cpu = wptr; 570 schedule_work(&adev->irq.ih1_work); 571 break; 572 case 2: 573 *adev->irq.ih2.wptr_cpu = wptr; 574 schedule_work(&adev->irq.ih2_work); 575 break; 576 default: break; 577 } 578 return 0; 579 } 580 581 static const struct amdgpu_irq_src_funcs navi10_ih_self_irq_funcs = { 582 .process = navi10_ih_self_irq, 583 }; 584 585 static void navi10_ih_set_self_irq_funcs(struct amdgpu_device *adev) 586 { 587 adev->irq.self_irq.num_types = 0; 588 adev->irq.self_irq.funcs = &navi10_ih_self_irq_funcs; 589 } 590 591 static int navi10_ih_early_init(void *handle) 592 { 593 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 594 595 navi10_ih_set_interrupt_funcs(adev); 596 navi10_ih_set_self_irq_funcs(adev); 597 return 0; 598 } 599 600 static int navi10_ih_sw_init(void *handle) 601 { 602 int r; 603 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 604 bool use_bus_addr; 605 606 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_IH, 0, 607 &adev->irq.self_irq); 608 609 if (r) 610 return r; 611 612 /* use gpu virtual address for ih ring 613 * until ih_checken is programmed to allow 614 * use bus address for ih ring by psp bl */ 615 if ((adev->flags & AMD_IS_APU) || 616 (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) 617 use_bus_addr = false; 618 else 619 use_bus_addr = true; 620 r = amdgpu_ih_ring_init(adev, &adev->irq.ih, 256 * 1024, use_bus_addr); 621 if (r) 622 return r; 623 624 adev->irq.ih.use_doorbell = true; 625 adev->irq.ih.doorbell_index = adev->doorbell_index.ih << 1; 626 627 adev->irq.ih1.ring_size = 0; 628 adev->irq.ih2.ring_size = 0; 629 630 if (adev->asic_type < CHIP_NAVI10) { 631 r = amdgpu_ih_ring_init(adev, &adev->irq.ih1, PAGE_SIZE, true); 632 if (r) 633 return r; 634 635 adev->irq.ih1.use_doorbell = true; 636 adev->irq.ih1.doorbell_index = 637 (adev->doorbell_index.ih + 1) << 1; 638 639 r = amdgpu_ih_ring_init(adev, &adev->irq.ih2, PAGE_SIZE, true); 640 if (r) 641 return r; 642 643 adev->irq.ih2.use_doorbell = true; 644 adev->irq.ih2.doorbell_index = 645 (adev->doorbell_index.ih + 2) << 1; 646 } 647 648 /* initialize ih control registers offset */ 649 navi10_ih_init_register_offset(adev); 650 651 r = amdgpu_ih_ring_init(adev, &adev->irq.ih_soft, PAGE_SIZE, true); 652 if (r) 653 return r; 654 655 r = amdgpu_irq_init(adev); 656 657 return r; 658 } 659 660 static int navi10_ih_sw_fini(void *handle) 661 { 662 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 663 664 amdgpu_irq_fini(adev); 665 amdgpu_ih_ring_fini(adev, &adev->irq.ih2); 666 amdgpu_ih_ring_fini(adev, &adev->irq.ih1); 667 amdgpu_ih_ring_fini(adev, &adev->irq.ih); 668 669 return 0; 670 } 671 672 static int navi10_ih_hw_init(void *handle) 673 { 674 int r; 675 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 676 677 r = navi10_ih_irq_init(adev); 678 if (r) 679 return r; 680 681 return 0; 682 } 683 684 static int navi10_ih_hw_fini(void *handle) 685 { 686 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 687 688 navi10_ih_irq_disable(adev); 689 690 return 0; 691 } 692 693 static int navi10_ih_suspend(void *handle) 694 { 695 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 696 697 return navi10_ih_hw_fini(adev); 698 } 699 700 static int navi10_ih_resume(void *handle) 701 { 702 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 703 704 return navi10_ih_hw_init(adev); 705 } 706 707 static bool navi10_ih_is_idle(void *handle) 708 { 709 /* todo */ 710 return true; 711 } 712 713 static int navi10_ih_wait_for_idle(void *handle) 714 { 715 /* todo */ 716 return -ETIMEDOUT; 717 } 718 719 static int navi10_ih_soft_reset(void *handle) 720 { 721 /* todo */ 722 return 0; 723 } 724 725 static void navi10_ih_update_clockgating_state(struct amdgpu_device *adev, 726 bool enable) 727 { 728 uint32_t data, def, field_val; 729 730 if (adev->cg_flags & AMD_CG_SUPPORT_IH_CG) { 731 def = data = RREG32_SOC15(OSSSYS, 0, mmIH_CLK_CTRL); 732 field_val = enable ? 0 : 1; 733 data = REG_SET_FIELD(data, IH_CLK_CTRL, 734 DBUS_MUX_CLK_SOFT_OVERRIDE, field_val); 735 data = REG_SET_FIELD(data, IH_CLK_CTRL, 736 OSSSYS_SHARE_CLK_SOFT_OVERRIDE, field_val); 737 data = REG_SET_FIELD(data, IH_CLK_CTRL, 738 LIMIT_SMN_CLK_SOFT_OVERRIDE, field_val); 739 data = REG_SET_FIELD(data, IH_CLK_CTRL, 740 DYN_CLK_SOFT_OVERRIDE, field_val); 741 data = REG_SET_FIELD(data, IH_CLK_CTRL, 742 REG_CLK_SOFT_OVERRIDE, field_val); 743 if (def != data) 744 WREG32_SOC15(OSSSYS, 0, mmIH_CLK_CTRL, data); 745 } 746 747 return; 748 } 749 750 static int navi10_ih_set_clockgating_state(void *handle, 751 enum amd_clockgating_state state) 752 { 753 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 754 755 navi10_ih_update_clockgating_state(adev, 756 state == AMD_CG_STATE_GATE); 757 return 0; 758 } 759 760 static int navi10_ih_set_powergating_state(void *handle, 761 enum amd_powergating_state state) 762 { 763 return 0; 764 } 765 766 static void navi10_ih_get_clockgating_state(void *handle, u32 *flags) 767 { 768 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 769 770 if (!RREG32_SOC15(OSSSYS, 0, mmIH_CLK_CTRL)) 771 *flags |= AMD_CG_SUPPORT_IH_CG; 772 773 return; 774 } 775 776 static const struct amd_ip_funcs navi10_ih_ip_funcs = { 777 .name = "navi10_ih", 778 .early_init = navi10_ih_early_init, 779 .late_init = NULL, 780 .sw_init = navi10_ih_sw_init, 781 .sw_fini = navi10_ih_sw_fini, 782 .hw_init = navi10_ih_hw_init, 783 .hw_fini = navi10_ih_hw_fini, 784 .suspend = navi10_ih_suspend, 785 .resume = navi10_ih_resume, 786 .is_idle = navi10_ih_is_idle, 787 .wait_for_idle = navi10_ih_wait_for_idle, 788 .soft_reset = navi10_ih_soft_reset, 789 .set_clockgating_state = navi10_ih_set_clockgating_state, 790 .set_powergating_state = navi10_ih_set_powergating_state, 791 .get_clockgating_state = navi10_ih_get_clockgating_state, 792 }; 793 794 static const struct amdgpu_ih_funcs navi10_ih_funcs = { 795 .get_wptr = navi10_ih_get_wptr, 796 .decode_iv = navi10_ih_decode_iv, 797 .set_rptr = navi10_ih_set_rptr 798 }; 799 800 static void navi10_ih_set_interrupt_funcs(struct amdgpu_device *adev) 801 { 802 if (adev->irq.ih_funcs == NULL) 803 adev->irq.ih_funcs = &navi10_ih_funcs; 804 } 805 806 const struct amdgpu_ip_block_version navi10_ih_ip_block = 807 { 808 .type = AMD_IP_BLOCK_TYPE_IH, 809 .major = 5, 810 .minor = 0, 811 .rev = 0, 812 .funcs = &navi10_ih_ip_funcs, 813 }; 814