1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/pci.h> 25 26 #include "amdgpu.h" 27 #include "amdgpu_ih.h" 28 29 #include "oss/osssys_5_0_0_offset.h" 30 #include "oss/osssys_5_0_0_sh_mask.h" 31 32 #include "soc15_common.h" 33 #include "navi10_ih.h" 34 35 #define MAX_REARM_RETRY 10 36 37 #define mmIH_CHICKEN_Sienna_Cichlid 0x018d 38 #define mmIH_CHICKEN_Sienna_Cichlid_BASE_IDX 0 39 40 static void navi10_ih_set_interrupt_funcs(struct amdgpu_device *adev); 41 42 /** 43 * navi10_ih_init_register_offset - Initialize register offset for ih rings 44 * 45 * @adev: amdgpu_device pointer 46 * 47 * Initialize register offset ih rings (NAVI10). 48 */ 49 static void navi10_ih_init_register_offset(struct amdgpu_device *adev) 50 { 51 struct amdgpu_ih_regs *ih_regs; 52 53 if (adev->irq.ih.ring_size) { 54 ih_regs = &adev->irq.ih.ih_regs; 55 ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE); 56 ih_regs->ih_rb_base_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_HI); 57 ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL); 58 ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR); 59 ih_regs->ih_rb_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR); 60 ih_regs->ih_doorbell_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_DOORBELL_RPTR); 61 ih_regs->ih_rb_wptr_addr_lo = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_ADDR_LO); 62 ih_regs->ih_rb_wptr_addr_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_ADDR_HI); 63 ih_regs->psp_reg_id = PSP_REG_IH_RB_CNTL; 64 } 65 66 if (adev->irq.ih1.ring_size) { 67 ih_regs = &adev->irq.ih1.ih_regs; 68 ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_RING1); 69 ih_regs->ih_rb_base_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_HI_RING1); 70 ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL_RING1); 71 ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_RING1); 72 ih_regs->ih_rb_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR_RING1); 73 ih_regs->ih_doorbell_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_DOORBELL_RPTR_RING1); 74 ih_regs->psp_reg_id = PSP_REG_IH_RB_CNTL_RING1; 75 } 76 77 if (adev->irq.ih2.ring_size) { 78 ih_regs = &adev->irq.ih2.ih_regs; 79 ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_RING2); 80 ih_regs->ih_rb_base_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_HI_RING2); 81 ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL_RING2); 82 ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_RING2); 83 ih_regs->ih_rb_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR_RING2); 84 ih_regs->ih_doorbell_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_DOORBELL_RPTR_RING2); 85 ih_regs->psp_reg_id = PSP_REG_IH_RB_CNTL_RING2; 86 } 87 } 88 89 /** 90 * force_update_wptr_for_self_int - Force update the wptr for self interrupt 91 * 92 * @adev: amdgpu_device pointer 93 * @threshold: threshold to trigger the wptr reporting 94 * @timeout: timeout to trigger the wptr reporting 95 * @enabled: Enable/disable timeout flush mechanism 96 * 97 * threshold input range: 0 ~ 15, default 0, 98 * real_threshold = 2^threshold 99 * timeout input range: 0 ~ 20, default 8, 100 * real_timeout = (2^timeout) * 1024 / (socclk_freq) 101 * 102 * Force update wptr for self interrupt ( >= SIENNA_CICHLID). 103 */ 104 static void 105 force_update_wptr_for_self_int(struct amdgpu_device *adev, 106 u32 threshold, u32 timeout, bool enabled) 107 { 108 u32 ih_cntl, ih_rb_cntl; 109 110 if (adev->asic_type < CHIP_SIENNA_CICHLID) 111 return; 112 113 ih_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_CNTL2); 114 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1); 115 116 ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL2, 117 SELF_IV_FORCE_WPTR_UPDATE_TIMEOUT, timeout); 118 ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL2, 119 SELF_IV_FORCE_WPTR_UPDATE_ENABLE, enabled); 120 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING1, 121 RB_USED_INT_THRESHOLD, threshold); 122 123 WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1, ih_rb_cntl); 124 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2); 125 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING2, 126 RB_USED_INT_THRESHOLD, threshold); 127 WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2, ih_rb_cntl); 128 WREG32_SOC15(OSSSYS, 0, mmIH_CNTL2, ih_cntl); 129 } 130 131 /** 132 * navi10_ih_enable_interrupts - Enable the interrupt ring buffer 133 * 134 * @adev: amdgpu_device pointer 135 * 136 * Enable the interrupt ring buffer (NAVI10). 137 */ 138 static void navi10_ih_enable_interrupts(struct amdgpu_device *adev) 139 { 140 u32 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL); 141 142 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 1); 143 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, ENABLE_INTR, 1); 144 if (amdgpu_sriov_vf(adev) && adev->asic_type < CHIP_NAVI10) { 145 if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL, ih_rb_cntl)) { 146 DRM_ERROR("PSP program IH_RB_CNTL failed!\n"); 147 return; 148 } 149 } else { 150 WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL, ih_rb_cntl); 151 } 152 153 adev->irq.ih.enabled = true; 154 155 if (adev->irq.ih1.ring_size) { 156 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1); 157 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING1, 158 RB_ENABLE, 1); 159 if (amdgpu_sriov_vf(adev) && adev->asic_type < CHIP_NAVI10) { 160 if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL_RING1, 161 ih_rb_cntl)) { 162 DRM_ERROR("program IH_RB_CNTL_RING1 failed!\n"); 163 return; 164 } 165 } else { 166 WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1, ih_rb_cntl); 167 } 168 adev->irq.ih1.enabled = true; 169 } 170 171 if (adev->irq.ih2.ring_size) { 172 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2); 173 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING2, 174 RB_ENABLE, 1); 175 if (amdgpu_sriov_vf(adev) && adev->asic_type < CHIP_NAVI10) { 176 if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL_RING2, 177 ih_rb_cntl)) { 178 DRM_ERROR("program IH_RB_CNTL_RING2 failed!\n"); 179 return; 180 } 181 } else { 182 WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2, ih_rb_cntl); 183 } 184 adev->irq.ih2.enabled = true; 185 } 186 187 if (adev->irq.ih_soft.ring_size) 188 adev->irq.ih_soft.enabled = true; 189 } 190 191 /** 192 * navi10_ih_disable_interrupts - Disable the interrupt ring buffer 193 * 194 * @adev: amdgpu_device pointer 195 * 196 * Disable the interrupt ring buffer (NAVI10). 197 */ 198 static void navi10_ih_disable_interrupts(struct amdgpu_device *adev) 199 { 200 u32 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL); 201 202 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 0); 203 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, ENABLE_INTR, 0); 204 if (amdgpu_sriov_vf(adev) && adev->asic_type < CHIP_NAVI10) { 205 if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL, ih_rb_cntl)) { 206 DRM_ERROR("PSP program IH_RB_CNTL failed!\n"); 207 return; 208 } 209 } else { 210 WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL, ih_rb_cntl); 211 } 212 213 /* set rptr, wptr to 0 */ 214 WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR, 0); 215 WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR, 0); 216 adev->irq.ih.enabled = false; 217 adev->irq.ih.rptr = 0; 218 219 if (adev->irq.ih1.ring_size) { 220 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1); 221 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING1, 222 RB_ENABLE, 0); 223 if (amdgpu_sriov_vf(adev) && adev->asic_type < CHIP_NAVI10) { 224 if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL_RING1, 225 ih_rb_cntl)) { 226 DRM_ERROR("program IH_RB_CNTL_RING1 failed!\n"); 227 return; 228 } 229 } else { 230 WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1, ih_rb_cntl); 231 } 232 /* set rptr, wptr to 0 */ 233 WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR_RING1, 0); 234 WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_RING1, 0); 235 adev->irq.ih1.enabled = false; 236 adev->irq.ih1.rptr = 0; 237 } 238 239 if (adev->irq.ih2.ring_size) { 240 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2); 241 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING2, 242 RB_ENABLE, 0); 243 if (amdgpu_sriov_vf(adev) && adev->asic_type < CHIP_NAVI10) { 244 if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL_RING2, 245 ih_rb_cntl)) { 246 DRM_ERROR("program IH_RB_CNTL_RING2 failed!\n"); 247 return; 248 } 249 } else { 250 WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2, ih_rb_cntl); 251 } 252 /* set rptr, wptr to 0 */ 253 WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR_RING2, 0); 254 WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_RING2, 0); 255 adev->irq.ih2.enabled = false; 256 adev->irq.ih2.rptr = 0; 257 } 258 259 } 260 261 /** 262 * navi10_ih_toggle_ring_interrupts - toggle the interrupt ring buffer 263 * 264 * @adev: amdgpu_device pointer 265 * @ih: amdgpu_ih_ring pointet 266 * @enable: true - enable the interrupts, false - disable the interrupts 267 * 268 * Toggle the interrupt ring buffer (NAVI10) 269 */ 270 static int navi10_ih_toggle_ring_interrupts(struct amdgpu_device *adev, 271 struct amdgpu_ih_ring *ih, 272 bool enable) 273 { 274 struct amdgpu_ih_regs *ih_regs; 275 uint32_t tmp; 276 277 ih_regs = &ih->ih_regs; 278 279 tmp = RREG32(ih_regs->ih_rb_cntl); 280 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RB_ENABLE, (enable ? 1 : 0)); 281 /* enable_intr field is only valid in ring0 */ 282 if (ih == &adev->irq.ih) 283 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, ENABLE_INTR, (enable ? 1 : 0)); 284 if (amdgpu_sriov_vf(adev) && adev->asic_type < CHIP_NAVI10) { 285 if (psp_reg_program(&adev->psp, ih_regs->psp_reg_id, tmp)) { 286 dev_err(adev->dev, "PSP program IH_RB_CNTL failed!\n"); 287 return -ETIMEDOUT; 288 } 289 } else { 290 WREG32(ih_regs->ih_rb_cntl, tmp); 291 } 292 293 if (enable) { 294 ih->enabled = true; 295 } else { 296 /* set rptr, wptr to 0 */ 297 WREG32(ih_regs->ih_rb_rptr, 0); 298 WREG32(ih_regs->ih_rb_wptr, 0); 299 ih->enabled = false; 300 ih->rptr = 0; 301 } 302 303 return 0; 304 } 305 306 static uint32_t navi10_ih_rb_cntl(struct amdgpu_ih_ring *ih, uint32_t ih_rb_cntl) 307 { 308 int rb_bufsz = order_base_2(ih->ring_size / 4); 309 310 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, 311 MC_SPACE, ih->use_bus_addr ? 1 : 4); 312 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, 313 WPTR_OVERFLOW_CLEAR, 1); 314 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, 315 WPTR_OVERFLOW_ENABLE, 1); 316 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_SIZE, rb_bufsz); 317 /* Ring Buffer write pointer writeback. If enabled, IH_RB_WPTR register 318 * value is written to memory 319 */ 320 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, 321 WPTR_WRITEBACK_ENABLE, 1); 322 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_SNOOP, 1); 323 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_RO, 0); 324 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_VMID, 0); 325 326 return ih_rb_cntl; 327 } 328 329 static uint32_t navi10_ih_doorbell_rptr(struct amdgpu_ih_ring *ih) 330 { 331 u32 ih_doorbell_rtpr = 0; 332 333 if (ih->use_doorbell) { 334 ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr, 335 IH_DOORBELL_RPTR, OFFSET, 336 ih->doorbell_index); 337 ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr, 338 IH_DOORBELL_RPTR, 339 ENABLE, 1); 340 } else { 341 ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr, 342 IH_DOORBELL_RPTR, 343 ENABLE, 0); 344 } 345 return ih_doorbell_rtpr; 346 } 347 348 /** 349 * navi10_ih_enable_ring - enable an ih ring buffer 350 * 351 * @adev: amdgpu_device pointer 352 * @ih: amdgpu_ih_ring pointer 353 * 354 * Enable an ih ring buffer (NAVI10) 355 */ 356 static int navi10_ih_enable_ring(struct amdgpu_device *adev, 357 struct amdgpu_ih_ring *ih) 358 { 359 struct amdgpu_ih_regs *ih_regs; 360 uint32_t tmp; 361 362 ih_regs = &ih->ih_regs; 363 364 /* Ring Buffer base. [39:8] of 40-bit address of the beginning of the ring buffer*/ 365 WREG32(ih_regs->ih_rb_base, ih->gpu_addr >> 8); 366 WREG32(ih_regs->ih_rb_base_hi, (ih->gpu_addr >> 40) & 0xff); 367 368 tmp = RREG32(ih_regs->ih_rb_cntl); 369 tmp = navi10_ih_rb_cntl(ih, tmp); 370 if (ih == &adev->irq.ih) 371 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RPTR_REARM, !!adev->irq.msi_enabled); 372 if (ih == &adev->irq.ih1) { 373 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_ENABLE, 0); 374 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RB_FULL_DRAIN_ENABLE, 1); 375 } 376 if (amdgpu_sriov_vf(adev) && adev->asic_type < CHIP_NAVI10) { 377 if (psp_reg_program(&adev->psp, ih_regs->psp_reg_id, tmp)) { 378 dev_err(adev->dev, "PSP program IH_RB_CNTL failed!\n"); 379 return -ETIMEDOUT; 380 } 381 } else { 382 WREG32(ih_regs->ih_rb_cntl, tmp); 383 } 384 385 if (ih == &adev->irq.ih) { 386 /* set the ih ring 0 writeback address whether it's enabled or not */ 387 WREG32(ih_regs->ih_rb_wptr_addr_lo, lower_32_bits(ih->wptr_addr)); 388 WREG32(ih_regs->ih_rb_wptr_addr_hi, upper_32_bits(ih->wptr_addr) & 0xFFFF); 389 } 390 391 /* set rptr, wptr to 0 */ 392 WREG32(ih_regs->ih_rb_wptr, 0); 393 WREG32(ih_regs->ih_rb_rptr, 0); 394 395 WREG32(ih_regs->ih_doorbell_rptr, navi10_ih_doorbell_rptr(ih)); 396 397 return 0; 398 } 399 400 static void navi10_ih_reroute_ih(struct amdgpu_device *adev) 401 { 402 uint32_t tmp; 403 404 /* Reroute to IH ring 1 for VMC */ 405 WREG32_SOC15(OSSSYS, 0, mmIH_CLIENT_CFG_INDEX, 0x12); 406 tmp = RREG32_SOC15(OSSSYS, 0, mmIH_CLIENT_CFG_DATA); 407 tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, CLIENT_TYPE, 1); 408 tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, RING_ID, 1); 409 WREG32_SOC15(OSSSYS, 0, mmIH_CLIENT_CFG_DATA, tmp); 410 411 /* Reroute IH ring 1 for UMC */ 412 WREG32_SOC15(OSSSYS, 0, mmIH_CLIENT_CFG_INDEX, 0x1B); 413 tmp = RREG32_SOC15(OSSSYS, 0, mmIH_CLIENT_CFG_DATA); 414 tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, RING_ID, 1); 415 WREG32_SOC15(OSSSYS, 0, mmIH_CLIENT_CFG_DATA, tmp); 416 } 417 418 /** 419 * navi10_ih_irq_init - init and enable the interrupt ring 420 * 421 * @adev: amdgpu_device pointer 422 * 423 * Allocate a ring buffer for the interrupt controller, 424 * enable the RLC, disable interrupts, enable the IH 425 * ring buffer and enable it (NAVI). 426 * Called at device load and reume. 427 * Returns 0 for success, errors for failure. 428 */ 429 static int navi10_ih_irq_init(struct amdgpu_device *adev) 430 { 431 struct amdgpu_ih_ring *ih = &adev->irq.ih; 432 u32 ih_rb_cntl, ih_chicken; 433 u32 tmp; 434 435 /* disable irqs */ 436 navi10_ih_disable_interrupts(adev); 437 438 adev->nbio.funcs->ih_control(adev); 439 440 /* Ring Buffer base. [39:8] of 40-bit address of the beginning of the ring buffer*/ 441 WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE, ih->gpu_addr >> 8); 442 WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE_HI, (ih->gpu_addr >> 40) & 0xff); 443 444 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL); 445 ih_rb_cntl = navi10_ih_rb_cntl(ih, ih_rb_cntl); 446 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RPTR_REARM, 447 !!adev->irq.msi_enabled); 448 if (amdgpu_sriov_vf(adev) && adev->asic_type < CHIP_NAVI10) { 449 if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL, ih_rb_cntl)) { 450 DRM_ERROR("PSP program IH_RB_CNTL failed!\n"); 451 return -ETIMEDOUT; 452 } 453 } else { 454 WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL, ih_rb_cntl); 455 } 456 if (adev->irq.ih1.ring_size) 457 navi10_ih_reroute_ih(adev); 458 459 if (unlikely(adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT)) { 460 if (ih->use_bus_addr) { 461 switch (adev->asic_type) { 462 case CHIP_SIENNA_CICHLID: 463 case CHIP_NAVY_FLOUNDER: 464 case CHIP_VANGOGH: 465 case CHIP_DIMGREY_CAVEFISH: 466 ih_chicken = RREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN_Sienna_Cichlid); 467 ih_chicken = REG_SET_FIELD(ih_chicken, 468 IH_CHICKEN, MC_SPACE_GPA_ENABLE, 1); 469 WREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN_Sienna_Cichlid, ih_chicken); 470 break; 471 default: 472 ih_chicken = RREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN); 473 ih_chicken = REG_SET_FIELD(ih_chicken, 474 IH_CHICKEN, MC_SPACE_GPA_ENABLE, 1); 475 WREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN, ih_chicken); 476 break; 477 } 478 } 479 } 480 481 /* set the writeback address whether it's enabled or not */ 482 WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_ADDR_LO, 483 lower_32_bits(ih->wptr_addr)); 484 WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_ADDR_HI, 485 upper_32_bits(ih->wptr_addr) & 0xFFFF); 486 487 /* set rptr, wptr to 0 */ 488 WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR, 0); 489 WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR, 0); 490 491 WREG32_SOC15(OSSSYS, 0, mmIH_DOORBELL_RPTR, 492 navi10_ih_doorbell_rptr(ih)); 493 494 adev->nbio.funcs->ih_doorbell_range(adev, ih->use_doorbell, 495 ih->doorbell_index); 496 497 ih = &adev->irq.ih1; 498 if (ih->ring_size) { 499 WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE_RING1, ih->gpu_addr >> 8); 500 WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE_HI_RING1, 501 (ih->gpu_addr >> 40) & 0xff); 502 503 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1); 504 ih_rb_cntl = navi10_ih_rb_cntl(ih, ih_rb_cntl); 505 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, 506 WPTR_OVERFLOW_ENABLE, 0); 507 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, 508 RB_FULL_DRAIN_ENABLE, 1); 509 if (amdgpu_sriov_vf(adev) && adev->asic_type < CHIP_NAVI10) { 510 if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL_RING1, 511 ih_rb_cntl)) { 512 DRM_ERROR("program IH_RB_CNTL_RING1 failed!\n"); 513 return -ETIMEDOUT; 514 } 515 } else { 516 WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1, ih_rb_cntl); 517 } 518 /* set rptr, wptr to 0 */ 519 WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_RING1, 0); 520 WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR_RING1, 0); 521 522 WREG32_SOC15(OSSSYS, 0, mmIH_DOORBELL_RPTR_RING1, 523 navi10_ih_doorbell_rptr(ih)); 524 } 525 526 ih = &adev->irq.ih2; 527 if (ih->ring_size) { 528 WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE_RING2, ih->gpu_addr >> 8); 529 WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE_HI_RING2, 530 (ih->gpu_addr >> 40) & 0xff); 531 532 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2); 533 ih_rb_cntl = navi10_ih_rb_cntl(ih, ih_rb_cntl); 534 535 if (amdgpu_sriov_vf(adev) && adev->asic_type < CHIP_NAVI10) { 536 if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL_RING2, 537 ih_rb_cntl)) { 538 DRM_ERROR("program IH_RB_CNTL_RING2 failed!\n"); 539 return -ETIMEDOUT; 540 } 541 } else { 542 WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2, ih_rb_cntl); 543 } 544 /* set rptr, wptr to 0 */ 545 WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_RING2, 0); 546 WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR_RING2, 0); 547 548 WREG32_SOC15(OSSSYS, 0, mmIH_DOORBELL_RPTR_RING2, 549 navi10_ih_doorbell_rptr(ih)); 550 } 551 552 553 tmp = RREG32_SOC15(OSSSYS, 0, mmIH_STORM_CLIENT_LIST_CNTL); 554 tmp = REG_SET_FIELD(tmp, IH_STORM_CLIENT_LIST_CNTL, 555 CLIENT18_IS_STORM_CLIENT, 1); 556 WREG32_SOC15(OSSSYS, 0, mmIH_STORM_CLIENT_LIST_CNTL, tmp); 557 558 tmp = RREG32_SOC15(OSSSYS, 0, mmIH_INT_FLOOD_CNTL); 559 tmp = REG_SET_FIELD(tmp, IH_INT_FLOOD_CNTL, FLOOD_CNTL_ENABLE, 1); 560 WREG32_SOC15(OSSSYS, 0, mmIH_INT_FLOOD_CNTL, tmp); 561 562 pci_set_master(adev->pdev); 563 564 /* enable interrupts */ 565 navi10_ih_enable_interrupts(adev); 566 /* enable wptr force update for self int */ 567 force_update_wptr_for_self_int(adev, 0, 8, true); 568 569 return 0; 570 } 571 572 /** 573 * navi10_ih_irq_disable - disable interrupts 574 * 575 * @adev: amdgpu_device pointer 576 * 577 * Disable interrupts on the hw (NAVI10). 578 */ 579 static void navi10_ih_irq_disable(struct amdgpu_device *adev) 580 { 581 force_update_wptr_for_self_int(adev, 0, 8, false); 582 navi10_ih_disable_interrupts(adev); 583 584 /* Wait and acknowledge irq */ 585 mdelay(1); 586 } 587 588 /** 589 * navi10_ih_get_wptr - get the IH ring buffer wptr 590 * 591 * @adev: amdgpu_device pointer 592 * @ih: IH ring buffer to fetch wptr 593 * 594 * Get the IH ring buffer wptr from either the register 595 * or the writeback memory buffer (NAVI10). Also check for 596 * ring buffer overflow and deal with it. 597 * Returns the value of the wptr. 598 */ 599 static u32 navi10_ih_get_wptr(struct amdgpu_device *adev, 600 struct amdgpu_ih_ring *ih) 601 { 602 u32 wptr, reg, tmp; 603 604 wptr = le32_to_cpu(*ih->wptr_cpu); 605 606 if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) 607 goto out; 608 609 if (ih == &adev->irq.ih) 610 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR); 611 else if (ih == &adev->irq.ih1) 612 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_RING1); 613 else if (ih == &adev->irq.ih2) 614 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_RING2); 615 else 616 BUG(); 617 618 wptr = RREG32_NO_KIQ(reg); 619 if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) 620 goto out; 621 wptr = REG_SET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW, 0); 622 623 /* When a ring buffer overflow happen start parsing interrupt 624 * from the last not overwritten vector (wptr + 32). Hopefully 625 * this should allow us to catch up. 626 */ 627 tmp = (wptr + 32) & ih->ptr_mask; 628 dev_warn(adev->dev, "IH ring buffer overflow " 629 "(0x%08X, 0x%08X, 0x%08X)\n", 630 wptr, ih->rptr, tmp); 631 ih->rptr = tmp; 632 633 if (ih == &adev->irq.ih) 634 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL); 635 else if (ih == &adev->irq.ih1) 636 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL_RING1); 637 else if (ih == &adev->irq.ih2) 638 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL_RING2); 639 else 640 BUG(); 641 642 tmp = RREG32_NO_KIQ(reg); 643 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1); 644 WREG32_NO_KIQ(reg, tmp); 645 out: 646 return (wptr & ih->ptr_mask); 647 } 648 649 /** 650 * navi10_ih_decode_iv - decode an interrupt vector 651 * 652 * @adev: amdgpu_device pointer 653 * @ih: IH ring buffer to decode 654 * @entry: IV entry to place decoded information into 655 * 656 * Decodes the interrupt vector at the current rptr 657 * position and also advance the position. 658 */ 659 static void navi10_ih_decode_iv(struct amdgpu_device *adev, 660 struct amdgpu_ih_ring *ih, 661 struct amdgpu_iv_entry *entry) 662 { 663 /* wptr/rptr are in bytes! */ 664 u32 ring_index = ih->rptr >> 2; 665 uint32_t dw[8]; 666 667 dw[0] = le32_to_cpu(ih->ring[ring_index + 0]); 668 dw[1] = le32_to_cpu(ih->ring[ring_index + 1]); 669 dw[2] = le32_to_cpu(ih->ring[ring_index + 2]); 670 dw[3] = le32_to_cpu(ih->ring[ring_index + 3]); 671 dw[4] = le32_to_cpu(ih->ring[ring_index + 4]); 672 dw[5] = le32_to_cpu(ih->ring[ring_index + 5]); 673 dw[6] = le32_to_cpu(ih->ring[ring_index + 6]); 674 dw[7] = le32_to_cpu(ih->ring[ring_index + 7]); 675 676 entry->client_id = dw[0] & 0xff; 677 entry->src_id = (dw[0] >> 8) & 0xff; 678 entry->ring_id = (dw[0] >> 16) & 0xff; 679 entry->vmid = (dw[0] >> 24) & 0xf; 680 entry->vmid_src = (dw[0] >> 31); 681 entry->timestamp = dw[1] | ((u64)(dw[2] & 0xffff) << 32); 682 entry->timestamp_src = dw[2] >> 31; 683 entry->pasid = dw[3] & 0xffff; 684 entry->pasid_src = dw[3] >> 31; 685 entry->src_data[0] = dw[4]; 686 entry->src_data[1] = dw[5]; 687 entry->src_data[2] = dw[6]; 688 entry->src_data[3] = dw[7]; 689 690 /* wptr/rptr are in bytes! */ 691 ih->rptr += 32; 692 } 693 694 /** 695 * navi10_ih_irq_rearm - rearm IRQ if lost 696 * 697 * @adev: amdgpu_device pointer 698 * @ih: IH ring to match 699 * 700 */ 701 static void navi10_ih_irq_rearm(struct amdgpu_device *adev, 702 struct amdgpu_ih_ring *ih) 703 { 704 uint32_t reg_rptr = 0; 705 uint32_t v = 0; 706 uint32_t i = 0; 707 708 if (ih == &adev->irq.ih) 709 reg_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR); 710 else if (ih == &adev->irq.ih1) 711 reg_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR_RING1); 712 else if (ih == &adev->irq.ih2) 713 reg_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR_RING2); 714 else 715 return; 716 717 /* Rearm IRQ / re-write doorbell if doorbell write is lost */ 718 for (i = 0; i < MAX_REARM_RETRY; i++) { 719 v = RREG32_NO_KIQ(reg_rptr); 720 if ((v < ih->ring_size) && (v != ih->rptr)) 721 WDOORBELL32(ih->doorbell_index, ih->rptr); 722 else 723 break; 724 } 725 } 726 727 /** 728 * navi10_ih_set_rptr - set the IH ring buffer rptr 729 * 730 * @adev: amdgpu_device pointer 731 * 732 * @ih: IH ring buffer to set rptr 733 * Set the IH ring buffer rptr. 734 */ 735 static void navi10_ih_set_rptr(struct amdgpu_device *adev, 736 struct amdgpu_ih_ring *ih) 737 { 738 if (ih->use_doorbell) { 739 /* XXX check if swapping is necessary on BE */ 740 *ih->rptr_cpu = ih->rptr; 741 WDOORBELL32(ih->doorbell_index, ih->rptr); 742 743 if (amdgpu_sriov_vf(adev)) 744 navi10_ih_irq_rearm(adev, ih); 745 } else if (ih == &adev->irq.ih) { 746 WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR, ih->rptr); 747 } else if (ih == &adev->irq.ih1) { 748 WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR_RING1, ih->rptr); 749 } else if (ih == &adev->irq.ih2) { 750 WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR_RING2, ih->rptr); 751 } 752 } 753 754 /** 755 * navi10_ih_self_irq - dispatch work for ring 1 and 2 756 * 757 * @adev: amdgpu_device pointer 758 * @source: irq source 759 * @entry: IV with WPTR update 760 * 761 * Update the WPTR from the IV and schedule work to handle the entries. 762 */ 763 static int navi10_ih_self_irq(struct amdgpu_device *adev, 764 struct amdgpu_irq_src *source, 765 struct amdgpu_iv_entry *entry) 766 { 767 uint32_t wptr = cpu_to_le32(entry->src_data[0]); 768 769 switch (entry->ring_id) { 770 case 1: 771 *adev->irq.ih1.wptr_cpu = wptr; 772 schedule_work(&adev->irq.ih1_work); 773 break; 774 case 2: 775 *adev->irq.ih2.wptr_cpu = wptr; 776 schedule_work(&adev->irq.ih2_work); 777 break; 778 default: break; 779 } 780 return 0; 781 } 782 783 static const struct amdgpu_irq_src_funcs navi10_ih_self_irq_funcs = { 784 .process = navi10_ih_self_irq, 785 }; 786 787 static void navi10_ih_set_self_irq_funcs(struct amdgpu_device *adev) 788 { 789 adev->irq.self_irq.num_types = 0; 790 adev->irq.self_irq.funcs = &navi10_ih_self_irq_funcs; 791 } 792 793 static int navi10_ih_early_init(void *handle) 794 { 795 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 796 797 navi10_ih_set_interrupt_funcs(adev); 798 navi10_ih_set_self_irq_funcs(adev); 799 return 0; 800 } 801 802 static int navi10_ih_sw_init(void *handle) 803 { 804 int r; 805 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 806 bool use_bus_addr; 807 808 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_IH, 0, 809 &adev->irq.self_irq); 810 811 if (r) 812 return r; 813 814 /* use gpu virtual address for ih ring 815 * until ih_checken is programmed to allow 816 * use bus address for ih ring by psp bl */ 817 if ((adev->flags & AMD_IS_APU) || 818 (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) 819 use_bus_addr = false; 820 else 821 use_bus_addr = true; 822 r = amdgpu_ih_ring_init(adev, &adev->irq.ih, 256 * 1024, use_bus_addr); 823 if (r) 824 return r; 825 826 adev->irq.ih.use_doorbell = true; 827 adev->irq.ih.doorbell_index = adev->doorbell_index.ih << 1; 828 829 adev->irq.ih1.ring_size = 0; 830 adev->irq.ih2.ring_size = 0; 831 832 if (adev->asic_type < CHIP_NAVI10) { 833 r = amdgpu_ih_ring_init(adev, &adev->irq.ih1, PAGE_SIZE, true); 834 if (r) 835 return r; 836 837 adev->irq.ih1.use_doorbell = true; 838 adev->irq.ih1.doorbell_index = 839 (adev->doorbell_index.ih + 1) << 1; 840 841 r = amdgpu_ih_ring_init(adev, &adev->irq.ih2, PAGE_SIZE, true); 842 if (r) 843 return r; 844 845 adev->irq.ih2.use_doorbell = true; 846 adev->irq.ih2.doorbell_index = 847 (adev->doorbell_index.ih + 2) << 1; 848 } 849 850 r = amdgpu_ih_ring_init(adev, &adev->irq.ih_soft, PAGE_SIZE, true); 851 if (r) 852 return r; 853 854 r = amdgpu_irq_init(adev); 855 856 return r; 857 } 858 859 static int navi10_ih_sw_fini(void *handle) 860 { 861 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 862 863 amdgpu_irq_fini(adev); 864 amdgpu_ih_ring_fini(adev, &adev->irq.ih2); 865 amdgpu_ih_ring_fini(adev, &adev->irq.ih1); 866 amdgpu_ih_ring_fini(adev, &adev->irq.ih); 867 868 return 0; 869 } 870 871 static int navi10_ih_hw_init(void *handle) 872 { 873 int r; 874 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 875 876 r = navi10_ih_irq_init(adev); 877 if (r) 878 return r; 879 880 return 0; 881 } 882 883 static int navi10_ih_hw_fini(void *handle) 884 { 885 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 886 887 navi10_ih_irq_disable(adev); 888 889 return 0; 890 } 891 892 static int navi10_ih_suspend(void *handle) 893 { 894 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 895 896 return navi10_ih_hw_fini(adev); 897 } 898 899 static int navi10_ih_resume(void *handle) 900 { 901 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 902 903 return navi10_ih_hw_init(adev); 904 } 905 906 static bool navi10_ih_is_idle(void *handle) 907 { 908 /* todo */ 909 return true; 910 } 911 912 static int navi10_ih_wait_for_idle(void *handle) 913 { 914 /* todo */ 915 return -ETIMEDOUT; 916 } 917 918 static int navi10_ih_soft_reset(void *handle) 919 { 920 /* todo */ 921 return 0; 922 } 923 924 static void navi10_ih_update_clockgating_state(struct amdgpu_device *adev, 925 bool enable) 926 { 927 uint32_t data, def, field_val; 928 929 if (adev->cg_flags & AMD_CG_SUPPORT_IH_CG) { 930 def = data = RREG32_SOC15(OSSSYS, 0, mmIH_CLK_CTRL); 931 field_val = enable ? 0 : 1; 932 data = REG_SET_FIELD(data, IH_CLK_CTRL, 933 DBUS_MUX_CLK_SOFT_OVERRIDE, field_val); 934 data = REG_SET_FIELD(data, IH_CLK_CTRL, 935 OSSSYS_SHARE_CLK_SOFT_OVERRIDE, field_val); 936 data = REG_SET_FIELD(data, IH_CLK_CTRL, 937 LIMIT_SMN_CLK_SOFT_OVERRIDE, field_val); 938 data = REG_SET_FIELD(data, IH_CLK_CTRL, 939 DYN_CLK_SOFT_OVERRIDE, field_val); 940 data = REG_SET_FIELD(data, IH_CLK_CTRL, 941 REG_CLK_SOFT_OVERRIDE, field_val); 942 if (def != data) 943 WREG32_SOC15(OSSSYS, 0, mmIH_CLK_CTRL, data); 944 } 945 946 return; 947 } 948 949 static int navi10_ih_set_clockgating_state(void *handle, 950 enum amd_clockgating_state state) 951 { 952 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 953 954 navi10_ih_update_clockgating_state(adev, 955 state == AMD_CG_STATE_GATE); 956 return 0; 957 } 958 959 static int navi10_ih_set_powergating_state(void *handle, 960 enum amd_powergating_state state) 961 { 962 return 0; 963 } 964 965 static void navi10_ih_get_clockgating_state(void *handle, u32 *flags) 966 { 967 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 968 969 if (!RREG32_SOC15(OSSSYS, 0, mmIH_CLK_CTRL)) 970 *flags |= AMD_CG_SUPPORT_IH_CG; 971 972 return; 973 } 974 975 static const struct amd_ip_funcs navi10_ih_ip_funcs = { 976 .name = "navi10_ih", 977 .early_init = navi10_ih_early_init, 978 .late_init = NULL, 979 .sw_init = navi10_ih_sw_init, 980 .sw_fini = navi10_ih_sw_fini, 981 .hw_init = navi10_ih_hw_init, 982 .hw_fini = navi10_ih_hw_fini, 983 .suspend = navi10_ih_suspend, 984 .resume = navi10_ih_resume, 985 .is_idle = navi10_ih_is_idle, 986 .wait_for_idle = navi10_ih_wait_for_idle, 987 .soft_reset = navi10_ih_soft_reset, 988 .set_clockgating_state = navi10_ih_set_clockgating_state, 989 .set_powergating_state = navi10_ih_set_powergating_state, 990 .get_clockgating_state = navi10_ih_get_clockgating_state, 991 }; 992 993 static const struct amdgpu_ih_funcs navi10_ih_funcs = { 994 .get_wptr = navi10_ih_get_wptr, 995 .decode_iv = navi10_ih_decode_iv, 996 .set_rptr = navi10_ih_set_rptr 997 }; 998 999 static void navi10_ih_set_interrupt_funcs(struct amdgpu_device *adev) 1000 { 1001 if (adev->irq.ih_funcs == NULL) 1002 adev->irq.ih_funcs = &navi10_ih_funcs; 1003 } 1004 1005 const struct amdgpu_ip_block_version navi10_ih_ip_block = 1006 { 1007 .type = AMD_IP_BLOCK_TYPE_IH, 1008 .major = 5, 1009 .minor = 0, 1010 .rev = 0, 1011 .funcs = &navi10_ih_ip_funcs, 1012 }; 1013