1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/pci.h> 25 26 #include "amdgpu.h" 27 #include "amdgpu_ih.h" 28 29 #include "oss/osssys_5_0_0_offset.h" 30 #include "oss/osssys_5_0_0_sh_mask.h" 31 32 #include "soc15_common.h" 33 #include "navi10_ih.h" 34 35 #define MAX_REARM_RETRY 10 36 37 #define mmIH_CHICKEN_Sienna_Cichlid 0x018d 38 #define mmIH_CHICKEN_Sienna_Cichlid_BASE_IDX 0 39 40 static void navi10_ih_set_interrupt_funcs(struct amdgpu_device *adev); 41 42 /** 43 * navi10_ih_init_register_offset - Initialize register offset for ih rings 44 * 45 * @adev: amdgpu_device pointer 46 * 47 * Initialize register offset ih rings (NAVI10). 48 */ 49 static void navi10_ih_init_register_offset(struct amdgpu_device *adev) 50 { 51 struct amdgpu_ih_regs *ih_regs; 52 53 if (adev->irq.ih.ring_size) { 54 ih_regs = &adev->irq.ih.ih_regs; 55 ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE); 56 ih_regs->ih_rb_base_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_HI); 57 ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL); 58 ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR); 59 ih_regs->ih_rb_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR); 60 ih_regs->ih_doorbell_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_DOORBELL_RPTR); 61 ih_regs->ih_rb_wptr_addr_lo = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_ADDR_LO); 62 ih_regs->ih_rb_wptr_addr_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_ADDR_HI); 63 ih_regs->psp_reg_id = PSP_REG_IH_RB_CNTL; 64 } 65 66 if (adev->irq.ih1.ring_size) { 67 ih_regs = &adev->irq.ih1.ih_regs; 68 ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_RING1); 69 ih_regs->ih_rb_base_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_HI_RING1); 70 ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL_RING1); 71 ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_RING1); 72 ih_regs->ih_rb_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR_RING1); 73 ih_regs->ih_doorbell_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_DOORBELL_RPTR_RING1); 74 ih_regs->psp_reg_id = PSP_REG_IH_RB_CNTL_RING1; 75 } 76 77 if (adev->irq.ih2.ring_size) { 78 ih_regs = &adev->irq.ih2.ih_regs; 79 ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_RING2); 80 ih_regs->ih_rb_base_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_HI_RING2); 81 ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL_RING2); 82 ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_RING2); 83 ih_regs->ih_rb_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR_RING2); 84 ih_regs->ih_doorbell_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_DOORBELL_RPTR_RING2); 85 ih_regs->psp_reg_id = PSP_REG_IH_RB_CNTL_RING2; 86 } 87 } 88 89 /** 90 * force_update_wptr_for_self_int - Force update the wptr for self interrupt 91 * 92 * @adev: amdgpu_device pointer 93 * @threshold: threshold to trigger the wptr reporting 94 * @timeout: timeout to trigger the wptr reporting 95 * @enabled: Enable/disable timeout flush mechanism 96 * 97 * threshold input range: 0 ~ 15, default 0, 98 * real_threshold = 2^threshold 99 * timeout input range: 0 ~ 20, default 8, 100 * real_timeout = (2^timeout) * 1024 / (socclk_freq) 101 * 102 * Force update wptr for self interrupt ( >= SIENNA_CICHLID). 103 */ 104 static void 105 force_update_wptr_for_self_int(struct amdgpu_device *adev, 106 u32 threshold, u32 timeout, bool enabled) 107 { 108 u32 ih_cntl, ih_rb_cntl; 109 110 if (adev->asic_type < CHIP_SIENNA_CICHLID) 111 return; 112 113 ih_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_CNTL2); 114 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1); 115 116 ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL2, 117 SELF_IV_FORCE_WPTR_UPDATE_TIMEOUT, timeout); 118 ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL2, 119 SELF_IV_FORCE_WPTR_UPDATE_ENABLE, enabled); 120 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING1, 121 RB_USED_INT_THRESHOLD, threshold); 122 123 WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1, ih_rb_cntl); 124 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2); 125 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING2, 126 RB_USED_INT_THRESHOLD, threshold); 127 WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2, ih_rb_cntl); 128 WREG32_SOC15(OSSSYS, 0, mmIH_CNTL2, ih_cntl); 129 } 130 131 /** 132 * navi10_ih_enable_interrupts - Enable the interrupt ring buffer 133 * 134 * @adev: amdgpu_device pointer 135 * 136 * Enable the interrupt ring buffer (NAVI10). 137 */ 138 static void navi10_ih_enable_interrupts(struct amdgpu_device *adev) 139 { 140 u32 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL); 141 142 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 1); 143 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, ENABLE_INTR, 1); 144 if (amdgpu_sriov_vf(adev) && adev->asic_type < CHIP_NAVI10) { 145 if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL, ih_rb_cntl)) { 146 DRM_ERROR("PSP program IH_RB_CNTL failed!\n"); 147 return; 148 } 149 } else { 150 WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL, ih_rb_cntl); 151 } 152 153 adev->irq.ih.enabled = true; 154 155 if (adev->irq.ih1.ring_size) { 156 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1); 157 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING1, 158 RB_ENABLE, 1); 159 if (amdgpu_sriov_vf(adev) && adev->asic_type < CHIP_NAVI10) { 160 if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL_RING1, 161 ih_rb_cntl)) { 162 DRM_ERROR("program IH_RB_CNTL_RING1 failed!\n"); 163 return; 164 } 165 } else { 166 WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1, ih_rb_cntl); 167 } 168 adev->irq.ih1.enabled = true; 169 } 170 171 if (adev->irq.ih2.ring_size) { 172 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2); 173 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING2, 174 RB_ENABLE, 1); 175 if (amdgpu_sriov_vf(adev) && adev->asic_type < CHIP_NAVI10) { 176 if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL_RING2, 177 ih_rb_cntl)) { 178 DRM_ERROR("program IH_RB_CNTL_RING2 failed!\n"); 179 return; 180 } 181 } else { 182 WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2, ih_rb_cntl); 183 } 184 adev->irq.ih2.enabled = true; 185 } 186 187 if (adev->irq.ih_soft.ring_size) 188 adev->irq.ih_soft.enabled = true; 189 } 190 191 /** 192 * navi10_ih_disable_interrupts - Disable the interrupt ring buffer 193 * 194 * @adev: amdgpu_device pointer 195 * 196 * Disable the interrupt ring buffer (NAVI10). 197 */ 198 static void navi10_ih_disable_interrupts(struct amdgpu_device *adev) 199 { 200 u32 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL); 201 202 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 0); 203 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, ENABLE_INTR, 0); 204 if (amdgpu_sriov_vf(adev) && adev->asic_type < CHIP_NAVI10) { 205 if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL, ih_rb_cntl)) { 206 DRM_ERROR("PSP program IH_RB_CNTL failed!\n"); 207 return; 208 } 209 } else { 210 WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL, ih_rb_cntl); 211 } 212 213 /* set rptr, wptr to 0 */ 214 WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR, 0); 215 WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR, 0); 216 adev->irq.ih.enabled = false; 217 adev->irq.ih.rptr = 0; 218 219 if (adev->irq.ih1.ring_size) { 220 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1); 221 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING1, 222 RB_ENABLE, 0); 223 if (amdgpu_sriov_vf(adev) && adev->asic_type < CHIP_NAVI10) { 224 if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL_RING1, 225 ih_rb_cntl)) { 226 DRM_ERROR("program IH_RB_CNTL_RING1 failed!\n"); 227 return; 228 } 229 } else { 230 WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1, ih_rb_cntl); 231 } 232 /* set rptr, wptr to 0 */ 233 WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR_RING1, 0); 234 WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_RING1, 0); 235 adev->irq.ih1.enabled = false; 236 adev->irq.ih1.rptr = 0; 237 } 238 239 if (adev->irq.ih2.ring_size) { 240 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2); 241 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING2, 242 RB_ENABLE, 0); 243 if (amdgpu_sriov_vf(adev) && adev->asic_type < CHIP_NAVI10) { 244 if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL_RING2, 245 ih_rb_cntl)) { 246 DRM_ERROR("program IH_RB_CNTL_RING2 failed!\n"); 247 return; 248 } 249 } else { 250 WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2, ih_rb_cntl); 251 } 252 /* set rptr, wptr to 0 */ 253 WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR_RING2, 0); 254 WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_RING2, 0); 255 adev->irq.ih2.enabled = false; 256 adev->irq.ih2.rptr = 0; 257 } 258 259 } 260 261 static uint32_t navi10_ih_rb_cntl(struct amdgpu_ih_ring *ih, uint32_t ih_rb_cntl) 262 { 263 int rb_bufsz = order_base_2(ih->ring_size / 4); 264 265 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, 266 MC_SPACE, ih->use_bus_addr ? 1 : 4); 267 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, 268 WPTR_OVERFLOW_CLEAR, 1); 269 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, 270 WPTR_OVERFLOW_ENABLE, 1); 271 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_SIZE, rb_bufsz); 272 /* Ring Buffer write pointer writeback. If enabled, IH_RB_WPTR register 273 * value is written to memory 274 */ 275 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, 276 WPTR_WRITEBACK_ENABLE, 1); 277 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_SNOOP, 1); 278 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_RO, 0); 279 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_VMID, 0); 280 281 return ih_rb_cntl; 282 } 283 284 static uint32_t navi10_ih_doorbell_rptr(struct amdgpu_ih_ring *ih) 285 { 286 u32 ih_doorbell_rtpr = 0; 287 288 if (ih->use_doorbell) { 289 ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr, 290 IH_DOORBELL_RPTR, OFFSET, 291 ih->doorbell_index); 292 ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr, 293 IH_DOORBELL_RPTR, 294 ENABLE, 1); 295 } else { 296 ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr, 297 IH_DOORBELL_RPTR, 298 ENABLE, 0); 299 } 300 return ih_doorbell_rtpr; 301 } 302 303 /** 304 * navi10_ih_enable_ring - enable an ih ring buffer 305 * 306 * @adev: amdgpu_device pointer 307 * @ih: amdgpu_ih_ring pointer 308 * 309 * Enable an ih ring buffer (NAVI10) 310 */ 311 static int navi10_ih_enable_ring(struct amdgpu_device *adev, 312 struct amdgpu_ih_ring *ih) 313 { 314 struct amdgpu_ih_regs *ih_regs; 315 uint32_t tmp; 316 317 ih_regs = &ih->ih_regs; 318 319 /* Ring Buffer base. [39:8] of 40-bit address of the beginning of the ring buffer*/ 320 WREG32(ih_regs->ih_rb_base, ih->gpu_addr >> 8); 321 WREG32(ih_regs->ih_rb_base_hi, (ih->gpu_addr >> 40) & 0xff); 322 323 tmp = RREG32(ih_regs->ih_rb_cntl); 324 tmp = navi10_ih_rb_cntl(ih, tmp); 325 if (ih == &adev->irq.ih) 326 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RPTR_REARM, !!adev->irq.msi_enabled); 327 if (ih == &adev->irq.ih1) { 328 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_ENABLE, 0); 329 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RB_FULL_DRAIN_ENABLE, 1); 330 } 331 if (amdgpu_sriov_vf(adev) && adev->asic_type < CHIP_NAVI10) { 332 if (psp_reg_program(&adev->psp, ih_regs->psp_reg_id, tmp)) { 333 dev_err(adev->dev, "PSP program IH_RB_CNTL failed!\n"); 334 return -ETIMEDOUT; 335 } 336 } else { 337 WREG32(ih_regs->ih_rb_cntl, tmp); 338 } 339 340 if (ih == &adev->irq.ih) { 341 /* set the ih ring 0 writeback address whether it's enabled or not */ 342 WREG32(ih_regs->ih_rb_wptr_addr_lo, lower_32_bits(ih->wptr_addr)); 343 WREG32(ih_regs->ih_rb_wptr_addr_hi, upper_32_bits(ih->wptr_addr) & 0xFFFF); 344 } 345 346 /* set rptr, wptr to 0 */ 347 WREG32(ih_regs->ih_rb_wptr, 0); 348 WREG32(ih_regs->ih_rb_rptr, 0); 349 350 WREG32(ih_regs->ih_doorbell_rptr, navi10_ih_doorbell_rptr(ih)); 351 352 return 0; 353 } 354 355 static void navi10_ih_reroute_ih(struct amdgpu_device *adev) 356 { 357 uint32_t tmp; 358 359 /* Reroute to IH ring 1 for VMC */ 360 WREG32_SOC15(OSSSYS, 0, mmIH_CLIENT_CFG_INDEX, 0x12); 361 tmp = RREG32_SOC15(OSSSYS, 0, mmIH_CLIENT_CFG_DATA); 362 tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, CLIENT_TYPE, 1); 363 tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, RING_ID, 1); 364 WREG32_SOC15(OSSSYS, 0, mmIH_CLIENT_CFG_DATA, tmp); 365 366 /* Reroute IH ring 1 for UMC */ 367 WREG32_SOC15(OSSSYS, 0, mmIH_CLIENT_CFG_INDEX, 0x1B); 368 tmp = RREG32_SOC15(OSSSYS, 0, mmIH_CLIENT_CFG_DATA); 369 tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, RING_ID, 1); 370 WREG32_SOC15(OSSSYS, 0, mmIH_CLIENT_CFG_DATA, tmp); 371 } 372 373 /** 374 * navi10_ih_irq_init - init and enable the interrupt ring 375 * 376 * @adev: amdgpu_device pointer 377 * 378 * Allocate a ring buffer for the interrupt controller, 379 * enable the RLC, disable interrupts, enable the IH 380 * ring buffer and enable it (NAVI). 381 * Called at device load and reume. 382 * Returns 0 for success, errors for failure. 383 */ 384 static int navi10_ih_irq_init(struct amdgpu_device *adev) 385 { 386 struct amdgpu_ih_ring *ih = &adev->irq.ih; 387 u32 ih_rb_cntl, ih_chicken; 388 u32 tmp; 389 390 /* disable irqs */ 391 navi10_ih_disable_interrupts(adev); 392 393 adev->nbio.funcs->ih_control(adev); 394 395 /* Ring Buffer base. [39:8] of 40-bit address of the beginning of the ring buffer*/ 396 WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE, ih->gpu_addr >> 8); 397 WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE_HI, (ih->gpu_addr >> 40) & 0xff); 398 399 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL); 400 ih_rb_cntl = navi10_ih_rb_cntl(ih, ih_rb_cntl); 401 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RPTR_REARM, 402 !!adev->irq.msi_enabled); 403 if (amdgpu_sriov_vf(adev) && adev->asic_type < CHIP_NAVI10) { 404 if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL, ih_rb_cntl)) { 405 DRM_ERROR("PSP program IH_RB_CNTL failed!\n"); 406 return -ETIMEDOUT; 407 } 408 } else { 409 WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL, ih_rb_cntl); 410 } 411 if (adev->irq.ih1.ring_size) 412 navi10_ih_reroute_ih(adev); 413 414 if (unlikely(adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT)) { 415 if (ih->use_bus_addr) { 416 switch (adev->asic_type) { 417 case CHIP_SIENNA_CICHLID: 418 case CHIP_NAVY_FLOUNDER: 419 case CHIP_VANGOGH: 420 case CHIP_DIMGREY_CAVEFISH: 421 ih_chicken = RREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN_Sienna_Cichlid); 422 ih_chicken = REG_SET_FIELD(ih_chicken, 423 IH_CHICKEN, MC_SPACE_GPA_ENABLE, 1); 424 WREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN_Sienna_Cichlid, ih_chicken); 425 break; 426 default: 427 ih_chicken = RREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN); 428 ih_chicken = REG_SET_FIELD(ih_chicken, 429 IH_CHICKEN, MC_SPACE_GPA_ENABLE, 1); 430 WREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN, ih_chicken); 431 break; 432 } 433 } 434 } 435 436 /* set the writeback address whether it's enabled or not */ 437 WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_ADDR_LO, 438 lower_32_bits(ih->wptr_addr)); 439 WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_ADDR_HI, 440 upper_32_bits(ih->wptr_addr) & 0xFFFF); 441 442 /* set rptr, wptr to 0 */ 443 WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR, 0); 444 WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR, 0); 445 446 WREG32_SOC15(OSSSYS, 0, mmIH_DOORBELL_RPTR, 447 navi10_ih_doorbell_rptr(ih)); 448 449 adev->nbio.funcs->ih_doorbell_range(adev, ih->use_doorbell, 450 ih->doorbell_index); 451 452 ih = &adev->irq.ih1; 453 if (ih->ring_size) { 454 WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE_RING1, ih->gpu_addr >> 8); 455 WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE_HI_RING1, 456 (ih->gpu_addr >> 40) & 0xff); 457 458 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1); 459 ih_rb_cntl = navi10_ih_rb_cntl(ih, ih_rb_cntl); 460 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, 461 WPTR_OVERFLOW_ENABLE, 0); 462 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, 463 RB_FULL_DRAIN_ENABLE, 1); 464 if (amdgpu_sriov_vf(adev) && adev->asic_type < CHIP_NAVI10) { 465 if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL_RING1, 466 ih_rb_cntl)) { 467 DRM_ERROR("program IH_RB_CNTL_RING1 failed!\n"); 468 return -ETIMEDOUT; 469 } 470 } else { 471 WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1, ih_rb_cntl); 472 } 473 /* set rptr, wptr to 0 */ 474 WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_RING1, 0); 475 WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR_RING1, 0); 476 477 WREG32_SOC15(OSSSYS, 0, mmIH_DOORBELL_RPTR_RING1, 478 navi10_ih_doorbell_rptr(ih)); 479 } 480 481 ih = &adev->irq.ih2; 482 if (ih->ring_size) { 483 WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE_RING2, ih->gpu_addr >> 8); 484 WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE_HI_RING2, 485 (ih->gpu_addr >> 40) & 0xff); 486 487 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2); 488 ih_rb_cntl = navi10_ih_rb_cntl(ih, ih_rb_cntl); 489 490 if (amdgpu_sriov_vf(adev) && adev->asic_type < CHIP_NAVI10) { 491 if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL_RING2, 492 ih_rb_cntl)) { 493 DRM_ERROR("program IH_RB_CNTL_RING2 failed!\n"); 494 return -ETIMEDOUT; 495 } 496 } else { 497 WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2, ih_rb_cntl); 498 } 499 /* set rptr, wptr to 0 */ 500 WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_RING2, 0); 501 WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR_RING2, 0); 502 503 WREG32_SOC15(OSSSYS, 0, mmIH_DOORBELL_RPTR_RING2, 504 navi10_ih_doorbell_rptr(ih)); 505 } 506 507 508 tmp = RREG32_SOC15(OSSSYS, 0, mmIH_STORM_CLIENT_LIST_CNTL); 509 tmp = REG_SET_FIELD(tmp, IH_STORM_CLIENT_LIST_CNTL, 510 CLIENT18_IS_STORM_CLIENT, 1); 511 WREG32_SOC15(OSSSYS, 0, mmIH_STORM_CLIENT_LIST_CNTL, tmp); 512 513 tmp = RREG32_SOC15(OSSSYS, 0, mmIH_INT_FLOOD_CNTL); 514 tmp = REG_SET_FIELD(tmp, IH_INT_FLOOD_CNTL, FLOOD_CNTL_ENABLE, 1); 515 WREG32_SOC15(OSSSYS, 0, mmIH_INT_FLOOD_CNTL, tmp); 516 517 pci_set_master(adev->pdev); 518 519 /* enable interrupts */ 520 navi10_ih_enable_interrupts(adev); 521 /* enable wptr force update for self int */ 522 force_update_wptr_for_self_int(adev, 0, 8, true); 523 524 return 0; 525 } 526 527 /** 528 * navi10_ih_irq_disable - disable interrupts 529 * 530 * @adev: amdgpu_device pointer 531 * 532 * Disable interrupts on the hw (NAVI10). 533 */ 534 static void navi10_ih_irq_disable(struct amdgpu_device *adev) 535 { 536 force_update_wptr_for_self_int(adev, 0, 8, false); 537 navi10_ih_disable_interrupts(adev); 538 539 /* Wait and acknowledge irq */ 540 mdelay(1); 541 } 542 543 /** 544 * navi10_ih_get_wptr - get the IH ring buffer wptr 545 * 546 * @adev: amdgpu_device pointer 547 * @ih: IH ring buffer to fetch wptr 548 * 549 * Get the IH ring buffer wptr from either the register 550 * or the writeback memory buffer (NAVI10). Also check for 551 * ring buffer overflow and deal with it. 552 * Returns the value of the wptr. 553 */ 554 static u32 navi10_ih_get_wptr(struct amdgpu_device *adev, 555 struct amdgpu_ih_ring *ih) 556 { 557 u32 wptr, reg, tmp; 558 559 wptr = le32_to_cpu(*ih->wptr_cpu); 560 561 if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) 562 goto out; 563 564 if (ih == &adev->irq.ih) 565 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR); 566 else if (ih == &adev->irq.ih1) 567 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_RING1); 568 else if (ih == &adev->irq.ih2) 569 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_RING2); 570 else 571 BUG(); 572 573 wptr = RREG32_NO_KIQ(reg); 574 if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) 575 goto out; 576 wptr = REG_SET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW, 0); 577 578 /* When a ring buffer overflow happen start parsing interrupt 579 * from the last not overwritten vector (wptr + 32). Hopefully 580 * this should allow us to catch up. 581 */ 582 tmp = (wptr + 32) & ih->ptr_mask; 583 dev_warn(adev->dev, "IH ring buffer overflow " 584 "(0x%08X, 0x%08X, 0x%08X)\n", 585 wptr, ih->rptr, tmp); 586 ih->rptr = tmp; 587 588 if (ih == &adev->irq.ih) 589 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL); 590 else if (ih == &adev->irq.ih1) 591 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL_RING1); 592 else if (ih == &adev->irq.ih2) 593 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL_RING2); 594 else 595 BUG(); 596 597 tmp = RREG32_NO_KIQ(reg); 598 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1); 599 WREG32_NO_KIQ(reg, tmp); 600 out: 601 return (wptr & ih->ptr_mask); 602 } 603 604 /** 605 * navi10_ih_decode_iv - decode an interrupt vector 606 * 607 * @adev: amdgpu_device pointer 608 * @ih: IH ring buffer to decode 609 * @entry: IV entry to place decoded information into 610 * 611 * Decodes the interrupt vector at the current rptr 612 * position and also advance the position. 613 */ 614 static void navi10_ih_decode_iv(struct amdgpu_device *adev, 615 struct amdgpu_ih_ring *ih, 616 struct amdgpu_iv_entry *entry) 617 { 618 /* wptr/rptr are in bytes! */ 619 u32 ring_index = ih->rptr >> 2; 620 uint32_t dw[8]; 621 622 dw[0] = le32_to_cpu(ih->ring[ring_index + 0]); 623 dw[1] = le32_to_cpu(ih->ring[ring_index + 1]); 624 dw[2] = le32_to_cpu(ih->ring[ring_index + 2]); 625 dw[3] = le32_to_cpu(ih->ring[ring_index + 3]); 626 dw[4] = le32_to_cpu(ih->ring[ring_index + 4]); 627 dw[5] = le32_to_cpu(ih->ring[ring_index + 5]); 628 dw[6] = le32_to_cpu(ih->ring[ring_index + 6]); 629 dw[7] = le32_to_cpu(ih->ring[ring_index + 7]); 630 631 entry->client_id = dw[0] & 0xff; 632 entry->src_id = (dw[0] >> 8) & 0xff; 633 entry->ring_id = (dw[0] >> 16) & 0xff; 634 entry->vmid = (dw[0] >> 24) & 0xf; 635 entry->vmid_src = (dw[0] >> 31); 636 entry->timestamp = dw[1] | ((u64)(dw[2] & 0xffff) << 32); 637 entry->timestamp_src = dw[2] >> 31; 638 entry->pasid = dw[3] & 0xffff; 639 entry->pasid_src = dw[3] >> 31; 640 entry->src_data[0] = dw[4]; 641 entry->src_data[1] = dw[5]; 642 entry->src_data[2] = dw[6]; 643 entry->src_data[3] = dw[7]; 644 645 /* wptr/rptr are in bytes! */ 646 ih->rptr += 32; 647 } 648 649 /** 650 * navi10_ih_irq_rearm - rearm IRQ if lost 651 * 652 * @adev: amdgpu_device pointer 653 * @ih: IH ring to match 654 * 655 */ 656 static void navi10_ih_irq_rearm(struct amdgpu_device *adev, 657 struct amdgpu_ih_ring *ih) 658 { 659 uint32_t reg_rptr = 0; 660 uint32_t v = 0; 661 uint32_t i = 0; 662 663 if (ih == &adev->irq.ih) 664 reg_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR); 665 else if (ih == &adev->irq.ih1) 666 reg_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR_RING1); 667 else if (ih == &adev->irq.ih2) 668 reg_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR_RING2); 669 else 670 return; 671 672 /* Rearm IRQ / re-write doorbell if doorbell write is lost */ 673 for (i = 0; i < MAX_REARM_RETRY; i++) { 674 v = RREG32_NO_KIQ(reg_rptr); 675 if ((v < ih->ring_size) && (v != ih->rptr)) 676 WDOORBELL32(ih->doorbell_index, ih->rptr); 677 else 678 break; 679 } 680 } 681 682 /** 683 * navi10_ih_set_rptr - set the IH ring buffer rptr 684 * 685 * @adev: amdgpu_device pointer 686 * 687 * @ih: IH ring buffer to set rptr 688 * Set the IH ring buffer rptr. 689 */ 690 static void navi10_ih_set_rptr(struct amdgpu_device *adev, 691 struct amdgpu_ih_ring *ih) 692 { 693 if (ih->use_doorbell) { 694 /* XXX check if swapping is necessary on BE */ 695 *ih->rptr_cpu = ih->rptr; 696 WDOORBELL32(ih->doorbell_index, ih->rptr); 697 698 if (amdgpu_sriov_vf(adev)) 699 navi10_ih_irq_rearm(adev, ih); 700 } else if (ih == &adev->irq.ih) { 701 WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR, ih->rptr); 702 } else if (ih == &adev->irq.ih1) { 703 WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR_RING1, ih->rptr); 704 } else if (ih == &adev->irq.ih2) { 705 WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR_RING2, ih->rptr); 706 } 707 } 708 709 /** 710 * navi10_ih_self_irq - dispatch work for ring 1 and 2 711 * 712 * @adev: amdgpu_device pointer 713 * @source: irq source 714 * @entry: IV with WPTR update 715 * 716 * Update the WPTR from the IV and schedule work to handle the entries. 717 */ 718 static int navi10_ih_self_irq(struct amdgpu_device *adev, 719 struct amdgpu_irq_src *source, 720 struct amdgpu_iv_entry *entry) 721 { 722 uint32_t wptr = cpu_to_le32(entry->src_data[0]); 723 724 switch (entry->ring_id) { 725 case 1: 726 *adev->irq.ih1.wptr_cpu = wptr; 727 schedule_work(&adev->irq.ih1_work); 728 break; 729 case 2: 730 *adev->irq.ih2.wptr_cpu = wptr; 731 schedule_work(&adev->irq.ih2_work); 732 break; 733 default: break; 734 } 735 return 0; 736 } 737 738 static const struct amdgpu_irq_src_funcs navi10_ih_self_irq_funcs = { 739 .process = navi10_ih_self_irq, 740 }; 741 742 static void navi10_ih_set_self_irq_funcs(struct amdgpu_device *adev) 743 { 744 adev->irq.self_irq.num_types = 0; 745 adev->irq.self_irq.funcs = &navi10_ih_self_irq_funcs; 746 } 747 748 static int navi10_ih_early_init(void *handle) 749 { 750 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 751 752 navi10_ih_set_interrupt_funcs(adev); 753 navi10_ih_set_self_irq_funcs(adev); 754 return 0; 755 } 756 757 static int navi10_ih_sw_init(void *handle) 758 { 759 int r; 760 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 761 bool use_bus_addr; 762 763 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_IH, 0, 764 &adev->irq.self_irq); 765 766 if (r) 767 return r; 768 769 /* use gpu virtual address for ih ring 770 * until ih_checken is programmed to allow 771 * use bus address for ih ring by psp bl */ 772 if ((adev->flags & AMD_IS_APU) || 773 (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) 774 use_bus_addr = false; 775 else 776 use_bus_addr = true; 777 r = amdgpu_ih_ring_init(adev, &adev->irq.ih, 256 * 1024, use_bus_addr); 778 if (r) 779 return r; 780 781 adev->irq.ih.use_doorbell = true; 782 adev->irq.ih.doorbell_index = adev->doorbell_index.ih << 1; 783 784 adev->irq.ih1.ring_size = 0; 785 adev->irq.ih2.ring_size = 0; 786 787 if (adev->asic_type < CHIP_NAVI10) { 788 r = amdgpu_ih_ring_init(adev, &adev->irq.ih1, PAGE_SIZE, true); 789 if (r) 790 return r; 791 792 adev->irq.ih1.use_doorbell = true; 793 adev->irq.ih1.doorbell_index = 794 (adev->doorbell_index.ih + 1) << 1; 795 796 r = amdgpu_ih_ring_init(adev, &adev->irq.ih2, PAGE_SIZE, true); 797 if (r) 798 return r; 799 800 adev->irq.ih2.use_doorbell = true; 801 adev->irq.ih2.doorbell_index = 802 (adev->doorbell_index.ih + 2) << 1; 803 } 804 805 r = amdgpu_ih_ring_init(adev, &adev->irq.ih_soft, PAGE_SIZE, true); 806 if (r) 807 return r; 808 809 r = amdgpu_irq_init(adev); 810 811 return r; 812 } 813 814 static int navi10_ih_sw_fini(void *handle) 815 { 816 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 817 818 amdgpu_irq_fini(adev); 819 amdgpu_ih_ring_fini(adev, &adev->irq.ih2); 820 amdgpu_ih_ring_fini(adev, &adev->irq.ih1); 821 amdgpu_ih_ring_fini(adev, &adev->irq.ih); 822 823 return 0; 824 } 825 826 static int navi10_ih_hw_init(void *handle) 827 { 828 int r; 829 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 830 831 r = navi10_ih_irq_init(adev); 832 if (r) 833 return r; 834 835 return 0; 836 } 837 838 static int navi10_ih_hw_fini(void *handle) 839 { 840 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 841 842 navi10_ih_irq_disable(adev); 843 844 return 0; 845 } 846 847 static int navi10_ih_suspend(void *handle) 848 { 849 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 850 851 return navi10_ih_hw_fini(adev); 852 } 853 854 static int navi10_ih_resume(void *handle) 855 { 856 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 857 858 return navi10_ih_hw_init(adev); 859 } 860 861 static bool navi10_ih_is_idle(void *handle) 862 { 863 /* todo */ 864 return true; 865 } 866 867 static int navi10_ih_wait_for_idle(void *handle) 868 { 869 /* todo */ 870 return -ETIMEDOUT; 871 } 872 873 static int navi10_ih_soft_reset(void *handle) 874 { 875 /* todo */ 876 return 0; 877 } 878 879 static void navi10_ih_update_clockgating_state(struct amdgpu_device *adev, 880 bool enable) 881 { 882 uint32_t data, def, field_val; 883 884 if (adev->cg_flags & AMD_CG_SUPPORT_IH_CG) { 885 def = data = RREG32_SOC15(OSSSYS, 0, mmIH_CLK_CTRL); 886 field_val = enable ? 0 : 1; 887 data = REG_SET_FIELD(data, IH_CLK_CTRL, 888 DBUS_MUX_CLK_SOFT_OVERRIDE, field_val); 889 data = REG_SET_FIELD(data, IH_CLK_CTRL, 890 OSSSYS_SHARE_CLK_SOFT_OVERRIDE, field_val); 891 data = REG_SET_FIELD(data, IH_CLK_CTRL, 892 LIMIT_SMN_CLK_SOFT_OVERRIDE, field_val); 893 data = REG_SET_FIELD(data, IH_CLK_CTRL, 894 DYN_CLK_SOFT_OVERRIDE, field_val); 895 data = REG_SET_FIELD(data, IH_CLK_CTRL, 896 REG_CLK_SOFT_OVERRIDE, field_val); 897 if (def != data) 898 WREG32_SOC15(OSSSYS, 0, mmIH_CLK_CTRL, data); 899 } 900 901 return; 902 } 903 904 static int navi10_ih_set_clockgating_state(void *handle, 905 enum amd_clockgating_state state) 906 { 907 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 908 909 navi10_ih_update_clockgating_state(adev, 910 state == AMD_CG_STATE_GATE); 911 return 0; 912 } 913 914 static int navi10_ih_set_powergating_state(void *handle, 915 enum amd_powergating_state state) 916 { 917 return 0; 918 } 919 920 static void navi10_ih_get_clockgating_state(void *handle, u32 *flags) 921 { 922 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 923 924 if (!RREG32_SOC15(OSSSYS, 0, mmIH_CLK_CTRL)) 925 *flags |= AMD_CG_SUPPORT_IH_CG; 926 927 return; 928 } 929 930 static const struct amd_ip_funcs navi10_ih_ip_funcs = { 931 .name = "navi10_ih", 932 .early_init = navi10_ih_early_init, 933 .late_init = NULL, 934 .sw_init = navi10_ih_sw_init, 935 .sw_fini = navi10_ih_sw_fini, 936 .hw_init = navi10_ih_hw_init, 937 .hw_fini = navi10_ih_hw_fini, 938 .suspend = navi10_ih_suspend, 939 .resume = navi10_ih_resume, 940 .is_idle = navi10_ih_is_idle, 941 .wait_for_idle = navi10_ih_wait_for_idle, 942 .soft_reset = navi10_ih_soft_reset, 943 .set_clockgating_state = navi10_ih_set_clockgating_state, 944 .set_powergating_state = navi10_ih_set_powergating_state, 945 .get_clockgating_state = navi10_ih_get_clockgating_state, 946 }; 947 948 static const struct amdgpu_ih_funcs navi10_ih_funcs = { 949 .get_wptr = navi10_ih_get_wptr, 950 .decode_iv = navi10_ih_decode_iv, 951 .set_rptr = navi10_ih_set_rptr 952 }; 953 954 static void navi10_ih_set_interrupt_funcs(struct amdgpu_device *adev) 955 { 956 if (adev->irq.ih_funcs == NULL) 957 adev->irq.ih_funcs = &navi10_ih_funcs; 958 } 959 960 const struct amdgpu_ip_block_version navi10_ih_ip_block = 961 { 962 .type = AMD_IP_BLOCK_TYPE_IH, 963 .major = 5, 964 .minor = 0, 965 .rev = 0, 966 .funcs = &navi10_ih_ip_funcs, 967 }; 968