1edc61147SHawking Zhang /* 2edc61147SHawking Zhang * Copyright 2019 Advanced Micro Devices, Inc. 3edc61147SHawking Zhang * 4edc61147SHawking Zhang * Permission is hereby granted, free of charge, to any person obtaining a 5edc61147SHawking Zhang * copy of this software and associated documentation files (the "Software"), 6edc61147SHawking Zhang * to deal in the Software without restriction, including without limitation 7edc61147SHawking Zhang * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8edc61147SHawking Zhang * and/or sell copies of the Software, and to permit persons to whom the 9edc61147SHawking Zhang * Software is furnished to do so, subject to the following conditions: 10edc61147SHawking Zhang * 11edc61147SHawking Zhang * The above copyright notice and this permission notice shall be included in 12edc61147SHawking Zhang * all copies or substantial portions of the Software. 13edc61147SHawking Zhang * 14edc61147SHawking Zhang * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15edc61147SHawking Zhang * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16edc61147SHawking Zhang * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17edc61147SHawking Zhang * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18edc61147SHawking Zhang * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19edc61147SHawking Zhang * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20edc61147SHawking Zhang * OTHER DEALINGS IN THE SOFTWARE. 21edc61147SHawking Zhang * 22edc61147SHawking Zhang */ 23edc61147SHawking Zhang 24edc61147SHawking Zhang #include <drm/drmP.h> 25edc61147SHawking Zhang #include "amdgpu.h" 26edc61147SHawking Zhang #include "amdgpu_ih.h" 27edc61147SHawking Zhang 28edc61147SHawking Zhang #include "oss/osssys_5_0_0_offset.h" 29edc61147SHawking Zhang #include "oss/osssys_5_0_0_sh_mask.h" 30edc61147SHawking Zhang 31edc61147SHawking Zhang #include "soc15_common.h" 32edc61147SHawking Zhang #include "navi10_ih.h" 33edc61147SHawking Zhang 34edc61147SHawking Zhang 35edc61147SHawking Zhang static void navi10_ih_set_interrupt_funcs(struct amdgpu_device *adev); 36edc61147SHawking Zhang 37edc61147SHawking Zhang /** 38edc61147SHawking Zhang * navi10_ih_enable_interrupts - Enable the interrupt ring buffer 39edc61147SHawking Zhang * 40edc61147SHawking Zhang * @adev: amdgpu_device pointer 41edc61147SHawking Zhang * 42edc61147SHawking Zhang * Enable the interrupt ring buffer (NAVI10). 43edc61147SHawking Zhang */ 44edc61147SHawking Zhang static void navi10_ih_enable_interrupts(struct amdgpu_device *adev) 45edc61147SHawking Zhang { 46edc61147SHawking Zhang u32 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL); 47edc61147SHawking Zhang 48edc61147SHawking Zhang ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 1); 49edc61147SHawking Zhang ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, ENABLE_INTR, 1); 50edc61147SHawking Zhang WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL, ih_rb_cntl); 51edc61147SHawking Zhang adev->irq.ih.enabled = true; 52edc61147SHawking Zhang } 53edc61147SHawking Zhang 54edc61147SHawking Zhang /** 55edc61147SHawking Zhang * navi10_ih_disable_interrupts - Disable the interrupt ring buffer 56edc61147SHawking Zhang * 57edc61147SHawking Zhang * @adev: amdgpu_device pointer 58edc61147SHawking Zhang * 59edc61147SHawking Zhang * Disable the interrupt ring buffer (NAVI10). 60edc61147SHawking Zhang */ 61edc61147SHawking Zhang static void navi10_ih_disable_interrupts(struct amdgpu_device *adev) 62edc61147SHawking Zhang { 63edc61147SHawking Zhang u32 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL); 64edc61147SHawking Zhang 65edc61147SHawking Zhang ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 0); 66edc61147SHawking Zhang ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, ENABLE_INTR, 0); 67edc61147SHawking Zhang WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL, ih_rb_cntl); 68edc61147SHawking Zhang /* set rptr, wptr to 0 */ 69edc61147SHawking Zhang WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR, 0); 70edc61147SHawking Zhang WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR, 0); 71edc61147SHawking Zhang adev->irq.ih.enabled = false; 72edc61147SHawking Zhang adev->irq.ih.rptr = 0; 73edc61147SHawking Zhang } 74edc61147SHawking Zhang 75edc61147SHawking Zhang static uint32_t navi10_ih_rb_cntl(struct amdgpu_ih_ring *ih, uint32_t ih_rb_cntl) 76edc61147SHawking Zhang { 77edc61147SHawking Zhang int rb_bufsz = order_base_2(ih->ring_size / 4); 78edc61147SHawking Zhang 79edc61147SHawking Zhang ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, 80edc61147SHawking Zhang MC_SPACE, ih->use_bus_addr ? 1 : 4); 81edc61147SHawking Zhang ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, 82edc61147SHawking Zhang WPTR_OVERFLOW_CLEAR, 1); 83edc61147SHawking Zhang ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, 84edc61147SHawking Zhang WPTR_OVERFLOW_ENABLE, 1); 85edc61147SHawking Zhang ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_SIZE, rb_bufsz); 86edc61147SHawking Zhang /* Ring Buffer write pointer writeback. If enabled, IH_RB_WPTR register 87edc61147SHawking Zhang * value is written to memory 88edc61147SHawking Zhang */ 89edc61147SHawking Zhang ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, 90edc61147SHawking Zhang WPTR_WRITEBACK_ENABLE, 1); 91edc61147SHawking Zhang ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_SNOOP, 1); 92edc61147SHawking Zhang ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_RO, 0); 93edc61147SHawking Zhang ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_VMID, 0); 94edc61147SHawking Zhang 95edc61147SHawking Zhang return ih_rb_cntl; 96edc61147SHawking Zhang } 97edc61147SHawking Zhang 98edc61147SHawking Zhang /** 99edc61147SHawking Zhang * navi10_ih_irq_init - init and enable the interrupt ring 100edc61147SHawking Zhang * 101edc61147SHawking Zhang * @adev: amdgpu_device pointer 102edc61147SHawking Zhang * 103edc61147SHawking Zhang * Allocate a ring buffer for the interrupt controller, 104edc61147SHawking Zhang * enable the RLC, disable interrupts, enable the IH 105edc61147SHawking Zhang * ring buffer and enable it (NAVI). 106edc61147SHawking Zhang * Called at device load and reume. 107edc61147SHawking Zhang * Returns 0 for success, errors for failure. 108edc61147SHawking Zhang */ 109edc61147SHawking Zhang static int navi10_ih_irq_init(struct amdgpu_device *adev) 110edc61147SHawking Zhang { 111edc61147SHawking Zhang struct amdgpu_ih_ring *ih = &adev->irq.ih; 112edc61147SHawking Zhang int ret = 0; 113edc61147SHawking Zhang u32 ih_rb_cntl, ih_doorbell_rtpr, ih_chicken; 114edc61147SHawking Zhang u32 tmp; 115edc61147SHawking Zhang 116edc61147SHawking Zhang /* disable irqs */ 117edc61147SHawking Zhang navi10_ih_disable_interrupts(adev); 118edc61147SHawking Zhang 119edc61147SHawking Zhang adev->nbio_funcs->ih_control(adev); 120edc61147SHawking Zhang 121edc61147SHawking Zhang /* Ring Buffer base. [39:8] of 40-bit address of the beginning of the ring buffer*/ 122edc61147SHawking Zhang WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE, ih->gpu_addr >> 8); 123edc61147SHawking Zhang WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE_HI, (ih->gpu_addr >> 40) & 0xff); 124edc61147SHawking Zhang 125edc61147SHawking Zhang ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL); 126edc61147SHawking Zhang ih_rb_cntl = navi10_ih_rb_cntl(ih, ih_rb_cntl); 127edc61147SHawking Zhang ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RPTR_REARM, 128edc61147SHawking Zhang !!adev->irq.msi_enabled); 129edc61147SHawking Zhang 130edc61147SHawking Zhang if (unlikely(adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT)) { 131edc61147SHawking Zhang if (ih->use_bus_addr) { 132edc61147SHawking Zhang ih_chicken = RREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN); 133edc61147SHawking Zhang ih_chicken = REG_SET_FIELD(ih_chicken, 134edc61147SHawking Zhang IH_CHICKEN, MC_SPACE_GPA_ENABLE, 1); 135edc61147SHawking Zhang WREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN, ih_chicken); 136edc61147SHawking Zhang } 137edc61147SHawking Zhang } 138edc61147SHawking Zhang 139edc61147SHawking Zhang WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL, ih_rb_cntl); 140edc61147SHawking Zhang 141edc61147SHawking Zhang /* set the writeback address whether it's enabled or not */ 142edc61147SHawking Zhang WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_ADDR_LO, 143edc61147SHawking Zhang lower_32_bits(ih->wptr_addr)); 144edc61147SHawking Zhang WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_ADDR_HI, 145edc61147SHawking Zhang upper_32_bits(ih->wptr_addr) & 0xFFFF); 146edc61147SHawking Zhang 147edc61147SHawking Zhang /* set rptr, wptr to 0 */ 148edc61147SHawking Zhang WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR, 0); 149edc61147SHawking Zhang WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR, 0); 150edc61147SHawking Zhang 151edc61147SHawking Zhang ih_doorbell_rtpr = RREG32_SOC15(OSSSYS, 0, mmIH_DOORBELL_RPTR); 152edc61147SHawking Zhang if (ih->use_doorbell) { 153edc61147SHawking Zhang ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr, 154edc61147SHawking Zhang IH_DOORBELL_RPTR, OFFSET, 155edc61147SHawking Zhang ih->doorbell_index); 156edc61147SHawking Zhang ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr, 157edc61147SHawking Zhang IH_DOORBELL_RPTR, ENABLE, 1); 158edc61147SHawking Zhang } else { 159edc61147SHawking Zhang ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr, 160edc61147SHawking Zhang IH_DOORBELL_RPTR, ENABLE, 0); 161edc61147SHawking Zhang } 162edc61147SHawking Zhang WREG32_SOC15(OSSSYS, 0, mmIH_DOORBELL_RPTR, ih_doorbell_rtpr); 163edc61147SHawking Zhang 164edc61147SHawking Zhang adev->nbio_funcs->ih_doorbell_range(adev, ih->use_doorbell, 165edc61147SHawking Zhang ih->doorbell_index); 166edc61147SHawking Zhang 167edc61147SHawking Zhang tmp = RREG32_SOC15(OSSSYS, 0, mmIH_STORM_CLIENT_LIST_CNTL); 168edc61147SHawking Zhang tmp = REG_SET_FIELD(tmp, IH_STORM_CLIENT_LIST_CNTL, 169edc61147SHawking Zhang CLIENT18_IS_STORM_CLIENT, 1); 170edc61147SHawking Zhang WREG32_SOC15(OSSSYS, 0, mmIH_STORM_CLIENT_LIST_CNTL, tmp); 171edc61147SHawking Zhang 172edc61147SHawking Zhang tmp = RREG32_SOC15(OSSSYS, 0, mmIH_INT_FLOOD_CNTL); 173edc61147SHawking Zhang tmp = REG_SET_FIELD(tmp, IH_INT_FLOOD_CNTL, FLOOD_CNTL_ENABLE, 1); 174edc61147SHawking Zhang WREG32_SOC15(OSSSYS, 0, mmIH_INT_FLOOD_CNTL, tmp); 175edc61147SHawking Zhang 176edc61147SHawking Zhang pci_set_master(adev->pdev); 177edc61147SHawking Zhang 178edc61147SHawking Zhang /* enable interrupts */ 179edc61147SHawking Zhang navi10_ih_enable_interrupts(adev); 180edc61147SHawking Zhang 181edc61147SHawking Zhang return ret; 182edc61147SHawking Zhang } 183edc61147SHawking Zhang 184edc61147SHawking Zhang /** 185edc61147SHawking Zhang * navi10_ih_irq_disable - disable interrupts 186edc61147SHawking Zhang * 187edc61147SHawking Zhang * @adev: amdgpu_device pointer 188edc61147SHawking Zhang * 189edc61147SHawking Zhang * Disable interrupts on the hw (NAVI10). 190edc61147SHawking Zhang */ 191edc61147SHawking Zhang static void navi10_ih_irq_disable(struct amdgpu_device *adev) 192edc61147SHawking Zhang { 193edc61147SHawking Zhang navi10_ih_disable_interrupts(adev); 194edc61147SHawking Zhang 195edc61147SHawking Zhang /* Wait and acknowledge irq */ 196edc61147SHawking Zhang mdelay(1); 197edc61147SHawking Zhang } 198edc61147SHawking Zhang 199edc61147SHawking Zhang /** 200edc61147SHawking Zhang * navi10_ih_get_wptr - get the IH ring buffer wptr 201edc61147SHawking Zhang * 202edc61147SHawking Zhang * @adev: amdgpu_device pointer 203edc61147SHawking Zhang * 204edc61147SHawking Zhang * Get the IH ring buffer wptr from either the register 205edc61147SHawking Zhang * or the writeback memory buffer (NAVI10). Also check for 206edc61147SHawking Zhang * ring buffer overflow and deal with it. 207edc61147SHawking Zhang * Returns the value of the wptr. 208edc61147SHawking Zhang */ 209edc61147SHawking Zhang static u32 navi10_ih_get_wptr(struct amdgpu_device *adev, 210edc61147SHawking Zhang struct amdgpu_ih_ring *ih) 211edc61147SHawking Zhang { 212edc61147SHawking Zhang u32 wptr, reg, tmp; 213edc61147SHawking Zhang 214edc61147SHawking Zhang wptr = le32_to_cpu(*ih->wptr_cpu); 215edc61147SHawking Zhang 216edc61147SHawking Zhang if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) 217edc61147SHawking Zhang goto out; 218edc61147SHawking Zhang 219edc61147SHawking Zhang reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR); 220edc61147SHawking Zhang wptr = RREG32_NO_KIQ(reg); 221edc61147SHawking Zhang if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) 222edc61147SHawking Zhang goto out; 223edc61147SHawking Zhang wptr = REG_SET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW, 0); 224edc61147SHawking Zhang 225edc61147SHawking Zhang /* When a ring buffer overflow happen start parsing interrupt 226edc61147SHawking Zhang * from the last not overwritten vector (wptr + 32). Hopefully 227edc61147SHawking Zhang * this should allow us to catch up. 228edc61147SHawking Zhang */ 229edc61147SHawking Zhang tmp = (wptr + 32) & ih->ptr_mask; 230edc61147SHawking Zhang dev_warn(adev->dev, "IH ring buffer overflow " 231edc61147SHawking Zhang "(0x%08X, 0x%08X, 0x%08X)\n", 232edc61147SHawking Zhang wptr, ih->rptr, tmp); 233edc61147SHawking Zhang ih->rptr = tmp; 234edc61147SHawking Zhang 235edc61147SHawking Zhang reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL); 236edc61147SHawking Zhang tmp = RREG32_NO_KIQ(reg); 237edc61147SHawking Zhang tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1); 238edc61147SHawking Zhang WREG32_NO_KIQ(reg, tmp); 239edc61147SHawking Zhang out: 240edc61147SHawking Zhang return (wptr & ih->ptr_mask); 241edc61147SHawking Zhang } 242edc61147SHawking Zhang 243edc61147SHawking Zhang /** 244edc61147SHawking Zhang * navi10_ih_decode_iv - decode an interrupt vector 245edc61147SHawking Zhang * 246edc61147SHawking Zhang * @adev: amdgpu_device pointer 247edc61147SHawking Zhang * 248edc61147SHawking Zhang * Decodes the interrupt vector at the current rptr 249edc61147SHawking Zhang * position and also advance the position. 250edc61147SHawking Zhang */ 251edc61147SHawking Zhang static void navi10_ih_decode_iv(struct amdgpu_device *adev, 252edc61147SHawking Zhang struct amdgpu_ih_ring *ih, 253edc61147SHawking Zhang struct amdgpu_iv_entry *entry) 254edc61147SHawking Zhang { 255edc61147SHawking Zhang /* wptr/rptr are in bytes! */ 256edc61147SHawking Zhang u32 ring_index = ih->rptr >> 2; 257edc61147SHawking Zhang uint32_t dw[8]; 258edc61147SHawking Zhang 259edc61147SHawking Zhang dw[0] = le32_to_cpu(ih->ring[ring_index + 0]); 260edc61147SHawking Zhang dw[1] = le32_to_cpu(ih->ring[ring_index + 1]); 261edc61147SHawking Zhang dw[2] = le32_to_cpu(ih->ring[ring_index + 2]); 262edc61147SHawking Zhang dw[3] = le32_to_cpu(ih->ring[ring_index + 3]); 263edc61147SHawking Zhang dw[4] = le32_to_cpu(ih->ring[ring_index + 4]); 264edc61147SHawking Zhang dw[5] = le32_to_cpu(ih->ring[ring_index + 5]); 265edc61147SHawking Zhang dw[6] = le32_to_cpu(ih->ring[ring_index + 6]); 266edc61147SHawking Zhang dw[7] = le32_to_cpu(ih->ring[ring_index + 7]); 267edc61147SHawking Zhang 268edc61147SHawking Zhang entry->client_id = dw[0] & 0xff; 269edc61147SHawking Zhang entry->src_id = (dw[0] >> 8) & 0xff; 270edc61147SHawking Zhang entry->ring_id = (dw[0] >> 16) & 0xff; 271edc61147SHawking Zhang entry->vmid = (dw[0] >> 24) & 0xf; 272edc61147SHawking Zhang entry->vmid_src = (dw[0] >> 31); 273edc61147SHawking Zhang entry->timestamp = dw[1] | ((u64)(dw[2] & 0xffff) << 32); 274edc61147SHawking Zhang entry->timestamp_src = dw[2] >> 31; 275edc61147SHawking Zhang entry->pasid = dw[3] & 0xffff; 276edc61147SHawking Zhang entry->pasid_src = dw[3] >> 31; 277edc61147SHawking Zhang entry->src_data[0] = dw[4]; 278edc61147SHawking Zhang entry->src_data[1] = dw[5]; 279edc61147SHawking Zhang entry->src_data[2] = dw[6]; 280edc61147SHawking Zhang entry->src_data[3] = dw[7]; 281edc61147SHawking Zhang 282edc61147SHawking Zhang /* wptr/rptr are in bytes! */ 283edc61147SHawking Zhang ih->rptr += 32; 284edc61147SHawking Zhang } 285edc61147SHawking Zhang 286edc61147SHawking Zhang /** 287edc61147SHawking Zhang * navi10_ih_set_rptr - set the IH ring buffer rptr 288edc61147SHawking Zhang * 289edc61147SHawking Zhang * @adev: amdgpu_device pointer 290edc61147SHawking Zhang * 291edc61147SHawking Zhang * Set the IH ring buffer rptr. 292edc61147SHawking Zhang */ 293edc61147SHawking Zhang static void navi10_ih_set_rptr(struct amdgpu_device *adev, 294edc61147SHawking Zhang struct amdgpu_ih_ring *ih) 295edc61147SHawking Zhang { 296edc61147SHawking Zhang if (ih->use_doorbell) { 297edc61147SHawking Zhang /* XXX check if swapping is necessary on BE */ 298edc61147SHawking Zhang *ih->rptr_cpu = ih->rptr; 299edc61147SHawking Zhang WDOORBELL32(ih->doorbell_index, ih->rptr); 300edc61147SHawking Zhang } else 301edc61147SHawking Zhang WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR, ih->rptr); 302edc61147SHawking Zhang } 303edc61147SHawking Zhang 304edc61147SHawking Zhang static int navi10_ih_early_init(void *handle) 305edc61147SHawking Zhang { 306edc61147SHawking Zhang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 307edc61147SHawking Zhang 308edc61147SHawking Zhang navi10_ih_set_interrupt_funcs(adev); 309edc61147SHawking Zhang return 0; 310edc61147SHawking Zhang } 311edc61147SHawking Zhang 312edc61147SHawking Zhang static int navi10_ih_sw_init(void *handle) 313edc61147SHawking Zhang { 314edc61147SHawking Zhang int r; 315edc61147SHawking Zhang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 316edc61147SHawking Zhang bool use_bus_addr; 317edc61147SHawking Zhang 318edc61147SHawking Zhang /* use gpu virtual address for ih ring 319edc61147SHawking Zhang * until ih_checken is programmed to allow 320edc61147SHawking Zhang * use bus address for ih ring by psp bl */ 321edc61147SHawking Zhang use_bus_addr = 322edc61147SHawking Zhang (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) ? false : true; 323edc61147SHawking Zhang r = amdgpu_ih_ring_init(adev, &adev->irq.ih, 256 * 1024, use_bus_addr); 324edc61147SHawking Zhang if (r) 325edc61147SHawking Zhang return r; 326edc61147SHawking Zhang 327edc61147SHawking Zhang adev->irq.ih.use_doorbell = true; 328edc61147SHawking Zhang adev->irq.ih.doorbell_index = adev->doorbell_index.ih << 1; 329edc61147SHawking Zhang 330edc61147SHawking Zhang r = amdgpu_irq_init(adev); 331edc61147SHawking Zhang 332edc61147SHawking Zhang return r; 333edc61147SHawking Zhang } 334edc61147SHawking Zhang 335edc61147SHawking Zhang static int navi10_ih_sw_fini(void *handle) 336edc61147SHawking Zhang { 337edc61147SHawking Zhang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 338edc61147SHawking Zhang 339edc61147SHawking Zhang amdgpu_irq_fini(adev); 340edc61147SHawking Zhang amdgpu_ih_ring_fini(adev, &adev->irq.ih); 341edc61147SHawking Zhang 342edc61147SHawking Zhang return 0; 343edc61147SHawking Zhang } 344edc61147SHawking Zhang 345edc61147SHawking Zhang static int navi10_ih_hw_init(void *handle) 346edc61147SHawking Zhang { 347edc61147SHawking Zhang int r; 348edc61147SHawking Zhang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 349edc61147SHawking Zhang 350edc61147SHawking Zhang r = navi10_ih_irq_init(adev); 351edc61147SHawking Zhang if (r) 352edc61147SHawking Zhang return r; 353edc61147SHawking Zhang 354edc61147SHawking Zhang return 0; 355edc61147SHawking Zhang } 356edc61147SHawking Zhang 357edc61147SHawking Zhang static int navi10_ih_hw_fini(void *handle) 358edc61147SHawking Zhang { 359edc61147SHawking Zhang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 360edc61147SHawking Zhang 361edc61147SHawking Zhang navi10_ih_irq_disable(adev); 362edc61147SHawking Zhang 363edc61147SHawking Zhang return 0; 364edc61147SHawking Zhang } 365edc61147SHawking Zhang 366edc61147SHawking Zhang static int navi10_ih_suspend(void *handle) 367edc61147SHawking Zhang { 368edc61147SHawking Zhang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 369edc61147SHawking Zhang 370edc61147SHawking Zhang return navi10_ih_hw_fini(adev); 371edc61147SHawking Zhang } 372edc61147SHawking Zhang 373edc61147SHawking Zhang static int navi10_ih_resume(void *handle) 374edc61147SHawking Zhang { 375edc61147SHawking Zhang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 376edc61147SHawking Zhang 377edc61147SHawking Zhang return navi10_ih_hw_init(adev); 378edc61147SHawking Zhang } 379edc61147SHawking Zhang 380edc61147SHawking Zhang static bool navi10_ih_is_idle(void *handle) 381edc61147SHawking Zhang { 382edc61147SHawking Zhang /* todo */ 383edc61147SHawking Zhang return true; 384edc61147SHawking Zhang } 385edc61147SHawking Zhang 386edc61147SHawking Zhang static int navi10_ih_wait_for_idle(void *handle) 387edc61147SHawking Zhang { 388edc61147SHawking Zhang /* todo */ 389edc61147SHawking Zhang return -ETIMEDOUT; 390edc61147SHawking Zhang } 391edc61147SHawking Zhang 392edc61147SHawking Zhang static int navi10_ih_soft_reset(void *handle) 393edc61147SHawking Zhang { 394edc61147SHawking Zhang /* todo */ 395edc61147SHawking Zhang return 0; 396edc61147SHawking Zhang } 397edc61147SHawking Zhang 398edc61147SHawking Zhang static void navi10_ih_update_clockgating_state(struct amdgpu_device *adev, 399edc61147SHawking Zhang bool enable) 400edc61147SHawking Zhang { 401edc61147SHawking Zhang uint32_t data, def, field_val; 402edc61147SHawking Zhang 403edc61147SHawking Zhang if (adev->cg_flags & AMD_CG_SUPPORT_IH_CG) { 404edc61147SHawking Zhang def = data = RREG32_SOC15(OSSSYS, 0, mmIH_CLK_CTRL); 405edc61147SHawking Zhang field_val = enable ? 0 : 1; 406edc61147SHawking Zhang data = REG_SET_FIELD(data, IH_CLK_CTRL, 407edc61147SHawking Zhang DBUS_MUX_CLK_SOFT_OVERRIDE, field_val); 408edc61147SHawking Zhang data = REG_SET_FIELD(data, IH_CLK_CTRL, 409edc61147SHawking Zhang OSSSYS_SHARE_CLK_SOFT_OVERRIDE, field_val); 410edc61147SHawking Zhang data = REG_SET_FIELD(data, IH_CLK_CTRL, 411edc61147SHawking Zhang LIMIT_SMN_CLK_SOFT_OVERRIDE, field_val); 412edc61147SHawking Zhang data = REG_SET_FIELD(data, IH_CLK_CTRL, 413edc61147SHawking Zhang DYN_CLK_SOFT_OVERRIDE, field_val); 414edc61147SHawking Zhang data = REG_SET_FIELD(data, IH_CLK_CTRL, 415edc61147SHawking Zhang REG_CLK_SOFT_OVERRIDE, field_val); 416edc61147SHawking Zhang if (def != data) 417edc61147SHawking Zhang WREG32_SOC15(OSSSYS, 0, mmIH_CLK_CTRL, data); 418edc61147SHawking Zhang } 419edc61147SHawking Zhang 420edc61147SHawking Zhang return; 421edc61147SHawking Zhang } 422edc61147SHawking Zhang 423edc61147SHawking Zhang static int navi10_ih_set_clockgating_state(void *handle, 424edc61147SHawking Zhang enum amd_clockgating_state state) 425edc61147SHawking Zhang { 426edc61147SHawking Zhang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 427edc61147SHawking Zhang 428edc61147SHawking Zhang navi10_ih_update_clockgating_state(adev, 429edc61147SHawking Zhang state == AMD_CG_STATE_GATE ? true : false); 430edc61147SHawking Zhang return 0; 431edc61147SHawking Zhang } 432edc61147SHawking Zhang 433edc61147SHawking Zhang static int navi10_ih_set_powergating_state(void *handle, 434edc61147SHawking Zhang enum amd_powergating_state state) 435edc61147SHawking Zhang { 436edc61147SHawking Zhang return 0; 437edc61147SHawking Zhang } 438edc61147SHawking Zhang 439edc61147SHawking Zhang static void navi10_ih_get_clockgating_state(void *handle, u32 *flags) 440edc61147SHawking Zhang { 441edc61147SHawking Zhang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 442edc61147SHawking Zhang 443edc61147SHawking Zhang if (!RREG32_SOC15(OSSSYS, 0, mmIH_CLK_CTRL)) 444edc61147SHawking Zhang *flags |= AMD_CG_SUPPORT_IH_CG; 445edc61147SHawking Zhang 446edc61147SHawking Zhang return; 447edc61147SHawking Zhang } 448edc61147SHawking Zhang 449edc61147SHawking Zhang static const struct amd_ip_funcs navi10_ih_ip_funcs = { 450edc61147SHawking Zhang .name = "navi10_ih", 451edc61147SHawking Zhang .early_init = navi10_ih_early_init, 452edc61147SHawking Zhang .late_init = NULL, 453edc61147SHawking Zhang .sw_init = navi10_ih_sw_init, 454edc61147SHawking Zhang .sw_fini = navi10_ih_sw_fini, 455edc61147SHawking Zhang .hw_init = navi10_ih_hw_init, 456edc61147SHawking Zhang .hw_fini = navi10_ih_hw_fini, 457edc61147SHawking Zhang .suspend = navi10_ih_suspend, 458edc61147SHawking Zhang .resume = navi10_ih_resume, 459edc61147SHawking Zhang .is_idle = navi10_ih_is_idle, 460edc61147SHawking Zhang .wait_for_idle = navi10_ih_wait_for_idle, 461edc61147SHawking Zhang .soft_reset = navi10_ih_soft_reset, 462edc61147SHawking Zhang .set_clockgating_state = navi10_ih_set_clockgating_state, 463edc61147SHawking Zhang .set_powergating_state = navi10_ih_set_powergating_state, 464edc61147SHawking Zhang .get_clockgating_state = navi10_ih_get_clockgating_state, 465edc61147SHawking Zhang }; 466edc61147SHawking Zhang 467edc61147SHawking Zhang static const struct amdgpu_ih_funcs navi10_ih_funcs = { 468edc61147SHawking Zhang .get_wptr = navi10_ih_get_wptr, 469edc61147SHawking Zhang .decode_iv = navi10_ih_decode_iv, 470edc61147SHawking Zhang .set_rptr = navi10_ih_set_rptr 471edc61147SHawking Zhang }; 472edc61147SHawking Zhang 473edc61147SHawking Zhang static void navi10_ih_set_interrupt_funcs(struct amdgpu_device *adev) 474edc61147SHawking Zhang { 475edc61147SHawking Zhang if (adev->irq.ih_funcs == NULL) 476edc61147SHawking Zhang adev->irq.ih_funcs = &navi10_ih_funcs; 477edc61147SHawking Zhang } 478edc61147SHawking Zhang 479edc61147SHawking Zhang const struct amdgpu_ip_block_version navi10_ih_ip_block = 480edc61147SHawking Zhang { 481edc61147SHawking Zhang .type = AMD_IP_BLOCK_TYPE_IH, 482edc61147SHawking Zhang .major = 5, 483edc61147SHawking Zhang .minor = 0, 484edc61147SHawking Zhang .rev = 0, 485edc61147SHawking Zhang .funcs = &navi10_ih_ip_funcs, 486edc61147SHawking Zhang }; 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