1edc61147SHawking Zhang /* 2edc61147SHawking Zhang * Copyright 2019 Advanced Micro Devices, Inc. 3edc61147SHawking Zhang * 4edc61147SHawking Zhang * Permission is hereby granted, free of charge, to any person obtaining a 5edc61147SHawking Zhang * copy of this software and associated documentation files (the "Software"), 6edc61147SHawking Zhang * to deal in the Software without restriction, including without limitation 7edc61147SHawking Zhang * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8edc61147SHawking Zhang * and/or sell copies of the Software, and to permit persons to whom the 9edc61147SHawking Zhang * Software is furnished to do so, subject to the following conditions: 10edc61147SHawking Zhang * 11edc61147SHawking Zhang * The above copyright notice and this permission notice shall be included in 12edc61147SHawking Zhang * all copies or substantial portions of the Software. 13edc61147SHawking Zhang * 14edc61147SHawking Zhang * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15edc61147SHawking Zhang * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16edc61147SHawking Zhang * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17edc61147SHawking Zhang * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18edc61147SHawking Zhang * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19edc61147SHawking Zhang * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20edc61147SHawking Zhang * OTHER DEALINGS IN THE SOFTWARE. 21edc61147SHawking Zhang * 22edc61147SHawking Zhang */ 23edc61147SHawking Zhang 24b23b2e9eSAlex Deucher #include <linux/pci.h> 25b23b2e9eSAlex Deucher 26edc61147SHawking Zhang #include "amdgpu.h" 27edc61147SHawking Zhang #include "amdgpu_ih.h" 28edc61147SHawking Zhang 29edc61147SHawking Zhang #include "oss/osssys_5_0_0_offset.h" 30edc61147SHawking Zhang #include "oss/osssys_5_0_0_sh_mask.h" 31edc61147SHawking Zhang 32edc61147SHawking Zhang #include "soc15_common.h" 33edc61147SHawking Zhang #include "navi10_ih.h" 34edc61147SHawking Zhang 35022b6518SSamir Dhume #define MAX_REARM_RETRY 10 36edc61147SHawking Zhang 37757b3af8SLikun Gao #define mmIH_CHICKEN_Sienna_Cichlid 0x018d 38757b3af8SLikun Gao #define mmIH_CHICKEN_Sienna_Cichlid_BASE_IDX 0 39757b3af8SLikun Gao 40edc61147SHawking Zhang static void navi10_ih_set_interrupt_funcs(struct amdgpu_device *adev); 41edc61147SHawking Zhang 42edc61147SHawking Zhang /** 435ea6f9c2SChengming Gui * force_update_wptr_for_self_int - Force update the wptr for self interrupt 445ea6f9c2SChengming Gui * 455ea6f9c2SChengming Gui * @adev: amdgpu_device pointer 465ea6f9c2SChengming Gui * @threshold: threshold to trigger the wptr reporting 475ea6f9c2SChengming Gui * @timeout: timeout to trigger the wptr reporting 485ea6f9c2SChengming Gui * @enabled: Enable/disable timeout flush mechanism 495ea6f9c2SChengming Gui * 505ea6f9c2SChengming Gui * threshold input range: 0 ~ 15, default 0, 515ea6f9c2SChengming Gui * real_threshold = 2^threshold 525ea6f9c2SChengming Gui * timeout input range: 0 ~ 20, default 8, 535ea6f9c2SChengming Gui * real_timeout = (2^timeout) * 1024 / (socclk_freq) 545ea6f9c2SChengming Gui * 555ea6f9c2SChengming Gui * Force update wptr for self interrupt ( >= SIENNA_CICHLID). 565ea6f9c2SChengming Gui */ 575ea6f9c2SChengming Gui static void 585ea6f9c2SChengming Gui force_update_wptr_for_self_int(struct amdgpu_device *adev, 595ea6f9c2SChengming Gui u32 threshold, u32 timeout, bool enabled) 605ea6f9c2SChengming Gui { 615ea6f9c2SChengming Gui u32 ih_cntl, ih_rb_cntl; 625ea6f9c2SChengming Gui 635ea6f9c2SChengming Gui if (adev->asic_type < CHIP_SIENNA_CICHLID) 645ea6f9c2SChengming Gui return; 655ea6f9c2SChengming Gui 665ea6f9c2SChengming Gui ih_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_CNTL2); 675ea6f9c2SChengming Gui ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1); 685ea6f9c2SChengming Gui 695ea6f9c2SChengming Gui ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL2, 705ea6f9c2SChengming Gui SELF_IV_FORCE_WPTR_UPDATE_TIMEOUT, timeout); 715ea6f9c2SChengming Gui ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL2, 725ea6f9c2SChengming Gui SELF_IV_FORCE_WPTR_UPDATE_ENABLE, enabled); 735ea6f9c2SChengming Gui ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING1, 745ea6f9c2SChengming Gui RB_USED_INT_THRESHOLD, threshold); 755ea6f9c2SChengming Gui 765ea6f9c2SChengming Gui WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1, ih_rb_cntl); 775ea6f9c2SChengming Gui ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2); 785ea6f9c2SChengming Gui ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING2, 795ea6f9c2SChengming Gui RB_USED_INT_THRESHOLD, threshold); 805ea6f9c2SChengming Gui WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2, ih_rb_cntl); 815ea6f9c2SChengming Gui WREG32_SOC15(OSSSYS, 0, mmIH_CNTL2, ih_cntl); 825ea6f9c2SChengming Gui } 835ea6f9c2SChengming Gui 845ea6f9c2SChengming Gui /** 85edc61147SHawking Zhang * navi10_ih_enable_interrupts - Enable the interrupt ring buffer 86edc61147SHawking Zhang * 87edc61147SHawking Zhang * @adev: amdgpu_device pointer 88edc61147SHawking Zhang * 89edc61147SHawking Zhang * Enable the interrupt ring buffer (NAVI10). 90edc61147SHawking Zhang */ 91edc61147SHawking Zhang static void navi10_ih_enable_interrupts(struct amdgpu_device *adev) 92edc61147SHawking Zhang { 93edc61147SHawking Zhang u32 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL); 94edc61147SHawking Zhang 95edc61147SHawking Zhang ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 1); 96edc61147SHawking Zhang ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, ENABLE_INTR, 1); 97193cce34SAlex Sierra if (amdgpu_sriov_vf(adev) && adev->asic_type < CHIP_NAVI10) { 980ab176e6SAlex Sierra if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL, ih_rb_cntl)) { 990ab176e6SAlex Sierra DRM_ERROR("PSP program IH_RB_CNTL failed!\n"); 1000ab176e6SAlex Sierra return; 1010ab176e6SAlex Sierra } 1020ab176e6SAlex Sierra } else { 103edc61147SHawking Zhang WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL, ih_rb_cntl); 1040ab176e6SAlex Sierra } 1050ab176e6SAlex Sierra 106edc61147SHawking Zhang adev->irq.ih.enabled = true; 107ab518012SAlex Sierra 108ab518012SAlex Sierra if (adev->irq.ih1.ring_size) { 109ab518012SAlex Sierra ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1); 110ab518012SAlex Sierra ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING1, 111ab518012SAlex Sierra RB_ENABLE, 1); 112193cce34SAlex Sierra if (amdgpu_sriov_vf(adev) && adev->asic_type < CHIP_NAVI10) { 1130ab176e6SAlex Sierra if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL_RING1, 1140ab176e6SAlex Sierra ih_rb_cntl)) { 1150ab176e6SAlex Sierra DRM_ERROR("program IH_RB_CNTL_RING1 failed!\n"); 1160ab176e6SAlex Sierra return; 1170ab176e6SAlex Sierra } 1180ab176e6SAlex Sierra } else { 119ab518012SAlex Sierra WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1, ih_rb_cntl); 1200ab176e6SAlex Sierra } 121ab518012SAlex Sierra adev->irq.ih1.enabled = true; 122ab518012SAlex Sierra } 123ab518012SAlex Sierra 124ab518012SAlex Sierra if (adev->irq.ih2.ring_size) { 125ab518012SAlex Sierra ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2); 126ab518012SAlex Sierra ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING2, 127ab518012SAlex Sierra RB_ENABLE, 1); 128193cce34SAlex Sierra if (amdgpu_sriov_vf(adev) && adev->asic_type < CHIP_NAVI10) { 1290ab176e6SAlex Sierra if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL_RING2, 1300ab176e6SAlex Sierra ih_rb_cntl)) { 1310ab176e6SAlex Sierra DRM_ERROR("program IH_RB_CNTL_RING2 failed!\n"); 1320ab176e6SAlex Sierra return; 1330ab176e6SAlex Sierra } 1340ab176e6SAlex Sierra } else { 135ab518012SAlex Sierra WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2, ih_rb_cntl); 1360ab176e6SAlex Sierra } 137ab518012SAlex Sierra adev->irq.ih2.enabled = true; 138ab518012SAlex Sierra } 139d4581f7dSChristian König 140d4581f7dSChristian König if (adev->irq.ih_soft.ring_size) 141d4581f7dSChristian König adev->irq.ih_soft.enabled = true; 142edc61147SHawking Zhang } 143edc61147SHawking Zhang 144edc61147SHawking Zhang /** 145edc61147SHawking Zhang * navi10_ih_disable_interrupts - Disable the interrupt ring buffer 146edc61147SHawking Zhang * 147edc61147SHawking Zhang * @adev: amdgpu_device pointer 148edc61147SHawking Zhang * 149edc61147SHawking Zhang * Disable the interrupt ring buffer (NAVI10). 150edc61147SHawking Zhang */ 151edc61147SHawking Zhang static void navi10_ih_disable_interrupts(struct amdgpu_device *adev) 152edc61147SHawking Zhang { 153edc61147SHawking Zhang u32 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL); 154edc61147SHawking Zhang 155edc61147SHawking Zhang ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 0); 156edc61147SHawking Zhang ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, ENABLE_INTR, 0); 157193cce34SAlex Sierra if (amdgpu_sriov_vf(adev) && adev->asic_type < CHIP_NAVI10) { 1580ab176e6SAlex Sierra if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL, ih_rb_cntl)) { 1590ab176e6SAlex Sierra DRM_ERROR("PSP program IH_RB_CNTL failed!\n"); 1600ab176e6SAlex Sierra return; 1610ab176e6SAlex Sierra } 1620ab176e6SAlex Sierra } else { 163edc61147SHawking Zhang WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL, ih_rb_cntl); 1640ab176e6SAlex Sierra } 1650ab176e6SAlex Sierra 166edc61147SHawking Zhang /* set rptr, wptr to 0 */ 167edc61147SHawking Zhang WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR, 0); 168edc61147SHawking Zhang WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR, 0); 169edc61147SHawking Zhang adev->irq.ih.enabled = false; 170edc61147SHawking Zhang adev->irq.ih.rptr = 0; 171ab518012SAlex Sierra 172ab518012SAlex Sierra if (adev->irq.ih1.ring_size) { 173ab518012SAlex Sierra ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1); 174ab518012SAlex Sierra ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING1, 175ab518012SAlex Sierra RB_ENABLE, 0); 176193cce34SAlex Sierra if (amdgpu_sriov_vf(adev) && adev->asic_type < CHIP_NAVI10) { 1770ab176e6SAlex Sierra if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL_RING1, 1780ab176e6SAlex Sierra ih_rb_cntl)) { 1790ab176e6SAlex Sierra DRM_ERROR("program IH_RB_CNTL_RING1 failed!\n"); 1800ab176e6SAlex Sierra return; 1810ab176e6SAlex Sierra } 1820ab176e6SAlex Sierra } else { 183ab518012SAlex Sierra WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1, ih_rb_cntl); 1840ab176e6SAlex Sierra } 185ab518012SAlex Sierra /* set rptr, wptr to 0 */ 186ab518012SAlex Sierra WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR_RING1, 0); 187ab518012SAlex Sierra WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_RING1, 0); 188ab518012SAlex Sierra adev->irq.ih1.enabled = false; 189ab518012SAlex Sierra adev->irq.ih1.rptr = 0; 190ab518012SAlex Sierra } 191ab518012SAlex Sierra 192ab518012SAlex Sierra if (adev->irq.ih2.ring_size) { 193ab518012SAlex Sierra ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2); 194ab518012SAlex Sierra ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING2, 195ab518012SAlex Sierra RB_ENABLE, 0); 196193cce34SAlex Sierra if (amdgpu_sriov_vf(adev) && adev->asic_type < CHIP_NAVI10) { 1970ab176e6SAlex Sierra if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL_RING2, 1980ab176e6SAlex Sierra ih_rb_cntl)) { 1990ab176e6SAlex Sierra DRM_ERROR("program IH_RB_CNTL_RING2 failed!\n"); 2000ab176e6SAlex Sierra return; 2010ab176e6SAlex Sierra } 2020ab176e6SAlex Sierra } else { 203ab518012SAlex Sierra WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2, ih_rb_cntl); 2040ab176e6SAlex Sierra } 205ab518012SAlex Sierra /* set rptr, wptr to 0 */ 206ab518012SAlex Sierra WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR_RING2, 0); 207ab518012SAlex Sierra WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_RING2, 0); 208ab518012SAlex Sierra adev->irq.ih2.enabled = false; 209ab518012SAlex Sierra adev->irq.ih2.rptr = 0; 210ab518012SAlex Sierra } 211ab518012SAlex Sierra 212edc61147SHawking Zhang } 213edc61147SHawking Zhang 214edc61147SHawking Zhang static uint32_t navi10_ih_rb_cntl(struct amdgpu_ih_ring *ih, uint32_t ih_rb_cntl) 215edc61147SHawking Zhang { 216edc61147SHawking Zhang int rb_bufsz = order_base_2(ih->ring_size / 4); 217edc61147SHawking Zhang 218edc61147SHawking Zhang ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, 219edc61147SHawking Zhang MC_SPACE, ih->use_bus_addr ? 1 : 4); 220edc61147SHawking Zhang ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, 221edc61147SHawking Zhang WPTR_OVERFLOW_CLEAR, 1); 222edc61147SHawking Zhang ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, 223edc61147SHawking Zhang WPTR_OVERFLOW_ENABLE, 1); 224edc61147SHawking Zhang ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_SIZE, rb_bufsz); 225edc61147SHawking Zhang /* Ring Buffer write pointer writeback. If enabled, IH_RB_WPTR register 226edc61147SHawking Zhang * value is written to memory 227edc61147SHawking Zhang */ 228edc61147SHawking Zhang ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, 229edc61147SHawking Zhang WPTR_WRITEBACK_ENABLE, 1); 230edc61147SHawking Zhang ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_SNOOP, 1); 231edc61147SHawking Zhang ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_RO, 0); 232edc61147SHawking Zhang ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_VMID, 0); 233edc61147SHawking Zhang 234edc61147SHawking Zhang return ih_rb_cntl; 235edc61147SHawking Zhang } 236edc61147SHawking Zhang 237ab518012SAlex Sierra static uint32_t navi10_ih_doorbell_rptr(struct amdgpu_ih_ring *ih) 238ab518012SAlex Sierra { 239ab518012SAlex Sierra u32 ih_doorbell_rtpr = 0; 240ab518012SAlex Sierra 241ab518012SAlex Sierra if (ih->use_doorbell) { 242ab518012SAlex Sierra ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr, 243ab518012SAlex Sierra IH_DOORBELL_RPTR, OFFSET, 244ab518012SAlex Sierra ih->doorbell_index); 245ab518012SAlex Sierra ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr, 246ab518012SAlex Sierra IH_DOORBELL_RPTR, 247ab518012SAlex Sierra ENABLE, 1); 248ab518012SAlex Sierra } else { 249ab518012SAlex Sierra ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr, 250ab518012SAlex Sierra IH_DOORBELL_RPTR, 251ab518012SAlex Sierra ENABLE, 0); 252ab518012SAlex Sierra } 253ab518012SAlex Sierra return ih_doorbell_rtpr; 254ab518012SAlex Sierra } 255ab518012SAlex Sierra 2569e94ff33SAlex Sierra static void navi10_ih_reroute_ih(struct amdgpu_device *adev) 2579e94ff33SAlex Sierra { 2589e94ff33SAlex Sierra uint32_t tmp; 2599e94ff33SAlex Sierra 2609e94ff33SAlex Sierra /* Reroute to IH ring 1 for VMC */ 2619e94ff33SAlex Sierra WREG32_SOC15(OSSSYS, 0, mmIH_CLIENT_CFG_INDEX, 0x12); 2629e94ff33SAlex Sierra tmp = RREG32_SOC15(OSSSYS, 0, mmIH_CLIENT_CFG_DATA); 2639e94ff33SAlex Sierra tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, CLIENT_TYPE, 1); 2649e94ff33SAlex Sierra tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, RING_ID, 1); 2659e94ff33SAlex Sierra WREG32_SOC15(OSSSYS, 0, mmIH_CLIENT_CFG_DATA, tmp); 2669e94ff33SAlex Sierra 2679e94ff33SAlex Sierra /* Reroute IH ring 1 for UMC */ 2689e94ff33SAlex Sierra WREG32_SOC15(OSSSYS, 0, mmIH_CLIENT_CFG_INDEX, 0x1B); 2699e94ff33SAlex Sierra tmp = RREG32_SOC15(OSSSYS, 0, mmIH_CLIENT_CFG_DATA); 2709e94ff33SAlex Sierra tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, RING_ID, 1); 2719e94ff33SAlex Sierra WREG32_SOC15(OSSSYS, 0, mmIH_CLIENT_CFG_DATA, tmp); 2729e94ff33SAlex Sierra } 2739e94ff33SAlex Sierra 274edc61147SHawking Zhang /** 275edc61147SHawking Zhang * navi10_ih_irq_init - init and enable the interrupt ring 276edc61147SHawking Zhang * 277edc61147SHawking Zhang * @adev: amdgpu_device pointer 278edc61147SHawking Zhang * 279edc61147SHawking Zhang * Allocate a ring buffer for the interrupt controller, 280edc61147SHawking Zhang * enable the RLC, disable interrupts, enable the IH 281edc61147SHawking Zhang * ring buffer and enable it (NAVI). 282edc61147SHawking Zhang * Called at device load and reume. 283edc61147SHawking Zhang * Returns 0 for success, errors for failure. 284edc61147SHawking Zhang */ 285edc61147SHawking Zhang static int navi10_ih_irq_init(struct amdgpu_device *adev) 286edc61147SHawking Zhang { 287edc61147SHawking Zhang struct amdgpu_ih_ring *ih = &adev->irq.ih; 288ab518012SAlex Sierra u32 ih_rb_cntl, ih_chicken; 289edc61147SHawking Zhang u32 tmp; 290edc61147SHawking Zhang 291edc61147SHawking Zhang /* disable irqs */ 292edc61147SHawking Zhang navi10_ih_disable_interrupts(adev); 293edc61147SHawking Zhang 294bebc0762SHawking Zhang adev->nbio.funcs->ih_control(adev); 295edc61147SHawking Zhang 296edc61147SHawking Zhang /* Ring Buffer base. [39:8] of 40-bit address of the beginning of the ring buffer*/ 297edc61147SHawking Zhang WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE, ih->gpu_addr >> 8); 298edc61147SHawking Zhang WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE_HI, (ih->gpu_addr >> 40) & 0xff); 299edc61147SHawking Zhang 300edc61147SHawking Zhang ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL); 301edc61147SHawking Zhang ih_rb_cntl = navi10_ih_rb_cntl(ih, ih_rb_cntl); 302edc61147SHawking Zhang ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RPTR_REARM, 303edc61147SHawking Zhang !!adev->irq.msi_enabled); 304193cce34SAlex Sierra if (amdgpu_sriov_vf(adev) && adev->asic_type < CHIP_NAVI10) { 3050ab176e6SAlex Sierra if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL, ih_rb_cntl)) { 3060ab176e6SAlex Sierra DRM_ERROR("PSP program IH_RB_CNTL failed!\n"); 3070ab176e6SAlex Sierra return -ETIMEDOUT; 3080ab176e6SAlex Sierra } 3090ab176e6SAlex Sierra } else { 3100ab176e6SAlex Sierra WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL, ih_rb_cntl); 3110ab176e6SAlex Sierra } 312abb6fccbSAlex Sierra if (adev->irq.ih1.ring_size) 3139e94ff33SAlex Sierra navi10_ih_reroute_ih(adev); 314edc61147SHawking Zhang 315edc61147SHawking Zhang if (unlikely(adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT)) { 316edc61147SHawking Zhang if (ih->use_bus_addr) { 317757b3af8SLikun Gao switch (adev->asic_type) { 318757b3af8SLikun Gao case CHIP_SIENNA_CICHLID: 319026c396bSJiansong Chen case CHIP_NAVY_FLOUNDER: 320bd4f2811SHuang Rui case CHIP_VANGOGH: 321771cc67eSTao Zhou case CHIP_DIMGREY_CAVEFISH: 322757b3af8SLikun Gao ih_chicken = RREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN_Sienna_Cichlid); 323757b3af8SLikun Gao ih_chicken = REG_SET_FIELD(ih_chicken, 324757b3af8SLikun Gao IH_CHICKEN, MC_SPACE_GPA_ENABLE, 1); 325757b3af8SLikun Gao WREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN_Sienna_Cichlid, ih_chicken); 326757b3af8SLikun Gao break; 327757b3af8SLikun Gao default: 328edc61147SHawking Zhang ih_chicken = RREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN); 329edc61147SHawking Zhang ih_chicken = REG_SET_FIELD(ih_chicken, 330edc61147SHawking Zhang IH_CHICKEN, MC_SPACE_GPA_ENABLE, 1); 331edc61147SHawking Zhang WREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN, ih_chicken); 332757b3af8SLikun Gao break; 333757b3af8SLikun Gao } 334edc61147SHawking Zhang } 335edc61147SHawking Zhang } 336edc61147SHawking Zhang 337edc61147SHawking Zhang /* set the writeback address whether it's enabled or not */ 338edc61147SHawking Zhang WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_ADDR_LO, 339edc61147SHawking Zhang lower_32_bits(ih->wptr_addr)); 340edc61147SHawking Zhang WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_ADDR_HI, 341edc61147SHawking Zhang upper_32_bits(ih->wptr_addr) & 0xFFFF); 342edc61147SHawking Zhang 343edc61147SHawking Zhang /* set rptr, wptr to 0 */ 344edc61147SHawking Zhang WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR, 0); 345edc61147SHawking Zhang WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR, 0); 346edc61147SHawking Zhang 347ab518012SAlex Sierra WREG32_SOC15(OSSSYS, 0, mmIH_DOORBELL_RPTR, 348ab518012SAlex Sierra navi10_ih_doorbell_rptr(ih)); 349edc61147SHawking Zhang 350bebc0762SHawking Zhang adev->nbio.funcs->ih_doorbell_range(adev, ih->use_doorbell, 351edc61147SHawking Zhang ih->doorbell_index); 352edc61147SHawking Zhang 353ab518012SAlex Sierra ih = &adev->irq.ih1; 354ab518012SAlex Sierra if (ih->ring_size) { 355ab518012SAlex Sierra WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE_RING1, ih->gpu_addr >> 8); 356ab518012SAlex Sierra WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE_HI_RING1, 357ab518012SAlex Sierra (ih->gpu_addr >> 40) & 0xff); 358ab518012SAlex Sierra 359ab518012SAlex Sierra ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1); 360ab518012SAlex Sierra ih_rb_cntl = navi10_ih_rb_cntl(ih, ih_rb_cntl); 361ab518012SAlex Sierra ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, 362ab518012SAlex Sierra WPTR_OVERFLOW_ENABLE, 0); 363ab518012SAlex Sierra ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, 364ab518012SAlex Sierra RB_FULL_DRAIN_ENABLE, 1); 365193cce34SAlex Sierra if (amdgpu_sriov_vf(adev) && adev->asic_type < CHIP_NAVI10) { 3660ab176e6SAlex Sierra if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL_RING1, 3670ab176e6SAlex Sierra ih_rb_cntl)) { 3680ab176e6SAlex Sierra DRM_ERROR("program IH_RB_CNTL_RING1 failed!\n"); 3690ab176e6SAlex Sierra return -ETIMEDOUT; 3700ab176e6SAlex Sierra } 3710ab176e6SAlex Sierra } else { 372ab518012SAlex Sierra WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1, ih_rb_cntl); 3730ab176e6SAlex Sierra } 374ab518012SAlex Sierra /* set rptr, wptr to 0 */ 375ab518012SAlex Sierra WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_RING1, 0); 376ab518012SAlex Sierra WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR_RING1, 0); 377ab518012SAlex Sierra 378ab518012SAlex Sierra WREG32_SOC15(OSSSYS, 0, mmIH_DOORBELL_RPTR_RING1, 379ab518012SAlex Sierra navi10_ih_doorbell_rptr(ih)); 380ab518012SAlex Sierra } 381ab518012SAlex Sierra 382ab518012SAlex Sierra ih = &adev->irq.ih2; 383ab518012SAlex Sierra if (ih->ring_size) { 384ab518012SAlex Sierra WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE_RING2, ih->gpu_addr >> 8); 385ab518012SAlex Sierra WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE_HI_RING2, 386ab518012SAlex Sierra (ih->gpu_addr >> 40) & 0xff); 387ab518012SAlex Sierra 388ab518012SAlex Sierra ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2); 389ab518012SAlex Sierra ih_rb_cntl = navi10_ih_rb_cntl(ih, ih_rb_cntl); 390ab518012SAlex Sierra 391193cce34SAlex Sierra if (amdgpu_sriov_vf(adev) && adev->asic_type < CHIP_NAVI10) { 3920ab176e6SAlex Sierra if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL_RING2, 3930ab176e6SAlex Sierra ih_rb_cntl)) { 3940ab176e6SAlex Sierra DRM_ERROR("program IH_RB_CNTL_RING2 failed!\n"); 3950ab176e6SAlex Sierra return -ETIMEDOUT; 3960ab176e6SAlex Sierra } 3970ab176e6SAlex Sierra } else { 398ab518012SAlex Sierra WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2, ih_rb_cntl); 3990ab176e6SAlex Sierra } 400ab518012SAlex Sierra /* set rptr, wptr to 0 */ 401ab518012SAlex Sierra WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_RING2, 0); 402ab518012SAlex Sierra WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR_RING2, 0); 403ab518012SAlex Sierra 404ab518012SAlex Sierra WREG32_SOC15(OSSSYS, 0, mmIH_DOORBELL_RPTR_RING2, 405ab518012SAlex Sierra navi10_ih_doorbell_rptr(ih)); 406ab518012SAlex Sierra } 407ab518012SAlex Sierra 408ab518012SAlex Sierra 409edc61147SHawking Zhang tmp = RREG32_SOC15(OSSSYS, 0, mmIH_STORM_CLIENT_LIST_CNTL); 410edc61147SHawking Zhang tmp = REG_SET_FIELD(tmp, IH_STORM_CLIENT_LIST_CNTL, 411edc61147SHawking Zhang CLIENT18_IS_STORM_CLIENT, 1); 412edc61147SHawking Zhang WREG32_SOC15(OSSSYS, 0, mmIH_STORM_CLIENT_LIST_CNTL, tmp); 413edc61147SHawking Zhang 414edc61147SHawking Zhang tmp = RREG32_SOC15(OSSSYS, 0, mmIH_INT_FLOOD_CNTL); 415edc61147SHawking Zhang tmp = REG_SET_FIELD(tmp, IH_INT_FLOOD_CNTL, FLOOD_CNTL_ENABLE, 1); 416edc61147SHawking Zhang WREG32_SOC15(OSSSYS, 0, mmIH_INT_FLOOD_CNTL, tmp); 417edc61147SHawking Zhang 418edc61147SHawking Zhang pci_set_master(adev->pdev); 419edc61147SHawking Zhang 420edc61147SHawking Zhang /* enable interrupts */ 421edc61147SHawking Zhang navi10_ih_enable_interrupts(adev); 4225ea6f9c2SChengming Gui /* enable wptr force update for self int */ 4235ea6f9c2SChengming Gui force_update_wptr_for_self_int(adev, 0, 8, true); 424edc61147SHawking Zhang 4257eca4006SMa Feng return 0; 426edc61147SHawking Zhang } 427edc61147SHawking Zhang 428edc61147SHawking Zhang /** 429edc61147SHawking Zhang * navi10_ih_irq_disable - disable interrupts 430edc61147SHawking Zhang * 431edc61147SHawking Zhang * @adev: amdgpu_device pointer 432edc61147SHawking Zhang * 433edc61147SHawking Zhang * Disable interrupts on the hw (NAVI10). 434edc61147SHawking Zhang */ 435edc61147SHawking Zhang static void navi10_ih_irq_disable(struct amdgpu_device *adev) 436edc61147SHawking Zhang { 4375ea6f9c2SChengming Gui force_update_wptr_for_self_int(adev, 0, 8, false); 438edc61147SHawking Zhang navi10_ih_disable_interrupts(adev); 439edc61147SHawking Zhang 440edc61147SHawking Zhang /* Wait and acknowledge irq */ 441edc61147SHawking Zhang mdelay(1); 442edc61147SHawking Zhang } 443edc61147SHawking Zhang 444edc61147SHawking Zhang /** 445edc61147SHawking Zhang * navi10_ih_get_wptr - get the IH ring buffer wptr 446edc61147SHawking Zhang * 447edc61147SHawking Zhang * @adev: amdgpu_device pointer 448*c56fb081SLee Jones * @ih: IH ring buffer to fetch wptr 449edc61147SHawking Zhang * 450edc61147SHawking Zhang * Get the IH ring buffer wptr from either the register 451edc61147SHawking Zhang * or the writeback memory buffer (NAVI10). Also check for 452edc61147SHawking Zhang * ring buffer overflow and deal with it. 453edc61147SHawking Zhang * Returns the value of the wptr. 454edc61147SHawking Zhang */ 455edc61147SHawking Zhang static u32 navi10_ih_get_wptr(struct amdgpu_device *adev, 456edc61147SHawking Zhang struct amdgpu_ih_ring *ih) 457edc61147SHawking Zhang { 458edc61147SHawking Zhang u32 wptr, reg, tmp; 459edc61147SHawking Zhang 460edc61147SHawking Zhang wptr = le32_to_cpu(*ih->wptr_cpu); 461edc61147SHawking Zhang 462edc61147SHawking Zhang if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) 463edc61147SHawking Zhang goto out; 464edc61147SHawking Zhang 465ab518012SAlex Sierra if (ih == &adev->irq.ih) 466edc61147SHawking Zhang reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR); 467ab518012SAlex Sierra else if (ih == &adev->irq.ih1) 468ab518012SAlex Sierra reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_RING1); 469ab518012SAlex Sierra else if (ih == &adev->irq.ih2) 470ab518012SAlex Sierra reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_RING2); 471ab518012SAlex Sierra else 472ab518012SAlex Sierra BUG(); 473ab518012SAlex Sierra 474edc61147SHawking Zhang wptr = RREG32_NO_KIQ(reg); 475edc61147SHawking Zhang if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) 476edc61147SHawking Zhang goto out; 477edc61147SHawking Zhang wptr = REG_SET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW, 0); 478edc61147SHawking Zhang 479edc61147SHawking Zhang /* When a ring buffer overflow happen start parsing interrupt 480edc61147SHawking Zhang * from the last not overwritten vector (wptr + 32). Hopefully 481edc61147SHawking Zhang * this should allow us to catch up. 482edc61147SHawking Zhang */ 483edc61147SHawking Zhang tmp = (wptr + 32) & ih->ptr_mask; 484edc61147SHawking Zhang dev_warn(adev->dev, "IH ring buffer overflow " 485edc61147SHawking Zhang "(0x%08X, 0x%08X, 0x%08X)\n", 486edc61147SHawking Zhang wptr, ih->rptr, tmp); 487edc61147SHawking Zhang ih->rptr = tmp; 488edc61147SHawking Zhang 489ab518012SAlex Sierra if (ih == &adev->irq.ih) 490edc61147SHawking Zhang reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL); 491ab518012SAlex Sierra else if (ih == &adev->irq.ih1) 492ab518012SAlex Sierra reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL_RING1); 493ab518012SAlex Sierra else if (ih == &adev->irq.ih2) 494ab518012SAlex Sierra reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL_RING2); 495ab518012SAlex Sierra else 496ab518012SAlex Sierra BUG(); 497ab518012SAlex Sierra 498edc61147SHawking Zhang tmp = RREG32_NO_KIQ(reg); 499edc61147SHawking Zhang tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1); 500edc61147SHawking Zhang WREG32_NO_KIQ(reg, tmp); 501edc61147SHawking Zhang out: 502edc61147SHawking Zhang return (wptr & ih->ptr_mask); 503edc61147SHawking Zhang } 504edc61147SHawking Zhang 505edc61147SHawking Zhang /** 506edc61147SHawking Zhang * navi10_ih_decode_iv - decode an interrupt vector 507edc61147SHawking Zhang * 508edc61147SHawking Zhang * @adev: amdgpu_device pointer 509*c56fb081SLee Jones * @ih: IH ring buffer to decode 510*c56fb081SLee Jones * @entry: IV entry to place decoded information into 511edc61147SHawking Zhang * 512edc61147SHawking Zhang * Decodes the interrupt vector at the current rptr 513edc61147SHawking Zhang * position and also advance the position. 514edc61147SHawking Zhang */ 515edc61147SHawking Zhang static void navi10_ih_decode_iv(struct amdgpu_device *adev, 516edc61147SHawking Zhang struct amdgpu_ih_ring *ih, 517edc61147SHawking Zhang struct amdgpu_iv_entry *entry) 518edc61147SHawking Zhang { 519edc61147SHawking Zhang /* wptr/rptr are in bytes! */ 520edc61147SHawking Zhang u32 ring_index = ih->rptr >> 2; 521edc61147SHawking Zhang uint32_t dw[8]; 522edc61147SHawking Zhang 523edc61147SHawking Zhang dw[0] = le32_to_cpu(ih->ring[ring_index + 0]); 524edc61147SHawking Zhang dw[1] = le32_to_cpu(ih->ring[ring_index + 1]); 525edc61147SHawking Zhang dw[2] = le32_to_cpu(ih->ring[ring_index + 2]); 526edc61147SHawking Zhang dw[3] = le32_to_cpu(ih->ring[ring_index + 3]); 527edc61147SHawking Zhang dw[4] = le32_to_cpu(ih->ring[ring_index + 4]); 528edc61147SHawking Zhang dw[5] = le32_to_cpu(ih->ring[ring_index + 5]); 529edc61147SHawking Zhang dw[6] = le32_to_cpu(ih->ring[ring_index + 6]); 530edc61147SHawking Zhang dw[7] = le32_to_cpu(ih->ring[ring_index + 7]); 531edc61147SHawking Zhang 532edc61147SHawking Zhang entry->client_id = dw[0] & 0xff; 533edc61147SHawking Zhang entry->src_id = (dw[0] >> 8) & 0xff; 534edc61147SHawking Zhang entry->ring_id = (dw[0] >> 16) & 0xff; 535edc61147SHawking Zhang entry->vmid = (dw[0] >> 24) & 0xf; 536edc61147SHawking Zhang entry->vmid_src = (dw[0] >> 31); 537edc61147SHawking Zhang entry->timestamp = dw[1] | ((u64)(dw[2] & 0xffff) << 32); 538edc61147SHawking Zhang entry->timestamp_src = dw[2] >> 31; 539edc61147SHawking Zhang entry->pasid = dw[3] & 0xffff; 540edc61147SHawking Zhang entry->pasid_src = dw[3] >> 31; 541edc61147SHawking Zhang entry->src_data[0] = dw[4]; 542edc61147SHawking Zhang entry->src_data[1] = dw[5]; 543edc61147SHawking Zhang entry->src_data[2] = dw[6]; 544edc61147SHawking Zhang entry->src_data[3] = dw[7]; 545edc61147SHawking Zhang 546edc61147SHawking Zhang /* wptr/rptr are in bytes! */ 547edc61147SHawking Zhang ih->rptr += 32; 548edc61147SHawking Zhang } 549edc61147SHawking Zhang 550edc61147SHawking Zhang /** 551022b6518SSamir Dhume * navi10_ih_irq_rearm - rearm IRQ if lost 552022b6518SSamir Dhume * 553022b6518SSamir Dhume * @adev: amdgpu_device pointer 554*c56fb081SLee Jones * @ih: IH ring to match 555022b6518SSamir Dhume * 556022b6518SSamir Dhume */ 557022b6518SSamir Dhume static void navi10_ih_irq_rearm(struct amdgpu_device *adev, 558022b6518SSamir Dhume struct amdgpu_ih_ring *ih) 559022b6518SSamir Dhume { 560022b6518SSamir Dhume uint32_t reg_rptr = 0; 561022b6518SSamir Dhume uint32_t v = 0; 562022b6518SSamir Dhume uint32_t i = 0; 563022b6518SSamir Dhume 564022b6518SSamir Dhume if (ih == &adev->irq.ih) 565022b6518SSamir Dhume reg_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR); 566022b6518SSamir Dhume else if (ih == &adev->irq.ih1) 567022b6518SSamir Dhume reg_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR_RING1); 568022b6518SSamir Dhume else if (ih == &adev->irq.ih2) 569022b6518SSamir Dhume reg_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR_RING2); 570022b6518SSamir Dhume else 571022b6518SSamir Dhume return; 572022b6518SSamir Dhume 573022b6518SSamir Dhume /* Rearm IRQ / re-write doorbell if doorbell write is lost */ 574022b6518SSamir Dhume for (i = 0; i < MAX_REARM_RETRY; i++) { 575022b6518SSamir Dhume v = RREG32_NO_KIQ(reg_rptr); 576022b6518SSamir Dhume if ((v < ih->ring_size) && (v != ih->rptr)) 577022b6518SSamir Dhume WDOORBELL32(ih->doorbell_index, ih->rptr); 578022b6518SSamir Dhume else 579022b6518SSamir Dhume break; 580022b6518SSamir Dhume } 581022b6518SSamir Dhume } 582022b6518SSamir Dhume 583022b6518SSamir Dhume /** 584edc61147SHawking Zhang * navi10_ih_set_rptr - set the IH ring buffer rptr 585edc61147SHawking Zhang * 586edc61147SHawking Zhang * @adev: amdgpu_device pointer 587edc61147SHawking Zhang * 588*c56fb081SLee Jones * @ih: IH ring buffer to set rptr 589edc61147SHawking Zhang * Set the IH ring buffer rptr. 590edc61147SHawking Zhang */ 591edc61147SHawking Zhang static void navi10_ih_set_rptr(struct amdgpu_device *adev, 592edc61147SHawking Zhang struct amdgpu_ih_ring *ih) 593edc61147SHawking Zhang { 594edc61147SHawking Zhang if (ih->use_doorbell) { 595edc61147SHawking Zhang /* XXX check if swapping is necessary on BE */ 596edc61147SHawking Zhang *ih->rptr_cpu = ih->rptr; 597edc61147SHawking Zhang WDOORBELL32(ih->doorbell_index, ih->rptr); 598022b6518SSamir Dhume 599022b6518SSamir Dhume if (amdgpu_sriov_vf(adev)) 600022b6518SSamir Dhume navi10_ih_irq_rearm(adev, ih); 601ab518012SAlex Sierra } else if (ih == &adev->irq.ih) { 602edc61147SHawking Zhang WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR, ih->rptr); 603ab518012SAlex Sierra } else if (ih == &adev->irq.ih1) { 604ab518012SAlex Sierra WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR_RING1, ih->rptr); 605ab518012SAlex Sierra } else if (ih == &adev->irq.ih2) { 606ab518012SAlex Sierra WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR_RING2, ih->rptr); 607ab518012SAlex Sierra } 608ab518012SAlex Sierra } 609ab518012SAlex Sierra 610ab518012SAlex Sierra /** 611ab518012SAlex Sierra * navi10_ih_self_irq - dispatch work for ring 1 and 2 612ab518012SAlex Sierra * 613ab518012SAlex Sierra * @adev: amdgpu_device pointer 614ab518012SAlex Sierra * @source: irq source 615ab518012SAlex Sierra * @entry: IV with WPTR update 616ab518012SAlex Sierra * 617ab518012SAlex Sierra * Update the WPTR from the IV and schedule work to handle the entries. 618ab518012SAlex Sierra */ 619ab518012SAlex Sierra static int navi10_ih_self_irq(struct amdgpu_device *adev, 620ab518012SAlex Sierra struct amdgpu_irq_src *source, 621ab518012SAlex Sierra struct amdgpu_iv_entry *entry) 622ab518012SAlex Sierra { 623ab518012SAlex Sierra uint32_t wptr = cpu_to_le32(entry->src_data[0]); 624ab518012SAlex Sierra 625ab518012SAlex Sierra switch (entry->ring_id) { 626ab518012SAlex Sierra case 1: 627ab518012SAlex Sierra *adev->irq.ih1.wptr_cpu = wptr; 628ab518012SAlex Sierra schedule_work(&adev->irq.ih1_work); 629ab518012SAlex Sierra break; 630ab518012SAlex Sierra case 2: 631ab518012SAlex Sierra *adev->irq.ih2.wptr_cpu = wptr; 632ab518012SAlex Sierra schedule_work(&adev->irq.ih2_work); 633ab518012SAlex Sierra break; 634ab518012SAlex Sierra default: break; 635ab518012SAlex Sierra } 636ab518012SAlex Sierra return 0; 637ab518012SAlex Sierra } 638ab518012SAlex Sierra 639ab518012SAlex Sierra static const struct amdgpu_irq_src_funcs navi10_ih_self_irq_funcs = { 640ab518012SAlex Sierra .process = navi10_ih_self_irq, 641ab518012SAlex Sierra }; 642ab518012SAlex Sierra 643ab518012SAlex Sierra static void navi10_ih_set_self_irq_funcs(struct amdgpu_device *adev) 644ab518012SAlex Sierra { 645ab518012SAlex Sierra adev->irq.self_irq.num_types = 0; 646ab518012SAlex Sierra adev->irq.self_irq.funcs = &navi10_ih_self_irq_funcs; 647edc61147SHawking Zhang } 648edc61147SHawking Zhang 649edc61147SHawking Zhang static int navi10_ih_early_init(void *handle) 650edc61147SHawking Zhang { 651edc61147SHawking Zhang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 652edc61147SHawking Zhang 653edc61147SHawking Zhang navi10_ih_set_interrupt_funcs(adev); 654ab518012SAlex Sierra navi10_ih_set_self_irq_funcs(adev); 655edc61147SHawking Zhang return 0; 656edc61147SHawking Zhang } 657edc61147SHawking Zhang 658edc61147SHawking Zhang static int navi10_ih_sw_init(void *handle) 659edc61147SHawking Zhang { 660edc61147SHawking Zhang int r; 661edc61147SHawking Zhang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 662edc61147SHawking Zhang bool use_bus_addr; 663edc61147SHawking Zhang 664ab518012SAlex Sierra r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_IH, 0, 665ab518012SAlex Sierra &adev->irq.self_irq); 666ab518012SAlex Sierra 667ab518012SAlex Sierra if (r) 668ab518012SAlex Sierra return r; 669ab518012SAlex Sierra 670edc61147SHawking Zhang /* use gpu virtual address for ih ring 671edc61147SHawking Zhang * until ih_checken is programmed to allow 672edc61147SHawking Zhang * use bus address for ih ring by psp bl */ 673bf13cb1fSHuang Rui if ((adev->flags & AMD_IS_APU) || 674bf13cb1fSHuang Rui (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) 675bf13cb1fSHuang Rui use_bus_addr = false; 676bf13cb1fSHuang Rui else 677bf13cb1fSHuang Rui use_bus_addr = true; 678edc61147SHawking Zhang r = amdgpu_ih_ring_init(adev, &adev->irq.ih, 256 * 1024, use_bus_addr); 679edc61147SHawking Zhang if (r) 680edc61147SHawking Zhang return r; 681edc61147SHawking Zhang 682edc61147SHawking Zhang adev->irq.ih.use_doorbell = true; 683edc61147SHawking Zhang adev->irq.ih.doorbell_index = adev->doorbell_index.ih << 1; 684edc61147SHawking Zhang 685abb6fccbSAlex Sierra adev->irq.ih1.ring_size = 0; 686abb6fccbSAlex Sierra adev->irq.ih2.ring_size = 0; 687abb6fccbSAlex Sierra 688abb6fccbSAlex Sierra if (adev->asic_type < CHIP_NAVI10) { 689ab518012SAlex Sierra r = amdgpu_ih_ring_init(adev, &adev->irq.ih1, PAGE_SIZE, true); 690ab518012SAlex Sierra if (r) 691ab518012SAlex Sierra return r; 692ab518012SAlex Sierra 693ab518012SAlex Sierra adev->irq.ih1.use_doorbell = true; 694abb6fccbSAlex Sierra adev->irq.ih1.doorbell_index = 695abb6fccbSAlex Sierra (adev->doorbell_index.ih + 1) << 1; 696ab518012SAlex Sierra 697ab518012SAlex Sierra r = amdgpu_ih_ring_init(adev, &adev->irq.ih2, PAGE_SIZE, true); 698ab518012SAlex Sierra if (r) 699ab518012SAlex Sierra return r; 700ab518012SAlex Sierra 701ab518012SAlex Sierra adev->irq.ih2.use_doorbell = true; 702abb6fccbSAlex Sierra adev->irq.ih2.doorbell_index = 703abb6fccbSAlex Sierra (adev->doorbell_index.ih + 2) << 1; 704abb6fccbSAlex Sierra } 705ab518012SAlex Sierra 706d4581f7dSChristian König r = amdgpu_ih_ring_init(adev, &adev->irq.ih_soft, PAGE_SIZE, true); 707d4581f7dSChristian König if (r) 708d4581f7dSChristian König return r; 709d4581f7dSChristian König 710edc61147SHawking Zhang r = amdgpu_irq_init(adev); 711edc61147SHawking Zhang 712edc61147SHawking Zhang return r; 713edc61147SHawking Zhang } 714edc61147SHawking Zhang 715edc61147SHawking Zhang static int navi10_ih_sw_fini(void *handle) 716edc61147SHawking Zhang { 717edc61147SHawking Zhang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 718edc61147SHawking Zhang 719edc61147SHawking Zhang amdgpu_irq_fini(adev); 720ab518012SAlex Sierra amdgpu_ih_ring_fini(adev, &adev->irq.ih2); 721ab518012SAlex Sierra amdgpu_ih_ring_fini(adev, &adev->irq.ih1); 722edc61147SHawking Zhang amdgpu_ih_ring_fini(adev, &adev->irq.ih); 723edc61147SHawking Zhang 724edc61147SHawking Zhang return 0; 725edc61147SHawking Zhang } 726edc61147SHawking Zhang 727edc61147SHawking Zhang static int navi10_ih_hw_init(void *handle) 728edc61147SHawking Zhang { 729edc61147SHawking Zhang int r; 730edc61147SHawking Zhang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 731edc61147SHawking Zhang 732edc61147SHawking Zhang r = navi10_ih_irq_init(adev); 733edc61147SHawking Zhang if (r) 734edc61147SHawking Zhang return r; 735edc61147SHawking Zhang 736edc61147SHawking Zhang return 0; 737edc61147SHawking Zhang } 738edc61147SHawking Zhang 739edc61147SHawking Zhang static int navi10_ih_hw_fini(void *handle) 740edc61147SHawking Zhang { 741edc61147SHawking Zhang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 742edc61147SHawking Zhang 743edc61147SHawking Zhang navi10_ih_irq_disable(adev); 744edc61147SHawking Zhang 745edc61147SHawking Zhang return 0; 746edc61147SHawking Zhang } 747edc61147SHawking Zhang 748edc61147SHawking Zhang static int navi10_ih_suspend(void *handle) 749edc61147SHawking Zhang { 750edc61147SHawking Zhang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 751edc61147SHawking Zhang 752edc61147SHawking Zhang return navi10_ih_hw_fini(adev); 753edc61147SHawking Zhang } 754edc61147SHawking Zhang 755edc61147SHawking Zhang static int navi10_ih_resume(void *handle) 756edc61147SHawking Zhang { 757edc61147SHawking Zhang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 758edc61147SHawking Zhang 759edc61147SHawking Zhang return navi10_ih_hw_init(adev); 760edc61147SHawking Zhang } 761edc61147SHawking Zhang 762edc61147SHawking Zhang static bool navi10_ih_is_idle(void *handle) 763edc61147SHawking Zhang { 764edc61147SHawking Zhang /* todo */ 765edc61147SHawking Zhang return true; 766edc61147SHawking Zhang } 767edc61147SHawking Zhang 768edc61147SHawking Zhang static int navi10_ih_wait_for_idle(void *handle) 769edc61147SHawking Zhang { 770edc61147SHawking Zhang /* todo */ 771edc61147SHawking Zhang return -ETIMEDOUT; 772edc61147SHawking Zhang } 773edc61147SHawking Zhang 774edc61147SHawking Zhang static int navi10_ih_soft_reset(void *handle) 775edc61147SHawking Zhang { 776edc61147SHawking Zhang /* todo */ 777edc61147SHawking Zhang return 0; 778edc61147SHawking Zhang } 779edc61147SHawking Zhang 780edc61147SHawking Zhang static void navi10_ih_update_clockgating_state(struct amdgpu_device *adev, 781edc61147SHawking Zhang bool enable) 782edc61147SHawking Zhang { 783edc61147SHawking Zhang uint32_t data, def, field_val; 784edc61147SHawking Zhang 785edc61147SHawking Zhang if (adev->cg_flags & AMD_CG_SUPPORT_IH_CG) { 786edc61147SHawking Zhang def = data = RREG32_SOC15(OSSSYS, 0, mmIH_CLK_CTRL); 787edc61147SHawking Zhang field_val = enable ? 0 : 1; 788edc61147SHawking Zhang data = REG_SET_FIELD(data, IH_CLK_CTRL, 789edc61147SHawking Zhang DBUS_MUX_CLK_SOFT_OVERRIDE, field_val); 790edc61147SHawking Zhang data = REG_SET_FIELD(data, IH_CLK_CTRL, 791edc61147SHawking Zhang OSSSYS_SHARE_CLK_SOFT_OVERRIDE, field_val); 792edc61147SHawking Zhang data = REG_SET_FIELD(data, IH_CLK_CTRL, 793edc61147SHawking Zhang LIMIT_SMN_CLK_SOFT_OVERRIDE, field_val); 794edc61147SHawking Zhang data = REG_SET_FIELD(data, IH_CLK_CTRL, 795edc61147SHawking Zhang DYN_CLK_SOFT_OVERRIDE, field_val); 796edc61147SHawking Zhang data = REG_SET_FIELD(data, IH_CLK_CTRL, 797edc61147SHawking Zhang REG_CLK_SOFT_OVERRIDE, field_val); 798edc61147SHawking Zhang if (def != data) 799edc61147SHawking Zhang WREG32_SOC15(OSSSYS, 0, mmIH_CLK_CTRL, data); 800edc61147SHawking Zhang } 801edc61147SHawking Zhang 802edc61147SHawking Zhang return; 803edc61147SHawking Zhang } 804edc61147SHawking Zhang 805edc61147SHawking Zhang static int navi10_ih_set_clockgating_state(void *handle, 806edc61147SHawking Zhang enum amd_clockgating_state state) 807edc61147SHawking Zhang { 808edc61147SHawking Zhang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 809edc61147SHawking Zhang 810edc61147SHawking Zhang navi10_ih_update_clockgating_state(adev, 811a9d4fe2fSNirmoy Das state == AMD_CG_STATE_GATE); 812edc61147SHawking Zhang return 0; 813edc61147SHawking Zhang } 814edc61147SHawking Zhang 815edc61147SHawking Zhang static int navi10_ih_set_powergating_state(void *handle, 816edc61147SHawking Zhang enum amd_powergating_state state) 817edc61147SHawking Zhang { 818edc61147SHawking Zhang return 0; 819edc61147SHawking Zhang } 820edc61147SHawking Zhang 821edc61147SHawking Zhang static void navi10_ih_get_clockgating_state(void *handle, u32 *flags) 822edc61147SHawking Zhang { 823edc61147SHawking Zhang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 824edc61147SHawking Zhang 825edc61147SHawking Zhang if (!RREG32_SOC15(OSSSYS, 0, mmIH_CLK_CTRL)) 826edc61147SHawking Zhang *flags |= AMD_CG_SUPPORT_IH_CG; 827edc61147SHawking Zhang 828edc61147SHawking Zhang return; 829edc61147SHawking Zhang } 830edc61147SHawking Zhang 831edc61147SHawking Zhang static const struct amd_ip_funcs navi10_ih_ip_funcs = { 832edc61147SHawking Zhang .name = "navi10_ih", 833edc61147SHawking Zhang .early_init = navi10_ih_early_init, 834edc61147SHawking Zhang .late_init = NULL, 835edc61147SHawking Zhang .sw_init = navi10_ih_sw_init, 836edc61147SHawking Zhang .sw_fini = navi10_ih_sw_fini, 837edc61147SHawking Zhang .hw_init = navi10_ih_hw_init, 838edc61147SHawking Zhang .hw_fini = navi10_ih_hw_fini, 839edc61147SHawking Zhang .suspend = navi10_ih_suspend, 840edc61147SHawking Zhang .resume = navi10_ih_resume, 841edc61147SHawking Zhang .is_idle = navi10_ih_is_idle, 842edc61147SHawking Zhang .wait_for_idle = navi10_ih_wait_for_idle, 843edc61147SHawking Zhang .soft_reset = navi10_ih_soft_reset, 844edc61147SHawking Zhang .set_clockgating_state = navi10_ih_set_clockgating_state, 845edc61147SHawking Zhang .set_powergating_state = navi10_ih_set_powergating_state, 846edc61147SHawking Zhang .get_clockgating_state = navi10_ih_get_clockgating_state, 847edc61147SHawking Zhang }; 848edc61147SHawking Zhang 849edc61147SHawking Zhang static const struct amdgpu_ih_funcs navi10_ih_funcs = { 850edc61147SHawking Zhang .get_wptr = navi10_ih_get_wptr, 851edc61147SHawking Zhang .decode_iv = navi10_ih_decode_iv, 852edc61147SHawking Zhang .set_rptr = navi10_ih_set_rptr 853edc61147SHawking Zhang }; 854edc61147SHawking Zhang 855edc61147SHawking Zhang static void navi10_ih_set_interrupt_funcs(struct amdgpu_device *adev) 856edc61147SHawking Zhang { 857edc61147SHawking Zhang if (adev->irq.ih_funcs == NULL) 858edc61147SHawking Zhang adev->irq.ih_funcs = &navi10_ih_funcs; 859edc61147SHawking Zhang } 860edc61147SHawking Zhang 861edc61147SHawking Zhang const struct amdgpu_ip_block_version navi10_ih_ip_block = 862edc61147SHawking Zhang { 863edc61147SHawking Zhang .type = AMD_IP_BLOCK_TYPE_IH, 864edc61147SHawking Zhang .major = 5, 865edc61147SHawking Zhang .minor = 0, 866edc61147SHawking Zhang .rev = 0, 867edc61147SHawking Zhang .funcs = &navi10_ih_ip_funcs, 868edc61147SHawking Zhang }; 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