1edc61147SHawking Zhang /* 2edc61147SHawking Zhang * Copyright 2019 Advanced Micro Devices, Inc. 3edc61147SHawking Zhang * 4edc61147SHawking Zhang * Permission is hereby granted, free of charge, to any person obtaining a 5edc61147SHawking Zhang * copy of this software and associated documentation files (the "Software"), 6edc61147SHawking Zhang * to deal in the Software without restriction, including without limitation 7edc61147SHawking Zhang * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8edc61147SHawking Zhang * and/or sell copies of the Software, and to permit persons to whom the 9edc61147SHawking Zhang * Software is furnished to do so, subject to the following conditions: 10edc61147SHawking Zhang * 11edc61147SHawking Zhang * The above copyright notice and this permission notice shall be included in 12edc61147SHawking Zhang * all copies or substantial portions of the Software. 13edc61147SHawking Zhang * 14edc61147SHawking Zhang * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15edc61147SHawking Zhang * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16edc61147SHawking Zhang * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17edc61147SHawking Zhang * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18edc61147SHawking Zhang * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19edc61147SHawking Zhang * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20edc61147SHawking Zhang * OTHER DEALINGS IN THE SOFTWARE. 21edc61147SHawking Zhang * 22edc61147SHawking Zhang */ 23edc61147SHawking Zhang 24b23b2e9eSAlex Deucher #include <linux/pci.h> 25b23b2e9eSAlex Deucher 26edc61147SHawking Zhang #include "amdgpu.h" 27edc61147SHawking Zhang #include "amdgpu_ih.h" 28edc61147SHawking Zhang 29edc61147SHawking Zhang #include "oss/osssys_5_0_0_offset.h" 30edc61147SHawking Zhang #include "oss/osssys_5_0_0_sh_mask.h" 31edc61147SHawking Zhang 32edc61147SHawking Zhang #include "soc15_common.h" 33edc61147SHawking Zhang #include "navi10_ih.h" 34edc61147SHawking Zhang 35022b6518SSamir Dhume #define MAX_REARM_RETRY 10 36edc61147SHawking Zhang 37757b3af8SLikun Gao #define mmIH_CHICKEN_Sienna_Cichlid 0x018d 38757b3af8SLikun Gao #define mmIH_CHICKEN_Sienna_Cichlid_BASE_IDX 0 39757b3af8SLikun Gao 40edc61147SHawking Zhang static void navi10_ih_set_interrupt_funcs(struct amdgpu_device *adev); 41edc61147SHawking Zhang 42edc61147SHawking Zhang /** 435ea6f9c2SChengming Gui * force_update_wptr_for_self_int - Force update the wptr for self interrupt 445ea6f9c2SChengming Gui * 455ea6f9c2SChengming Gui * @adev: amdgpu_device pointer 465ea6f9c2SChengming Gui * @threshold: threshold to trigger the wptr reporting 475ea6f9c2SChengming Gui * @timeout: timeout to trigger the wptr reporting 485ea6f9c2SChengming Gui * @enabled: Enable/disable timeout flush mechanism 495ea6f9c2SChengming Gui * 505ea6f9c2SChengming Gui * threshold input range: 0 ~ 15, default 0, 515ea6f9c2SChengming Gui * real_threshold = 2^threshold 525ea6f9c2SChengming Gui * timeout input range: 0 ~ 20, default 8, 535ea6f9c2SChengming Gui * real_timeout = (2^timeout) * 1024 / (socclk_freq) 545ea6f9c2SChengming Gui * 555ea6f9c2SChengming Gui * Force update wptr for self interrupt ( >= SIENNA_CICHLID). 565ea6f9c2SChengming Gui */ 575ea6f9c2SChengming Gui static void 585ea6f9c2SChengming Gui force_update_wptr_for_self_int(struct amdgpu_device *adev, 595ea6f9c2SChengming Gui u32 threshold, u32 timeout, bool enabled) 605ea6f9c2SChengming Gui { 615ea6f9c2SChengming Gui u32 ih_cntl, ih_rb_cntl; 625ea6f9c2SChengming Gui 635ea6f9c2SChengming Gui if (adev->asic_type < CHIP_SIENNA_CICHLID) 645ea6f9c2SChengming Gui return; 655ea6f9c2SChengming Gui 665ea6f9c2SChengming Gui ih_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_CNTL2); 675ea6f9c2SChengming Gui ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1); 685ea6f9c2SChengming Gui 695ea6f9c2SChengming Gui ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL2, 705ea6f9c2SChengming Gui SELF_IV_FORCE_WPTR_UPDATE_TIMEOUT, timeout); 715ea6f9c2SChengming Gui ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL2, 725ea6f9c2SChengming Gui SELF_IV_FORCE_WPTR_UPDATE_ENABLE, enabled); 735ea6f9c2SChengming Gui ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING1, 745ea6f9c2SChengming Gui RB_USED_INT_THRESHOLD, threshold); 755ea6f9c2SChengming Gui 765ea6f9c2SChengming Gui WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1, ih_rb_cntl); 775ea6f9c2SChengming Gui ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2); 785ea6f9c2SChengming Gui ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING2, 795ea6f9c2SChengming Gui RB_USED_INT_THRESHOLD, threshold); 805ea6f9c2SChengming Gui WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2, ih_rb_cntl); 815ea6f9c2SChengming Gui WREG32_SOC15(OSSSYS, 0, mmIH_CNTL2, ih_cntl); 825ea6f9c2SChengming Gui } 835ea6f9c2SChengming Gui 845ea6f9c2SChengming Gui /** 85edc61147SHawking Zhang * navi10_ih_enable_interrupts - Enable the interrupt ring buffer 86edc61147SHawking Zhang * 87edc61147SHawking Zhang * @adev: amdgpu_device pointer 88edc61147SHawking Zhang * 89edc61147SHawking Zhang * Enable the interrupt ring buffer (NAVI10). 90edc61147SHawking Zhang */ 91edc61147SHawking Zhang static void navi10_ih_enable_interrupts(struct amdgpu_device *adev) 92edc61147SHawking Zhang { 93edc61147SHawking Zhang u32 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL); 94edc61147SHawking Zhang 95edc61147SHawking Zhang ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 1); 96edc61147SHawking Zhang ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, ENABLE_INTR, 1); 97193cce34SAlex Sierra if (amdgpu_sriov_vf(adev) && adev->asic_type < CHIP_NAVI10) { 980ab176e6SAlex Sierra if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL, ih_rb_cntl)) { 990ab176e6SAlex Sierra DRM_ERROR("PSP program IH_RB_CNTL failed!\n"); 1000ab176e6SAlex Sierra return; 1010ab176e6SAlex Sierra } 1020ab176e6SAlex Sierra } else { 103edc61147SHawking Zhang WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL, ih_rb_cntl); 1040ab176e6SAlex Sierra } 1050ab176e6SAlex Sierra 106edc61147SHawking Zhang adev->irq.ih.enabled = true; 107ab518012SAlex Sierra 108ab518012SAlex Sierra if (adev->irq.ih1.ring_size) { 109ab518012SAlex Sierra ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1); 110ab518012SAlex Sierra ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING1, 111ab518012SAlex Sierra RB_ENABLE, 1); 112193cce34SAlex Sierra if (amdgpu_sriov_vf(adev) && adev->asic_type < CHIP_NAVI10) { 1130ab176e6SAlex Sierra if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL_RING1, 1140ab176e6SAlex Sierra ih_rb_cntl)) { 1150ab176e6SAlex Sierra DRM_ERROR("program IH_RB_CNTL_RING1 failed!\n"); 1160ab176e6SAlex Sierra return; 1170ab176e6SAlex Sierra } 1180ab176e6SAlex Sierra } else { 119ab518012SAlex Sierra WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1, ih_rb_cntl); 1200ab176e6SAlex Sierra } 121ab518012SAlex Sierra adev->irq.ih1.enabled = true; 122ab518012SAlex Sierra } 123ab518012SAlex Sierra 124ab518012SAlex Sierra if (adev->irq.ih2.ring_size) { 125ab518012SAlex Sierra ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2); 126ab518012SAlex Sierra ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING2, 127ab518012SAlex Sierra RB_ENABLE, 1); 128193cce34SAlex Sierra if (amdgpu_sriov_vf(adev) && adev->asic_type < CHIP_NAVI10) { 1290ab176e6SAlex Sierra if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL_RING2, 1300ab176e6SAlex Sierra ih_rb_cntl)) { 1310ab176e6SAlex Sierra DRM_ERROR("program IH_RB_CNTL_RING2 failed!\n"); 1320ab176e6SAlex Sierra return; 1330ab176e6SAlex Sierra } 1340ab176e6SAlex Sierra } else { 135ab518012SAlex Sierra WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2, ih_rb_cntl); 1360ab176e6SAlex Sierra } 137ab518012SAlex Sierra adev->irq.ih2.enabled = true; 138ab518012SAlex Sierra } 139edc61147SHawking Zhang } 140edc61147SHawking Zhang 141edc61147SHawking Zhang /** 142edc61147SHawking Zhang * navi10_ih_disable_interrupts - Disable the interrupt ring buffer 143edc61147SHawking Zhang * 144edc61147SHawking Zhang * @adev: amdgpu_device pointer 145edc61147SHawking Zhang * 146edc61147SHawking Zhang * Disable the interrupt ring buffer (NAVI10). 147edc61147SHawking Zhang */ 148edc61147SHawking Zhang static void navi10_ih_disable_interrupts(struct amdgpu_device *adev) 149edc61147SHawking Zhang { 150edc61147SHawking Zhang u32 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL); 151edc61147SHawking Zhang 152edc61147SHawking Zhang ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 0); 153edc61147SHawking Zhang ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, ENABLE_INTR, 0); 154193cce34SAlex Sierra if (amdgpu_sriov_vf(adev) && adev->asic_type < CHIP_NAVI10) { 1550ab176e6SAlex Sierra if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL, ih_rb_cntl)) { 1560ab176e6SAlex Sierra DRM_ERROR("PSP program IH_RB_CNTL failed!\n"); 1570ab176e6SAlex Sierra return; 1580ab176e6SAlex Sierra } 1590ab176e6SAlex Sierra } else { 160edc61147SHawking Zhang WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL, ih_rb_cntl); 1610ab176e6SAlex Sierra } 1620ab176e6SAlex Sierra 163edc61147SHawking Zhang /* set rptr, wptr to 0 */ 164edc61147SHawking Zhang WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR, 0); 165edc61147SHawking Zhang WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR, 0); 166edc61147SHawking Zhang adev->irq.ih.enabled = false; 167edc61147SHawking Zhang adev->irq.ih.rptr = 0; 168ab518012SAlex Sierra 169ab518012SAlex Sierra if (adev->irq.ih1.ring_size) { 170ab518012SAlex Sierra ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1); 171ab518012SAlex Sierra ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING1, 172ab518012SAlex Sierra RB_ENABLE, 0); 173193cce34SAlex Sierra if (amdgpu_sriov_vf(adev) && adev->asic_type < CHIP_NAVI10) { 1740ab176e6SAlex Sierra if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL_RING1, 1750ab176e6SAlex Sierra ih_rb_cntl)) { 1760ab176e6SAlex Sierra DRM_ERROR("program IH_RB_CNTL_RING1 failed!\n"); 1770ab176e6SAlex Sierra return; 1780ab176e6SAlex Sierra } 1790ab176e6SAlex Sierra } else { 180ab518012SAlex Sierra WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1, ih_rb_cntl); 1810ab176e6SAlex Sierra } 182ab518012SAlex Sierra /* set rptr, wptr to 0 */ 183ab518012SAlex Sierra WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR_RING1, 0); 184ab518012SAlex Sierra WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_RING1, 0); 185ab518012SAlex Sierra adev->irq.ih1.enabled = false; 186ab518012SAlex Sierra adev->irq.ih1.rptr = 0; 187ab518012SAlex Sierra } 188ab518012SAlex Sierra 189ab518012SAlex Sierra if (adev->irq.ih2.ring_size) { 190ab518012SAlex Sierra ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2); 191ab518012SAlex Sierra ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING2, 192ab518012SAlex Sierra RB_ENABLE, 0); 193193cce34SAlex Sierra if (amdgpu_sriov_vf(adev) && adev->asic_type < CHIP_NAVI10) { 1940ab176e6SAlex Sierra if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL_RING2, 1950ab176e6SAlex Sierra ih_rb_cntl)) { 1960ab176e6SAlex Sierra DRM_ERROR("program IH_RB_CNTL_RING2 failed!\n"); 1970ab176e6SAlex Sierra return; 1980ab176e6SAlex Sierra } 1990ab176e6SAlex Sierra } else { 200ab518012SAlex Sierra WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2, ih_rb_cntl); 2010ab176e6SAlex Sierra } 202ab518012SAlex Sierra /* set rptr, wptr to 0 */ 203ab518012SAlex Sierra WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR_RING2, 0); 204ab518012SAlex Sierra WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_RING2, 0); 205ab518012SAlex Sierra adev->irq.ih2.enabled = false; 206ab518012SAlex Sierra adev->irq.ih2.rptr = 0; 207ab518012SAlex Sierra } 208ab518012SAlex Sierra 209edc61147SHawking Zhang } 210edc61147SHawking Zhang 211edc61147SHawking Zhang static uint32_t navi10_ih_rb_cntl(struct amdgpu_ih_ring *ih, uint32_t ih_rb_cntl) 212edc61147SHawking Zhang { 213edc61147SHawking Zhang int rb_bufsz = order_base_2(ih->ring_size / 4); 214edc61147SHawking Zhang 215edc61147SHawking Zhang ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, 216edc61147SHawking Zhang MC_SPACE, ih->use_bus_addr ? 1 : 4); 217edc61147SHawking Zhang ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, 218edc61147SHawking Zhang WPTR_OVERFLOW_CLEAR, 1); 219edc61147SHawking Zhang ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, 220edc61147SHawking Zhang WPTR_OVERFLOW_ENABLE, 1); 221edc61147SHawking Zhang ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_SIZE, rb_bufsz); 222edc61147SHawking Zhang /* Ring Buffer write pointer writeback. If enabled, IH_RB_WPTR register 223edc61147SHawking Zhang * value is written to memory 224edc61147SHawking Zhang */ 225edc61147SHawking Zhang ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, 226edc61147SHawking Zhang WPTR_WRITEBACK_ENABLE, 1); 227edc61147SHawking Zhang ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_SNOOP, 1); 228edc61147SHawking Zhang ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_RO, 0); 229edc61147SHawking Zhang ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_VMID, 0); 230edc61147SHawking Zhang 231edc61147SHawking Zhang return ih_rb_cntl; 232edc61147SHawking Zhang } 233edc61147SHawking Zhang 234ab518012SAlex Sierra static uint32_t navi10_ih_doorbell_rptr(struct amdgpu_ih_ring *ih) 235ab518012SAlex Sierra { 236ab518012SAlex Sierra u32 ih_doorbell_rtpr = 0; 237ab518012SAlex Sierra 238ab518012SAlex Sierra if (ih->use_doorbell) { 239ab518012SAlex Sierra ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr, 240ab518012SAlex Sierra IH_DOORBELL_RPTR, OFFSET, 241ab518012SAlex Sierra ih->doorbell_index); 242ab518012SAlex Sierra ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr, 243ab518012SAlex Sierra IH_DOORBELL_RPTR, 244ab518012SAlex Sierra ENABLE, 1); 245ab518012SAlex Sierra } else { 246ab518012SAlex Sierra ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr, 247ab518012SAlex Sierra IH_DOORBELL_RPTR, 248ab518012SAlex Sierra ENABLE, 0); 249ab518012SAlex Sierra } 250ab518012SAlex Sierra return ih_doorbell_rtpr; 251ab518012SAlex Sierra } 252ab518012SAlex Sierra 2539e94ff33SAlex Sierra static void navi10_ih_reroute_ih(struct amdgpu_device *adev) 2549e94ff33SAlex Sierra { 2559e94ff33SAlex Sierra uint32_t tmp; 2569e94ff33SAlex Sierra 2579e94ff33SAlex Sierra /* Reroute to IH ring 1 for VMC */ 2589e94ff33SAlex Sierra WREG32_SOC15(OSSSYS, 0, mmIH_CLIENT_CFG_INDEX, 0x12); 2599e94ff33SAlex Sierra tmp = RREG32_SOC15(OSSSYS, 0, mmIH_CLIENT_CFG_DATA); 2609e94ff33SAlex Sierra tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, CLIENT_TYPE, 1); 2619e94ff33SAlex Sierra tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, RING_ID, 1); 2629e94ff33SAlex Sierra WREG32_SOC15(OSSSYS, 0, mmIH_CLIENT_CFG_DATA, tmp); 2639e94ff33SAlex Sierra 2649e94ff33SAlex Sierra /* Reroute IH ring 1 for UMC */ 2659e94ff33SAlex Sierra WREG32_SOC15(OSSSYS, 0, mmIH_CLIENT_CFG_INDEX, 0x1B); 2669e94ff33SAlex Sierra tmp = RREG32_SOC15(OSSSYS, 0, mmIH_CLIENT_CFG_DATA); 2679e94ff33SAlex Sierra tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, RING_ID, 1); 2689e94ff33SAlex Sierra WREG32_SOC15(OSSSYS, 0, mmIH_CLIENT_CFG_DATA, tmp); 2699e94ff33SAlex Sierra } 2709e94ff33SAlex Sierra 271edc61147SHawking Zhang /** 272edc61147SHawking Zhang * navi10_ih_irq_init - init and enable the interrupt ring 273edc61147SHawking Zhang * 274edc61147SHawking Zhang * @adev: amdgpu_device pointer 275edc61147SHawking Zhang * 276edc61147SHawking Zhang * Allocate a ring buffer for the interrupt controller, 277edc61147SHawking Zhang * enable the RLC, disable interrupts, enable the IH 278edc61147SHawking Zhang * ring buffer and enable it (NAVI). 279edc61147SHawking Zhang * Called at device load and reume. 280edc61147SHawking Zhang * Returns 0 for success, errors for failure. 281edc61147SHawking Zhang */ 282edc61147SHawking Zhang static int navi10_ih_irq_init(struct amdgpu_device *adev) 283edc61147SHawking Zhang { 284edc61147SHawking Zhang struct amdgpu_ih_ring *ih = &adev->irq.ih; 285ab518012SAlex Sierra u32 ih_rb_cntl, ih_chicken; 286edc61147SHawking Zhang u32 tmp; 287edc61147SHawking Zhang 288edc61147SHawking Zhang /* disable irqs */ 289edc61147SHawking Zhang navi10_ih_disable_interrupts(adev); 290edc61147SHawking Zhang 291bebc0762SHawking Zhang adev->nbio.funcs->ih_control(adev); 292edc61147SHawking Zhang 293edc61147SHawking Zhang /* Ring Buffer base. [39:8] of 40-bit address of the beginning of the ring buffer*/ 294edc61147SHawking Zhang WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE, ih->gpu_addr >> 8); 295edc61147SHawking Zhang WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE_HI, (ih->gpu_addr >> 40) & 0xff); 296edc61147SHawking Zhang 297edc61147SHawking Zhang ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL); 298edc61147SHawking Zhang ih_rb_cntl = navi10_ih_rb_cntl(ih, ih_rb_cntl); 299edc61147SHawking Zhang ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RPTR_REARM, 300edc61147SHawking Zhang !!adev->irq.msi_enabled); 301193cce34SAlex Sierra if (amdgpu_sriov_vf(adev) && adev->asic_type < CHIP_NAVI10) { 3020ab176e6SAlex Sierra if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL, ih_rb_cntl)) { 3030ab176e6SAlex Sierra DRM_ERROR("PSP program IH_RB_CNTL failed!\n"); 3040ab176e6SAlex Sierra return -ETIMEDOUT; 3050ab176e6SAlex Sierra } 3060ab176e6SAlex Sierra } else { 3070ab176e6SAlex Sierra WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL, ih_rb_cntl); 3080ab176e6SAlex Sierra } 309abb6fccbSAlex Sierra if (adev->irq.ih1.ring_size) 3109e94ff33SAlex Sierra navi10_ih_reroute_ih(adev); 311edc61147SHawking Zhang 312edc61147SHawking Zhang if (unlikely(adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT)) { 313edc61147SHawking Zhang if (ih->use_bus_addr) { 314757b3af8SLikun Gao switch (adev->asic_type) { 315757b3af8SLikun Gao case CHIP_SIENNA_CICHLID: 316026c396bSJiansong Chen case CHIP_NAVY_FLOUNDER: 317bd4f2811SHuang Rui case CHIP_VANGOGH: 318757b3af8SLikun Gao ih_chicken = RREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN_Sienna_Cichlid); 319757b3af8SLikun Gao ih_chicken = REG_SET_FIELD(ih_chicken, 320757b3af8SLikun Gao IH_CHICKEN, MC_SPACE_GPA_ENABLE, 1); 321757b3af8SLikun Gao WREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN_Sienna_Cichlid, ih_chicken); 322757b3af8SLikun Gao break; 323757b3af8SLikun Gao default: 324edc61147SHawking Zhang ih_chicken = RREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN); 325edc61147SHawking Zhang ih_chicken = REG_SET_FIELD(ih_chicken, 326edc61147SHawking Zhang IH_CHICKEN, MC_SPACE_GPA_ENABLE, 1); 327edc61147SHawking Zhang WREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN, ih_chicken); 328757b3af8SLikun Gao break; 329757b3af8SLikun Gao } 330edc61147SHawking Zhang } 331edc61147SHawking Zhang } 332edc61147SHawking Zhang 333edc61147SHawking Zhang /* set the writeback address whether it's enabled or not */ 334edc61147SHawking Zhang WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_ADDR_LO, 335edc61147SHawking Zhang lower_32_bits(ih->wptr_addr)); 336edc61147SHawking Zhang WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_ADDR_HI, 337edc61147SHawking Zhang upper_32_bits(ih->wptr_addr) & 0xFFFF); 338edc61147SHawking Zhang 339edc61147SHawking Zhang /* set rptr, wptr to 0 */ 340edc61147SHawking Zhang WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR, 0); 341edc61147SHawking Zhang WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR, 0); 342edc61147SHawking Zhang 343ab518012SAlex Sierra WREG32_SOC15(OSSSYS, 0, mmIH_DOORBELL_RPTR, 344ab518012SAlex Sierra navi10_ih_doorbell_rptr(ih)); 345edc61147SHawking Zhang 346bebc0762SHawking Zhang adev->nbio.funcs->ih_doorbell_range(adev, ih->use_doorbell, 347edc61147SHawking Zhang ih->doorbell_index); 348edc61147SHawking Zhang 349ab518012SAlex Sierra ih = &adev->irq.ih1; 350ab518012SAlex Sierra if (ih->ring_size) { 351ab518012SAlex Sierra WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE_RING1, ih->gpu_addr >> 8); 352ab518012SAlex Sierra WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE_HI_RING1, 353ab518012SAlex Sierra (ih->gpu_addr >> 40) & 0xff); 354ab518012SAlex Sierra 355ab518012SAlex Sierra ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1); 356ab518012SAlex Sierra ih_rb_cntl = navi10_ih_rb_cntl(ih, ih_rb_cntl); 357ab518012SAlex Sierra ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, 358ab518012SAlex Sierra WPTR_OVERFLOW_ENABLE, 0); 359ab518012SAlex Sierra ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, 360ab518012SAlex Sierra RB_FULL_DRAIN_ENABLE, 1); 361193cce34SAlex Sierra if (amdgpu_sriov_vf(adev) && adev->asic_type < CHIP_NAVI10) { 3620ab176e6SAlex Sierra if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL_RING1, 3630ab176e6SAlex Sierra ih_rb_cntl)) { 3640ab176e6SAlex Sierra DRM_ERROR("program IH_RB_CNTL_RING1 failed!\n"); 3650ab176e6SAlex Sierra return -ETIMEDOUT; 3660ab176e6SAlex Sierra } 3670ab176e6SAlex Sierra } else { 368ab518012SAlex Sierra WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1, ih_rb_cntl); 3690ab176e6SAlex Sierra } 370ab518012SAlex Sierra /* set rptr, wptr to 0 */ 371ab518012SAlex Sierra WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_RING1, 0); 372ab518012SAlex Sierra WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR_RING1, 0); 373ab518012SAlex Sierra 374ab518012SAlex Sierra WREG32_SOC15(OSSSYS, 0, mmIH_DOORBELL_RPTR_RING1, 375ab518012SAlex Sierra navi10_ih_doorbell_rptr(ih)); 376ab518012SAlex Sierra } 377ab518012SAlex Sierra 378ab518012SAlex Sierra ih = &adev->irq.ih2; 379ab518012SAlex Sierra if (ih->ring_size) { 380ab518012SAlex Sierra WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE_RING2, ih->gpu_addr >> 8); 381ab518012SAlex Sierra WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE_HI_RING2, 382ab518012SAlex Sierra (ih->gpu_addr >> 40) & 0xff); 383ab518012SAlex Sierra 384ab518012SAlex Sierra ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2); 385ab518012SAlex Sierra ih_rb_cntl = navi10_ih_rb_cntl(ih, ih_rb_cntl); 386ab518012SAlex Sierra 387193cce34SAlex Sierra if (amdgpu_sriov_vf(adev) && adev->asic_type < CHIP_NAVI10) { 3880ab176e6SAlex Sierra if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL_RING2, 3890ab176e6SAlex Sierra ih_rb_cntl)) { 3900ab176e6SAlex Sierra DRM_ERROR("program IH_RB_CNTL_RING2 failed!\n"); 3910ab176e6SAlex Sierra return -ETIMEDOUT; 3920ab176e6SAlex Sierra } 3930ab176e6SAlex Sierra } else { 394ab518012SAlex Sierra WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2, ih_rb_cntl); 3950ab176e6SAlex Sierra } 396ab518012SAlex Sierra /* set rptr, wptr to 0 */ 397ab518012SAlex Sierra WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_RING2, 0); 398ab518012SAlex Sierra WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR_RING2, 0); 399ab518012SAlex Sierra 400ab518012SAlex Sierra WREG32_SOC15(OSSSYS, 0, mmIH_DOORBELL_RPTR_RING2, 401ab518012SAlex Sierra navi10_ih_doorbell_rptr(ih)); 402ab518012SAlex Sierra } 403ab518012SAlex Sierra 404ab518012SAlex Sierra 405edc61147SHawking Zhang tmp = RREG32_SOC15(OSSSYS, 0, mmIH_STORM_CLIENT_LIST_CNTL); 406edc61147SHawking Zhang tmp = REG_SET_FIELD(tmp, IH_STORM_CLIENT_LIST_CNTL, 407edc61147SHawking Zhang CLIENT18_IS_STORM_CLIENT, 1); 408edc61147SHawking Zhang WREG32_SOC15(OSSSYS, 0, mmIH_STORM_CLIENT_LIST_CNTL, tmp); 409edc61147SHawking Zhang 410edc61147SHawking Zhang tmp = RREG32_SOC15(OSSSYS, 0, mmIH_INT_FLOOD_CNTL); 411edc61147SHawking Zhang tmp = REG_SET_FIELD(tmp, IH_INT_FLOOD_CNTL, FLOOD_CNTL_ENABLE, 1); 412edc61147SHawking Zhang WREG32_SOC15(OSSSYS, 0, mmIH_INT_FLOOD_CNTL, tmp); 413edc61147SHawking Zhang 414edc61147SHawking Zhang pci_set_master(adev->pdev); 415edc61147SHawking Zhang 416edc61147SHawking Zhang /* enable interrupts */ 417edc61147SHawking Zhang navi10_ih_enable_interrupts(adev); 4185ea6f9c2SChengming Gui /* enable wptr force update for self int */ 4195ea6f9c2SChengming Gui force_update_wptr_for_self_int(adev, 0, 8, true); 420edc61147SHawking Zhang 4217eca4006SMa Feng return 0; 422edc61147SHawking Zhang } 423edc61147SHawking Zhang 424edc61147SHawking Zhang /** 425edc61147SHawking Zhang * navi10_ih_irq_disable - disable interrupts 426edc61147SHawking Zhang * 427edc61147SHawking Zhang * @adev: amdgpu_device pointer 428edc61147SHawking Zhang * 429edc61147SHawking Zhang * Disable interrupts on the hw (NAVI10). 430edc61147SHawking Zhang */ 431edc61147SHawking Zhang static void navi10_ih_irq_disable(struct amdgpu_device *adev) 432edc61147SHawking Zhang { 4335ea6f9c2SChengming Gui force_update_wptr_for_self_int(adev, 0, 8, false); 434edc61147SHawking Zhang navi10_ih_disable_interrupts(adev); 435edc61147SHawking Zhang 436edc61147SHawking Zhang /* Wait and acknowledge irq */ 437edc61147SHawking Zhang mdelay(1); 438edc61147SHawking Zhang } 439edc61147SHawking Zhang 440edc61147SHawking Zhang /** 441edc61147SHawking Zhang * navi10_ih_get_wptr - get the IH ring buffer wptr 442edc61147SHawking Zhang * 443edc61147SHawking Zhang * @adev: amdgpu_device pointer 444edc61147SHawking Zhang * 445edc61147SHawking Zhang * Get the IH ring buffer wptr from either the register 446edc61147SHawking Zhang * or the writeback memory buffer (NAVI10). Also check for 447edc61147SHawking Zhang * ring buffer overflow and deal with it. 448edc61147SHawking Zhang * Returns the value of the wptr. 449edc61147SHawking Zhang */ 450edc61147SHawking Zhang static u32 navi10_ih_get_wptr(struct amdgpu_device *adev, 451edc61147SHawking Zhang struct amdgpu_ih_ring *ih) 452edc61147SHawking Zhang { 453edc61147SHawking Zhang u32 wptr, reg, tmp; 454edc61147SHawking Zhang 455edc61147SHawking Zhang wptr = le32_to_cpu(*ih->wptr_cpu); 456edc61147SHawking Zhang 457edc61147SHawking Zhang if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) 458edc61147SHawking Zhang goto out; 459edc61147SHawking Zhang 460ab518012SAlex Sierra if (ih == &adev->irq.ih) 461edc61147SHawking Zhang reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR); 462ab518012SAlex Sierra else if (ih == &adev->irq.ih1) 463ab518012SAlex Sierra reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_RING1); 464ab518012SAlex Sierra else if (ih == &adev->irq.ih2) 465ab518012SAlex Sierra reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_RING2); 466ab518012SAlex Sierra else 467ab518012SAlex Sierra BUG(); 468ab518012SAlex Sierra 469edc61147SHawking Zhang wptr = RREG32_NO_KIQ(reg); 470edc61147SHawking Zhang if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) 471edc61147SHawking Zhang goto out; 472edc61147SHawking Zhang wptr = REG_SET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW, 0); 473edc61147SHawking Zhang 474edc61147SHawking Zhang /* When a ring buffer overflow happen start parsing interrupt 475edc61147SHawking Zhang * from the last not overwritten vector (wptr + 32). Hopefully 476edc61147SHawking Zhang * this should allow us to catch up. 477edc61147SHawking Zhang */ 478edc61147SHawking Zhang tmp = (wptr + 32) & ih->ptr_mask; 479edc61147SHawking Zhang dev_warn(adev->dev, "IH ring buffer overflow " 480edc61147SHawking Zhang "(0x%08X, 0x%08X, 0x%08X)\n", 481edc61147SHawking Zhang wptr, ih->rptr, tmp); 482edc61147SHawking Zhang ih->rptr = tmp; 483edc61147SHawking Zhang 484ab518012SAlex Sierra if (ih == &adev->irq.ih) 485edc61147SHawking Zhang reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL); 486ab518012SAlex Sierra else if (ih == &adev->irq.ih1) 487ab518012SAlex Sierra reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL_RING1); 488ab518012SAlex Sierra else if (ih == &adev->irq.ih2) 489ab518012SAlex Sierra reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL_RING2); 490ab518012SAlex Sierra else 491ab518012SAlex Sierra BUG(); 492ab518012SAlex Sierra 493edc61147SHawking Zhang tmp = RREG32_NO_KIQ(reg); 494edc61147SHawking Zhang tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1); 495edc61147SHawking Zhang WREG32_NO_KIQ(reg, tmp); 496edc61147SHawking Zhang out: 497edc61147SHawking Zhang return (wptr & ih->ptr_mask); 498edc61147SHawking Zhang } 499edc61147SHawking Zhang 500edc61147SHawking Zhang /** 501edc61147SHawking Zhang * navi10_ih_decode_iv - decode an interrupt vector 502edc61147SHawking Zhang * 503edc61147SHawking Zhang * @adev: amdgpu_device pointer 504edc61147SHawking Zhang * 505edc61147SHawking Zhang * Decodes the interrupt vector at the current rptr 506edc61147SHawking Zhang * position and also advance the position. 507edc61147SHawking Zhang */ 508edc61147SHawking Zhang static void navi10_ih_decode_iv(struct amdgpu_device *adev, 509edc61147SHawking Zhang struct amdgpu_ih_ring *ih, 510edc61147SHawking Zhang struct amdgpu_iv_entry *entry) 511edc61147SHawking Zhang { 512edc61147SHawking Zhang /* wptr/rptr are in bytes! */ 513edc61147SHawking Zhang u32 ring_index = ih->rptr >> 2; 514edc61147SHawking Zhang uint32_t dw[8]; 515edc61147SHawking Zhang 516edc61147SHawking Zhang dw[0] = le32_to_cpu(ih->ring[ring_index + 0]); 517edc61147SHawking Zhang dw[1] = le32_to_cpu(ih->ring[ring_index + 1]); 518edc61147SHawking Zhang dw[2] = le32_to_cpu(ih->ring[ring_index + 2]); 519edc61147SHawking Zhang dw[3] = le32_to_cpu(ih->ring[ring_index + 3]); 520edc61147SHawking Zhang dw[4] = le32_to_cpu(ih->ring[ring_index + 4]); 521edc61147SHawking Zhang dw[5] = le32_to_cpu(ih->ring[ring_index + 5]); 522edc61147SHawking Zhang dw[6] = le32_to_cpu(ih->ring[ring_index + 6]); 523edc61147SHawking Zhang dw[7] = le32_to_cpu(ih->ring[ring_index + 7]); 524edc61147SHawking Zhang 525edc61147SHawking Zhang entry->client_id = dw[0] & 0xff; 526edc61147SHawking Zhang entry->src_id = (dw[0] >> 8) & 0xff; 527edc61147SHawking Zhang entry->ring_id = (dw[0] >> 16) & 0xff; 528edc61147SHawking Zhang entry->vmid = (dw[0] >> 24) & 0xf; 529edc61147SHawking Zhang entry->vmid_src = (dw[0] >> 31); 530edc61147SHawking Zhang entry->timestamp = dw[1] | ((u64)(dw[2] & 0xffff) << 32); 531edc61147SHawking Zhang entry->timestamp_src = dw[2] >> 31; 532edc61147SHawking Zhang entry->pasid = dw[3] & 0xffff; 533edc61147SHawking Zhang entry->pasid_src = dw[3] >> 31; 534edc61147SHawking Zhang entry->src_data[0] = dw[4]; 535edc61147SHawking Zhang entry->src_data[1] = dw[5]; 536edc61147SHawking Zhang entry->src_data[2] = dw[6]; 537edc61147SHawking Zhang entry->src_data[3] = dw[7]; 538edc61147SHawking Zhang 539edc61147SHawking Zhang /* wptr/rptr are in bytes! */ 540edc61147SHawking Zhang ih->rptr += 32; 541edc61147SHawking Zhang } 542edc61147SHawking Zhang 543edc61147SHawking Zhang /** 544022b6518SSamir Dhume * navi10_ih_irq_rearm - rearm IRQ if lost 545022b6518SSamir Dhume * 546022b6518SSamir Dhume * @adev: amdgpu_device pointer 547022b6518SSamir Dhume * 548022b6518SSamir Dhume */ 549022b6518SSamir Dhume static void navi10_ih_irq_rearm(struct amdgpu_device *adev, 550022b6518SSamir Dhume struct amdgpu_ih_ring *ih) 551022b6518SSamir Dhume { 552022b6518SSamir Dhume uint32_t reg_rptr = 0; 553022b6518SSamir Dhume uint32_t v = 0; 554022b6518SSamir Dhume uint32_t i = 0; 555022b6518SSamir Dhume 556022b6518SSamir Dhume if (ih == &adev->irq.ih) 557022b6518SSamir Dhume reg_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR); 558022b6518SSamir Dhume else if (ih == &adev->irq.ih1) 559022b6518SSamir Dhume reg_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR_RING1); 560022b6518SSamir Dhume else if (ih == &adev->irq.ih2) 561022b6518SSamir Dhume reg_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR_RING2); 562022b6518SSamir Dhume else 563022b6518SSamir Dhume return; 564022b6518SSamir Dhume 565022b6518SSamir Dhume /* Rearm IRQ / re-write doorbell if doorbell write is lost */ 566022b6518SSamir Dhume for (i = 0; i < MAX_REARM_RETRY; i++) { 567022b6518SSamir Dhume v = RREG32_NO_KIQ(reg_rptr); 568022b6518SSamir Dhume if ((v < ih->ring_size) && (v != ih->rptr)) 569022b6518SSamir Dhume WDOORBELL32(ih->doorbell_index, ih->rptr); 570022b6518SSamir Dhume else 571022b6518SSamir Dhume break; 572022b6518SSamir Dhume } 573022b6518SSamir Dhume } 574022b6518SSamir Dhume 575022b6518SSamir Dhume /** 576edc61147SHawking Zhang * navi10_ih_set_rptr - set the IH ring buffer rptr 577edc61147SHawking Zhang * 578edc61147SHawking Zhang * @adev: amdgpu_device pointer 579edc61147SHawking Zhang * 580edc61147SHawking Zhang * Set the IH ring buffer rptr. 581edc61147SHawking Zhang */ 582edc61147SHawking Zhang static void navi10_ih_set_rptr(struct amdgpu_device *adev, 583edc61147SHawking Zhang struct amdgpu_ih_ring *ih) 584edc61147SHawking Zhang { 585edc61147SHawking Zhang if (ih->use_doorbell) { 586edc61147SHawking Zhang /* XXX check if swapping is necessary on BE */ 587edc61147SHawking Zhang *ih->rptr_cpu = ih->rptr; 588edc61147SHawking Zhang WDOORBELL32(ih->doorbell_index, ih->rptr); 589022b6518SSamir Dhume 590022b6518SSamir Dhume if (amdgpu_sriov_vf(adev)) 591022b6518SSamir Dhume navi10_ih_irq_rearm(adev, ih); 592ab518012SAlex Sierra } else if (ih == &adev->irq.ih) { 593edc61147SHawking Zhang WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR, ih->rptr); 594ab518012SAlex Sierra } else if (ih == &adev->irq.ih1) { 595ab518012SAlex Sierra WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR_RING1, ih->rptr); 596ab518012SAlex Sierra } else if (ih == &adev->irq.ih2) { 597ab518012SAlex Sierra WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR_RING2, ih->rptr); 598ab518012SAlex Sierra } 599ab518012SAlex Sierra } 600ab518012SAlex Sierra 601ab518012SAlex Sierra /** 602ab518012SAlex Sierra * navi10_ih_self_irq - dispatch work for ring 1 and 2 603ab518012SAlex Sierra * 604ab518012SAlex Sierra * @adev: amdgpu_device pointer 605ab518012SAlex Sierra * @source: irq source 606ab518012SAlex Sierra * @entry: IV with WPTR update 607ab518012SAlex Sierra * 608ab518012SAlex Sierra * Update the WPTR from the IV and schedule work to handle the entries. 609ab518012SAlex Sierra */ 610ab518012SAlex Sierra static int navi10_ih_self_irq(struct amdgpu_device *adev, 611ab518012SAlex Sierra struct amdgpu_irq_src *source, 612ab518012SAlex Sierra struct amdgpu_iv_entry *entry) 613ab518012SAlex Sierra { 614ab518012SAlex Sierra uint32_t wptr = cpu_to_le32(entry->src_data[0]); 615ab518012SAlex Sierra 616ab518012SAlex Sierra switch (entry->ring_id) { 617ab518012SAlex Sierra case 1: 618ab518012SAlex Sierra *adev->irq.ih1.wptr_cpu = wptr; 619ab518012SAlex Sierra schedule_work(&adev->irq.ih1_work); 620ab518012SAlex Sierra break; 621ab518012SAlex Sierra case 2: 622ab518012SAlex Sierra *adev->irq.ih2.wptr_cpu = wptr; 623ab518012SAlex Sierra schedule_work(&adev->irq.ih2_work); 624ab518012SAlex Sierra break; 625ab518012SAlex Sierra default: break; 626ab518012SAlex Sierra } 627ab518012SAlex Sierra return 0; 628ab518012SAlex Sierra } 629ab518012SAlex Sierra 630ab518012SAlex Sierra static const struct amdgpu_irq_src_funcs navi10_ih_self_irq_funcs = { 631ab518012SAlex Sierra .process = navi10_ih_self_irq, 632ab518012SAlex Sierra }; 633ab518012SAlex Sierra 634ab518012SAlex Sierra static void navi10_ih_set_self_irq_funcs(struct amdgpu_device *adev) 635ab518012SAlex Sierra { 636ab518012SAlex Sierra adev->irq.self_irq.num_types = 0; 637ab518012SAlex Sierra adev->irq.self_irq.funcs = &navi10_ih_self_irq_funcs; 638edc61147SHawking Zhang } 639edc61147SHawking Zhang 640edc61147SHawking Zhang static int navi10_ih_early_init(void *handle) 641edc61147SHawking Zhang { 642edc61147SHawking Zhang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 643edc61147SHawking Zhang 644edc61147SHawking Zhang navi10_ih_set_interrupt_funcs(adev); 645ab518012SAlex Sierra navi10_ih_set_self_irq_funcs(adev); 646edc61147SHawking Zhang return 0; 647edc61147SHawking Zhang } 648edc61147SHawking Zhang 649edc61147SHawking Zhang static int navi10_ih_sw_init(void *handle) 650edc61147SHawking Zhang { 651edc61147SHawking Zhang int r; 652edc61147SHawking Zhang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 653edc61147SHawking Zhang bool use_bus_addr; 654edc61147SHawking Zhang 655ab518012SAlex Sierra r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_IH, 0, 656ab518012SAlex Sierra &adev->irq.self_irq); 657ab518012SAlex Sierra 658ab518012SAlex Sierra if (r) 659ab518012SAlex Sierra return r; 660ab518012SAlex Sierra 661edc61147SHawking Zhang /* use gpu virtual address for ih ring 662edc61147SHawking Zhang * until ih_checken is programmed to allow 663edc61147SHawking Zhang * use bus address for ih ring by psp bl */ 664*bf13cb1fSHuang Rui if ((adev->flags & AMD_IS_APU) || 665*bf13cb1fSHuang Rui (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) 666*bf13cb1fSHuang Rui use_bus_addr = false; 667*bf13cb1fSHuang Rui else 668*bf13cb1fSHuang Rui use_bus_addr = true; 669edc61147SHawking Zhang r = amdgpu_ih_ring_init(adev, &adev->irq.ih, 256 * 1024, use_bus_addr); 670edc61147SHawking Zhang if (r) 671edc61147SHawking Zhang return r; 672edc61147SHawking Zhang 673edc61147SHawking Zhang adev->irq.ih.use_doorbell = true; 674edc61147SHawking Zhang adev->irq.ih.doorbell_index = adev->doorbell_index.ih << 1; 675edc61147SHawking Zhang 676abb6fccbSAlex Sierra adev->irq.ih1.ring_size = 0; 677abb6fccbSAlex Sierra adev->irq.ih2.ring_size = 0; 678abb6fccbSAlex Sierra 679abb6fccbSAlex Sierra if (adev->asic_type < CHIP_NAVI10) { 680ab518012SAlex Sierra r = amdgpu_ih_ring_init(adev, &adev->irq.ih1, PAGE_SIZE, true); 681ab518012SAlex Sierra if (r) 682ab518012SAlex Sierra return r; 683ab518012SAlex Sierra 684ab518012SAlex Sierra adev->irq.ih1.use_doorbell = true; 685abb6fccbSAlex Sierra adev->irq.ih1.doorbell_index = 686abb6fccbSAlex Sierra (adev->doorbell_index.ih + 1) << 1; 687ab518012SAlex Sierra 688ab518012SAlex Sierra r = amdgpu_ih_ring_init(adev, &adev->irq.ih2, PAGE_SIZE, true); 689ab518012SAlex Sierra if (r) 690ab518012SAlex Sierra return r; 691ab518012SAlex Sierra 692ab518012SAlex Sierra adev->irq.ih2.use_doorbell = true; 693abb6fccbSAlex Sierra adev->irq.ih2.doorbell_index = 694abb6fccbSAlex Sierra (adev->doorbell_index.ih + 2) << 1; 695abb6fccbSAlex Sierra } 696ab518012SAlex Sierra 697edc61147SHawking Zhang r = amdgpu_irq_init(adev); 698edc61147SHawking Zhang 699edc61147SHawking Zhang return r; 700edc61147SHawking Zhang } 701edc61147SHawking Zhang 702edc61147SHawking Zhang static int navi10_ih_sw_fini(void *handle) 703edc61147SHawking Zhang { 704edc61147SHawking Zhang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 705edc61147SHawking Zhang 706edc61147SHawking Zhang amdgpu_irq_fini(adev); 707ab518012SAlex Sierra amdgpu_ih_ring_fini(adev, &adev->irq.ih2); 708ab518012SAlex Sierra amdgpu_ih_ring_fini(adev, &adev->irq.ih1); 709edc61147SHawking Zhang amdgpu_ih_ring_fini(adev, &adev->irq.ih); 710edc61147SHawking Zhang 711edc61147SHawking Zhang return 0; 712edc61147SHawking Zhang } 713edc61147SHawking Zhang 714edc61147SHawking Zhang static int navi10_ih_hw_init(void *handle) 715edc61147SHawking Zhang { 716edc61147SHawking Zhang int r; 717edc61147SHawking Zhang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 718edc61147SHawking Zhang 719edc61147SHawking Zhang r = navi10_ih_irq_init(adev); 720edc61147SHawking Zhang if (r) 721edc61147SHawking Zhang return r; 722edc61147SHawking Zhang 723edc61147SHawking Zhang return 0; 724edc61147SHawking Zhang } 725edc61147SHawking Zhang 726edc61147SHawking Zhang static int navi10_ih_hw_fini(void *handle) 727edc61147SHawking Zhang { 728edc61147SHawking Zhang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 729edc61147SHawking Zhang 730edc61147SHawking Zhang navi10_ih_irq_disable(adev); 731edc61147SHawking Zhang 732edc61147SHawking Zhang return 0; 733edc61147SHawking Zhang } 734edc61147SHawking Zhang 735edc61147SHawking Zhang static int navi10_ih_suspend(void *handle) 736edc61147SHawking Zhang { 737edc61147SHawking Zhang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 738edc61147SHawking Zhang 739edc61147SHawking Zhang return navi10_ih_hw_fini(adev); 740edc61147SHawking Zhang } 741edc61147SHawking Zhang 742edc61147SHawking Zhang static int navi10_ih_resume(void *handle) 743edc61147SHawking Zhang { 744edc61147SHawking Zhang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 745edc61147SHawking Zhang 746edc61147SHawking Zhang return navi10_ih_hw_init(adev); 747edc61147SHawking Zhang } 748edc61147SHawking Zhang 749edc61147SHawking Zhang static bool navi10_ih_is_idle(void *handle) 750edc61147SHawking Zhang { 751edc61147SHawking Zhang /* todo */ 752edc61147SHawking Zhang return true; 753edc61147SHawking Zhang } 754edc61147SHawking Zhang 755edc61147SHawking Zhang static int navi10_ih_wait_for_idle(void *handle) 756edc61147SHawking Zhang { 757edc61147SHawking Zhang /* todo */ 758edc61147SHawking Zhang return -ETIMEDOUT; 759edc61147SHawking Zhang } 760edc61147SHawking Zhang 761edc61147SHawking Zhang static int navi10_ih_soft_reset(void *handle) 762edc61147SHawking Zhang { 763edc61147SHawking Zhang /* todo */ 764edc61147SHawking Zhang return 0; 765edc61147SHawking Zhang } 766edc61147SHawking Zhang 767edc61147SHawking Zhang static void navi10_ih_update_clockgating_state(struct amdgpu_device *adev, 768edc61147SHawking Zhang bool enable) 769edc61147SHawking Zhang { 770edc61147SHawking Zhang uint32_t data, def, field_val; 771edc61147SHawking Zhang 772edc61147SHawking Zhang if (adev->cg_flags & AMD_CG_SUPPORT_IH_CG) { 773edc61147SHawking Zhang def = data = RREG32_SOC15(OSSSYS, 0, mmIH_CLK_CTRL); 774edc61147SHawking Zhang field_val = enable ? 0 : 1; 775edc61147SHawking Zhang data = REG_SET_FIELD(data, IH_CLK_CTRL, 776edc61147SHawking Zhang DBUS_MUX_CLK_SOFT_OVERRIDE, field_val); 777edc61147SHawking Zhang data = REG_SET_FIELD(data, IH_CLK_CTRL, 778edc61147SHawking Zhang OSSSYS_SHARE_CLK_SOFT_OVERRIDE, field_val); 779edc61147SHawking Zhang data = REG_SET_FIELD(data, IH_CLK_CTRL, 780edc61147SHawking Zhang LIMIT_SMN_CLK_SOFT_OVERRIDE, field_val); 781edc61147SHawking Zhang data = REG_SET_FIELD(data, IH_CLK_CTRL, 782edc61147SHawking Zhang DYN_CLK_SOFT_OVERRIDE, field_val); 783edc61147SHawking Zhang data = REG_SET_FIELD(data, IH_CLK_CTRL, 784edc61147SHawking Zhang REG_CLK_SOFT_OVERRIDE, field_val); 785edc61147SHawking Zhang if (def != data) 786edc61147SHawking Zhang WREG32_SOC15(OSSSYS, 0, mmIH_CLK_CTRL, data); 787edc61147SHawking Zhang } 788edc61147SHawking Zhang 789edc61147SHawking Zhang return; 790edc61147SHawking Zhang } 791edc61147SHawking Zhang 792edc61147SHawking Zhang static int navi10_ih_set_clockgating_state(void *handle, 793edc61147SHawking Zhang enum amd_clockgating_state state) 794edc61147SHawking Zhang { 795edc61147SHawking Zhang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 796edc61147SHawking Zhang 797edc61147SHawking Zhang navi10_ih_update_clockgating_state(adev, 798a9d4fe2fSNirmoy Das state == AMD_CG_STATE_GATE); 799edc61147SHawking Zhang return 0; 800edc61147SHawking Zhang } 801edc61147SHawking Zhang 802edc61147SHawking Zhang static int navi10_ih_set_powergating_state(void *handle, 803edc61147SHawking Zhang enum amd_powergating_state state) 804edc61147SHawking Zhang { 805edc61147SHawking Zhang return 0; 806edc61147SHawking Zhang } 807edc61147SHawking Zhang 808edc61147SHawking Zhang static void navi10_ih_get_clockgating_state(void *handle, u32 *flags) 809edc61147SHawking Zhang { 810edc61147SHawking Zhang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 811edc61147SHawking Zhang 812edc61147SHawking Zhang if (!RREG32_SOC15(OSSSYS, 0, mmIH_CLK_CTRL)) 813edc61147SHawking Zhang *flags |= AMD_CG_SUPPORT_IH_CG; 814edc61147SHawking Zhang 815edc61147SHawking Zhang return; 816edc61147SHawking Zhang } 817edc61147SHawking Zhang 818edc61147SHawking Zhang static const struct amd_ip_funcs navi10_ih_ip_funcs = { 819edc61147SHawking Zhang .name = "navi10_ih", 820edc61147SHawking Zhang .early_init = navi10_ih_early_init, 821edc61147SHawking Zhang .late_init = NULL, 822edc61147SHawking Zhang .sw_init = navi10_ih_sw_init, 823edc61147SHawking Zhang .sw_fini = navi10_ih_sw_fini, 824edc61147SHawking Zhang .hw_init = navi10_ih_hw_init, 825edc61147SHawking Zhang .hw_fini = navi10_ih_hw_fini, 826edc61147SHawking Zhang .suspend = navi10_ih_suspend, 827edc61147SHawking Zhang .resume = navi10_ih_resume, 828edc61147SHawking Zhang .is_idle = navi10_ih_is_idle, 829edc61147SHawking Zhang .wait_for_idle = navi10_ih_wait_for_idle, 830edc61147SHawking Zhang .soft_reset = navi10_ih_soft_reset, 831edc61147SHawking Zhang .set_clockgating_state = navi10_ih_set_clockgating_state, 832edc61147SHawking Zhang .set_powergating_state = navi10_ih_set_powergating_state, 833edc61147SHawking Zhang .get_clockgating_state = navi10_ih_get_clockgating_state, 834edc61147SHawking Zhang }; 835edc61147SHawking Zhang 836edc61147SHawking Zhang static const struct amdgpu_ih_funcs navi10_ih_funcs = { 837edc61147SHawking Zhang .get_wptr = navi10_ih_get_wptr, 838edc61147SHawking Zhang .decode_iv = navi10_ih_decode_iv, 839edc61147SHawking Zhang .set_rptr = navi10_ih_set_rptr 840edc61147SHawking Zhang }; 841edc61147SHawking Zhang 842edc61147SHawking Zhang static void navi10_ih_set_interrupt_funcs(struct amdgpu_device *adev) 843edc61147SHawking Zhang { 844edc61147SHawking Zhang if (adev->irq.ih_funcs == NULL) 845edc61147SHawking Zhang adev->irq.ih_funcs = &navi10_ih_funcs; 846edc61147SHawking Zhang } 847edc61147SHawking Zhang 848edc61147SHawking Zhang const struct amdgpu_ip_block_version navi10_ih_ip_block = 849edc61147SHawking Zhang { 850edc61147SHawking Zhang .type = AMD_IP_BLOCK_TYPE_IH, 851edc61147SHawking Zhang .major = 5, 852edc61147SHawking Zhang .minor = 0, 853edc61147SHawking Zhang .rev = 0, 854edc61147SHawking Zhang .funcs = &navi10_ih_ip_funcs, 855edc61147SHawking Zhang }; 856