1edc61147SHawking Zhang /* 2edc61147SHawking Zhang * Copyright 2019 Advanced Micro Devices, Inc. 3edc61147SHawking Zhang * 4edc61147SHawking Zhang * Permission is hereby granted, free of charge, to any person obtaining a 5edc61147SHawking Zhang * copy of this software and associated documentation files (the "Software"), 6edc61147SHawking Zhang * to deal in the Software without restriction, including without limitation 7edc61147SHawking Zhang * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8edc61147SHawking Zhang * and/or sell copies of the Software, and to permit persons to whom the 9edc61147SHawking Zhang * Software is furnished to do so, subject to the following conditions: 10edc61147SHawking Zhang * 11edc61147SHawking Zhang * The above copyright notice and this permission notice shall be included in 12edc61147SHawking Zhang * all copies or substantial portions of the Software. 13edc61147SHawking Zhang * 14edc61147SHawking Zhang * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15edc61147SHawking Zhang * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16edc61147SHawking Zhang * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17edc61147SHawking Zhang * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18edc61147SHawking Zhang * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19edc61147SHawking Zhang * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20edc61147SHawking Zhang * OTHER DEALINGS IN THE SOFTWARE. 21edc61147SHawking Zhang * 22edc61147SHawking Zhang */ 23edc61147SHawking Zhang 24b23b2e9eSAlex Deucher #include <linux/pci.h> 25b23b2e9eSAlex Deucher 26edc61147SHawking Zhang #include "amdgpu.h" 27edc61147SHawking Zhang #include "amdgpu_ih.h" 28edc61147SHawking Zhang 29edc61147SHawking Zhang #include "oss/osssys_5_0_0_offset.h" 30edc61147SHawking Zhang #include "oss/osssys_5_0_0_sh_mask.h" 31edc61147SHawking Zhang 32edc61147SHawking Zhang #include "soc15_common.h" 33edc61147SHawking Zhang #include "navi10_ih.h" 34edc61147SHawking Zhang 35022b6518SSamir Dhume #define MAX_REARM_RETRY 10 36edc61147SHawking Zhang 37edc61147SHawking Zhang static void navi10_ih_set_interrupt_funcs(struct amdgpu_device *adev); 38edc61147SHawking Zhang 39edc61147SHawking Zhang /** 40edc61147SHawking Zhang * navi10_ih_enable_interrupts - Enable the interrupt ring buffer 41edc61147SHawking Zhang * 42edc61147SHawking Zhang * @adev: amdgpu_device pointer 43edc61147SHawking Zhang * 44edc61147SHawking Zhang * Enable the interrupt ring buffer (NAVI10). 45edc61147SHawking Zhang */ 46edc61147SHawking Zhang static void navi10_ih_enable_interrupts(struct amdgpu_device *adev) 47edc61147SHawking Zhang { 48edc61147SHawking Zhang u32 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL); 49edc61147SHawking Zhang 50edc61147SHawking Zhang ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 1); 51edc61147SHawking Zhang ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, ENABLE_INTR, 1); 52edc61147SHawking Zhang WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL, ih_rb_cntl); 53edc61147SHawking Zhang adev->irq.ih.enabled = true; 54ab518012SAlex Sierra 55ab518012SAlex Sierra if (adev->irq.ih1.ring_size) { 56ab518012SAlex Sierra ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1); 57ab518012SAlex Sierra ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING1, 58ab518012SAlex Sierra RB_ENABLE, 1); 59ab518012SAlex Sierra WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1, ih_rb_cntl); 60ab518012SAlex Sierra adev->irq.ih1.enabled = true; 61ab518012SAlex Sierra } 62ab518012SAlex Sierra 63ab518012SAlex Sierra if (adev->irq.ih2.ring_size) { 64ab518012SAlex Sierra ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2); 65ab518012SAlex Sierra ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING2, 66ab518012SAlex Sierra RB_ENABLE, 1); 67ab518012SAlex Sierra WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2, ih_rb_cntl); 68ab518012SAlex Sierra adev->irq.ih2.enabled = true; 69ab518012SAlex Sierra } 70edc61147SHawking Zhang } 71edc61147SHawking Zhang 72edc61147SHawking Zhang /** 73edc61147SHawking Zhang * navi10_ih_disable_interrupts - Disable the interrupt ring buffer 74edc61147SHawking Zhang * 75edc61147SHawking Zhang * @adev: amdgpu_device pointer 76edc61147SHawking Zhang * 77edc61147SHawking Zhang * Disable the interrupt ring buffer (NAVI10). 78edc61147SHawking Zhang */ 79edc61147SHawking Zhang static void navi10_ih_disable_interrupts(struct amdgpu_device *adev) 80edc61147SHawking Zhang { 81edc61147SHawking Zhang u32 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL); 82edc61147SHawking Zhang 83edc61147SHawking Zhang ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 0); 84edc61147SHawking Zhang ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, ENABLE_INTR, 0); 85edc61147SHawking Zhang WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL, ih_rb_cntl); 86edc61147SHawking Zhang /* set rptr, wptr to 0 */ 87edc61147SHawking Zhang WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR, 0); 88edc61147SHawking Zhang WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR, 0); 89edc61147SHawking Zhang adev->irq.ih.enabled = false; 90edc61147SHawking Zhang adev->irq.ih.rptr = 0; 91ab518012SAlex Sierra 92ab518012SAlex Sierra if (adev->irq.ih1.ring_size) { 93ab518012SAlex Sierra ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1); 94ab518012SAlex Sierra ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING1, 95ab518012SAlex Sierra RB_ENABLE, 0); 96ab518012SAlex Sierra WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1, ih_rb_cntl); 97ab518012SAlex Sierra /* set rptr, wptr to 0 */ 98ab518012SAlex Sierra WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR_RING1, 0); 99ab518012SAlex Sierra WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_RING1, 0); 100ab518012SAlex Sierra adev->irq.ih1.enabled = false; 101ab518012SAlex Sierra adev->irq.ih1.rptr = 0; 102ab518012SAlex Sierra } 103ab518012SAlex Sierra 104ab518012SAlex Sierra if (adev->irq.ih2.ring_size) { 105ab518012SAlex Sierra ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2); 106ab518012SAlex Sierra ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING2, 107ab518012SAlex Sierra RB_ENABLE, 0); 108ab518012SAlex Sierra WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2, ih_rb_cntl); 109ab518012SAlex Sierra /* set rptr, wptr to 0 */ 110ab518012SAlex Sierra WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR_RING2, 0); 111ab518012SAlex Sierra WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_RING2, 0); 112ab518012SAlex Sierra adev->irq.ih2.enabled = false; 113ab518012SAlex Sierra adev->irq.ih2.rptr = 0; 114ab518012SAlex Sierra } 115ab518012SAlex Sierra 116edc61147SHawking Zhang } 117edc61147SHawking Zhang 118edc61147SHawking Zhang static uint32_t navi10_ih_rb_cntl(struct amdgpu_ih_ring *ih, uint32_t ih_rb_cntl) 119edc61147SHawking Zhang { 120edc61147SHawking Zhang int rb_bufsz = order_base_2(ih->ring_size / 4); 121edc61147SHawking Zhang 122edc61147SHawking Zhang ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, 123edc61147SHawking Zhang MC_SPACE, ih->use_bus_addr ? 1 : 4); 124edc61147SHawking Zhang ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, 125edc61147SHawking Zhang WPTR_OVERFLOW_CLEAR, 1); 126edc61147SHawking Zhang ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, 127edc61147SHawking Zhang WPTR_OVERFLOW_ENABLE, 1); 128edc61147SHawking Zhang ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_SIZE, rb_bufsz); 129edc61147SHawking Zhang /* Ring Buffer write pointer writeback. If enabled, IH_RB_WPTR register 130edc61147SHawking Zhang * value is written to memory 131edc61147SHawking Zhang */ 132edc61147SHawking Zhang ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, 133edc61147SHawking Zhang WPTR_WRITEBACK_ENABLE, 1); 134edc61147SHawking Zhang ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_SNOOP, 1); 135edc61147SHawking Zhang ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_RO, 0); 136edc61147SHawking Zhang ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_VMID, 0); 137edc61147SHawking Zhang 138edc61147SHawking Zhang return ih_rb_cntl; 139edc61147SHawking Zhang } 140edc61147SHawking Zhang 141ab518012SAlex Sierra static uint32_t navi10_ih_doorbell_rptr(struct amdgpu_ih_ring *ih) 142ab518012SAlex Sierra { 143ab518012SAlex Sierra u32 ih_doorbell_rtpr = 0; 144ab518012SAlex Sierra 145ab518012SAlex Sierra if (ih->use_doorbell) { 146ab518012SAlex Sierra ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr, 147ab518012SAlex Sierra IH_DOORBELL_RPTR, OFFSET, 148ab518012SAlex Sierra ih->doorbell_index); 149ab518012SAlex Sierra ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr, 150ab518012SAlex Sierra IH_DOORBELL_RPTR, 151ab518012SAlex Sierra ENABLE, 1); 152ab518012SAlex Sierra } else { 153ab518012SAlex Sierra ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr, 154ab518012SAlex Sierra IH_DOORBELL_RPTR, 155ab518012SAlex Sierra ENABLE, 0); 156ab518012SAlex Sierra } 157ab518012SAlex Sierra return ih_doorbell_rtpr; 158ab518012SAlex Sierra } 159ab518012SAlex Sierra 160edc61147SHawking Zhang /** 161edc61147SHawking Zhang * navi10_ih_irq_init - init and enable the interrupt ring 162edc61147SHawking Zhang * 163edc61147SHawking Zhang * @adev: amdgpu_device pointer 164edc61147SHawking Zhang * 165edc61147SHawking Zhang * Allocate a ring buffer for the interrupt controller, 166edc61147SHawking Zhang * enable the RLC, disable interrupts, enable the IH 167edc61147SHawking Zhang * ring buffer and enable it (NAVI). 168edc61147SHawking Zhang * Called at device load and reume. 169edc61147SHawking Zhang * Returns 0 for success, errors for failure. 170edc61147SHawking Zhang */ 171edc61147SHawking Zhang static int navi10_ih_irq_init(struct amdgpu_device *adev) 172edc61147SHawking Zhang { 173edc61147SHawking Zhang struct amdgpu_ih_ring *ih = &adev->irq.ih; 174ab518012SAlex Sierra u32 ih_rb_cntl, ih_chicken; 175edc61147SHawking Zhang u32 tmp; 176edc61147SHawking Zhang 177edc61147SHawking Zhang /* disable irqs */ 178edc61147SHawking Zhang navi10_ih_disable_interrupts(adev); 179edc61147SHawking Zhang 180bebc0762SHawking Zhang adev->nbio.funcs->ih_control(adev); 181edc61147SHawking Zhang 182edc61147SHawking Zhang /* Ring Buffer base. [39:8] of 40-bit address of the beginning of the ring buffer*/ 183edc61147SHawking Zhang WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE, ih->gpu_addr >> 8); 184edc61147SHawking Zhang WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE_HI, (ih->gpu_addr >> 40) & 0xff); 185edc61147SHawking Zhang 186edc61147SHawking Zhang ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL); 187edc61147SHawking Zhang ih_rb_cntl = navi10_ih_rb_cntl(ih, ih_rb_cntl); 188edc61147SHawking Zhang ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RPTR_REARM, 189edc61147SHawking Zhang !!adev->irq.msi_enabled); 190edc61147SHawking Zhang 191edc61147SHawking Zhang if (unlikely(adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT)) { 192edc61147SHawking Zhang if (ih->use_bus_addr) { 193edc61147SHawking Zhang ih_chicken = RREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN); 194edc61147SHawking Zhang ih_chicken = REG_SET_FIELD(ih_chicken, 195edc61147SHawking Zhang IH_CHICKEN, MC_SPACE_GPA_ENABLE, 1); 196edc61147SHawking Zhang WREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN, ih_chicken); 197edc61147SHawking Zhang } 198edc61147SHawking Zhang } 199edc61147SHawking Zhang 200edc61147SHawking Zhang WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL, ih_rb_cntl); 201edc61147SHawking Zhang 202edc61147SHawking Zhang /* set the writeback address whether it's enabled or not */ 203edc61147SHawking Zhang WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_ADDR_LO, 204edc61147SHawking Zhang lower_32_bits(ih->wptr_addr)); 205edc61147SHawking Zhang WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_ADDR_HI, 206edc61147SHawking Zhang upper_32_bits(ih->wptr_addr) & 0xFFFF); 207edc61147SHawking Zhang 208edc61147SHawking Zhang /* set rptr, wptr to 0 */ 209edc61147SHawking Zhang WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR, 0); 210edc61147SHawking Zhang WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR, 0); 211edc61147SHawking Zhang 212ab518012SAlex Sierra WREG32_SOC15(OSSSYS, 0, mmIH_DOORBELL_RPTR, 213ab518012SAlex Sierra navi10_ih_doorbell_rptr(ih)); 214edc61147SHawking Zhang 215bebc0762SHawking Zhang adev->nbio.funcs->ih_doorbell_range(adev, ih->use_doorbell, 216edc61147SHawking Zhang ih->doorbell_index); 217edc61147SHawking Zhang 218ab518012SAlex Sierra ih = &adev->irq.ih1; 219ab518012SAlex Sierra if (ih->ring_size) { 220ab518012SAlex Sierra WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE_RING1, ih->gpu_addr >> 8); 221ab518012SAlex Sierra WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE_HI_RING1, 222ab518012SAlex Sierra (ih->gpu_addr >> 40) & 0xff); 223ab518012SAlex Sierra 224ab518012SAlex Sierra ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1); 225ab518012SAlex Sierra ih_rb_cntl = navi10_ih_rb_cntl(ih, ih_rb_cntl); 226ab518012SAlex Sierra ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, 227ab518012SAlex Sierra WPTR_OVERFLOW_ENABLE, 0); 228ab518012SAlex Sierra ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, 229ab518012SAlex Sierra RB_FULL_DRAIN_ENABLE, 1); 230ab518012SAlex Sierra WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1, ih_rb_cntl); 231ab518012SAlex Sierra /* set rptr, wptr to 0 */ 232ab518012SAlex Sierra WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_RING1, 0); 233ab518012SAlex Sierra WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR_RING1, 0); 234ab518012SAlex Sierra 235ab518012SAlex Sierra WREG32_SOC15(OSSSYS, 0, mmIH_DOORBELL_RPTR_RING1, 236ab518012SAlex Sierra navi10_ih_doorbell_rptr(ih)); 237ab518012SAlex Sierra } 238ab518012SAlex Sierra 239ab518012SAlex Sierra ih = &adev->irq.ih2; 240ab518012SAlex Sierra if (ih->ring_size) { 241ab518012SAlex Sierra WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE_RING2, ih->gpu_addr >> 8); 242ab518012SAlex Sierra WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE_HI_RING2, 243ab518012SAlex Sierra (ih->gpu_addr >> 40) & 0xff); 244ab518012SAlex Sierra 245ab518012SAlex Sierra ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2); 246ab518012SAlex Sierra ih_rb_cntl = navi10_ih_rb_cntl(ih, ih_rb_cntl); 247ab518012SAlex Sierra 248ab518012SAlex Sierra WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2, ih_rb_cntl); 249ab518012SAlex Sierra /* set rptr, wptr to 0 */ 250ab518012SAlex Sierra WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_RING2, 0); 251ab518012SAlex Sierra WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR_RING2, 0); 252ab518012SAlex Sierra 253ab518012SAlex Sierra WREG32_SOC15(OSSSYS, 0, mmIH_DOORBELL_RPTR_RING2, 254ab518012SAlex Sierra navi10_ih_doorbell_rptr(ih)); 255ab518012SAlex Sierra } 256ab518012SAlex Sierra 257ab518012SAlex Sierra 258edc61147SHawking Zhang tmp = RREG32_SOC15(OSSSYS, 0, mmIH_STORM_CLIENT_LIST_CNTL); 259edc61147SHawking Zhang tmp = REG_SET_FIELD(tmp, IH_STORM_CLIENT_LIST_CNTL, 260edc61147SHawking Zhang CLIENT18_IS_STORM_CLIENT, 1); 261edc61147SHawking Zhang WREG32_SOC15(OSSSYS, 0, mmIH_STORM_CLIENT_LIST_CNTL, tmp); 262edc61147SHawking Zhang 263edc61147SHawking Zhang tmp = RREG32_SOC15(OSSSYS, 0, mmIH_INT_FLOOD_CNTL); 264edc61147SHawking Zhang tmp = REG_SET_FIELD(tmp, IH_INT_FLOOD_CNTL, FLOOD_CNTL_ENABLE, 1); 265edc61147SHawking Zhang WREG32_SOC15(OSSSYS, 0, mmIH_INT_FLOOD_CNTL, tmp); 266edc61147SHawking Zhang 267edc61147SHawking Zhang pci_set_master(adev->pdev); 268edc61147SHawking Zhang 269edc61147SHawking Zhang /* enable interrupts */ 270edc61147SHawking Zhang navi10_ih_enable_interrupts(adev); 271edc61147SHawking Zhang 2727eca4006SMa Feng return 0; 273edc61147SHawking Zhang } 274edc61147SHawking Zhang 275edc61147SHawking Zhang /** 276edc61147SHawking Zhang * navi10_ih_irq_disable - disable interrupts 277edc61147SHawking Zhang * 278edc61147SHawking Zhang * @adev: amdgpu_device pointer 279edc61147SHawking Zhang * 280edc61147SHawking Zhang * Disable interrupts on the hw (NAVI10). 281edc61147SHawking Zhang */ 282edc61147SHawking Zhang static void navi10_ih_irq_disable(struct amdgpu_device *adev) 283edc61147SHawking Zhang { 284edc61147SHawking Zhang navi10_ih_disable_interrupts(adev); 285edc61147SHawking Zhang 286edc61147SHawking Zhang /* Wait and acknowledge irq */ 287edc61147SHawking Zhang mdelay(1); 288edc61147SHawking Zhang } 289edc61147SHawking Zhang 290edc61147SHawking Zhang /** 291edc61147SHawking Zhang * navi10_ih_get_wptr - get the IH ring buffer wptr 292edc61147SHawking Zhang * 293edc61147SHawking Zhang * @adev: amdgpu_device pointer 294edc61147SHawking Zhang * 295edc61147SHawking Zhang * Get the IH ring buffer wptr from either the register 296edc61147SHawking Zhang * or the writeback memory buffer (NAVI10). Also check for 297edc61147SHawking Zhang * ring buffer overflow and deal with it. 298edc61147SHawking Zhang * Returns the value of the wptr. 299edc61147SHawking Zhang */ 300edc61147SHawking Zhang static u32 navi10_ih_get_wptr(struct amdgpu_device *adev, 301edc61147SHawking Zhang struct amdgpu_ih_ring *ih) 302edc61147SHawking Zhang { 303edc61147SHawking Zhang u32 wptr, reg, tmp; 304edc61147SHawking Zhang 305edc61147SHawking Zhang wptr = le32_to_cpu(*ih->wptr_cpu); 306edc61147SHawking Zhang 307edc61147SHawking Zhang if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) 308edc61147SHawking Zhang goto out; 309edc61147SHawking Zhang 310ab518012SAlex Sierra if (ih == &adev->irq.ih) 311edc61147SHawking Zhang reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR); 312ab518012SAlex Sierra else if (ih == &adev->irq.ih1) 313ab518012SAlex Sierra reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_RING1); 314ab518012SAlex Sierra else if (ih == &adev->irq.ih2) 315ab518012SAlex Sierra reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_RING2); 316ab518012SAlex Sierra else 317ab518012SAlex Sierra BUG(); 318ab518012SAlex Sierra 319edc61147SHawking Zhang wptr = RREG32_NO_KIQ(reg); 320edc61147SHawking Zhang if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) 321edc61147SHawking Zhang goto out; 322edc61147SHawking Zhang wptr = REG_SET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW, 0); 323edc61147SHawking Zhang 324edc61147SHawking Zhang /* When a ring buffer overflow happen start parsing interrupt 325edc61147SHawking Zhang * from the last not overwritten vector (wptr + 32). Hopefully 326edc61147SHawking Zhang * this should allow us to catch up. 327edc61147SHawking Zhang */ 328edc61147SHawking Zhang tmp = (wptr + 32) & ih->ptr_mask; 329edc61147SHawking Zhang dev_warn(adev->dev, "IH ring buffer overflow " 330edc61147SHawking Zhang "(0x%08X, 0x%08X, 0x%08X)\n", 331edc61147SHawking Zhang wptr, ih->rptr, tmp); 332edc61147SHawking Zhang ih->rptr = tmp; 333edc61147SHawking Zhang 334ab518012SAlex Sierra if (ih == &adev->irq.ih) 335edc61147SHawking Zhang reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL); 336ab518012SAlex Sierra else if (ih == &adev->irq.ih1) 337ab518012SAlex Sierra reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL_RING1); 338ab518012SAlex Sierra else if (ih == &adev->irq.ih2) 339ab518012SAlex Sierra reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL_RING2); 340ab518012SAlex Sierra else 341ab518012SAlex Sierra BUG(); 342ab518012SAlex Sierra 343edc61147SHawking Zhang tmp = RREG32_NO_KIQ(reg); 344edc61147SHawking Zhang tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1); 345edc61147SHawking Zhang WREG32_NO_KIQ(reg, tmp); 346edc61147SHawking Zhang out: 347edc61147SHawking Zhang return (wptr & ih->ptr_mask); 348edc61147SHawking Zhang } 349edc61147SHawking Zhang 350edc61147SHawking Zhang /** 351edc61147SHawking Zhang * navi10_ih_decode_iv - decode an interrupt vector 352edc61147SHawking Zhang * 353edc61147SHawking Zhang * @adev: amdgpu_device pointer 354edc61147SHawking Zhang * 355edc61147SHawking Zhang * Decodes the interrupt vector at the current rptr 356edc61147SHawking Zhang * position and also advance the position. 357edc61147SHawking Zhang */ 358edc61147SHawking Zhang static void navi10_ih_decode_iv(struct amdgpu_device *adev, 359edc61147SHawking Zhang struct amdgpu_ih_ring *ih, 360edc61147SHawking Zhang struct amdgpu_iv_entry *entry) 361edc61147SHawking Zhang { 362edc61147SHawking Zhang /* wptr/rptr are in bytes! */ 363edc61147SHawking Zhang u32 ring_index = ih->rptr >> 2; 364edc61147SHawking Zhang uint32_t dw[8]; 365edc61147SHawking Zhang 366edc61147SHawking Zhang dw[0] = le32_to_cpu(ih->ring[ring_index + 0]); 367edc61147SHawking Zhang dw[1] = le32_to_cpu(ih->ring[ring_index + 1]); 368edc61147SHawking Zhang dw[2] = le32_to_cpu(ih->ring[ring_index + 2]); 369edc61147SHawking Zhang dw[3] = le32_to_cpu(ih->ring[ring_index + 3]); 370edc61147SHawking Zhang dw[4] = le32_to_cpu(ih->ring[ring_index + 4]); 371edc61147SHawking Zhang dw[5] = le32_to_cpu(ih->ring[ring_index + 5]); 372edc61147SHawking Zhang dw[6] = le32_to_cpu(ih->ring[ring_index + 6]); 373edc61147SHawking Zhang dw[7] = le32_to_cpu(ih->ring[ring_index + 7]); 374edc61147SHawking Zhang 375edc61147SHawking Zhang entry->client_id = dw[0] & 0xff; 376edc61147SHawking Zhang entry->src_id = (dw[0] >> 8) & 0xff; 377edc61147SHawking Zhang entry->ring_id = (dw[0] >> 16) & 0xff; 378edc61147SHawking Zhang entry->vmid = (dw[0] >> 24) & 0xf; 379edc61147SHawking Zhang entry->vmid_src = (dw[0] >> 31); 380edc61147SHawking Zhang entry->timestamp = dw[1] | ((u64)(dw[2] & 0xffff) << 32); 381edc61147SHawking Zhang entry->timestamp_src = dw[2] >> 31; 382edc61147SHawking Zhang entry->pasid = dw[3] & 0xffff; 383edc61147SHawking Zhang entry->pasid_src = dw[3] >> 31; 384edc61147SHawking Zhang entry->src_data[0] = dw[4]; 385edc61147SHawking Zhang entry->src_data[1] = dw[5]; 386edc61147SHawking Zhang entry->src_data[2] = dw[6]; 387edc61147SHawking Zhang entry->src_data[3] = dw[7]; 388edc61147SHawking Zhang 389edc61147SHawking Zhang /* wptr/rptr are in bytes! */ 390edc61147SHawking Zhang ih->rptr += 32; 391edc61147SHawking Zhang } 392edc61147SHawking Zhang 393edc61147SHawking Zhang /** 394022b6518SSamir Dhume * navi10_ih_irq_rearm - rearm IRQ if lost 395022b6518SSamir Dhume * 396022b6518SSamir Dhume * @adev: amdgpu_device pointer 397022b6518SSamir Dhume * 398022b6518SSamir Dhume */ 399022b6518SSamir Dhume static void navi10_ih_irq_rearm(struct amdgpu_device *adev, 400022b6518SSamir Dhume struct amdgpu_ih_ring *ih) 401022b6518SSamir Dhume { 402022b6518SSamir Dhume uint32_t reg_rptr = 0; 403022b6518SSamir Dhume uint32_t v = 0; 404022b6518SSamir Dhume uint32_t i = 0; 405022b6518SSamir Dhume 406022b6518SSamir Dhume if (ih == &adev->irq.ih) 407022b6518SSamir Dhume reg_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR); 408022b6518SSamir Dhume else if (ih == &adev->irq.ih1) 409022b6518SSamir Dhume reg_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR_RING1); 410022b6518SSamir Dhume else if (ih == &adev->irq.ih2) 411022b6518SSamir Dhume reg_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR_RING2); 412022b6518SSamir Dhume else 413022b6518SSamir Dhume return; 414022b6518SSamir Dhume 415022b6518SSamir Dhume /* Rearm IRQ / re-write doorbell if doorbell write is lost */ 416022b6518SSamir Dhume for (i = 0; i < MAX_REARM_RETRY; i++) { 417022b6518SSamir Dhume v = RREG32_NO_KIQ(reg_rptr); 418022b6518SSamir Dhume if ((v < ih->ring_size) && (v != ih->rptr)) 419022b6518SSamir Dhume WDOORBELL32(ih->doorbell_index, ih->rptr); 420022b6518SSamir Dhume else 421022b6518SSamir Dhume break; 422022b6518SSamir Dhume } 423022b6518SSamir Dhume } 424022b6518SSamir Dhume 425022b6518SSamir Dhume /** 426edc61147SHawking Zhang * navi10_ih_set_rptr - set the IH ring buffer rptr 427edc61147SHawking Zhang * 428edc61147SHawking Zhang * @adev: amdgpu_device pointer 429edc61147SHawking Zhang * 430edc61147SHawking Zhang * Set the IH ring buffer rptr. 431edc61147SHawking Zhang */ 432edc61147SHawking Zhang static void navi10_ih_set_rptr(struct amdgpu_device *adev, 433edc61147SHawking Zhang struct amdgpu_ih_ring *ih) 434edc61147SHawking Zhang { 435edc61147SHawking Zhang if (ih->use_doorbell) { 436edc61147SHawking Zhang /* XXX check if swapping is necessary on BE */ 437edc61147SHawking Zhang *ih->rptr_cpu = ih->rptr; 438edc61147SHawking Zhang WDOORBELL32(ih->doorbell_index, ih->rptr); 439022b6518SSamir Dhume 440022b6518SSamir Dhume if (amdgpu_sriov_vf(adev)) 441022b6518SSamir Dhume navi10_ih_irq_rearm(adev, ih); 442ab518012SAlex Sierra } else if (ih == &adev->irq.ih) { 443edc61147SHawking Zhang WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR, ih->rptr); 444ab518012SAlex Sierra } else if (ih == &adev->irq.ih1) { 445ab518012SAlex Sierra WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR_RING1, ih->rptr); 446ab518012SAlex Sierra } else if (ih == &adev->irq.ih2) { 447ab518012SAlex Sierra WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR_RING2, ih->rptr); 448ab518012SAlex Sierra } 449ab518012SAlex Sierra } 450ab518012SAlex Sierra 451ab518012SAlex Sierra /** 452ab518012SAlex Sierra * navi10_ih_self_irq - dispatch work for ring 1 and 2 453ab518012SAlex Sierra * 454ab518012SAlex Sierra * @adev: amdgpu_device pointer 455ab518012SAlex Sierra * @source: irq source 456ab518012SAlex Sierra * @entry: IV with WPTR update 457ab518012SAlex Sierra * 458ab518012SAlex Sierra * Update the WPTR from the IV and schedule work to handle the entries. 459ab518012SAlex Sierra */ 460ab518012SAlex Sierra static int navi10_ih_self_irq(struct amdgpu_device *adev, 461ab518012SAlex Sierra struct amdgpu_irq_src *source, 462ab518012SAlex Sierra struct amdgpu_iv_entry *entry) 463ab518012SAlex Sierra { 464ab518012SAlex Sierra uint32_t wptr = cpu_to_le32(entry->src_data[0]); 465ab518012SAlex Sierra 466ab518012SAlex Sierra switch (entry->ring_id) { 467ab518012SAlex Sierra case 1: 468ab518012SAlex Sierra *adev->irq.ih1.wptr_cpu = wptr; 469ab518012SAlex Sierra schedule_work(&adev->irq.ih1_work); 470ab518012SAlex Sierra break; 471ab518012SAlex Sierra case 2: 472ab518012SAlex Sierra *adev->irq.ih2.wptr_cpu = wptr; 473ab518012SAlex Sierra schedule_work(&adev->irq.ih2_work); 474ab518012SAlex Sierra break; 475ab518012SAlex Sierra default: break; 476ab518012SAlex Sierra } 477ab518012SAlex Sierra return 0; 478ab518012SAlex Sierra } 479ab518012SAlex Sierra 480ab518012SAlex Sierra static const struct amdgpu_irq_src_funcs navi10_ih_self_irq_funcs = { 481ab518012SAlex Sierra .process = navi10_ih_self_irq, 482ab518012SAlex Sierra }; 483ab518012SAlex Sierra 484ab518012SAlex Sierra static void navi10_ih_set_self_irq_funcs(struct amdgpu_device *adev) 485ab518012SAlex Sierra { 486ab518012SAlex Sierra adev->irq.self_irq.num_types = 0; 487ab518012SAlex Sierra adev->irq.self_irq.funcs = &navi10_ih_self_irq_funcs; 488edc61147SHawking Zhang } 489edc61147SHawking Zhang 490edc61147SHawking Zhang static int navi10_ih_early_init(void *handle) 491edc61147SHawking Zhang { 492edc61147SHawking Zhang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 493edc61147SHawking Zhang 494edc61147SHawking Zhang navi10_ih_set_interrupt_funcs(adev); 495ab518012SAlex Sierra navi10_ih_set_self_irq_funcs(adev); 496edc61147SHawking Zhang return 0; 497edc61147SHawking Zhang } 498edc61147SHawking Zhang 499edc61147SHawking Zhang static int navi10_ih_sw_init(void *handle) 500edc61147SHawking Zhang { 501edc61147SHawking Zhang int r; 502edc61147SHawking Zhang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 503edc61147SHawking Zhang bool use_bus_addr; 504edc61147SHawking Zhang 505ab518012SAlex Sierra r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_IH, 0, 506ab518012SAlex Sierra &adev->irq.self_irq); 507ab518012SAlex Sierra 508ab518012SAlex Sierra if (r) 509ab518012SAlex Sierra return r; 510ab518012SAlex Sierra 511edc61147SHawking Zhang /* use gpu virtual address for ih ring 512edc61147SHawking Zhang * until ih_checken is programmed to allow 513edc61147SHawking Zhang * use bus address for ih ring by psp bl */ 514edc61147SHawking Zhang use_bus_addr = 515edc61147SHawking Zhang (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) ? false : true; 516edc61147SHawking Zhang r = amdgpu_ih_ring_init(adev, &adev->irq.ih, 256 * 1024, use_bus_addr); 517edc61147SHawking Zhang if (r) 518edc61147SHawking Zhang return r; 519edc61147SHawking Zhang 520edc61147SHawking Zhang adev->irq.ih.use_doorbell = true; 521edc61147SHawking Zhang adev->irq.ih.doorbell_index = adev->doorbell_index.ih << 1; 522edc61147SHawking Zhang 523ab518012SAlex Sierra r = amdgpu_ih_ring_init(adev, &adev->irq.ih1, PAGE_SIZE, true); 524ab518012SAlex Sierra if (r) 525ab518012SAlex Sierra return r; 526ab518012SAlex Sierra 527ab518012SAlex Sierra adev->irq.ih1.use_doorbell = true; 528ab518012SAlex Sierra adev->irq.ih1.doorbell_index = (adev->doorbell_index.ih + 1) << 1; 529ab518012SAlex Sierra 530ab518012SAlex Sierra r = amdgpu_ih_ring_init(adev, &adev->irq.ih2, PAGE_SIZE, true); 531ab518012SAlex Sierra if (r) 532ab518012SAlex Sierra return r; 533ab518012SAlex Sierra 534ab518012SAlex Sierra adev->irq.ih2.use_doorbell = true; 535ab518012SAlex Sierra adev->irq.ih2.doorbell_index = (adev->doorbell_index.ih + 2) << 1; 536ab518012SAlex Sierra 537edc61147SHawking Zhang r = amdgpu_irq_init(adev); 538edc61147SHawking Zhang 539edc61147SHawking Zhang return r; 540edc61147SHawking Zhang } 541edc61147SHawking Zhang 542edc61147SHawking Zhang static int navi10_ih_sw_fini(void *handle) 543edc61147SHawking Zhang { 544edc61147SHawking Zhang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 545edc61147SHawking Zhang 546edc61147SHawking Zhang amdgpu_irq_fini(adev); 547ab518012SAlex Sierra amdgpu_ih_ring_fini(adev, &adev->irq.ih2); 548ab518012SAlex Sierra amdgpu_ih_ring_fini(adev, &adev->irq.ih1); 549edc61147SHawking Zhang amdgpu_ih_ring_fini(adev, &adev->irq.ih); 550edc61147SHawking Zhang 551edc61147SHawking Zhang return 0; 552edc61147SHawking Zhang } 553edc61147SHawking Zhang 554edc61147SHawking Zhang static int navi10_ih_hw_init(void *handle) 555edc61147SHawking Zhang { 556edc61147SHawking Zhang int r; 557edc61147SHawking Zhang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 558edc61147SHawking Zhang 559edc61147SHawking Zhang r = navi10_ih_irq_init(adev); 560edc61147SHawking Zhang if (r) 561edc61147SHawking Zhang return r; 562edc61147SHawking Zhang 563edc61147SHawking Zhang return 0; 564edc61147SHawking Zhang } 565edc61147SHawking Zhang 566edc61147SHawking Zhang static int navi10_ih_hw_fini(void *handle) 567edc61147SHawking Zhang { 568edc61147SHawking Zhang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 569edc61147SHawking Zhang 570edc61147SHawking Zhang navi10_ih_irq_disable(adev); 571edc61147SHawking Zhang 572edc61147SHawking Zhang return 0; 573edc61147SHawking Zhang } 574edc61147SHawking Zhang 575edc61147SHawking Zhang static int navi10_ih_suspend(void *handle) 576edc61147SHawking Zhang { 577edc61147SHawking Zhang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 578edc61147SHawking Zhang 579edc61147SHawking Zhang return navi10_ih_hw_fini(adev); 580edc61147SHawking Zhang } 581edc61147SHawking Zhang 582edc61147SHawking Zhang static int navi10_ih_resume(void *handle) 583edc61147SHawking Zhang { 584edc61147SHawking Zhang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 585edc61147SHawking Zhang 586edc61147SHawking Zhang return navi10_ih_hw_init(adev); 587edc61147SHawking Zhang } 588edc61147SHawking Zhang 589edc61147SHawking Zhang static bool navi10_ih_is_idle(void *handle) 590edc61147SHawking Zhang { 591edc61147SHawking Zhang /* todo */ 592edc61147SHawking Zhang return true; 593edc61147SHawking Zhang } 594edc61147SHawking Zhang 595edc61147SHawking Zhang static int navi10_ih_wait_for_idle(void *handle) 596edc61147SHawking Zhang { 597edc61147SHawking Zhang /* todo */ 598edc61147SHawking Zhang return -ETIMEDOUT; 599edc61147SHawking Zhang } 600edc61147SHawking Zhang 601edc61147SHawking Zhang static int navi10_ih_soft_reset(void *handle) 602edc61147SHawking Zhang { 603edc61147SHawking Zhang /* todo */ 604edc61147SHawking Zhang return 0; 605edc61147SHawking Zhang } 606edc61147SHawking Zhang 607edc61147SHawking Zhang static void navi10_ih_update_clockgating_state(struct amdgpu_device *adev, 608edc61147SHawking Zhang bool enable) 609edc61147SHawking Zhang { 610edc61147SHawking Zhang uint32_t data, def, field_val; 611edc61147SHawking Zhang 612edc61147SHawking Zhang if (adev->cg_flags & AMD_CG_SUPPORT_IH_CG) { 613edc61147SHawking Zhang def = data = RREG32_SOC15(OSSSYS, 0, mmIH_CLK_CTRL); 614edc61147SHawking Zhang field_val = enable ? 0 : 1; 615edc61147SHawking Zhang data = REG_SET_FIELD(data, IH_CLK_CTRL, 616edc61147SHawking Zhang DBUS_MUX_CLK_SOFT_OVERRIDE, field_val); 617edc61147SHawking Zhang data = REG_SET_FIELD(data, IH_CLK_CTRL, 618edc61147SHawking Zhang OSSSYS_SHARE_CLK_SOFT_OVERRIDE, field_val); 619edc61147SHawking Zhang data = REG_SET_FIELD(data, IH_CLK_CTRL, 620edc61147SHawking Zhang LIMIT_SMN_CLK_SOFT_OVERRIDE, field_val); 621edc61147SHawking Zhang data = REG_SET_FIELD(data, IH_CLK_CTRL, 622edc61147SHawking Zhang DYN_CLK_SOFT_OVERRIDE, field_val); 623edc61147SHawking Zhang data = REG_SET_FIELD(data, IH_CLK_CTRL, 624edc61147SHawking Zhang REG_CLK_SOFT_OVERRIDE, field_val); 625edc61147SHawking Zhang if (def != data) 626edc61147SHawking Zhang WREG32_SOC15(OSSSYS, 0, mmIH_CLK_CTRL, data); 627edc61147SHawking Zhang } 628edc61147SHawking Zhang 629edc61147SHawking Zhang return; 630edc61147SHawking Zhang } 631edc61147SHawking Zhang 632edc61147SHawking Zhang static int navi10_ih_set_clockgating_state(void *handle, 633edc61147SHawking Zhang enum amd_clockgating_state state) 634edc61147SHawking Zhang { 635edc61147SHawking Zhang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 636edc61147SHawking Zhang 637edc61147SHawking Zhang navi10_ih_update_clockgating_state(adev, 638a9d4fe2fSNirmoy Das state == AMD_CG_STATE_GATE); 639edc61147SHawking Zhang return 0; 640edc61147SHawking Zhang } 641edc61147SHawking Zhang 642edc61147SHawking Zhang static int navi10_ih_set_powergating_state(void *handle, 643edc61147SHawking Zhang enum amd_powergating_state state) 644edc61147SHawking Zhang { 645edc61147SHawking Zhang return 0; 646edc61147SHawking Zhang } 647edc61147SHawking Zhang 648edc61147SHawking Zhang static void navi10_ih_get_clockgating_state(void *handle, u32 *flags) 649edc61147SHawking Zhang { 650edc61147SHawking Zhang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 651edc61147SHawking Zhang 652edc61147SHawking Zhang if (!RREG32_SOC15(OSSSYS, 0, mmIH_CLK_CTRL)) 653edc61147SHawking Zhang *flags |= AMD_CG_SUPPORT_IH_CG; 654edc61147SHawking Zhang 655edc61147SHawking Zhang return; 656edc61147SHawking Zhang } 657edc61147SHawking Zhang 658edc61147SHawking Zhang static const struct amd_ip_funcs navi10_ih_ip_funcs = { 659edc61147SHawking Zhang .name = "navi10_ih", 660edc61147SHawking Zhang .early_init = navi10_ih_early_init, 661edc61147SHawking Zhang .late_init = NULL, 662edc61147SHawking Zhang .sw_init = navi10_ih_sw_init, 663edc61147SHawking Zhang .sw_fini = navi10_ih_sw_fini, 664edc61147SHawking Zhang .hw_init = navi10_ih_hw_init, 665edc61147SHawking Zhang .hw_fini = navi10_ih_hw_fini, 666edc61147SHawking Zhang .suspend = navi10_ih_suspend, 667edc61147SHawking Zhang .resume = navi10_ih_resume, 668edc61147SHawking Zhang .is_idle = navi10_ih_is_idle, 669edc61147SHawking Zhang .wait_for_idle = navi10_ih_wait_for_idle, 670edc61147SHawking Zhang .soft_reset = navi10_ih_soft_reset, 671edc61147SHawking Zhang .set_clockgating_state = navi10_ih_set_clockgating_state, 672edc61147SHawking Zhang .set_powergating_state = navi10_ih_set_powergating_state, 673edc61147SHawking Zhang .get_clockgating_state = navi10_ih_get_clockgating_state, 674edc61147SHawking Zhang }; 675edc61147SHawking Zhang 676edc61147SHawking Zhang static const struct amdgpu_ih_funcs navi10_ih_funcs = { 677edc61147SHawking Zhang .get_wptr = navi10_ih_get_wptr, 678edc61147SHawking Zhang .decode_iv = navi10_ih_decode_iv, 679edc61147SHawking Zhang .set_rptr = navi10_ih_set_rptr 680edc61147SHawking Zhang }; 681edc61147SHawking Zhang 682edc61147SHawking Zhang static void navi10_ih_set_interrupt_funcs(struct amdgpu_device *adev) 683edc61147SHawking Zhang { 684edc61147SHawking Zhang if (adev->irq.ih_funcs == NULL) 685edc61147SHawking Zhang adev->irq.ih_funcs = &navi10_ih_funcs; 686edc61147SHawking Zhang } 687edc61147SHawking Zhang 688edc61147SHawking Zhang const struct amdgpu_ip_block_version navi10_ih_ip_block = 689edc61147SHawking Zhang { 690edc61147SHawking Zhang .type = AMD_IP_BLOCK_TYPE_IH, 691edc61147SHawking Zhang .major = 5, 692edc61147SHawking Zhang .minor = 0, 693edc61147SHawking Zhang .rev = 0, 694edc61147SHawking Zhang .funcs = &navi10_ih_ip_funcs, 695edc61147SHawking Zhang }; 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