1edc61147SHawking Zhang /* 2edc61147SHawking Zhang * Copyright 2019 Advanced Micro Devices, Inc. 3edc61147SHawking Zhang * 4edc61147SHawking Zhang * Permission is hereby granted, free of charge, to any person obtaining a 5edc61147SHawking Zhang * copy of this software and associated documentation files (the "Software"), 6edc61147SHawking Zhang * to deal in the Software without restriction, including without limitation 7edc61147SHawking Zhang * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8edc61147SHawking Zhang * and/or sell copies of the Software, and to permit persons to whom the 9edc61147SHawking Zhang * Software is furnished to do so, subject to the following conditions: 10edc61147SHawking Zhang * 11edc61147SHawking Zhang * The above copyright notice and this permission notice shall be included in 12edc61147SHawking Zhang * all copies or substantial portions of the Software. 13edc61147SHawking Zhang * 14edc61147SHawking Zhang * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15edc61147SHawking Zhang * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16edc61147SHawking Zhang * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17edc61147SHawking Zhang * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18edc61147SHawking Zhang * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19edc61147SHawking Zhang * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20edc61147SHawking Zhang * OTHER DEALINGS IN THE SOFTWARE. 21edc61147SHawking Zhang * 22edc61147SHawking Zhang */ 23edc61147SHawking Zhang 24b23b2e9eSAlex Deucher #include <linux/pci.h> 25b23b2e9eSAlex Deucher 26edc61147SHawking Zhang #include "amdgpu.h" 27edc61147SHawking Zhang #include "amdgpu_ih.h" 28edc61147SHawking Zhang 29edc61147SHawking Zhang #include "oss/osssys_5_0_0_offset.h" 30edc61147SHawking Zhang #include "oss/osssys_5_0_0_sh_mask.h" 31edc61147SHawking Zhang 32edc61147SHawking Zhang #include "soc15_common.h" 33edc61147SHawking Zhang #include "navi10_ih.h" 34edc61147SHawking Zhang 35022b6518SSamir Dhume #define MAX_REARM_RETRY 10 36edc61147SHawking Zhang 37757b3af8SLikun Gao #define mmIH_CHICKEN_Sienna_Cichlid 0x018d 38757b3af8SLikun Gao #define mmIH_CHICKEN_Sienna_Cichlid_BASE_IDX 0 39757b3af8SLikun Gao 40edc61147SHawking Zhang static void navi10_ih_set_interrupt_funcs(struct amdgpu_device *adev); 41edc61147SHawking Zhang 42edc61147SHawking Zhang /** 435212d163SHawking Zhang * navi10_ih_init_register_offset - Initialize register offset for ih rings 445212d163SHawking Zhang * 455212d163SHawking Zhang * @adev: amdgpu_device pointer 465212d163SHawking Zhang * 475212d163SHawking Zhang * Initialize register offset ih rings (NAVI10). 485212d163SHawking Zhang */ 495212d163SHawking Zhang static void navi10_ih_init_register_offset(struct amdgpu_device *adev) 505212d163SHawking Zhang { 515212d163SHawking Zhang struct amdgpu_ih_regs *ih_regs; 525212d163SHawking Zhang 535212d163SHawking Zhang if (adev->irq.ih.ring_size) { 545212d163SHawking Zhang ih_regs = &adev->irq.ih.ih_regs; 555212d163SHawking Zhang ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE); 565212d163SHawking Zhang ih_regs->ih_rb_base_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_HI); 575212d163SHawking Zhang ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL); 585212d163SHawking Zhang ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR); 595212d163SHawking Zhang ih_regs->ih_rb_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR); 605212d163SHawking Zhang ih_regs->ih_doorbell_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_DOORBELL_RPTR); 615212d163SHawking Zhang ih_regs->ih_rb_wptr_addr_lo = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_ADDR_LO); 625212d163SHawking Zhang ih_regs->ih_rb_wptr_addr_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_ADDR_HI); 635212d163SHawking Zhang ih_regs->psp_reg_id = PSP_REG_IH_RB_CNTL; 645212d163SHawking Zhang } 655212d163SHawking Zhang 665212d163SHawking Zhang if (adev->irq.ih1.ring_size) { 675212d163SHawking Zhang ih_regs = &adev->irq.ih1.ih_regs; 685212d163SHawking Zhang ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_RING1); 695212d163SHawking Zhang ih_regs->ih_rb_base_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_HI_RING1); 705212d163SHawking Zhang ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL_RING1); 715212d163SHawking Zhang ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_RING1); 725212d163SHawking Zhang ih_regs->ih_rb_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR_RING1); 735212d163SHawking Zhang ih_regs->ih_doorbell_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_DOORBELL_RPTR_RING1); 745212d163SHawking Zhang ih_regs->psp_reg_id = PSP_REG_IH_RB_CNTL_RING1; 755212d163SHawking Zhang } 765212d163SHawking Zhang 775212d163SHawking Zhang if (adev->irq.ih2.ring_size) { 785212d163SHawking Zhang ih_regs = &adev->irq.ih2.ih_regs; 795212d163SHawking Zhang ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_RING2); 805212d163SHawking Zhang ih_regs->ih_rb_base_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_HI_RING2); 815212d163SHawking Zhang ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL_RING2); 825212d163SHawking Zhang ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_RING2); 835212d163SHawking Zhang ih_regs->ih_rb_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR_RING2); 845212d163SHawking Zhang ih_regs->ih_doorbell_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_DOORBELL_RPTR_RING2); 855212d163SHawking Zhang ih_regs->psp_reg_id = PSP_REG_IH_RB_CNTL_RING2; 865212d163SHawking Zhang } 875212d163SHawking Zhang } 885212d163SHawking Zhang 895212d163SHawking Zhang /** 905ea6f9c2SChengming Gui * force_update_wptr_for_self_int - Force update the wptr for self interrupt 915ea6f9c2SChengming Gui * 925ea6f9c2SChengming Gui * @adev: amdgpu_device pointer 935ea6f9c2SChengming Gui * @threshold: threshold to trigger the wptr reporting 945ea6f9c2SChengming Gui * @timeout: timeout to trigger the wptr reporting 955ea6f9c2SChengming Gui * @enabled: Enable/disable timeout flush mechanism 965ea6f9c2SChengming Gui * 975ea6f9c2SChengming Gui * threshold input range: 0 ~ 15, default 0, 985ea6f9c2SChengming Gui * real_threshold = 2^threshold 995ea6f9c2SChengming Gui * timeout input range: 0 ~ 20, default 8, 1005ea6f9c2SChengming Gui * real_timeout = (2^timeout) * 1024 / (socclk_freq) 1015ea6f9c2SChengming Gui * 1025ea6f9c2SChengming Gui * Force update wptr for self interrupt ( >= SIENNA_CICHLID). 1035ea6f9c2SChengming Gui */ 1045ea6f9c2SChengming Gui static void 1055ea6f9c2SChengming Gui force_update_wptr_for_self_int(struct amdgpu_device *adev, 1065ea6f9c2SChengming Gui u32 threshold, u32 timeout, bool enabled) 1075ea6f9c2SChengming Gui { 1085ea6f9c2SChengming Gui u32 ih_cntl, ih_rb_cntl; 1095ea6f9c2SChengming Gui 1105ea6f9c2SChengming Gui if (adev->asic_type < CHIP_SIENNA_CICHLID) 1115ea6f9c2SChengming Gui return; 1125ea6f9c2SChengming Gui 1135ea6f9c2SChengming Gui ih_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_CNTL2); 1145ea6f9c2SChengming Gui ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1); 1155ea6f9c2SChengming Gui 1165ea6f9c2SChengming Gui ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL2, 1175ea6f9c2SChengming Gui SELF_IV_FORCE_WPTR_UPDATE_TIMEOUT, timeout); 1185ea6f9c2SChengming Gui ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL2, 1195ea6f9c2SChengming Gui SELF_IV_FORCE_WPTR_UPDATE_ENABLE, enabled); 1205ea6f9c2SChengming Gui ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING1, 1215ea6f9c2SChengming Gui RB_USED_INT_THRESHOLD, threshold); 1225ea6f9c2SChengming Gui 1235ea6f9c2SChengming Gui WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1, ih_rb_cntl); 1245ea6f9c2SChengming Gui ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2); 1255ea6f9c2SChengming Gui ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING2, 1265ea6f9c2SChengming Gui RB_USED_INT_THRESHOLD, threshold); 1275ea6f9c2SChengming Gui WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2, ih_rb_cntl); 1285ea6f9c2SChengming Gui WREG32_SOC15(OSSSYS, 0, mmIH_CNTL2, ih_cntl); 1295ea6f9c2SChengming Gui } 1305ea6f9c2SChengming Gui 1315ea6f9c2SChengming Gui /** 1321ce6940eSHawking Zhang * navi10_ih_toggle_ring_interrupts - toggle the interrupt ring buffer 1331ce6940eSHawking Zhang * 1341ce6940eSHawking Zhang * @adev: amdgpu_device pointer 1351ce6940eSHawking Zhang * @ih: amdgpu_ih_ring pointet 1361ce6940eSHawking Zhang * @enable: true - enable the interrupts, false - disable the interrupts 1371ce6940eSHawking Zhang * 1381ce6940eSHawking Zhang * Toggle the interrupt ring buffer (NAVI10) 1391ce6940eSHawking Zhang */ 1401ce6940eSHawking Zhang static int navi10_ih_toggle_ring_interrupts(struct amdgpu_device *adev, 1411ce6940eSHawking Zhang struct amdgpu_ih_ring *ih, 1421ce6940eSHawking Zhang bool enable) 1431ce6940eSHawking Zhang { 1441ce6940eSHawking Zhang struct amdgpu_ih_regs *ih_regs; 1451ce6940eSHawking Zhang uint32_t tmp; 1461ce6940eSHawking Zhang 1471ce6940eSHawking Zhang ih_regs = &ih->ih_regs; 1481ce6940eSHawking Zhang 1491ce6940eSHawking Zhang tmp = RREG32(ih_regs->ih_rb_cntl); 1501ce6940eSHawking Zhang tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RB_ENABLE, (enable ? 1 : 0)); 1511ce6940eSHawking Zhang /* enable_intr field is only valid in ring0 */ 1521ce6940eSHawking Zhang if (ih == &adev->irq.ih) 1531ce6940eSHawking Zhang tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, ENABLE_INTR, (enable ? 1 : 0)); 1541ce6940eSHawking Zhang WREG32(ih_regs->ih_rb_cntl, tmp); 1551ce6940eSHawking Zhang 1561ce6940eSHawking Zhang if (enable) { 1571ce6940eSHawking Zhang ih->enabled = true; 1581ce6940eSHawking Zhang } else { 1591ce6940eSHawking Zhang /* set rptr, wptr to 0 */ 1601ce6940eSHawking Zhang WREG32(ih_regs->ih_rb_rptr, 0); 1611ce6940eSHawking Zhang WREG32(ih_regs->ih_rb_wptr, 0); 1621ce6940eSHawking Zhang ih->enabled = false; 1631ce6940eSHawking Zhang ih->rptr = 0; 1641ce6940eSHawking Zhang } 1651ce6940eSHawking Zhang 1661ce6940eSHawking Zhang return 0; 1671ce6940eSHawking Zhang } 1681ce6940eSHawking Zhang 1696e7b7c7fSHawking Zhang /** 1706e7b7c7fSHawking Zhang * navi10_ih_toggle_interrupts - Toggle all the available interrupt ring buffers 1716e7b7c7fSHawking Zhang * 1726e7b7c7fSHawking Zhang * @adev: amdgpu_device pointer 1736e7b7c7fSHawking Zhang * @enable: enable or disable interrupt ring buffers 1746e7b7c7fSHawking Zhang * 1756e7b7c7fSHawking Zhang * Toggle all the available interrupt ring buffers (NAVI10). 1766e7b7c7fSHawking Zhang */ 1776e7b7c7fSHawking Zhang static int navi10_ih_toggle_interrupts(struct amdgpu_device *adev, bool enable) 1786e7b7c7fSHawking Zhang { 1796e7b7c7fSHawking Zhang struct amdgpu_ih_ring *ih[] = {&adev->irq.ih, &adev->irq.ih1, &adev->irq.ih2}; 1806e7b7c7fSHawking Zhang int i; 1816e7b7c7fSHawking Zhang int r; 1826e7b7c7fSHawking Zhang 1836e7b7c7fSHawking Zhang for (i = 0; i < ARRAY_SIZE(ih); i++) { 1846e7b7c7fSHawking Zhang if (ih[i]->ring_size) { 1856e7b7c7fSHawking Zhang r = navi10_ih_toggle_ring_interrupts(adev, ih[i], enable); 1866e7b7c7fSHawking Zhang if (r) 1876e7b7c7fSHawking Zhang return r; 1886e7b7c7fSHawking Zhang } 1896e7b7c7fSHawking Zhang } 1906e7b7c7fSHawking Zhang 1916e7b7c7fSHawking Zhang return 0; 1926e7b7c7fSHawking Zhang } 1936e7b7c7fSHawking Zhang 194edc61147SHawking Zhang static uint32_t navi10_ih_rb_cntl(struct amdgpu_ih_ring *ih, uint32_t ih_rb_cntl) 195edc61147SHawking Zhang { 196edc61147SHawking Zhang int rb_bufsz = order_base_2(ih->ring_size / 4); 197edc61147SHawking Zhang 198edc61147SHawking Zhang ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, 199edc61147SHawking Zhang MC_SPACE, ih->use_bus_addr ? 1 : 4); 200edc61147SHawking Zhang ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, 201edc61147SHawking Zhang WPTR_OVERFLOW_CLEAR, 1); 202edc61147SHawking Zhang ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, 203edc61147SHawking Zhang WPTR_OVERFLOW_ENABLE, 1); 204edc61147SHawking Zhang ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_SIZE, rb_bufsz); 205edc61147SHawking Zhang /* Ring Buffer write pointer writeback. If enabled, IH_RB_WPTR register 206edc61147SHawking Zhang * value is written to memory 207edc61147SHawking Zhang */ 208edc61147SHawking Zhang ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, 209edc61147SHawking Zhang WPTR_WRITEBACK_ENABLE, 1); 210edc61147SHawking Zhang ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_SNOOP, 1); 211edc61147SHawking Zhang ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_RO, 0); 212edc61147SHawking Zhang ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_VMID, 0); 213edc61147SHawking Zhang 214edc61147SHawking Zhang return ih_rb_cntl; 215edc61147SHawking Zhang } 216edc61147SHawking Zhang 217ab518012SAlex Sierra static uint32_t navi10_ih_doorbell_rptr(struct amdgpu_ih_ring *ih) 218ab518012SAlex Sierra { 219ab518012SAlex Sierra u32 ih_doorbell_rtpr = 0; 220ab518012SAlex Sierra 221ab518012SAlex Sierra if (ih->use_doorbell) { 222ab518012SAlex Sierra ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr, 223ab518012SAlex Sierra IH_DOORBELL_RPTR, OFFSET, 224ab518012SAlex Sierra ih->doorbell_index); 225ab518012SAlex Sierra ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr, 226ab518012SAlex Sierra IH_DOORBELL_RPTR, 227ab518012SAlex Sierra ENABLE, 1); 228ab518012SAlex Sierra } else { 229ab518012SAlex Sierra ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr, 230ab518012SAlex Sierra IH_DOORBELL_RPTR, 231ab518012SAlex Sierra ENABLE, 0); 232ab518012SAlex Sierra } 233ab518012SAlex Sierra return ih_doorbell_rtpr; 234ab518012SAlex Sierra } 235ab518012SAlex Sierra 2361514cb7dSHawking Zhang /** 2371514cb7dSHawking Zhang * navi10_ih_enable_ring - enable an ih ring buffer 2381514cb7dSHawking Zhang * 2391514cb7dSHawking Zhang * @adev: amdgpu_device pointer 2401514cb7dSHawking Zhang * @ih: amdgpu_ih_ring pointer 2411514cb7dSHawking Zhang * 2421514cb7dSHawking Zhang * Enable an ih ring buffer (NAVI10) 2431514cb7dSHawking Zhang */ 2441514cb7dSHawking Zhang static int navi10_ih_enable_ring(struct amdgpu_device *adev, 2451514cb7dSHawking Zhang struct amdgpu_ih_ring *ih) 2461514cb7dSHawking Zhang { 2471514cb7dSHawking Zhang struct amdgpu_ih_regs *ih_regs; 2481514cb7dSHawking Zhang uint32_t tmp; 2491514cb7dSHawking Zhang 2501514cb7dSHawking Zhang ih_regs = &ih->ih_regs; 2511514cb7dSHawking Zhang 2521514cb7dSHawking Zhang /* Ring Buffer base. [39:8] of 40-bit address of the beginning of the ring buffer*/ 2531514cb7dSHawking Zhang WREG32(ih_regs->ih_rb_base, ih->gpu_addr >> 8); 2541514cb7dSHawking Zhang WREG32(ih_regs->ih_rb_base_hi, (ih->gpu_addr >> 40) & 0xff); 2551514cb7dSHawking Zhang 2561514cb7dSHawking Zhang tmp = RREG32(ih_regs->ih_rb_cntl); 2571514cb7dSHawking Zhang tmp = navi10_ih_rb_cntl(ih, tmp); 2581514cb7dSHawking Zhang if (ih == &adev->irq.ih) 2591514cb7dSHawking Zhang tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RPTR_REARM, !!adev->irq.msi_enabled); 2601514cb7dSHawking Zhang if (ih == &adev->irq.ih1) { 2611514cb7dSHawking Zhang tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_ENABLE, 0); 2621514cb7dSHawking Zhang tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RB_FULL_DRAIN_ENABLE, 1); 2631514cb7dSHawking Zhang } 2641514cb7dSHawking Zhang WREG32(ih_regs->ih_rb_cntl, tmp); 2651514cb7dSHawking Zhang 2661514cb7dSHawking Zhang if (ih == &adev->irq.ih) { 2671514cb7dSHawking Zhang /* set the ih ring 0 writeback address whether it's enabled or not */ 2681514cb7dSHawking Zhang WREG32(ih_regs->ih_rb_wptr_addr_lo, lower_32_bits(ih->wptr_addr)); 2691514cb7dSHawking Zhang WREG32(ih_regs->ih_rb_wptr_addr_hi, upper_32_bits(ih->wptr_addr) & 0xFFFF); 2701514cb7dSHawking Zhang } 2711514cb7dSHawking Zhang 2721514cb7dSHawking Zhang /* set rptr, wptr to 0 */ 2731514cb7dSHawking Zhang WREG32(ih_regs->ih_rb_wptr, 0); 2741514cb7dSHawking Zhang WREG32(ih_regs->ih_rb_rptr, 0); 2751514cb7dSHawking Zhang 2761514cb7dSHawking Zhang WREG32(ih_regs->ih_doorbell_rptr, navi10_ih_doorbell_rptr(ih)); 2771514cb7dSHawking Zhang 2781514cb7dSHawking Zhang return 0; 2791514cb7dSHawking Zhang } 2801514cb7dSHawking Zhang 281edc61147SHawking Zhang /** 282edc61147SHawking Zhang * navi10_ih_irq_init - init and enable the interrupt ring 283edc61147SHawking Zhang * 284edc61147SHawking Zhang * @adev: amdgpu_device pointer 285edc61147SHawking Zhang * 286edc61147SHawking Zhang * Allocate a ring buffer for the interrupt controller, 287edc61147SHawking Zhang * enable the RLC, disable interrupts, enable the IH 288edc61147SHawking Zhang * ring buffer and enable it (NAVI). 289edc61147SHawking Zhang * Called at device load and reume. 290edc61147SHawking Zhang * Returns 0 for success, errors for failure. 291edc61147SHawking Zhang */ 292edc61147SHawking Zhang static int navi10_ih_irq_init(struct amdgpu_device *adev) 293edc61147SHawking Zhang { 294fc4aa19fSHawking Zhang struct amdgpu_ih_ring *ih[] = {&adev->irq.ih, &adev->irq.ih1, &adev->irq.ih2}; 295fc4aa19fSHawking Zhang u32 ih_chicken; 296edc61147SHawking Zhang u32 tmp; 2976e7b7c7fSHawking Zhang int ret; 298fc4aa19fSHawking Zhang int i; 299edc61147SHawking Zhang 300edc61147SHawking Zhang /* disable irqs */ 3016e7b7c7fSHawking Zhang ret = navi10_ih_toggle_interrupts(adev, false); 3026e7b7c7fSHawking Zhang if (ret) 3036e7b7c7fSHawking Zhang return ret; 304edc61147SHawking Zhang 305bebc0762SHawking Zhang adev->nbio.funcs->ih_control(adev); 306edc61147SHawking Zhang 307edc61147SHawking Zhang if (unlikely(adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT)) { 308fc4aa19fSHawking Zhang if (ih[0]->use_bus_addr) { 309757b3af8SLikun Gao switch (adev->asic_type) { 310757b3af8SLikun Gao case CHIP_SIENNA_CICHLID: 311026c396bSJiansong Chen case CHIP_NAVY_FLOUNDER: 312bd4f2811SHuang Rui case CHIP_VANGOGH: 313771cc67eSTao Zhou case CHIP_DIMGREY_CAVEFISH: 314*a1dede36SChengming Gui case CHIP_BEIGE_GOBY: 315757b3af8SLikun Gao ih_chicken = RREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN_Sienna_Cichlid); 316757b3af8SLikun Gao ih_chicken = REG_SET_FIELD(ih_chicken, 317757b3af8SLikun Gao IH_CHICKEN, MC_SPACE_GPA_ENABLE, 1); 318757b3af8SLikun Gao WREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN_Sienna_Cichlid, ih_chicken); 319757b3af8SLikun Gao break; 320757b3af8SLikun Gao default: 321edc61147SHawking Zhang ih_chicken = RREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN); 322edc61147SHawking Zhang ih_chicken = REG_SET_FIELD(ih_chicken, 323edc61147SHawking Zhang IH_CHICKEN, MC_SPACE_GPA_ENABLE, 1); 324edc61147SHawking Zhang WREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN, ih_chicken); 325757b3af8SLikun Gao break; 326757b3af8SLikun Gao } 327edc61147SHawking Zhang } 328edc61147SHawking Zhang } 329edc61147SHawking Zhang 330fc4aa19fSHawking Zhang for (i = 0; i < ARRAY_SIZE(ih); i++) { 331fc4aa19fSHawking Zhang if (ih[i]->ring_size) { 332fc4aa19fSHawking Zhang ret = navi10_ih_enable_ring(adev, ih[i]); 333fc4aa19fSHawking Zhang if (ret) 334fc4aa19fSHawking Zhang return ret; 3350ab176e6SAlex Sierra } 336ab518012SAlex Sierra } 337ab518012SAlex Sierra 338fc4aa19fSHawking Zhang /* update doorbell range for ih ring 0*/ 339fc4aa19fSHawking Zhang adev->nbio.funcs->ih_doorbell_range(adev, ih[0]->use_doorbell, 340fc4aa19fSHawking Zhang ih[0]->doorbell_index); 341ab518012SAlex Sierra 342edc61147SHawking Zhang tmp = RREG32_SOC15(OSSSYS, 0, mmIH_STORM_CLIENT_LIST_CNTL); 343edc61147SHawking Zhang tmp = REG_SET_FIELD(tmp, IH_STORM_CLIENT_LIST_CNTL, 344edc61147SHawking Zhang CLIENT18_IS_STORM_CLIENT, 1); 345edc61147SHawking Zhang WREG32_SOC15(OSSSYS, 0, mmIH_STORM_CLIENT_LIST_CNTL, tmp); 346edc61147SHawking Zhang 347edc61147SHawking Zhang tmp = RREG32_SOC15(OSSSYS, 0, mmIH_INT_FLOOD_CNTL); 348edc61147SHawking Zhang tmp = REG_SET_FIELD(tmp, IH_INT_FLOOD_CNTL, FLOOD_CNTL_ENABLE, 1); 349edc61147SHawking Zhang WREG32_SOC15(OSSSYS, 0, mmIH_INT_FLOOD_CNTL, tmp); 350edc61147SHawking Zhang 351edc61147SHawking Zhang pci_set_master(adev->pdev); 352edc61147SHawking Zhang 353edc61147SHawking Zhang /* enable interrupts */ 3546e7b7c7fSHawking Zhang ret = navi10_ih_toggle_interrupts(adev, true); 3556e7b7c7fSHawking Zhang if (ret) 3566e7b7c7fSHawking Zhang return ret; 3575ea6f9c2SChengming Gui /* enable wptr force update for self int */ 3585ea6f9c2SChengming Gui force_update_wptr_for_self_int(adev, 0, 8, true); 359edc61147SHawking Zhang 3607f03b148SHawking Zhang if (adev->irq.ih_soft.ring_size) 3617f03b148SHawking Zhang adev->irq.ih_soft.enabled = true; 3627f03b148SHawking Zhang 3637eca4006SMa Feng return 0; 364edc61147SHawking Zhang } 365edc61147SHawking Zhang 366edc61147SHawking Zhang /** 367edc61147SHawking Zhang * navi10_ih_irq_disable - disable interrupts 368edc61147SHawking Zhang * 369edc61147SHawking Zhang * @adev: amdgpu_device pointer 370edc61147SHawking Zhang * 371edc61147SHawking Zhang * Disable interrupts on the hw (NAVI10). 372edc61147SHawking Zhang */ 373edc61147SHawking Zhang static void navi10_ih_irq_disable(struct amdgpu_device *adev) 374edc61147SHawking Zhang { 3755ea6f9c2SChengming Gui force_update_wptr_for_self_int(adev, 0, 8, false); 3766e7b7c7fSHawking Zhang navi10_ih_toggle_interrupts(adev, false); 377edc61147SHawking Zhang 378edc61147SHawking Zhang /* Wait and acknowledge irq */ 379edc61147SHawking Zhang mdelay(1); 380edc61147SHawking Zhang } 381edc61147SHawking Zhang 382edc61147SHawking Zhang /** 383edc61147SHawking Zhang * navi10_ih_get_wptr - get the IH ring buffer wptr 384edc61147SHawking Zhang * 385edc61147SHawking Zhang * @adev: amdgpu_device pointer 386c56fb081SLee Jones * @ih: IH ring buffer to fetch wptr 387edc61147SHawking Zhang * 388edc61147SHawking Zhang * Get the IH ring buffer wptr from either the register 389edc61147SHawking Zhang * or the writeback memory buffer (NAVI10). Also check for 390edc61147SHawking Zhang * ring buffer overflow and deal with it. 391edc61147SHawking Zhang * Returns the value of the wptr. 392edc61147SHawking Zhang */ 393edc61147SHawking Zhang static u32 navi10_ih_get_wptr(struct amdgpu_device *adev, 394edc61147SHawking Zhang struct amdgpu_ih_ring *ih) 395edc61147SHawking Zhang { 3962d2fbf68SHawking Zhang u32 wptr, tmp; 3972d2fbf68SHawking Zhang struct amdgpu_ih_regs *ih_regs; 398edc61147SHawking Zhang 399edc61147SHawking Zhang wptr = le32_to_cpu(*ih->wptr_cpu); 4002d2fbf68SHawking Zhang ih_regs = &ih->ih_regs; 401edc61147SHawking Zhang 402edc61147SHawking Zhang if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) 403edc61147SHawking Zhang goto out; 404edc61147SHawking Zhang 4052d2fbf68SHawking Zhang wptr = RREG32_NO_KIQ(ih_regs->ih_rb_wptr); 406edc61147SHawking Zhang if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) 407edc61147SHawking Zhang goto out; 408edc61147SHawking Zhang wptr = REG_SET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW, 0); 409edc61147SHawking Zhang 410edc61147SHawking Zhang /* When a ring buffer overflow happen start parsing interrupt 411edc61147SHawking Zhang * from the last not overwritten vector (wptr + 32). Hopefully 412edc61147SHawking Zhang * this should allow us to catch up. 413edc61147SHawking Zhang */ 414edc61147SHawking Zhang tmp = (wptr + 32) & ih->ptr_mask; 415edc61147SHawking Zhang dev_warn(adev->dev, "IH ring buffer overflow " 416edc61147SHawking Zhang "(0x%08X, 0x%08X, 0x%08X)\n", 417edc61147SHawking Zhang wptr, ih->rptr, tmp); 418edc61147SHawking Zhang ih->rptr = tmp; 419edc61147SHawking Zhang 4202d2fbf68SHawking Zhang tmp = RREG32_NO_KIQ(ih_regs->ih_rb_cntl); 421edc61147SHawking Zhang tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1); 4222d2fbf68SHawking Zhang WREG32_NO_KIQ(ih_regs->ih_rb_cntl, tmp); 423edc61147SHawking Zhang out: 424edc61147SHawking Zhang return (wptr & ih->ptr_mask); 425edc61147SHawking Zhang } 426edc61147SHawking Zhang 427edc61147SHawking Zhang /** 428022b6518SSamir Dhume * navi10_ih_irq_rearm - rearm IRQ if lost 429022b6518SSamir Dhume * 430022b6518SSamir Dhume * @adev: amdgpu_device pointer 431c56fb081SLee Jones * @ih: IH ring to match 432022b6518SSamir Dhume * 433022b6518SSamir Dhume */ 434022b6518SSamir Dhume static void navi10_ih_irq_rearm(struct amdgpu_device *adev, 435022b6518SSamir Dhume struct amdgpu_ih_ring *ih) 436022b6518SSamir Dhume { 437022b6518SSamir Dhume uint32_t v = 0; 438022b6518SSamir Dhume uint32_t i = 0; 4392d2fbf68SHawking Zhang struct amdgpu_ih_regs *ih_regs; 440022b6518SSamir Dhume 4412d2fbf68SHawking Zhang ih_regs = &ih->ih_regs; 442022b6518SSamir Dhume 443022b6518SSamir Dhume /* Rearm IRQ / re-write doorbell if doorbell write is lost */ 444022b6518SSamir Dhume for (i = 0; i < MAX_REARM_RETRY; i++) { 4452d2fbf68SHawking Zhang v = RREG32_NO_KIQ(ih_regs->ih_rb_rptr); 446022b6518SSamir Dhume if ((v < ih->ring_size) && (v != ih->rptr)) 447022b6518SSamir Dhume WDOORBELL32(ih->doorbell_index, ih->rptr); 448022b6518SSamir Dhume else 449022b6518SSamir Dhume break; 450022b6518SSamir Dhume } 451022b6518SSamir Dhume } 452022b6518SSamir Dhume 453022b6518SSamir Dhume /** 454edc61147SHawking Zhang * navi10_ih_set_rptr - set the IH ring buffer rptr 455edc61147SHawking Zhang * 456edc61147SHawking Zhang * @adev: amdgpu_device pointer 457edc61147SHawking Zhang * 458c56fb081SLee Jones * @ih: IH ring buffer to set rptr 459edc61147SHawking Zhang * Set the IH ring buffer rptr. 460edc61147SHawking Zhang */ 461edc61147SHawking Zhang static void navi10_ih_set_rptr(struct amdgpu_device *adev, 462edc61147SHawking Zhang struct amdgpu_ih_ring *ih) 463edc61147SHawking Zhang { 4642d2fbf68SHawking Zhang struct amdgpu_ih_regs *ih_regs; 4652d2fbf68SHawking Zhang 466edc61147SHawking Zhang if (ih->use_doorbell) { 467edc61147SHawking Zhang /* XXX check if swapping is necessary on BE */ 468edc61147SHawking Zhang *ih->rptr_cpu = ih->rptr; 469edc61147SHawking Zhang WDOORBELL32(ih->doorbell_index, ih->rptr); 470022b6518SSamir Dhume 471022b6518SSamir Dhume if (amdgpu_sriov_vf(adev)) 472022b6518SSamir Dhume navi10_ih_irq_rearm(adev, ih); 4732d2fbf68SHawking Zhang } else { 4742d2fbf68SHawking Zhang ih_regs = &ih->ih_regs; 4752d2fbf68SHawking Zhang WREG32(ih_regs->ih_rb_rptr, ih->rptr); 476ab518012SAlex Sierra } 477ab518012SAlex Sierra } 478ab518012SAlex Sierra 479ab518012SAlex Sierra /** 480ab518012SAlex Sierra * navi10_ih_self_irq - dispatch work for ring 1 and 2 481ab518012SAlex Sierra * 482ab518012SAlex Sierra * @adev: amdgpu_device pointer 483ab518012SAlex Sierra * @source: irq source 484ab518012SAlex Sierra * @entry: IV with WPTR update 485ab518012SAlex Sierra * 486ab518012SAlex Sierra * Update the WPTR from the IV and schedule work to handle the entries. 487ab518012SAlex Sierra */ 488ab518012SAlex Sierra static int navi10_ih_self_irq(struct amdgpu_device *adev, 489ab518012SAlex Sierra struct amdgpu_irq_src *source, 490ab518012SAlex Sierra struct amdgpu_iv_entry *entry) 491ab518012SAlex Sierra { 492ab518012SAlex Sierra uint32_t wptr = cpu_to_le32(entry->src_data[0]); 493ab518012SAlex Sierra 494ab518012SAlex Sierra switch (entry->ring_id) { 495ab518012SAlex Sierra case 1: 496ab518012SAlex Sierra *adev->irq.ih1.wptr_cpu = wptr; 497ab518012SAlex Sierra schedule_work(&adev->irq.ih1_work); 498ab518012SAlex Sierra break; 499ab518012SAlex Sierra case 2: 500ab518012SAlex Sierra *adev->irq.ih2.wptr_cpu = wptr; 501ab518012SAlex Sierra schedule_work(&adev->irq.ih2_work); 502ab518012SAlex Sierra break; 503ab518012SAlex Sierra default: break; 504ab518012SAlex Sierra } 505ab518012SAlex Sierra return 0; 506ab518012SAlex Sierra } 507ab518012SAlex Sierra 508ab518012SAlex Sierra static const struct amdgpu_irq_src_funcs navi10_ih_self_irq_funcs = { 509ab518012SAlex Sierra .process = navi10_ih_self_irq, 510ab518012SAlex Sierra }; 511ab518012SAlex Sierra 512ab518012SAlex Sierra static void navi10_ih_set_self_irq_funcs(struct amdgpu_device *adev) 513ab518012SAlex Sierra { 514ab518012SAlex Sierra adev->irq.self_irq.num_types = 0; 515ab518012SAlex Sierra adev->irq.self_irq.funcs = &navi10_ih_self_irq_funcs; 516edc61147SHawking Zhang } 517edc61147SHawking Zhang 518edc61147SHawking Zhang static int navi10_ih_early_init(void *handle) 519edc61147SHawking Zhang { 520edc61147SHawking Zhang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 521edc61147SHawking Zhang 522edc61147SHawking Zhang navi10_ih_set_interrupt_funcs(adev); 523ab518012SAlex Sierra navi10_ih_set_self_irq_funcs(adev); 524edc61147SHawking Zhang return 0; 525edc61147SHawking Zhang } 526edc61147SHawking Zhang 527edc61147SHawking Zhang static int navi10_ih_sw_init(void *handle) 528edc61147SHawking Zhang { 529edc61147SHawking Zhang int r; 530edc61147SHawking Zhang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 531edc61147SHawking Zhang bool use_bus_addr; 532edc61147SHawking Zhang 533ab518012SAlex Sierra r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_IH, 0, 534ab518012SAlex Sierra &adev->irq.self_irq); 535ab518012SAlex Sierra 536ab518012SAlex Sierra if (r) 537ab518012SAlex Sierra return r; 538ab518012SAlex Sierra 539edc61147SHawking Zhang /* use gpu virtual address for ih ring 540edc61147SHawking Zhang * until ih_checken is programmed to allow 541edc61147SHawking Zhang * use bus address for ih ring by psp bl */ 542bf13cb1fSHuang Rui if ((adev->flags & AMD_IS_APU) || 543bf13cb1fSHuang Rui (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) 544bf13cb1fSHuang Rui use_bus_addr = false; 545bf13cb1fSHuang Rui else 546bf13cb1fSHuang Rui use_bus_addr = true; 547edc61147SHawking Zhang r = amdgpu_ih_ring_init(adev, &adev->irq.ih, 256 * 1024, use_bus_addr); 548edc61147SHawking Zhang if (r) 549edc61147SHawking Zhang return r; 550edc61147SHawking Zhang 551edc61147SHawking Zhang adev->irq.ih.use_doorbell = true; 552edc61147SHawking Zhang adev->irq.ih.doorbell_index = adev->doorbell_index.ih << 1; 553edc61147SHawking Zhang 554abb6fccbSAlex Sierra adev->irq.ih1.ring_size = 0; 555abb6fccbSAlex Sierra adev->irq.ih2.ring_size = 0; 556abb6fccbSAlex Sierra 557a362976bSHawking Zhang /* initialize ih control registers offset */ 558a362976bSHawking Zhang navi10_ih_init_register_offset(adev); 559a362976bSHawking Zhang 560d4581f7dSChristian König r = amdgpu_ih_ring_init(adev, &adev->irq.ih_soft, PAGE_SIZE, true); 561d4581f7dSChristian König if (r) 562d4581f7dSChristian König return r; 563d4581f7dSChristian König 564edc61147SHawking Zhang r = amdgpu_irq_init(adev); 565edc61147SHawking Zhang 566edc61147SHawking Zhang return r; 567edc61147SHawking Zhang } 568edc61147SHawking Zhang 569edc61147SHawking Zhang static int navi10_ih_sw_fini(void *handle) 570edc61147SHawking Zhang { 571edc61147SHawking Zhang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 572edc61147SHawking Zhang 573edc61147SHawking Zhang amdgpu_irq_fini(adev); 5744a0a0d6dSHawking Zhang amdgpu_ih_ring_fini(adev, &adev->irq.ih_soft); 575ab518012SAlex Sierra amdgpu_ih_ring_fini(adev, &adev->irq.ih2); 576ab518012SAlex Sierra amdgpu_ih_ring_fini(adev, &adev->irq.ih1); 577edc61147SHawking Zhang amdgpu_ih_ring_fini(adev, &adev->irq.ih); 578edc61147SHawking Zhang 579edc61147SHawking Zhang return 0; 580edc61147SHawking Zhang } 581edc61147SHawking Zhang 582edc61147SHawking Zhang static int navi10_ih_hw_init(void *handle) 583edc61147SHawking Zhang { 584edc61147SHawking Zhang int r; 585edc61147SHawking Zhang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 586edc61147SHawking Zhang 587edc61147SHawking Zhang r = navi10_ih_irq_init(adev); 588edc61147SHawking Zhang if (r) 589edc61147SHawking Zhang return r; 590edc61147SHawking Zhang 591edc61147SHawking Zhang return 0; 592edc61147SHawking Zhang } 593edc61147SHawking Zhang 594edc61147SHawking Zhang static int navi10_ih_hw_fini(void *handle) 595edc61147SHawking Zhang { 596edc61147SHawking Zhang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 597edc61147SHawking Zhang 598edc61147SHawking Zhang navi10_ih_irq_disable(adev); 599edc61147SHawking Zhang 600edc61147SHawking Zhang return 0; 601edc61147SHawking Zhang } 602edc61147SHawking Zhang 603edc61147SHawking Zhang static int navi10_ih_suspend(void *handle) 604edc61147SHawking Zhang { 605edc61147SHawking Zhang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 606edc61147SHawking Zhang 607edc61147SHawking Zhang return navi10_ih_hw_fini(adev); 608edc61147SHawking Zhang } 609edc61147SHawking Zhang 610edc61147SHawking Zhang static int navi10_ih_resume(void *handle) 611edc61147SHawking Zhang { 612edc61147SHawking Zhang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 613edc61147SHawking Zhang 614edc61147SHawking Zhang return navi10_ih_hw_init(adev); 615edc61147SHawking Zhang } 616edc61147SHawking Zhang 617edc61147SHawking Zhang static bool navi10_ih_is_idle(void *handle) 618edc61147SHawking Zhang { 619edc61147SHawking Zhang /* todo */ 620edc61147SHawking Zhang return true; 621edc61147SHawking Zhang } 622edc61147SHawking Zhang 623edc61147SHawking Zhang static int navi10_ih_wait_for_idle(void *handle) 624edc61147SHawking Zhang { 625edc61147SHawking Zhang /* todo */ 626edc61147SHawking Zhang return -ETIMEDOUT; 627edc61147SHawking Zhang } 628edc61147SHawking Zhang 629edc61147SHawking Zhang static int navi10_ih_soft_reset(void *handle) 630edc61147SHawking Zhang { 631edc61147SHawking Zhang /* todo */ 632edc61147SHawking Zhang return 0; 633edc61147SHawking Zhang } 634edc61147SHawking Zhang 635edc61147SHawking Zhang static void navi10_ih_update_clockgating_state(struct amdgpu_device *adev, 636edc61147SHawking Zhang bool enable) 637edc61147SHawking Zhang { 638edc61147SHawking Zhang uint32_t data, def, field_val; 639edc61147SHawking Zhang 640edc61147SHawking Zhang if (adev->cg_flags & AMD_CG_SUPPORT_IH_CG) { 641edc61147SHawking Zhang def = data = RREG32_SOC15(OSSSYS, 0, mmIH_CLK_CTRL); 642edc61147SHawking Zhang field_val = enable ? 0 : 1; 643edc61147SHawking Zhang data = REG_SET_FIELD(data, IH_CLK_CTRL, 644edc61147SHawking Zhang DBUS_MUX_CLK_SOFT_OVERRIDE, field_val); 645edc61147SHawking Zhang data = REG_SET_FIELD(data, IH_CLK_CTRL, 646edc61147SHawking Zhang OSSSYS_SHARE_CLK_SOFT_OVERRIDE, field_val); 647edc61147SHawking Zhang data = REG_SET_FIELD(data, IH_CLK_CTRL, 648edc61147SHawking Zhang LIMIT_SMN_CLK_SOFT_OVERRIDE, field_val); 649edc61147SHawking Zhang data = REG_SET_FIELD(data, IH_CLK_CTRL, 650edc61147SHawking Zhang DYN_CLK_SOFT_OVERRIDE, field_val); 651edc61147SHawking Zhang data = REG_SET_FIELD(data, IH_CLK_CTRL, 652edc61147SHawking Zhang REG_CLK_SOFT_OVERRIDE, field_val); 653edc61147SHawking Zhang if (def != data) 654edc61147SHawking Zhang WREG32_SOC15(OSSSYS, 0, mmIH_CLK_CTRL, data); 655edc61147SHawking Zhang } 656edc61147SHawking Zhang 657edc61147SHawking Zhang return; 658edc61147SHawking Zhang } 659edc61147SHawking Zhang 660edc61147SHawking Zhang static int navi10_ih_set_clockgating_state(void *handle, 661edc61147SHawking Zhang enum amd_clockgating_state state) 662edc61147SHawking Zhang { 663edc61147SHawking Zhang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 664edc61147SHawking Zhang 665edc61147SHawking Zhang navi10_ih_update_clockgating_state(adev, 666a9d4fe2fSNirmoy Das state == AMD_CG_STATE_GATE); 667edc61147SHawking Zhang return 0; 668edc61147SHawking Zhang } 669edc61147SHawking Zhang 670edc61147SHawking Zhang static int navi10_ih_set_powergating_state(void *handle, 671edc61147SHawking Zhang enum amd_powergating_state state) 672edc61147SHawking Zhang { 673edc61147SHawking Zhang return 0; 674edc61147SHawking Zhang } 675edc61147SHawking Zhang 676edc61147SHawking Zhang static void navi10_ih_get_clockgating_state(void *handle, u32 *flags) 677edc61147SHawking Zhang { 678edc61147SHawking Zhang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 679edc61147SHawking Zhang 680edc61147SHawking Zhang if (!RREG32_SOC15(OSSSYS, 0, mmIH_CLK_CTRL)) 681edc61147SHawking Zhang *flags |= AMD_CG_SUPPORT_IH_CG; 682edc61147SHawking Zhang 683edc61147SHawking Zhang return; 684edc61147SHawking Zhang } 685edc61147SHawking Zhang 686edc61147SHawking Zhang static const struct amd_ip_funcs navi10_ih_ip_funcs = { 687edc61147SHawking Zhang .name = "navi10_ih", 688edc61147SHawking Zhang .early_init = navi10_ih_early_init, 689edc61147SHawking Zhang .late_init = NULL, 690edc61147SHawking Zhang .sw_init = navi10_ih_sw_init, 691edc61147SHawking Zhang .sw_fini = navi10_ih_sw_fini, 692edc61147SHawking Zhang .hw_init = navi10_ih_hw_init, 693edc61147SHawking Zhang .hw_fini = navi10_ih_hw_fini, 694edc61147SHawking Zhang .suspend = navi10_ih_suspend, 695edc61147SHawking Zhang .resume = navi10_ih_resume, 696edc61147SHawking Zhang .is_idle = navi10_ih_is_idle, 697edc61147SHawking Zhang .wait_for_idle = navi10_ih_wait_for_idle, 698edc61147SHawking Zhang .soft_reset = navi10_ih_soft_reset, 699edc61147SHawking Zhang .set_clockgating_state = navi10_ih_set_clockgating_state, 700edc61147SHawking Zhang .set_powergating_state = navi10_ih_set_powergating_state, 701edc61147SHawking Zhang .get_clockgating_state = navi10_ih_get_clockgating_state, 702edc61147SHawking Zhang }; 703edc61147SHawking Zhang 704edc61147SHawking Zhang static const struct amdgpu_ih_funcs navi10_ih_funcs = { 705edc61147SHawking Zhang .get_wptr = navi10_ih_get_wptr, 70640838281SHawking Zhang .decode_iv = amdgpu_ih_decode_iv_helper, 707edc61147SHawking Zhang .set_rptr = navi10_ih_set_rptr 708edc61147SHawking Zhang }; 709edc61147SHawking Zhang 710edc61147SHawking Zhang static void navi10_ih_set_interrupt_funcs(struct amdgpu_device *adev) 711edc61147SHawking Zhang { 712edc61147SHawking Zhang if (adev->irq.ih_funcs == NULL) 713edc61147SHawking Zhang adev->irq.ih_funcs = &navi10_ih_funcs; 714edc61147SHawking Zhang } 715edc61147SHawking Zhang 716edc61147SHawking Zhang const struct amdgpu_ip_block_version navi10_ih_ip_block = 717edc61147SHawking Zhang { 718edc61147SHawking Zhang .type = AMD_IP_BLOCK_TYPE_IH, 719edc61147SHawking Zhang .major = 5, 720edc61147SHawking Zhang .minor = 0, 721edc61147SHawking Zhang .rev = 0, 722edc61147SHawking Zhang .funcs = &navi10_ih_ip_funcs, 723edc61147SHawking Zhang }; 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