1edc61147SHawking Zhang /* 2edc61147SHawking Zhang * Copyright 2019 Advanced Micro Devices, Inc. 3edc61147SHawking Zhang * 4edc61147SHawking Zhang * Permission is hereby granted, free of charge, to any person obtaining a 5edc61147SHawking Zhang * copy of this software and associated documentation files (the "Software"), 6edc61147SHawking Zhang * to deal in the Software without restriction, including without limitation 7edc61147SHawking Zhang * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8edc61147SHawking Zhang * and/or sell copies of the Software, and to permit persons to whom the 9edc61147SHawking Zhang * Software is furnished to do so, subject to the following conditions: 10edc61147SHawking Zhang * 11edc61147SHawking Zhang * The above copyright notice and this permission notice shall be included in 12edc61147SHawking Zhang * all copies or substantial portions of the Software. 13edc61147SHawking Zhang * 14edc61147SHawking Zhang * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15edc61147SHawking Zhang * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16edc61147SHawking Zhang * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17edc61147SHawking Zhang * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18edc61147SHawking Zhang * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19edc61147SHawking Zhang * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20edc61147SHawking Zhang * OTHER DEALINGS IN THE SOFTWARE. 21edc61147SHawking Zhang * 22edc61147SHawking Zhang */ 23edc61147SHawking Zhang 24b23b2e9eSAlex Deucher #include <linux/pci.h> 25b23b2e9eSAlex Deucher 26edc61147SHawking Zhang #include "amdgpu.h" 27edc61147SHawking Zhang #include "amdgpu_ih.h" 28edc61147SHawking Zhang 29edc61147SHawking Zhang #include "oss/osssys_5_0_0_offset.h" 30edc61147SHawking Zhang #include "oss/osssys_5_0_0_sh_mask.h" 31edc61147SHawking Zhang 32edc61147SHawking Zhang #include "soc15_common.h" 33edc61147SHawking Zhang #include "navi10_ih.h" 34edc61147SHawking Zhang 35022b6518SSamir Dhume #define MAX_REARM_RETRY 10 36edc61147SHawking Zhang 37edc61147SHawking Zhang static void navi10_ih_set_interrupt_funcs(struct amdgpu_device *adev); 38edc61147SHawking Zhang 39edc61147SHawking Zhang /** 40edc61147SHawking Zhang * navi10_ih_enable_interrupts - Enable the interrupt ring buffer 41edc61147SHawking Zhang * 42edc61147SHawking Zhang * @adev: amdgpu_device pointer 43edc61147SHawking Zhang * 44edc61147SHawking Zhang * Enable the interrupt ring buffer (NAVI10). 45edc61147SHawking Zhang */ 46edc61147SHawking Zhang static void navi10_ih_enable_interrupts(struct amdgpu_device *adev) 47edc61147SHawking Zhang { 48edc61147SHawking Zhang u32 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL); 49edc61147SHawking Zhang 50edc61147SHawking Zhang ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 1); 51edc61147SHawking Zhang ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, ENABLE_INTR, 1); 520ab176e6SAlex Sierra if (amdgpu_sriov_vf(adev)) { 530ab176e6SAlex Sierra if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL, ih_rb_cntl)) { 540ab176e6SAlex Sierra DRM_ERROR("PSP program IH_RB_CNTL failed!\n"); 550ab176e6SAlex Sierra return; 560ab176e6SAlex Sierra } 570ab176e6SAlex Sierra } else { 58edc61147SHawking Zhang WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL, ih_rb_cntl); 590ab176e6SAlex Sierra } 600ab176e6SAlex Sierra 61edc61147SHawking Zhang adev->irq.ih.enabled = true; 62ab518012SAlex Sierra 63ab518012SAlex Sierra if (adev->irq.ih1.ring_size) { 64ab518012SAlex Sierra ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1); 65ab518012SAlex Sierra ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING1, 66ab518012SAlex Sierra RB_ENABLE, 1); 670ab176e6SAlex Sierra if (amdgpu_sriov_vf(adev)) { 680ab176e6SAlex Sierra if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL_RING1, 690ab176e6SAlex Sierra ih_rb_cntl)) { 700ab176e6SAlex Sierra DRM_ERROR("program IH_RB_CNTL_RING1 failed!\n"); 710ab176e6SAlex Sierra return; 720ab176e6SAlex Sierra } 730ab176e6SAlex Sierra } else { 74ab518012SAlex Sierra WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1, ih_rb_cntl); 750ab176e6SAlex Sierra } 76ab518012SAlex Sierra adev->irq.ih1.enabled = true; 77ab518012SAlex Sierra } 78ab518012SAlex Sierra 79ab518012SAlex Sierra if (adev->irq.ih2.ring_size) { 80ab518012SAlex Sierra ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2); 81ab518012SAlex Sierra ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING2, 82ab518012SAlex Sierra RB_ENABLE, 1); 830ab176e6SAlex Sierra if (amdgpu_sriov_vf(adev)) { 840ab176e6SAlex Sierra if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL_RING2, 850ab176e6SAlex Sierra ih_rb_cntl)) { 860ab176e6SAlex Sierra DRM_ERROR("program IH_RB_CNTL_RING2 failed!\n"); 870ab176e6SAlex Sierra return; 880ab176e6SAlex Sierra } 890ab176e6SAlex Sierra } else { 90ab518012SAlex Sierra WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2, ih_rb_cntl); 910ab176e6SAlex Sierra } 92ab518012SAlex Sierra adev->irq.ih2.enabled = true; 93ab518012SAlex Sierra } 94edc61147SHawking Zhang } 95edc61147SHawking Zhang 96edc61147SHawking Zhang /** 97edc61147SHawking Zhang * navi10_ih_disable_interrupts - Disable the interrupt ring buffer 98edc61147SHawking Zhang * 99edc61147SHawking Zhang * @adev: amdgpu_device pointer 100edc61147SHawking Zhang * 101edc61147SHawking Zhang * Disable the interrupt ring buffer (NAVI10). 102edc61147SHawking Zhang */ 103edc61147SHawking Zhang static void navi10_ih_disable_interrupts(struct amdgpu_device *adev) 104edc61147SHawking Zhang { 105edc61147SHawking Zhang u32 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL); 106edc61147SHawking Zhang 107edc61147SHawking Zhang ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 0); 108edc61147SHawking Zhang ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, ENABLE_INTR, 0); 1090ab176e6SAlex Sierra if (amdgpu_sriov_vf(adev)) { 1100ab176e6SAlex Sierra if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL, ih_rb_cntl)) { 1110ab176e6SAlex Sierra DRM_ERROR("PSP program IH_RB_CNTL failed!\n"); 1120ab176e6SAlex Sierra return; 1130ab176e6SAlex Sierra } 1140ab176e6SAlex Sierra } else { 115edc61147SHawking Zhang WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL, ih_rb_cntl); 1160ab176e6SAlex Sierra } 1170ab176e6SAlex Sierra 118edc61147SHawking Zhang /* set rptr, wptr to 0 */ 119edc61147SHawking Zhang WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR, 0); 120edc61147SHawking Zhang WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR, 0); 121edc61147SHawking Zhang adev->irq.ih.enabled = false; 122edc61147SHawking Zhang adev->irq.ih.rptr = 0; 123ab518012SAlex Sierra 124ab518012SAlex Sierra if (adev->irq.ih1.ring_size) { 125ab518012SAlex Sierra ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1); 126ab518012SAlex Sierra ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING1, 127ab518012SAlex Sierra RB_ENABLE, 0); 1280ab176e6SAlex Sierra if (amdgpu_sriov_vf(adev)) { 1290ab176e6SAlex Sierra if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL_RING1, 1300ab176e6SAlex Sierra ih_rb_cntl)) { 1310ab176e6SAlex Sierra DRM_ERROR("program IH_RB_CNTL_RING1 failed!\n"); 1320ab176e6SAlex Sierra return; 1330ab176e6SAlex Sierra } 1340ab176e6SAlex Sierra } else { 135ab518012SAlex Sierra WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1, ih_rb_cntl); 1360ab176e6SAlex Sierra } 137ab518012SAlex Sierra /* set rptr, wptr to 0 */ 138ab518012SAlex Sierra WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR_RING1, 0); 139ab518012SAlex Sierra WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_RING1, 0); 140ab518012SAlex Sierra adev->irq.ih1.enabled = false; 141ab518012SAlex Sierra adev->irq.ih1.rptr = 0; 142ab518012SAlex Sierra } 143ab518012SAlex Sierra 144ab518012SAlex Sierra if (adev->irq.ih2.ring_size) { 145ab518012SAlex Sierra ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2); 146ab518012SAlex Sierra ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING2, 147ab518012SAlex Sierra RB_ENABLE, 0); 1480ab176e6SAlex Sierra if (amdgpu_sriov_vf(adev)) { 1490ab176e6SAlex Sierra if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL_RING2, 1500ab176e6SAlex Sierra ih_rb_cntl)) { 1510ab176e6SAlex Sierra DRM_ERROR("program IH_RB_CNTL_RING2 failed!\n"); 1520ab176e6SAlex Sierra return; 1530ab176e6SAlex Sierra } 1540ab176e6SAlex Sierra } else { 155ab518012SAlex Sierra WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2, ih_rb_cntl); 1560ab176e6SAlex Sierra } 157ab518012SAlex Sierra /* set rptr, wptr to 0 */ 158ab518012SAlex Sierra WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR_RING2, 0); 159ab518012SAlex Sierra WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_RING2, 0); 160ab518012SAlex Sierra adev->irq.ih2.enabled = false; 161ab518012SAlex Sierra adev->irq.ih2.rptr = 0; 162ab518012SAlex Sierra } 163ab518012SAlex Sierra 164edc61147SHawking Zhang } 165edc61147SHawking Zhang 166edc61147SHawking Zhang static uint32_t navi10_ih_rb_cntl(struct amdgpu_ih_ring *ih, uint32_t ih_rb_cntl) 167edc61147SHawking Zhang { 168edc61147SHawking Zhang int rb_bufsz = order_base_2(ih->ring_size / 4); 169edc61147SHawking Zhang 170edc61147SHawking Zhang ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, 171edc61147SHawking Zhang MC_SPACE, ih->use_bus_addr ? 1 : 4); 172edc61147SHawking Zhang ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, 173edc61147SHawking Zhang WPTR_OVERFLOW_CLEAR, 1); 174edc61147SHawking Zhang ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, 175edc61147SHawking Zhang WPTR_OVERFLOW_ENABLE, 1); 176edc61147SHawking Zhang ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_SIZE, rb_bufsz); 177edc61147SHawking Zhang /* Ring Buffer write pointer writeback. If enabled, IH_RB_WPTR register 178edc61147SHawking Zhang * value is written to memory 179edc61147SHawking Zhang */ 180edc61147SHawking Zhang ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, 181edc61147SHawking Zhang WPTR_WRITEBACK_ENABLE, 1); 182edc61147SHawking Zhang ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_SNOOP, 1); 183edc61147SHawking Zhang ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_RO, 0); 184edc61147SHawking Zhang ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_VMID, 0); 185edc61147SHawking Zhang 186edc61147SHawking Zhang return ih_rb_cntl; 187edc61147SHawking Zhang } 188edc61147SHawking Zhang 189ab518012SAlex Sierra static uint32_t navi10_ih_doorbell_rptr(struct amdgpu_ih_ring *ih) 190ab518012SAlex Sierra { 191ab518012SAlex Sierra u32 ih_doorbell_rtpr = 0; 192ab518012SAlex Sierra 193ab518012SAlex Sierra if (ih->use_doorbell) { 194ab518012SAlex Sierra ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr, 195ab518012SAlex Sierra IH_DOORBELL_RPTR, OFFSET, 196ab518012SAlex Sierra ih->doorbell_index); 197ab518012SAlex Sierra ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr, 198ab518012SAlex Sierra IH_DOORBELL_RPTR, 199ab518012SAlex Sierra ENABLE, 1); 200ab518012SAlex Sierra } else { 201ab518012SAlex Sierra ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr, 202ab518012SAlex Sierra IH_DOORBELL_RPTR, 203ab518012SAlex Sierra ENABLE, 0); 204ab518012SAlex Sierra } 205ab518012SAlex Sierra return ih_doorbell_rtpr; 206ab518012SAlex Sierra } 207ab518012SAlex Sierra 2089e94ff33SAlex Sierra static void navi10_ih_reroute_ih(struct amdgpu_device *adev) 2099e94ff33SAlex Sierra { 2109e94ff33SAlex Sierra uint32_t tmp; 2119e94ff33SAlex Sierra 2129e94ff33SAlex Sierra /* Reroute to IH ring 1 for VMC */ 2139e94ff33SAlex Sierra WREG32_SOC15(OSSSYS, 0, mmIH_CLIENT_CFG_INDEX, 0x12); 2149e94ff33SAlex Sierra tmp = RREG32_SOC15(OSSSYS, 0, mmIH_CLIENT_CFG_DATA); 2159e94ff33SAlex Sierra tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, CLIENT_TYPE, 1); 2169e94ff33SAlex Sierra tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, RING_ID, 1); 2179e94ff33SAlex Sierra WREG32_SOC15(OSSSYS, 0, mmIH_CLIENT_CFG_DATA, tmp); 2189e94ff33SAlex Sierra 2199e94ff33SAlex Sierra /* Reroute IH ring 1 for UMC */ 2209e94ff33SAlex Sierra WREG32_SOC15(OSSSYS, 0, mmIH_CLIENT_CFG_INDEX, 0x1B); 2219e94ff33SAlex Sierra tmp = RREG32_SOC15(OSSSYS, 0, mmIH_CLIENT_CFG_DATA); 2229e94ff33SAlex Sierra tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, RING_ID, 1); 2239e94ff33SAlex Sierra WREG32_SOC15(OSSSYS, 0, mmIH_CLIENT_CFG_DATA, tmp); 2249e94ff33SAlex Sierra } 2259e94ff33SAlex Sierra 226edc61147SHawking Zhang /** 227edc61147SHawking Zhang * navi10_ih_irq_init - init and enable the interrupt ring 228edc61147SHawking Zhang * 229edc61147SHawking Zhang * @adev: amdgpu_device pointer 230edc61147SHawking Zhang * 231edc61147SHawking Zhang * Allocate a ring buffer for the interrupt controller, 232edc61147SHawking Zhang * enable the RLC, disable interrupts, enable the IH 233edc61147SHawking Zhang * ring buffer and enable it (NAVI). 234edc61147SHawking Zhang * Called at device load and reume. 235edc61147SHawking Zhang * Returns 0 for success, errors for failure. 236edc61147SHawking Zhang */ 237edc61147SHawking Zhang static int navi10_ih_irq_init(struct amdgpu_device *adev) 238edc61147SHawking Zhang { 239edc61147SHawking Zhang struct amdgpu_ih_ring *ih = &adev->irq.ih; 240ab518012SAlex Sierra u32 ih_rb_cntl, ih_chicken; 241edc61147SHawking Zhang u32 tmp; 242edc61147SHawking Zhang 243edc61147SHawking Zhang /* disable irqs */ 244edc61147SHawking Zhang navi10_ih_disable_interrupts(adev); 245edc61147SHawking Zhang 246bebc0762SHawking Zhang adev->nbio.funcs->ih_control(adev); 247edc61147SHawking Zhang 248edc61147SHawking Zhang /* Ring Buffer base. [39:8] of 40-bit address of the beginning of the ring buffer*/ 249edc61147SHawking Zhang WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE, ih->gpu_addr >> 8); 250edc61147SHawking Zhang WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE_HI, (ih->gpu_addr >> 40) & 0xff); 251edc61147SHawking Zhang 252edc61147SHawking Zhang ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL); 253edc61147SHawking Zhang ih_rb_cntl = navi10_ih_rb_cntl(ih, ih_rb_cntl); 254edc61147SHawking Zhang ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RPTR_REARM, 255edc61147SHawking Zhang !!adev->irq.msi_enabled); 2560ab176e6SAlex Sierra if (amdgpu_sriov_vf(adev)) { 2570ab176e6SAlex Sierra if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL, ih_rb_cntl)) { 2580ab176e6SAlex Sierra DRM_ERROR("PSP program IH_RB_CNTL failed!\n"); 2590ab176e6SAlex Sierra return -ETIMEDOUT; 2600ab176e6SAlex Sierra } 2610ab176e6SAlex Sierra } else { 2620ab176e6SAlex Sierra WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL, ih_rb_cntl); 2630ab176e6SAlex Sierra } 2649e94ff33SAlex Sierra navi10_ih_reroute_ih(adev); 265edc61147SHawking Zhang 266edc61147SHawking Zhang if (unlikely(adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT)) { 267edc61147SHawking Zhang if (ih->use_bus_addr) { 268edc61147SHawking Zhang ih_chicken = RREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN); 269edc61147SHawking Zhang ih_chicken = REG_SET_FIELD(ih_chicken, 270edc61147SHawking Zhang IH_CHICKEN, MC_SPACE_GPA_ENABLE, 1); 271edc61147SHawking Zhang WREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN, ih_chicken); 272edc61147SHawking Zhang } 273edc61147SHawking Zhang } 274edc61147SHawking Zhang 275edc61147SHawking Zhang /* set the writeback address whether it's enabled or not */ 276edc61147SHawking Zhang WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_ADDR_LO, 277edc61147SHawking Zhang lower_32_bits(ih->wptr_addr)); 278edc61147SHawking Zhang WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_ADDR_HI, 279edc61147SHawking Zhang upper_32_bits(ih->wptr_addr) & 0xFFFF); 280edc61147SHawking Zhang 281edc61147SHawking Zhang /* set rptr, wptr to 0 */ 282edc61147SHawking Zhang WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR, 0); 283edc61147SHawking Zhang WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR, 0); 284edc61147SHawking Zhang 285ab518012SAlex Sierra WREG32_SOC15(OSSSYS, 0, mmIH_DOORBELL_RPTR, 286ab518012SAlex Sierra navi10_ih_doorbell_rptr(ih)); 287edc61147SHawking Zhang 288bebc0762SHawking Zhang adev->nbio.funcs->ih_doorbell_range(adev, ih->use_doorbell, 289edc61147SHawking Zhang ih->doorbell_index); 290edc61147SHawking Zhang 291ab518012SAlex Sierra ih = &adev->irq.ih1; 292ab518012SAlex Sierra if (ih->ring_size) { 293ab518012SAlex Sierra WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE_RING1, ih->gpu_addr >> 8); 294ab518012SAlex Sierra WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE_HI_RING1, 295ab518012SAlex Sierra (ih->gpu_addr >> 40) & 0xff); 296ab518012SAlex Sierra 297ab518012SAlex Sierra ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1); 298ab518012SAlex Sierra ih_rb_cntl = navi10_ih_rb_cntl(ih, ih_rb_cntl); 299ab518012SAlex Sierra ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, 300ab518012SAlex Sierra WPTR_OVERFLOW_ENABLE, 0); 301ab518012SAlex Sierra ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, 302ab518012SAlex Sierra RB_FULL_DRAIN_ENABLE, 1); 3030ab176e6SAlex Sierra if (amdgpu_sriov_vf(adev)) { 3040ab176e6SAlex Sierra if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL_RING1, 3050ab176e6SAlex Sierra ih_rb_cntl)) { 3060ab176e6SAlex Sierra DRM_ERROR("program IH_RB_CNTL_RING1 failed!\n"); 3070ab176e6SAlex Sierra return -ETIMEDOUT; 3080ab176e6SAlex Sierra } 3090ab176e6SAlex Sierra } else { 310ab518012SAlex Sierra WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1, ih_rb_cntl); 3110ab176e6SAlex Sierra } 312ab518012SAlex Sierra /* set rptr, wptr to 0 */ 313ab518012SAlex Sierra WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_RING1, 0); 314ab518012SAlex Sierra WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR_RING1, 0); 315ab518012SAlex Sierra 316ab518012SAlex Sierra WREG32_SOC15(OSSSYS, 0, mmIH_DOORBELL_RPTR_RING1, 317ab518012SAlex Sierra navi10_ih_doorbell_rptr(ih)); 318ab518012SAlex Sierra } 319ab518012SAlex Sierra 320ab518012SAlex Sierra ih = &adev->irq.ih2; 321ab518012SAlex Sierra if (ih->ring_size) { 322ab518012SAlex Sierra WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE_RING2, ih->gpu_addr >> 8); 323ab518012SAlex Sierra WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE_HI_RING2, 324ab518012SAlex Sierra (ih->gpu_addr >> 40) & 0xff); 325ab518012SAlex Sierra 326ab518012SAlex Sierra ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2); 327ab518012SAlex Sierra ih_rb_cntl = navi10_ih_rb_cntl(ih, ih_rb_cntl); 328ab518012SAlex Sierra 3290ab176e6SAlex Sierra if (amdgpu_sriov_vf(adev)) { 3300ab176e6SAlex Sierra if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL_RING2, 3310ab176e6SAlex Sierra ih_rb_cntl)) { 3320ab176e6SAlex Sierra DRM_ERROR("program IH_RB_CNTL_RING2 failed!\n"); 3330ab176e6SAlex Sierra return -ETIMEDOUT; 3340ab176e6SAlex Sierra } 3350ab176e6SAlex Sierra } else { 336ab518012SAlex Sierra WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2, ih_rb_cntl); 3370ab176e6SAlex Sierra } 338ab518012SAlex Sierra /* set rptr, wptr to 0 */ 339ab518012SAlex Sierra WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_RING2, 0); 340ab518012SAlex Sierra WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR_RING2, 0); 341ab518012SAlex Sierra 342ab518012SAlex Sierra WREG32_SOC15(OSSSYS, 0, mmIH_DOORBELL_RPTR_RING2, 343ab518012SAlex Sierra navi10_ih_doorbell_rptr(ih)); 344ab518012SAlex Sierra } 345ab518012SAlex Sierra 346ab518012SAlex Sierra 347edc61147SHawking Zhang tmp = RREG32_SOC15(OSSSYS, 0, mmIH_STORM_CLIENT_LIST_CNTL); 348edc61147SHawking Zhang tmp = REG_SET_FIELD(tmp, IH_STORM_CLIENT_LIST_CNTL, 349edc61147SHawking Zhang CLIENT18_IS_STORM_CLIENT, 1); 350edc61147SHawking Zhang WREG32_SOC15(OSSSYS, 0, mmIH_STORM_CLIENT_LIST_CNTL, tmp); 351edc61147SHawking Zhang 352edc61147SHawking Zhang tmp = RREG32_SOC15(OSSSYS, 0, mmIH_INT_FLOOD_CNTL); 353edc61147SHawking Zhang tmp = REG_SET_FIELD(tmp, IH_INT_FLOOD_CNTL, FLOOD_CNTL_ENABLE, 1); 354edc61147SHawking Zhang WREG32_SOC15(OSSSYS, 0, mmIH_INT_FLOOD_CNTL, tmp); 355edc61147SHawking Zhang 356edc61147SHawking Zhang pci_set_master(adev->pdev); 357edc61147SHawking Zhang 358edc61147SHawking Zhang /* enable interrupts */ 359edc61147SHawking Zhang navi10_ih_enable_interrupts(adev); 360edc61147SHawking Zhang 3617eca4006SMa Feng return 0; 362edc61147SHawking Zhang } 363edc61147SHawking Zhang 364edc61147SHawking Zhang /** 365edc61147SHawking Zhang * navi10_ih_irq_disable - disable interrupts 366edc61147SHawking Zhang * 367edc61147SHawking Zhang * @adev: amdgpu_device pointer 368edc61147SHawking Zhang * 369edc61147SHawking Zhang * Disable interrupts on the hw (NAVI10). 370edc61147SHawking Zhang */ 371edc61147SHawking Zhang static void navi10_ih_irq_disable(struct amdgpu_device *adev) 372edc61147SHawking Zhang { 373edc61147SHawking Zhang navi10_ih_disable_interrupts(adev); 374edc61147SHawking Zhang 375edc61147SHawking Zhang /* Wait and acknowledge irq */ 376edc61147SHawking Zhang mdelay(1); 377edc61147SHawking Zhang } 378edc61147SHawking Zhang 379edc61147SHawking Zhang /** 380edc61147SHawking Zhang * navi10_ih_get_wptr - get the IH ring buffer wptr 381edc61147SHawking Zhang * 382edc61147SHawking Zhang * @adev: amdgpu_device pointer 383edc61147SHawking Zhang * 384edc61147SHawking Zhang * Get the IH ring buffer wptr from either the register 385edc61147SHawking Zhang * or the writeback memory buffer (NAVI10). Also check for 386edc61147SHawking Zhang * ring buffer overflow and deal with it. 387edc61147SHawking Zhang * Returns the value of the wptr. 388edc61147SHawking Zhang */ 389edc61147SHawking Zhang static u32 navi10_ih_get_wptr(struct amdgpu_device *adev, 390edc61147SHawking Zhang struct amdgpu_ih_ring *ih) 391edc61147SHawking Zhang { 392edc61147SHawking Zhang u32 wptr, reg, tmp; 393edc61147SHawking Zhang 394edc61147SHawking Zhang wptr = le32_to_cpu(*ih->wptr_cpu); 395edc61147SHawking Zhang 396edc61147SHawking Zhang if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) 397edc61147SHawking Zhang goto out; 398edc61147SHawking Zhang 399ab518012SAlex Sierra if (ih == &adev->irq.ih) 400edc61147SHawking Zhang reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR); 401ab518012SAlex Sierra else if (ih == &adev->irq.ih1) 402ab518012SAlex Sierra reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_RING1); 403ab518012SAlex Sierra else if (ih == &adev->irq.ih2) 404ab518012SAlex Sierra reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_RING2); 405ab518012SAlex Sierra else 406ab518012SAlex Sierra BUG(); 407ab518012SAlex Sierra 408edc61147SHawking Zhang wptr = RREG32_NO_KIQ(reg); 409edc61147SHawking Zhang if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) 410edc61147SHawking Zhang goto out; 411edc61147SHawking Zhang wptr = REG_SET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW, 0); 412edc61147SHawking Zhang 413edc61147SHawking Zhang /* When a ring buffer overflow happen start parsing interrupt 414edc61147SHawking Zhang * from the last not overwritten vector (wptr + 32). Hopefully 415edc61147SHawking Zhang * this should allow us to catch up. 416edc61147SHawking Zhang */ 417edc61147SHawking Zhang tmp = (wptr + 32) & ih->ptr_mask; 418edc61147SHawking Zhang dev_warn(adev->dev, "IH ring buffer overflow " 419edc61147SHawking Zhang "(0x%08X, 0x%08X, 0x%08X)\n", 420edc61147SHawking Zhang wptr, ih->rptr, tmp); 421edc61147SHawking Zhang ih->rptr = tmp; 422edc61147SHawking Zhang 423ab518012SAlex Sierra if (ih == &adev->irq.ih) 424edc61147SHawking Zhang reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL); 425ab518012SAlex Sierra else if (ih == &adev->irq.ih1) 426ab518012SAlex Sierra reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL_RING1); 427ab518012SAlex Sierra else if (ih == &adev->irq.ih2) 428ab518012SAlex Sierra reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL_RING2); 429ab518012SAlex Sierra else 430ab518012SAlex Sierra BUG(); 431ab518012SAlex Sierra 432edc61147SHawking Zhang tmp = RREG32_NO_KIQ(reg); 433edc61147SHawking Zhang tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1); 434edc61147SHawking Zhang WREG32_NO_KIQ(reg, tmp); 435edc61147SHawking Zhang out: 436edc61147SHawking Zhang return (wptr & ih->ptr_mask); 437edc61147SHawking Zhang } 438edc61147SHawking Zhang 439edc61147SHawking Zhang /** 440edc61147SHawking Zhang * navi10_ih_decode_iv - decode an interrupt vector 441edc61147SHawking Zhang * 442edc61147SHawking Zhang * @adev: amdgpu_device pointer 443edc61147SHawking Zhang * 444edc61147SHawking Zhang * Decodes the interrupt vector at the current rptr 445edc61147SHawking Zhang * position and also advance the position. 446edc61147SHawking Zhang */ 447edc61147SHawking Zhang static void navi10_ih_decode_iv(struct amdgpu_device *adev, 448edc61147SHawking Zhang struct amdgpu_ih_ring *ih, 449edc61147SHawking Zhang struct amdgpu_iv_entry *entry) 450edc61147SHawking Zhang { 451edc61147SHawking Zhang /* wptr/rptr are in bytes! */ 452edc61147SHawking Zhang u32 ring_index = ih->rptr >> 2; 453edc61147SHawking Zhang uint32_t dw[8]; 454edc61147SHawking Zhang 455edc61147SHawking Zhang dw[0] = le32_to_cpu(ih->ring[ring_index + 0]); 456edc61147SHawking Zhang dw[1] = le32_to_cpu(ih->ring[ring_index + 1]); 457edc61147SHawking Zhang dw[2] = le32_to_cpu(ih->ring[ring_index + 2]); 458edc61147SHawking Zhang dw[3] = le32_to_cpu(ih->ring[ring_index + 3]); 459edc61147SHawking Zhang dw[4] = le32_to_cpu(ih->ring[ring_index + 4]); 460edc61147SHawking Zhang dw[5] = le32_to_cpu(ih->ring[ring_index + 5]); 461edc61147SHawking Zhang dw[6] = le32_to_cpu(ih->ring[ring_index + 6]); 462edc61147SHawking Zhang dw[7] = le32_to_cpu(ih->ring[ring_index + 7]); 463edc61147SHawking Zhang 464edc61147SHawking Zhang entry->client_id = dw[0] & 0xff; 465edc61147SHawking Zhang entry->src_id = (dw[0] >> 8) & 0xff; 466edc61147SHawking Zhang entry->ring_id = (dw[0] >> 16) & 0xff; 467edc61147SHawking Zhang entry->vmid = (dw[0] >> 24) & 0xf; 468edc61147SHawking Zhang entry->vmid_src = (dw[0] >> 31); 469edc61147SHawking Zhang entry->timestamp = dw[1] | ((u64)(dw[2] & 0xffff) << 32); 470edc61147SHawking Zhang entry->timestamp_src = dw[2] >> 31; 471edc61147SHawking Zhang entry->pasid = dw[3] & 0xffff; 472edc61147SHawking Zhang entry->pasid_src = dw[3] >> 31; 473edc61147SHawking Zhang entry->src_data[0] = dw[4]; 474edc61147SHawking Zhang entry->src_data[1] = dw[5]; 475edc61147SHawking Zhang entry->src_data[2] = dw[6]; 476edc61147SHawking Zhang entry->src_data[3] = dw[7]; 477edc61147SHawking Zhang 478edc61147SHawking Zhang /* wptr/rptr are in bytes! */ 479edc61147SHawking Zhang ih->rptr += 32; 480edc61147SHawking Zhang } 481edc61147SHawking Zhang 482edc61147SHawking Zhang /** 483022b6518SSamir Dhume * navi10_ih_irq_rearm - rearm IRQ if lost 484022b6518SSamir Dhume * 485022b6518SSamir Dhume * @adev: amdgpu_device pointer 486022b6518SSamir Dhume * 487022b6518SSamir Dhume */ 488022b6518SSamir Dhume static void navi10_ih_irq_rearm(struct amdgpu_device *adev, 489022b6518SSamir Dhume struct amdgpu_ih_ring *ih) 490022b6518SSamir Dhume { 491022b6518SSamir Dhume uint32_t reg_rptr = 0; 492022b6518SSamir Dhume uint32_t v = 0; 493022b6518SSamir Dhume uint32_t i = 0; 494022b6518SSamir Dhume 495022b6518SSamir Dhume if (ih == &adev->irq.ih) 496022b6518SSamir Dhume reg_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR); 497022b6518SSamir Dhume else if (ih == &adev->irq.ih1) 498022b6518SSamir Dhume reg_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR_RING1); 499022b6518SSamir Dhume else if (ih == &adev->irq.ih2) 500022b6518SSamir Dhume reg_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR_RING2); 501022b6518SSamir Dhume else 502022b6518SSamir Dhume return; 503022b6518SSamir Dhume 504022b6518SSamir Dhume /* Rearm IRQ / re-write doorbell if doorbell write is lost */ 505022b6518SSamir Dhume for (i = 0; i < MAX_REARM_RETRY; i++) { 506022b6518SSamir Dhume v = RREG32_NO_KIQ(reg_rptr); 507022b6518SSamir Dhume if ((v < ih->ring_size) && (v != ih->rptr)) 508022b6518SSamir Dhume WDOORBELL32(ih->doorbell_index, ih->rptr); 509022b6518SSamir Dhume else 510022b6518SSamir Dhume break; 511022b6518SSamir Dhume } 512022b6518SSamir Dhume } 513022b6518SSamir Dhume 514022b6518SSamir Dhume /** 515edc61147SHawking Zhang * navi10_ih_set_rptr - set the IH ring buffer rptr 516edc61147SHawking Zhang * 517edc61147SHawking Zhang * @adev: amdgpu_device pointer 518edc61147SHawking Zhang * 519edc61147SHawking Zhang * Set the IH ring buffer rptr. 520edc61147SHawking Zhang */ 521edc61147SHawking Zhang static void navi10_ih_set_rptr(struct amdgpu_device *adev, 522edc61147SHawking Zhang struct amdgpu_ih_ring *ih) 523edc61147SHawking Zhang { 524edc61147SHawking Zhang if (ih->use_doorbell) { 525edc61147SHawking Zhang /* XXX check if swapping is necessary on BE */ 526edc61147SHawking Zhang *ih->rptr_cpu = ih->rptr; 527edc61147SHawking Zhang WDOORBELL32(ih->doorbell_index, ih->rptr); 528022b6518SSamir Dhume 529022b6518SSamir Dhume if (amdgpu_sriov_vf(adev)) 530022b6518SSamir Dhume navi10_ih_irq_rearm(adev, ih); 531ab518012SAlex Sierra } else if (ih == &adev->irq.ih) { 532edc61147SHawking Zhang WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR, ih->rptr); 533ab518012SAlex Sierra } else if (ih == &adev->irq.ih1) { 534ab518012SAlex Sierra WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR_RING1, ih->rptr); 535ab518012SAlex Sierra } else if (ih == &adev->irq.ih2) { 536ab518012SAlex Sierra WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR_RING2, ih->rptr); 537ab518012SAlex Sierra } 538ab518012SAlex Sierra } 539ab518012SAlex Sierra 540ab518012SAlex Sierra /** 541ab518012SAlex Sierra * navi10_ih_self_irq - dispatch work for ring 1 and 2 542ab518012SAlex Sierra * 543ab518012SAlex Sierra * @adev: amdgpu_device pointer 544ab518012SAlex Sierra * @source: irq source 545ab518012SAlex Sierra * @entry: IV with WPTR update 546ab518012SAlex Sierra * 547ab518012SAlex Sierra * Update the WPTR from the IV and schedule work to handle the entries. 548ab518012SAlex Sierra */ 549ab518012SAlex Sierra static int navi10_ih_self_irq(struct amdgpu_device *adev, 550ab518012SAlex Sierra struct amdgpu_irq_src *source, 551ab518012SAlex Sierra struct amdgpu_iv_entry *entry) 552ab518012SAlex Sierra { 553ab518012SAlex Sierra uint32_t wptr = cpu_to_le32(entry->src_data[0]); 554ab518012SAlex Sierra 555ab518012SAlex Sierra switch (entry->ring_id) { 556ab518012SAlex Sierra case 1: 557ab518012SAlex Sierra *adev->irq.ih1.wptr_cpu = wptr; 558ab518012SAlex Sierra schedule_work(&adev->irq.ih1_work); 559ab518012SAlex Sierra break; 560ab518012SAlex Sierra case 2: 561ab518012SAlex Sierra *adev->irq.ih2.wptr_cpu = wptr; 562ab518012SAlex Sierra schedule_work(&adev->irq.ih2_work); 563ab518012SAlex Sierra break; 564ab518012SAlex Sierra default: break; 565ab518012SAlex Sierra } 566ab518012SAlex Sierra return 0; 567ab518012SAlex Sierra } 568ab518012SAlex Sierra 569ab518012SAlex Sierra static const struct amdgpu_irq_src_funcs navi10_ih_self_irq_funcs = { 570ab518012SAlex Sierra .process = navi10_ih_self_irq, 571ab518012SAlex Sierra }; 572ab518012SAlex Sierra 573ab518012SAlex Sierra static void navi10_ih_set_self_irq_funcs(struct amdgpu_device *adev) 574ab518012SAlex Sierra { 575ab518012SAlex Sierra adev->irq.self_irq.num_types = 0; 576ab518012SAlex Sierra adev->irq.self_irq.funcs = &navi10_ih_self_irq_funcs; 577edc61147SHawking Zhang } 578edc61147SHawking Zhang 579edc61147SHawking Zhang static int navi10_ih_early_init(void *handle) 580edc61147SHawking Zhang { 581edc61147SHawking Zhang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 582edc61147SHawking Zhang 583edc61147SHawking Zhang navi10_ih_set_interrupt_funcs(adev); 584ab518012SAlex Sierra navi10_ih_set_self_irq_funcs(adev); 585edc61147SHawking Zhang return 0; 586edc61147SHawking Zhang } 587edc61147SHawking Zhang 588edc61147SHawking Zhang static int navi10_ih_sw_init(void *handle) 589edc61147SHawking Zhang { 590edc61147SHawking Zhang int r; 591edc61147SHawking Zhang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 592edc61147SHawking Zhang bool use_bus_addr; 593edc61147SHawking Zhang 594ab518012SAlex Sierra r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_IH, 0, 595ab518012SAlex Sierra &adev->irq.self_irq); 596ab518012SAlex Sierra 597ab518012SAlex Sierra if (r) 598ab518012SAlex Sierra return r; 599ab518012SAlex Sierra 600edc61147SHawking Zhang /* use gpu virtual address for ih ring 601edc61147SHawking Zhang * until ih_checken is programmed to allow 602edc61147SHawking Zhang * use bus address for ih ring by psp bl */ 603edc61147SHawking Zhang use_bus_addr = 604edc61147SHawking Zhang (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) ? false : true; 605edc61147SHawking Zhang r = amdgpu_ih_ring_init(adev, &adev->irq.ih, 256 * 1024, use_bus_addr); 606edc61147SHawking Zhang if (r) 607edc61147SHawking Zhang return r; 608edc61147SHawking Zhang 609edc61147SHawking Zhang adev->irq.ih.use_doorbell = true; 610edc61147SHawking Zhang adev->irq.ih.doorbell_index = adev->doorbell_index.ih << 1; 611edc61147SHawking Zhang 612ab518012SAlex Sierra r = amdgpu_ih_ring_init(adev, &adev->irq.ih1, PAGE_SIZE, true); 613ab518012SAlex Sierra if (r) 614ab518012SAlex Sierra return r; 615ab518012SAlex Sierra 616ab518012SAlex Sierra adev->irq.ih1.use_doorbell = true; 617ab518012SAlex Sierra adev->irq.ih1.doorbell_index = (adev->doorbell_index.ih + 1) << 1; 618ab518012SAlex Sierra 619ab518012SAlex Sierra r = amdgpu_ih_ring_init(adev, &adev->irq.ih2, PAGE_SIZE, true); 620ab518012SAlex Sierra if (r) 621ab518012SAlex Sierra return r; 622ab518012SAlex Sierra 623ab518012SAlex Sierra adev->irq.ih2.use_doorbell = true; 624ab518012SAlex Sierra adev->irq.ih2.doorbell_index = (adev->doorbell_index.ih + 2) << 1; 625ab518012SAlex Sierra 626edc61147SHawking Zhang r = amdgpu_irq_init(adev); 627edc61147SHawking Zhang 628edc61147SHawking Zhang return r; 629edc61147SHawking Zhang } 630edc61147SHawking Zhang 631edc61147SHawking Zhang static int navi10_ih_sw_fini(void *handle) 632edc61147SHawking Zhang { 633edc61147SHawking Zhang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 634edc61147SHawking Zhang 635edc61147SHawking Zhang amdgpu_irq_fini(adev); 636ab518012SAlex Sierra amdgpu_ih_ring_fini(adev, &adev->irq.ih2); 637ab518012SAlex Sierra amdgpu_ih_ring_fini(adev, &adev->irq.ih1); 638edc61147SHawking Zhang amdgpu_ih_ring_fini(adev, &adev->irq.ih); 639edc61147SHawking Zhang 640edc61147SHawking Zhang return 0; 641edc61147SHawking Zhang } 642edc61147SHawking Zhang 643edc61147SHawking Zhang static int navi10_ih_hw_init(void *handle) 644edc61147SHawking Zhang { 645edc61147SHawking Zhang int r; 646edc61147SHawking Zhang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 647edc61147SHawking Zhang 648edc61147SHawking Zhang r = navi10_ih_irq_init(adev); 649edc61147SHawking Zhang if (r) 650edc61147SHawking Zhang return r; 651edc61147SHawking Zhang 652edc61147SHawking Zhang return 0; 653edc61147SHawking Zhang } 654edc61147SHawking Zhang 655edc61147SHawking Zhang static int navi10_ih_hw_fini(void *handle) 656edc61147SHawking Zhang { 657edc61147SHawking Zhang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 658edc61147SHawking Zhang 659edc61147SHawking Zhang navi10_ih_irq_disable(adev); 660edc61147SHawking Zhang 661edc61147SHawking Zhang return 0; 662edc61147SHawking Zhang } 663edc61147SHawking Zhang 664edc61147SHawking Zhang static int navi10_ih_suspend(void *handle) 665edc61147SHawking Zhang { 666edc61147SHawking Zhang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 667edc61147SHawking Zhang 668edc61147SHawking Zhang return navi10_ih_hw_fini(adev); 669edc61147SHawking Zhang } 670edc61147SHawking Zhang 671edc61147SHawking Zhang static int navi10_ih_resume(void *handle) 672edc61147SHawking Zhang { 673edc61147SHawking Zhang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 674edc61147SHawking Zhang 675edc61147SHawking Zhang return navi10_ih_hw_init(adev); 676edc61147SHawking Zhang } 677edc61147SHawking Zhang 678edc61147SHawking Zhang static bool navi10_ih_is_idle(void *handle) 679edc61147SHawking Zhang { 680edc61147SHawking Zhang /* todo */ 681edc61147SHawking Zhang return true; 682edc61147SHawking Zhang } 683edc61147SHawking Zhang 684edc61147SHawking Zhang static int navi10_ih_wait_for_idle(void *handle) 685edc61147SHawking Zhang { 686edc61147SHawking Zhang /* todo */ 687edc61147SHawking Zhang return -ETIMEDOUT; 688edc61147SHawking Zhang } 689edc61147SHawking Zhang 690edc61147SHawking Zhang static int navi10_ih_soft_reset(void *handle) 691edc61147SHawking Zhang { 692edc61147SHawking Zhang /* todo */ 693edc61147SHawking Zhang return 0; 694edc61147SHawking Zhang } 695edc61147SHawking Zhang 696edc61147SHawking Zhang static void navi10_ih_update_clockgating_state(struct amdgpu_device *adev, 697edc61147SHawking Zhang bool enable) 698edc61147SHawking Zhang { 699edc61147SHawking Zhang uint32_t data, def, field_val; 700edc61147SHawking Zhang 701edc61147SHawking Zhang if (adev->cg_flags & AMD_CG_SUPPORT_IH_CG) { 702edc61147SHawking Zhang def = data = RREG32_SOC15(OSSSYS, 0, mmIH_CLK_CTRL); 703edc61147SHawking Zhang field_val = enable ? 0 : 1; 704edc61147SHawking Zhang data = REG_SET_FIELD(data, IH_CLK_CTRL, 705edc61147SHawking Zhang DBUS_MUX_CLK_SOFT_OVERRIDE, field_val); 706edc61147SHawking Zhang data = REG_SET_FIELD(data, IH_CLK_CTRL, 707edc61147SHawking Zhang OSSSYS_SHARE_CLK_SOFT_OVERRIDE, field_val); 708edc61147SHawking Zhang data = REG_SET_FIELD(data, IH_CLK_CTRL, 709edc61147SHawking Zhang LIMIT_SMN_CLK_SOFT_OVERRIDE, field_val); 710edc61147SHawking Zhang data = REG_SET_FIELD(data, IH_CLK_CTRL, 711edc61147SHawking Zhang DYN_CLK_SOFT_OVERRIDE, field_val); 712edc61147SHawking Zhang data = REG_SET_FIELD(data, IH_CLK_CTRL, 713edc61147SHawking Zhang REG_CLK_SOFT_OVERRIDE, field_val); 714edc61147SHawking Zhang if (def != data) 715edc61147SHawking Zhang WREG32_SOC15(OSSSYS, 0, mmIH_CLK_CTRL, data); 716edc61147SHawking Zhang } 717edc61147SHawking Zhang 718edc61147SHawking Zhang return; 719edc61147SHawking Zhang } 720edc61147SHawking Zhang 721edc61147SHawking Zhang static int navi10_ih_set_clockgating_state(void *handle, 722edc61147SHawking Zhang enum amd_clockgating_state state) 723edc61147SHawking Zhang { 724edc61147SHawking Zhang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 725edc61147SHawking Zhang 726edc61147SHawking Zhang navi10_ih_update_clockgating_state(adev, 727a9d4fe2fSNirmoy Das state == AMD_CG_STATE_GATE); 728edc61147SHawking Zhang return 0; 729edc61147SHawking Zhang } 730edc61147SHawking Zhang 731edc61147SHawking Zhang static int navi10_ih_set_powergating_state(void *handle, 732edc61147SHawking Zhang enum amd_powergating_state state) 733edc61147SHawking Zhang { 734edc61147SHawking Zhang return 0; 735edc61147SHawking Zhang } 736edc61147SHawking Zhang 737edc61147SHawking Zhang static void navi10_ih_get_clockgating_state(void *handle, u32 *flags) 738edc61147SHawking Zhang { 739edc61147SHawking Zhang struct amdgpu_device *adev = (struct amdgpu_device *)handle; 740edc61147SHawking Zhang 741edc61147SHawking Zhang if (!RREG32_SOC15(OSSSYS, 0, mmIH_CLK_CTRL)) 742edc61147SHawking Zhang *flags |= AMD_CG_SUPPORT_IH_CG; 743edc61147SHawking Zhang 744edc61147SHawking Zhang return; 745edc61147SHawking Zhang } 746edc61147SHawking Zhang 747edc61147SHawking Zhang static const struct amd_ip_funcs navi10_ih_ip_funcs = { 748edc61147SHawking Zhang .name = "navi10_ih", 749edc61147SHawking Zhang .early_init = navi10_ih_early_init, 750edc61147SHawking Zhang .late_init = NULL, 751edc61147SHawking Zhang .sw_init = navi10_ih_sw_init, 752edc61147SHawking Zhang .sw_fini = navi10_ih_sw_fini, 753edc61147SHawking Zhang .hw_init = navi10_ih_hw_init, 754edc61147SHawking Zhang .hw_fini = navi10_ih_hw_fini, 755edc61147SHawking Zhang .suspend = navi10_ih_suspend, 756edc61147SHawking Zhang .resume = navi10_ih_resume, 757edc61147SHawking Zhang .is_idle = navi10_ih_is_idle, 758edc61147SHawking Zhang .wait_for_idle = navi10_ih_wait_for_idle, 759edc61147SHawking Zhang .soft_reset = navi10_ih_soft_reset, 760edc61147SHawking Zhang .set_clockgating_state = navi10_ih_set_clockgating_state, 761edc61147SHawking Zhang .set_powergating_state = navi10_ih_set_powergating_state, 762edc61147SHawking Zhang .get_clockgating_state = navi10_ih_get_clockgating_state, 763edc61147SHawking Zhang }; 764edc61147SHawking Zhang 765edc61147SHawking Zhang static const struct amdgpu_ih_funcs navi10_ih_funcs = { 766edc61147SHawking Zhang .get_wptr = navi10_ih_get_wptr, 767edc61147SHawking Zhang .decode_iv = navi10_ih_decode_iv, 768edc61147SHawking Zhang .set_rptr = navi10_ih_set_rptr 769edc61147SHawking Zhang }; 770edc61147SHawking Zhang 771edc61147SHawking Zhang static void navi10_ih_set_interrupt_funcs(struct amdgpu_device *adev) 772edc61147SHawking Zhang { 773edc61147SHawking Zhang if (adev->irq.ih_funcs == NULL) 774edc61147SHawking Zhang adev->irq.ih_funcs = &navi10_ih_funcs; 775edc61147SHawking Zhang } 776edc61147SHawking Zhang 777edc61147SHawking Zhang const struct amdgpu_ip_block_version navi10_ih_ip_block = 778edc61147SHawking Zhang { 779edc61147SHawking Zhang .type = AMD_IP_BLOCK_TYPE_IH, 780edc61147SHawking Zhang .major = 5, 781edc61147SHawking Zhang .minor = 0, 782edc61147SHawking Zhang .rev = 0, 783edc61147SHawking Zhang .funcs = &navi10_ih_ip_funcs, 784edc61147SHawking Zhang }; 785